Array substrate and display panel

Abstract

The array substrate comprises a hole opening area, a display area surrounding the hole opening area, and a hole opening peripheral area located between the hole opening area and the display area. The array substrate comprises a substrate and a driving circuit layer located on the substrate. The driving circuit layer comprises a constant-voltage conducting ring and a plurality of signal lines. At least part of the signal lines are target signal lines, each target signal line comprises a lead part and a winding part which are connected, the lead parts extend to the display area from the opening peripheral area, and the winding parts are located in the opening peripheral area and arranged along the edge of the opening area. The constant-voltage conducting ring is located in the opening peripheral area and arranged around the opening area, and the winding part is located between the constant-voltage conducting ring and the opening area in the direction from the display area to the opening area.

Description

Array substrate and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Display devices can be used to display images. With the rapid development of display technology, display devices have gradually become prevalent in people's lives.

[0003] Summary of the Invention

[0004] On the one hand, an array substrate is provided. The array substrate includes: an aperture area, a display area surrounding the aperture area, and an aperture peripheral area located between the aperture area and the display area. The array substrate includes a substrate and a drive circuit layer located on the substrate. The drive circuit layer includes a constant voltage conductive ring and a plurality of signal lines. The plurality of signal lines include a plurality of target signal lines, and the target signal lines include a lead portion and a winding portion connected to each other. The lead portion extends from the aperture peripheral area to the display area, and the winding portion is located in the aperture peripheral area and is arranged along the edge of the aperture area. The constant voltage conductive ring is located in the aperture peripheral area and is arranged around the aperture area. In the direction from the display area to the aperture area, the orthographic projection of the winding portion on the substrate is located between the orthographic projection of the constant voltage conductive ring on the substrate and the aperture area.

[0005] In some embodiments, the lead portion includes a first overlapping portion, the orthographic projection of the first overlapping portion on the substrate overlaps with the orthographic projection of the constant voltage conductive ring on the substrate, and the areas of the first overlapping portions of the lead portions of multiple target signal lines are equal.

[0006] In some embodiments, the plurality of target signal lines include a plurality of first signal lines, wherein lead portions of the plurality of first signal lines extend along a first direction and are arranged in a second direction, and the first direction and the second direction intersect. The plurality of first signal lines are divided into a first portion of signal lines and a second portion of signal lines, and along the second direction, the lead portions of the first portion of signal lines and the lead portions of the second portion of signal lines are respectively located on opposite sides of the opening area.

[0007] In some embodiments, the plurality of target signal lines further include a plurality of second signal lines, wherein lead portions of the plurality of second signal lines extend along the second direction and are arranged in the first direction. The plurality of second signal lines are divided into a third portion of signal lines and a fourth portion of signal lines, wherein the lead portions of the third portion of signal lines and the lead portions of the fourth portion of signal lines are respectively located on opposite sides of the opening area along the first direction.

[0008] In some embodiments, the first signal line comprises a gate control signal line, and the second signal line comprises a data signal line.

[0009] In some embodiments, the drive circuit layer includes multiple metal conductive layers stacked on the substrate. In a direction away from the substrate, the multiple metal conductive layers are respectively a first gate metal layer, a second gate metal layer, a first routing metal layer, and a second routing metal layer. Among the multiple first signal lines, the winding portions of some of the first signal lines are located in the first gate metal layer, while the winding portions of another portion of the first signal lines are located in the second gate metal layer. Among the multiple second signal lines, the winding portions of some of the second signal lines are located in the first routing metal layer, while the winding portions of another portion of the second signal lines are located in the second routing metal layer.

[0010] In some embodiments, the winding portion of the plurality of winding portions, in an orthographic projection onto the substrate, that portion is furthest from the opening area is an outer winding portion. The driving circuit layer further includes a dummy winding portion. The dummy winding portion is located between the outer winding portion and the display area, and is on the same layer as the outer winding portion.

[0011] In some embodiments, the winding portion farthest from the opening area among the plurality of winding portions located in the same metal conductive layer is an edge winding portion. The driving circuit layer further includes a dummy winding portion. The dummy winding portion corresponds one-to-one with the edge winding portion, is located between the edge winding portion and the display area, and is on the same layer as the corresponding edge winding portion.

[0012] In some embodiments, along a direction from the opening area to the display area, a width of the virtual winding portion is equal to a width of the winding portion.

[0013] In some embodiments, in a direction from the opening area to the display area, the spacing between the virtual winding portion and the adjacent winding portion is equal to the spacing between any two adjacent winding portions.

[0014] In some embodiments, the winding portion of the plurality of winding portions, in an orthographic projection onto the substrate, that portion farthest from the opening area is an outer winding portion, and the winding portions of the plurality of winding portions other than the outer winding portion are first inner winding portions. Along a direction from the opening area to the display area, a width d1 of the outer winding portion is greater than a width d2 of the first inner winding portion.

[0015] In some embodiments, the winding portion farthest from the opening area among the plurality of winding portions located in the same metal conductive layer is an edge winding portion, and the winding portions other than the edge winding portion are second inner winding portions. Along a direction from the opening area to the display area, a width d1 of the edge winding portion is greater than a width d2 of the second inner winding portion.

[0016] In some embodiments, 1.1d2≤d1≤1.15d2.

[0017] In some embodiments, d1 = 1.3d2.

[0018] In some embodiments, the driving circuit layer further includes a plurality of pixel driving circuits, each of which includes a driving transistor, and the plurality of pixel driving circuits are located in the display area. The driving circuit layer further includes a bottom shielding layer, the bottom shielding layer being located between the pixel driving circuit and the substrate, the constant voltage conductive ring being electrically connected to the bottom shielding layer. The bottom shielding layer includes a plurality of shielding patterns, the orthographic projections of the shielding patterns on the substrate covering the orthographic projections of the driving transistor on the substrate, and adjacent two of the shielding patterns being connected to each other.

[0019] In some embodiments, the constant voltage conductive ring is placed on the same layer as the bottom shielding layer.

[0020] In some embodiments, the bottom shielding layer further includes a conductive connection portion configured to connect the constant voltage conductive ring and the shielding pattern. The driving circuit layer further includes a plurality of connecting vias, wherein the orthographic projection of the conductive connection portion on the substrate does not overlap with the orthographic projection of the connecting vias on the substrate.

[0021] In some embodiments, a minimum distance between an orthographic projection of the conductive connection portion on the substrate and an orthographic projection of the connecting through hole on the substrate is greater than or equal to 3 μm.

[0022] In some embodiments, the conductive connection portion and the constant voltage conductive ring are in the same layer. The conductive connection portion includes a first conductive connection portion, the first conductive connection portion intersects with the constant voltage conductive ring to form a first acute angle, and the first conductive connection portion and the constant voltage conductive ring intersect to form a first space. The driving circuit layer also includes a first compensation portion, the first compensation portion and the constant voltage conductive ring are in the same layer. The first compensation portion is located in the first space, the first compensation portion and the first conductive connection portion intersect to form a first angle, and the first compensation portion and the constant voltage conductive ring intersect to form a second angle. Wherein, the first angle and the second angle are both greater than or equal to 90°.

[0023] In another aspect, a display panel is provided, comprising: a light-emitting device layer and an array substrate as described in any one of the above embodiments, wherein the light-emitting device layer is located on a side of the array substrate away from a substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and do not limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, etc. involved in the embodiments of the present disclosure.

[0025] FIG1 is a structural diagram of a display device according to some embodiments;

[0026] FIG2 is a structural diagram of a display panel according to some embodiments;

[0027] FIG3 is a cross-sectional view of a display panel according to some embodiments;

[0028] FIG4 is a structural diagram of an array substrate according to some possible implementations;

[0029] FIG5 is a cross-sectional view of an array substrate according to some embodiments;

[0030] FIG6 is a partial enlarged view of M1 in FIG4 ;

[0031] FIG7 is a partial enlarged view of M2 in FIG4 ;

[0032] FIG8 is a partial enlarged view of M3 in FIG4 ;

[0033] FIG9 is a connection diagram of the bottom shielding layer and the constant voltage conductive ring of M2 in FIG4 ;

[0034] FIG10 is a structural diagram of an array substrate according to some embodiments;

[0035] FIG11 is a partial enlarged view of N3 in FIG10 ;

[0036] FIG12 is a partial enlarged view of K in FIG11 ;

[0037] FIG13 is a cross-sectional view taken along line II' in FIG10;

[0038] FIG14 is another partial enlarged view of N3 in FIG10 ;

[0039] FIG15 is a cross-sectional view taken along line H1-H1' in FIG14;

[0040] FIG16 is another partial enlarged view of N3 in FIG10 ;

[0041] FIG17 is a cross-sectional view taken along line H2-H2' in FIG16;

[0042] FIG18 is another partial enlarged view of N3 in FIG10 ;

[0043] FIG19 is a cross-sectional view taken along line H3-H3' in FIG18;

[0044] FIG20 is another partial enlarged view of N3 in FIG10 ;

[0045] FIG. 21 is a cross-sectional view taken along line H4 - H4 ' in FIG. 20 . DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0050] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0053] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0057] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0058] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0059] FIG. 1 is a structural diagram of a display device according to some embodiments.

[0060] As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 300 , which includes a display panel 200 .

[0061] Exemplarily, the display device 300 further includes a frame and other electronic components.

[0062] Exemplarily, the display device 300 may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0063] Exemplarily, the display device 300 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0064] Some embodiments of the present disclosure further provide a display panel. This display panel can be used as the display panel in the display device provided in any of the above embodiments. Of course, this display panel can also be used in other display devices, and this disclosure does not limit this.

[0065] Figure 2 is a structural diagram of a display panel according to some embodiments, illustrating the structure of a display area in the display panel. It should be noted that Figure 2 only illustrates the structure of the display area of ​​the display panel, while omitting the structure of the peripheral area, for example, omitting the scan drive circuit.

[0066] In some embodiments, as shown in FIG. 2 , the display panel 200 includes a light-transmitting area W1, an active area (AA) AA, also referred to as an effective display area, and a peripheral area SA. The active area AA surrounds the light-transmitting area W1, and the peripheral area SA may be located on at least one side (e.g., one side; or, for example, all four sides, i.e., including the upper and lower sides and the left and right sides) of the display area AA.

[0067] The display panel 200 includes a plurality of sub-pixels P disposed in the display area AA. No pixels P are disposed in the light-transmitting area W1.

[0068] The plurality of sub-pixels P may be arranged in an array. Through the light emitted by the plurality of sub-pixels P, the display panel 200 may display an image in the display area AA.

[0069] Specifically, the plurality of sub-pixels P may include a plurality of sub-pixels emitting different luminous colors. Exemplarily, the plurality of sub-pixels P include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each emit three primary colors of light. For example, the first sub-pixel P1 may emit red light, the second sub-pixel P2 may emit green light, and the third sub-pixel P3 may emit blue light.

[0070] Based on this, by adjusting the brightness (grayscale) of sub-pixels P of different colors, multiple colors can be displayed through color combination and superposition, thereby achieving full-color display of the display panel 200.

[0071] In some examples, as shown in FIG2 , the shape of the light-transmitting area W1 may be circular. However, the embodiment of the present disclosure is not limited to this shape of the light-transmitting area W1. For example, the shape of the light-transmitting area W1 may also be square or oval.

[0072] Exemplarily, the light-transmitting area W1 may be a camera area or a fingerprint recognition area, etc. The following only takes the light-transmitting area W1 as an example of a camera area, and the same is applicable to fingerprint recognition.

[0073] FIG. 3 is a cross-sectional view of a display panel according to some embodiments.

[0074] As shown in combination with FIG. 2 and FIG. 3 , a sub-pixel P may include a light-emitting device O and a pixel driving circuit Q coupled to the light-emitting device O.

[0075] The light-emitting device O may be one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a light-emitting diode (LED), and a liquid crystal light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the type of light-emitting device. That is, the light-emitting device O may be any other light-emitting device (e.g., a light-emitting device that emits light through discharge), as long as it can emit light so that the display panel 200 can display an image.

[0076] The pixel driving circuit Q can be configured to provide an electrical signal (such as a driving voltage or a driving current) to the light-emitting device O coupled to the pixel driving circuit Q in response to the received scan signal and data signal, so as to drive the light-emitting device O to emit light, so that the display panel 200 can display the picture.

[0077] As shown in FIG. 3 , the display panel 200 includes an array substrate 100 and a light emitting device layer 210 stacked in sequence. The light emitting device layer 210 is located on a side of the array substrate 100 close to a light emitting surface of the display panel 200 .

[0078] The array substrate 100 includes a plurality of pixel driving circuits Q, the light emitting device layer 210 includes a plurality of light emitting devices O, and the plurality of pixel driving circuits Q are electrically connected to the plurality of light emitting devices O to drive the light emitting devices O to emit light.

[0079] In some examples, the multiple pixel driving circuits Q and the multiple light-emitting devices O can be electrically connected in a one-to-one correspondence. In other examples, one pixel driving circuit Q can be coupled to multiple light-emitting devices O, or multiple pixel driving circuits Q can be coupled to one light-emitting device O. Below, the present disclosure uses the coupling of one pixel driving circuit Q to one light-emitting device O as an example to schematically illustrate the structure of the display panel 200.

[0080] In some examples, the light emitting device layer 210 includes an anode layer, a light emitting functional layer, and a cathode layer stacked in sequence, wherein the light emitting functional layer includes a light emitting layer.

[0081] In other examples, the light-emitting functional layer includes, in addition to the light-emitting layer, one or more layers of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0082] In some examples, the display panel 200 further includes an encapsulation layer, which is located on a side of the light-emitting device layer 210 away from the array substrate 100. Here, the encapsulation layer can be an encapsulation film or an encapsulation substrate.

[0083] The encapsulation layer can cover the multiple light-emitting devices O in the light-emitting device layer 210 and encapsulate the light-emitting devices O to prevent moisture and oxygen in the external environment from entering the display panel 200 and damaging the organic materials in the light-emitting devices O, thereby shortening the life of the display panel 200.

[0084] Some embodiments of the present disclosure further provide an array substrate. This array substrate can be used as the array substrate in the display panel provided in any of the above embodiments. Of course, this array substrate can also be used in other display panels, and this disclosure does not limit this.

[0085] Figure 4 is a structural diagram of an array substrate according to some possible implementations. Figure 4 illustrates signal lines surrounding an opening area Q within the display area of ​​the array substrate. It should be noted that Figure 4 only illustrates the signal lines surrounding the opening area Q within the display area of ​​the array substrate, while omitting other structures surrounding the opening area Q. For example, structures such as the pixel driver circuit surrounding the opening area Q are omitted.

[0086] In some embodiments, as shown in FIG4 , the array substrate 100 includes an opening area W2, a display area (full name: Active Area, AA area for short; also referred to as the effective display area) AA, and an opening peripheral area S1. The display area AA surrounds the opening area W2, and the opening peripheral area S1 surrounds the opening area W2, with the opening peripheral area S1 being located between the opening area W2 and the display area AA.

[0087] The display area AA of the array substrate 100 may correspond to the display area AA of the display panel 200 (as shown in FIG. 2 ), and the opening area W2 of the array substrate 100 may correspond to the light-transmitting area W1 of the display panel 200 .

[0088] FIG. 5 is a cross-sectional view of an array substrate according to some embodiments.

[0089] In some embodiments, as shown in Figures 4 and 5 , the array substrate 100 includes a substrate 10 and a driving circuit layer 20 located on the substrate 10. The driving circuit layer 20 is located on one side of the substrate 10. For example, the driving circuit layer 20 is located on a side of the substrate 10 that is close to the light-emitting device layer 210 (as shown in Figure 3 ). The driving circuit layer 20 includes a plurality of pixel driving circuits Q.

[0090] In some examples, the substrate 10 may be a flexible substrate. For example, the material of the substrate 10 may be an organic material. For example, the material of the substrate 10 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0091] In other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0092] In some examples, the driving circuit layer 20 includes a plurality of pixel driving circuits Q disposed in the display area AA. A pixel driving circuit Q is not disposed in the opening area W2. The pixel driving circuit Q can be configured to provide an electrical signal (e.g., a driving voltage or a driving current) to a light-emitting device O coupled to the pixel driving circuit Q in response to received scan signals and data signals, thereby driving the light-emitting device O to emit light, thereby enabling the display panel 200 to display an image.

[0093] The plurality of pixel driving circuits Q are arranged in multiple rows and columns. For the convenience of description, the plurality of pixel driving circuits Q are described in this disclosure by taking a matrix arrangement as an example.

[0094] In some examples, the pixel driving circuit Q may include multiple transistors and at least one (e.g., one; for example, multiple) capacitors. The multiple transistors include a driving transistor. The structure of the pixel driving circuit Q in the present disclosure includes multiple types, which can be selected according to actual needs. For example, the structure of the pixel driving circuit Q may include "2T1C", "6T1C", "7T1C", "6T2C", "7T2C" or "8T1C", etc. Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C.

[0095] In some embodiments, as shown in FIG. 4 and FIG. 5 , the pixel driving circuit Q needs to be electrically connected to a plurality of signal lines 30 , so as to utilize the plurality of signal lines 30 to provide different signals and provide the required signals to the pixel driving circuit Q.

[0096] In some examples, the plurality of signal lines 30 include a plurality of first signal lines 31 , wherein the lead portions L1 of the plurality of first signal lines 31 extend along a first direction X and are arranged in a second direction Y. The first signal lines 31 may be gate control signal lines, and the plurality of gate control signal lines are used to provide scanning signals. The first direction X and the second direction Y intersect.

[0097] The plurality of signal lines 30 further include a plurality of second signal lines 32 , the lead portions L1 of the plurality of second signal lines 32 extending along the second direction Y and arranged in the first direction X. The second signal lines 32 may be data signal lines for providing data signals.

[0098] Based on this, the pixel driving circuit Q can be configured to provide an electrical signal (such as a driving voltage or a driving current) to the light-emitting device O coupled to the pixel driving circuit Q in response to the received scanning signal and data signal, so as to drive the light-emitting device O to emit light, so that the display panel 200 can display the picture.

[0099] In some examples, the first direction X and the second direction Y may be approximately perpendicular, and in this case, the angle between the first direction X and the second direction Y is approximately 90°. For example, the angle between the first direction X and the second direction Y may be 85°, 90°, or 95°.

[0100] As shown in FIG4 , since the plurality of pixel driving circuits Q are all located in the display area AA, and no pixel driving circuits Q are provided in the opening area W2, at least some of the plurality of signal lines 30 pass through the opening area W2 to provide electrical signals (e.g., scanning signals, data signals, etc.) to the pixel driving circuits Q located on both sides of the opening area W2.

[0101] Among the plurality of signal lines 30 , the signal line 30 that passes through the opening area W2 is the target signal line 30A, where “passing through” can be understood as the orthographic projection of the signal line 30 on the substrate 10 overlapping with the opening area W2 .

[0102] Since the target signal line 30A is generally made of metal, when passing through the opening area W2, the target signal line 30A is shielded from light, which will affect the light transmittance of the opening area W2 of the array substrate 100 and the subsequent imaging effect of the display panel.

[0103] Figure 6 is a partial enlarged view of M1 in Figure 4 , Figure 7 is a partial enlarged view of M2 in Figure 4 , and Figure 8 is a partial enlarged view of M3 in Figure 4 . Figure 6 illustrates the structure of the aperture perimeter region S1 near the connection between the winding portion L2 and the lead portion L1 of the plurality of target signal lines 30A, Figure 7 illustrates the structure of the aperture perimeter region S1 near the end of the winding portion L2 of the plurality of target signal lines 30A, and Figure 8 illustrates the structure of the aperture perimeter region S1 near the middle of the winding portion L2 of the plurality of target signal lines 30A.

[0104] Based on this, as shown in Figures 4 to 8 , multiple target signal lines 30A need to avoid the opening area W2. Thus, the target signal line 30A can include a lead portion L1 and a winding portion L2 connected to each other. The lead portion L1 extends from the opening peripheral area S1 to the display area, and the winding portion L2 is located in the opening peripheral area S1 and is arranged along the edge of the opening area W2.

[0105] 4 and 6 schematically illustrate that the target signal line 30A is separated into two lead portions L1 by the opening area W2, and the two lead portions L1 are connected by the winding portion L2 located in the opening peripheral area S1 to form the target signal line 30A avoiding the opening area W2.

[0106] In some examples, all of the plurality of signal lines 30 may be set as target signal lines 30A.

[0107] In other examples, a portion of the plurality of signal lines 30 may be target signal lines 30A. In this case, another portion of the plurality of signal lines 30 may be regular signal lines. Regular signal lines are those signal lines 30 that do not pass through the opening area W2. That is, the orthographic projections of the regular signal lines on the substrate 10 do not overlap with the opening area W2.

[0108] The number of target signal lines 30A in the plurality of signal lines 30 may be adjusted according to the length of the opening area W2 along the direction in which the plurality of signal lines 30 are arranged, but the present disclosure is not limited thereto.

[0109] The inventors discovered, as shown in Figures 4 and 5 , that to prevent the transmittance of the aperture area W2 from being affected, the multiple pixel drive circuits Q in the drive circuit layer 20 are located in the display area AA, rather than in the light-transmitting area W1. As a result, some structures in the drive circuit layer 20 are interrupted in the light-transmitting area W1. For example, the bottom shielding layer in the drive circuit layer 20 is disconnected at the location of the light-transmitting area W1.

[0110] This can cause static electricity to accumulate on the side of the driving circuit layer 20 near the opening area W2 in the display area AA. When the accumulated static electricity energy is too large, it can easily affect the pixel driving circuit Q of the driving circuit layer 20 near the opening area W2 in the display area AA, or even damage that portion of the pixel driving circuit Q, thereby reducing the quality of the array substrate 100.

[0111] The following describes an example of a structure in which the light-transmitting area W1 of the driving circuit layer 20 is cut off.

[0112] FIG9 is a connection diagram of the bottom shielding layer and the constant voltage conductive ring of M2 in FIG4 .

[0113] In some embodiments, as shown in conjunction with FIG4 and FIG9 , the driving circuit layer 20 further includes a bottom shield metal (BSM) 60, which is located between the pixel driving circuit Q and the substrate 10. The bottom shield layer 60 includes a plurality of shielding patterns 61, and the orthographic projections of the shielding patterns 61 on the substrate 10 cover the orthographic projections of the driving transistors in the pixel driving circuit Q on the substrate 10.

[0114] Based on this, the bottom shielding layer 60 can be used to shield the influence of static electricity on the driving transistor in each pixel driving circuit Q. In addition, the bottom shielding layer 60 can also serve as a light shielding layer to reduce the influence of external light incident from the substrate 10 side on the pixel driving circuit Q.

[0115] In some examples, as shown in combination with Figures 4 and 9, the positive projection of the driving transistor in the pixel driving circuit Q on the substrate 10 is located within the boundary of the positive projection of the bottom shielding layer 60 on the substrate 10, so that the bottom shield 60 can completely cover the driving transistor to shield the influence of static electricity on the driving transistor.

[0116] In addition, the two shielding patterns 61 corresponding to two adjacent pixel driving circuits Q can be electrically connected via the conductive portion 63 , thereby reducing the impedance of the bottom shielding layer 60 .

[0117] In some examples, the bottom shielding layer 60 is configured to receive a first power signal, thereby reducing static electricity accumulation on the bottom shielding layer 60 .

[0118] In some examples, the pixel driving circuit Q is electrically connected to the first signal lines 31 and the second signal lines 32 and is also electrically connected to a first power signal line configured to provide the pixel driving circuit Q with a first power signal.

[0119] When the pixel driving circuit Q is in the light-emitting stage, the constant voltage power signal provided by the first power signal line can flow through the driving transistor to the anode of the light-emitting device O (as shown in FIG3 ), and the cathode of the light-emitting device O can be electrically connected to the second power signal line, thereby driving the light-emitting device O to emit light. The first power signal line can be a high power signal line, and the second power signal line can be a low power signal line. The voltage value of the second power signal provided by the second power signal line is less than the voltage value of the first power signal provided by the first power signal line.

[0120] Based on this, the bottom shielding layer 60 can be electrically connected to the first power signal line. Furthermore, there is no need to provide a separate signal line in the driver circuit layer 20 to provide the first power signal to the bottom shielding layer 60. This can save space in the driver circuit layer 20 and facilitate the flexible arrangement of other wiring in the subsequent driver circuit layer 20.

[0121] Because the multiple pixel driving circuits Q in the driving circuit layer 20 are all disposed in the display area AA and not within the opening area W2, the bottom shielding layer 60 also needs to have an opening avoidance area 62. The opening area W2 is located within the boundary of the opening area 62. Therefore, the multiple shielding patterns 61 in the bottom shielding layer 60 need to be truncated within the opening avoidance area 62. In other words, the multiple shielding patterns 61 in the bottom shielding layer 60 need to be disposed around the opening area W2.

[0122] However, since the side of the multiple shielding patterns 61 arranged around the opening area W2 is not connected to other structures near the opening area W2, the side of the partial shielding pattern 61 near the opening area W2 is in a suspended state. Based on this, the electrostatic charge will be concentrated on the side of the partial shielding pattern 61 near the opening area W2 to form a concave-convex structure (similar to the shape of a tip discharge). When the accumulated electrostatic energy is too large, according to the law of tip discharge, the static electricity will be preferentially discharged through the tip. As a result, the side of the partial shielding pattern 61 near the opening area W2 is prone to form a tip discharge phenomenon, which is easy to damage the pixel driving circuit Q near the opening area W2, thereby reducing the quality of the array substrate 100.

[0123] In some embodiments, as shown in FIG. 9 , the bottom shielding layer 60 further includes a conductive connecting portion 64 , which is used to connect the constant voltage conductive ring 40 and a plurality of shielding patterns 61 adjacent to the opening area W2 .

[0124] In the driver circuit layer 20, the transistors in the pixel driver circuit Q need to be electrically connected to other transistors, or some transistors also need to be electrically connected to the signal line 30. The above electrical connection can generally be achieved through vias. Furthermore, the driver circuit layer 20 will include multiple connecting through holes F.

[0125] The orthographic projection of the conductive connection portion 64 on the substrate 10 is set to not overlap with the orthographic projection of the connecting through hole F on the substrate 10 to prevent external moisture from entering the interior of the driving circuit layer 20 through the connecting through hole F, thereby affecting the lifespan of the bottom shielding layer 60 and the conductive connection portion 64 and other structures, and causing the problem of growing dark spots (GDS).

[0126] In some examples, the connection via F may include a first connection via F1 , wherein the first connection via F1 is a via located in an interlayer dielectric layer between the gate metal layer and the routing metal layer.

[0127] In some examples, the connecting through hole F may also be a second connecting through hole F2. When the pixel driving circuit Q includes an Indium Gallium Zinc Oxide (IGZO) transistor, the second connecting through hole F2 may be a through hole connecting the IGZO transistor and the signal line.

[0128] In some embodiments, as shown in FIG. 9 , a minimum distance between an orthographic projection of the conductive connection portion 64 on the substrate 10 and an orthographic projection of the connection through hole F on the substrate 10 is greater than or equal to 3 μm.

[0129] When the minimum distance between the orthographic projection of the conductive connection portion 64 on the substrate 10 and the orthographic projection of the connection through hole F on the substrate 10 is equal to or close to 3 μm, the distance between the conductive connection portion 64 and the connection through hole F can be guaranteed, thereby improving the problem of poor GDS. It can also prevent the distance between the conductive connection portion 64 and the connection through hole F from being too large, thereby occupying too much space on the array substrate 100 and affecting the layout flexibility of the array substrate 100.

[0130] In some examples, a minimum distance between an orthographic projection of the conductive connection portion 64 on the substrate 10 and an orthographic projection of the connecting through hole F on the substrate 10 is greater than or equal to 5 μm.

[0131] When the minimum distance between the orthographic projection of the conductive connection portion 64 on the substrate 10 and the orthographic projection of the connection through hole F on the substrate 10 is equal to or close to 5 μm, the GDS defect problem can be improved and the layout requirements of the array substrate 100 can be met.

[0132] For example, the minimum distance between the orthographic projection of the conductive connection portion 64 on the substrate 10 and the orthographic projection of the connection through hole F on the substrate 10 is about 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm. However, the present disclosure is not limited thereto.

[0133] Taking the example of a minimum distance of about 3 μm between the orthographic projection of the conductive connection portion 64 on the substrate 10 and the orthographic projection of the connecting through hole F on the substrate 10 , this can not only improve the problem of poor GDS, but also meet the layout requirements of the array substrate 100 .

[0134] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the minimum spacing between the orthographic projection of the conductive connection part 64 on the substrate 10 and the orthographic projection of the connecting through hole F on the substrate 10 floats within the range of 10%×3μm, it can also be considered that the minimum spacing between the orthographic projection of the conductive connection part 64 on the substrate 10 and the orthographic projection of the connecting through hole F on the substrate 10 satisfies and is equal to 3μm.

[0135] Based on this, the driving circuit layer 20 in the array substrate 100 provided in the embodiment of the present disclosure further includes a constant voltage conductive ring 40 . The constant voltage conductive ring 40 is located in the opening peripheral area S1 and is disposed around the opening area W2 .

[0136] In this configuration, as shown in Figures 4 and 9 , the constant-voltage conductive ring 40 is a closed shape. Positioned between the aperture area W2 and the display area AA, the constant-voltage conductive ring 40 absorbs and disperses static electricity from the drive circuit layer 20 on the side of the display area AA near the aperture area W2. Furthermore, the constant-voltage conductive ring 40 prevents excessive static energy from accumulating at a specific location, thereby improving the quality of the array substrate 100.

[0137] In some embodiments, the constant voltage conductive ring 40 is electrically connected to the bottom shielding layer 60. This is equivalent to using the annular constant voltage conductive ring 40 to connect in series the multiple shielding patterns 61 arranged around the edge of the opening area W2. The constant voltage conductive ring 40 can be used to destroy the concave and convex structure formed by the multiple shielding patterns 61 arranged around the edge of the opening area W2. Static electricity concentrated on the side of the shielding patterns 61 near the opening area W2 is dispersed to the constant voltage conductive ring 40, thereby improving the problem of tip discharge on the side of the shielding patterns 61 near the opening area W2. This is conducive to improving the quality of the array substrate 100.

[0138] In some examples, the constant-voltage conductive ring 40 and the bottom shielding layer 60 are on the same layer, so that the constant-voltage conductive ring 40 is in contact with and connected to the bottom shielding layer 60 .

[0139] With this arrangement, no other conductive structure is required to electrically connect the constant-voltage conductive ring 40 and the bottom shielding layer 60, thereby simplifying the wiring layout of the array substrate 100. Furthermore, because the constant-voltage conductive ring 40 and the bottom shielding layer 60 are on the same layer, they can be formed through a single patterning process, which helps simplify the manufacturing process of the array substrate 100.

[0140] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0141] In some examples, the constant voltage conductive ring 40 is electrically connected to the bottom shielding layer 60 , and a first power signal line can be connected to the constant voltage conductive ring 40 through a via, so that the first power signal line transmits the first power signal to the constant voltage conductive ring 40 and the bottom shielding layer 60 .

[0142] The first portion of the constant-voltage conductive ring 40 is electrically connected to the first power signal line through a via. The width of the first portion of the constant-voltage conductive ring 40 can be widened. The width of the first portion of the constant-voltage conductive ring 40 can be set to be greater than the width of other portions of the constant-voltage conductive ring 40. This facilitates the electrical connection of the constant-voltage conductive ring 40 to the first power signal line through the via.

[0143] In some examples, the width of the constant voltage conductive ring 40 ranges from 8 μm to 20 μm.

[0144] When the width of the constant-voltage conductive ring 40 is equal to or close to 8 μm, the narrower width of the constant-voltage conductive ring 40 can reduce the space it occupies in the opening peripheral area S1, thereby reducing the area of ​​the opening peripheral area S1. Furthermore, the constant-voltage conductive ring 40 can also be used to connect multiple shielding patterns 61 arranged around the edge of the opening area W2, thereby improving the problem of tip discharge on the side of the shielding patterns 61 near the opening area W2.

[0145] When the width of the constant-voltage conductive ring 40 is equal to or close to 20 μm, the wider width of the constant-voltage conductive ring 40 can better connect the multiple shielding patterns 61 arranged around the edge of the opening area W2, thereby connecting the concave-convex structure formed by them into a closed pattern. This reduces the problem of tip discharge on the side of the shielding pattern 61 near the opening area W2. In addition, the constant-voltage conductive ring 40 can also meet the size requirements of the opening peripheral area S1.

[0146] In other examples, the width of the constant voltage conductive ring 40 ranges from 10 μm to 20 μm.

[0147] When the ring width of the constant voltage conductive ring 40 is within the range of 10 μm to 20 μm, the constant voltage conductive ring 40 can not only improve the electrostatic breakdown problem on the side of the display area AA close to the opening area W2 , but also meet the size requirements of the opening peripheral area S1 .

[0148] For example, the width of the constant voltage conductive ring 40 is about 10 μm, 12 μm, 15 μm, 18 μm or 20 μm. However, the present disclosure is not limited to this width of the constant voltage conductive ring 40.

[0149] Taking the constant voltage conductive ring 40 with a width of about 10 μm as an example, the constant voltage conductive ring 40 can not only improve the electrostatic breakdown problem on the side of the display area AA close to the opening area W2, but also meet the size requirements of the opening peripheral area S1.

[0150] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the ring width of the constant voltage conductive ring 40 fluctuates within the range of 10%×10μm, it can also be considered that the ring width of the constant voltage conductive ring 40 satisfies the requirement of being equal to 10μm.

[0151] However, the inventors have discovered that, as shown in FIG4 , adding a constant-voltage conductive ring 40 to the array substrate 100 results in different loads on the multiple target signal lines 30A. This, in turn, affects the signals transmitted by the target signal lines 30A, thereby affecting the output signals of the pixel drive circuits Q electrically connected thereto, and thus affecting the brightness of the light-emitting devices O (shown in FIG3 ) in the display panel 200, thereby reducing the display quality of the display panel 200 (shown in FIG3 ).

[0152] As shown in Figures 4 to 8, the winding portions L2 of multiple target signal lines 30A are all located in the opening peripheral area S1 and are arranged around the opening area W2. The starting points of the winding portions L2 of the target signal lines 30A are different. Among the multiple winding portions L2 at the position N3 in the opening peripheral area S1, the farther the winding portion L2 is from the hole area W2, the greater the degree of curvature, which will cause the structure composed of the multiple winding portions L2 to not be a regular circle. In other words, the structure composed of the multiple winding portions L2 may be elliptical. However, the constant voltage conductive ring 40 is arranged around the opening area W2, and the shape of the constant voltage conductive ring 40 is generally circular.

[0153] Based on this, the multiple winding portions L2 at the position N3 in the aperture peripheral area S1 protrude from the constant-voltage conductive ring 40. Consequently, the orthographic projections of the multiple target signal lines 30A on the substrate 10 and the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 overlap in different areas, resulting in different loads on different target signal lines 30A.

[0154] Specifically, at the location of the aperture perimeter area S1 shown in Figures 6 and 7 , the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 overlaps with the orthographic projections of the lead portions L1 of some target signal lines 30A on the substrate 10. The area of ​​the overlapping region is roughly the product of the width of the constant-voltage conductive ring 40 along the direction in which the lead portions L1 extend, and the width of the lead portions L1 in the direction in which the multiple lead portions L1 are arranged. However, at the location of the aperture perimeter area S1 shown in Figure 8 , the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 overlaps with the orthographic projections of the winding portions L2 of other target signal lines 30A on the substrate 10, and the areas of the overlapping regions are different.

[0155] Although the areas of the overlapping regions formed by the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 and the orthographic projection of the target signal line 30A on the substrate 10 at the locations of the aperture perimeter area S1 shown in Figures 6 and 7 are approximately equal, the areas of the overlapping regions formed by the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 and the orthographic projection of the target signal line 30A on the substrate 10 at the locations of the aperture perimeter area S1 shown in Figures 6 and 7 and the locations of the aperture perimeter area S1 shown in Figure 8 are significantly different. Furthermore, at the locations of the aperture perimeter area S1 shown in Figure 8, the areas of the overlapping regions formed by the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 and the orthographic projections of the multiple target signal lines 30A on the substrate 10 are also different.

[0156] As can be seen, the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 not only overlaps with the winding portion L2 at a certain location but also overlaps with the winding portion L2 at different locations. As a result, the parasitic capacitances formed between the constant-voltage conductive ring 40 and different target signal lines 30A vary, resulting in different loads on different target signal lines 30A. This affects the signals transmitted by the target signal lines 30A and degrades the display quality of the display panel 200 (as shown in FIG. 3 ).

[0157] Figure 10 is a structural diagram of an array substrate according to some embodiments, and Figure 11 is a partial enlarged view of N3 in Figure 10. The enlarged view of position N1 in Figure 10 can refer to the structure of M1 in Figure 4 shown in Figure 6, and the enlarged view of position N2 in Figure 10 can refer to the structure of M2 in Figure 4 shown in Figure 7.

[0158] Based on this, in the array substrate 100 provided in the embodiment of the present disclosure, in combination with Figures 10 and 11, and in combination with Figures 6 and 7, it is arranged that in the direction along the display area AA pointing to the opening area W2, the orthographic projection of the winding portion L2 on the substrate 10 is located between the orthographic projection of the constant voltage conductive ring 40 on the substrate 10 and the opening area W2.

[0159] This is equivalent to adjusting the shape of the constant voltage conductive ring 40 so that the shape of the constant voltage conductive ring 40 corresponds to the shape of the structure composed of the multiple winding parts L2, so that the constant voltage conductive ring 40 avoids the multiple winding parts L2, and the constant voltage conductive ring 40 is arranged around the edge of the structure composed of the multiple winding parts L2. For example, when the shape of the structure composed of the multiple winding parts L2 is roughly elliptical, the shape of the constant voltage conductive ring 40 can also be an elliptical ring. It should be noted that the "elliptical ring" can be a hollow ellipse.

[0160] Furthermore, the orthographic projection of the constant voltage conductive ring 40 on the substrate 10 can be made to have no overlap with the orthographic projection of the winding portion L2 on the substrate 10, and the orthographic projection of the constant voltage conductive ring 40 on the substrate 10 can overlap with the orthographic projection of the lead portion L1 on the substrate 10.

[0161] Thus, the difference in the area of ​​the overlapping region formed by the orthographic projection of the multiple winding portions L2 on the substrate 10 and the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 can be reduced, thereby reducing the difference in parasitic capacitance formed between the multiple target signal lines 30A and the constant-voltage conductive ring 40. This alleviates the problem of different loads on the multiple target signal lines 30A, thereby improving the display effect of the display panel 200.

[0162] In summary, a constant voltage conductive ring 40 can be added to the driving circuit layer 20 of the array substrate 100 of the present disclosure to improve the problem of static electricity accumulation on the side of the display area AA of the array substrate 100 close to the opening area W2 by using the constant voltage conductive ring 40, so as to improve the quality of the array substrate 100. In addition, the winding portion L2 is arranged along the edge of the structure composed of multiple winding portions L2, so that the winding portion L2 is located between the constant voltage conductive ring 40 and the opening area W2. The problem of different loads on multiple target signal lines 30A caused by the difference in the area of ​​the overlapping area formed by the orthographic projection of the multiple winding portions L2 on the substrate 10 and the orthographic projection of the constant voltage conductive ring 40 on the substrate 10 is improved. Furthermore, it is beneficial to improve the display effect of the display panel 200.

[0163] In some embodiments, as shown in conjunction with FIG10 and FIG11 , and in conjunction with FIG6 and FIG7 , the portion where the orthographic projection of the lead portion L1 on the substrate 10 overlaps with the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 is a first overlapping portion E1. The areas of the first overlapping portions E1 of the plurality of lead portions L1 are substantially equal.

[0164] When the orthographic projection of the constant voltage conductive ring 40 on the substrate 10 does not overlap with the orthographic projection of the winding portion L2 on the substrate 10, and the orthographic projection of the constant voltage conductive ring 40 on the substrate 10 overlaps with the orthographic projection of the lead portion L1 on the substrate 10: the area of ​​the region formed by the overlap of the orthographic projection of the constant voltage conductive ring 40 on the substrate 10 and the orthographic projection of the lead portion L1 of the target signal line 30A on the substrate 10 is approximately the product of the width of the constant voltage conductive ring 40 in the direction in which the lead portion L1 extends and the line width of the lead portion L1 in the direction in which the multiple lead portions L1 are arranged.

[0165] The width of the constant-voltage conductive ring 40 along the direction in which the lead portion L1 extends is substantially equal to the ring width of the constant-voltage conductive ring 40. In other words, the area of ​​the region formed by the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 and the orthographic projection of the lead portion L1 of each target signal line 30A on the substrate 10, which overlaps with each other, is substantially equal to the product of the ring width of the constant-voltage conductive ring 40 and the line width of the lead portion L1.

[0166] Based on this, the area of ​​the first overlapping portions E1 of the multiple lead portions L1 is approximately the product of the ring width of the constant voltage conductive ring 40 and the line width of the lead portion L1. Since the ring width of the constant voltage conductive ring 40 and the line width of the lead portion L1 are constant, the areas of the first overlapping portions E1 of the multiple lead portions L1 can be approximately equal.

[0167] Furthermore, the parasitic capacitances formed between the multiple target signal lines 30A and the constant voltage conductive ring 40 can be made substantially equal, so that the loads of the multiple target signal lines 30A are substantially equal, which is beneficial to improving the display effect of the display panel 200 .

[0168] It should be noted that, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the difference between the areas of the first overlapping portions E1 of any two lead portions L1 fluctuates within 10% of the area of ​​the first overlapping portion E1 of any one of the two lead portions L1, the areas of the first overlapping portions E1 of the two lead portions L1 can also be considered to be equal.

[0169] When the shape of the constant-voltage conductive ring 40 is adjusted so that the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 does not overlap with the orthographic projection of the winding portion L2 on the substrate 10, and the orthographic projection of the constant-voltage conductive ring 40 on the substrate 10 overlaps with the orthographic projection of the lead portion L1 on the substrate 10, the size of the constant-voltage conductive ring 40 is increased to a certain extent. As shown in FIG. 9 , this is equivalent to stretching the constant-voltage conductive ring 40 along the second direction Y.

[0170] Figure 12 is a partial enlarged view of K in Figure 11. Figure 12 schematically illustrates the first conductive connection portion 641 and the constant voltage conductive ring 40 at the position K in Figure 11, so as to clearly observe how the first conductive connection portion 641 and the constant voltage conductive ring 40 are connected.

[0171] Based on this, in some embodiments, as shown in Figures 11 and 12 , the conductive connection portion 64 and the constant voltage conductive ring 40 are on the same layer. The conductive connection portion 64 includes a first conductive connection portion 641 that intersects with the constant voltage conductive ring 40 to achieve a connection between the conductive connection portion 64 and the constant voltage conductive ring 40.

[0172] This arrangement can reduce the space occupied by the conductive connection portion 64 and the constant voltage conductive ring 40 in the aperture peripheral area S1. This helps reduce the distance between the constant voltage conductive ring and the first shielding pattern 61 (as shown in FIG9 ). Furthermore, it helps reduce the distance between the constant voltage conductive ring and the display area AA, facilitating a reduction in the size of the aperture peripheral area S1.

[0173] However, the first conductive connection portion 641 intersects the constant-voltage conductive ring 40 to form a first acute angle θ, and the first conductive connection portion 641 intersects the constant-voltage conductive ring 40 to form a first space R1.

[0174] The inventors have discovered that the problem of tip discharge is prone to occur between the first conductive connection part 641 and the constant voltage conductive ring 40 in the first space R1. Specifically, since the conductive connection part 64 and the constant voltage conductive ring 40 are on the same layer, the conductive connection part 64 and the constant voltage conductive ring 40 are of an integrated design. However, the first conductive connection part 641 intersects with the constant voltage conductive ring 40 to form a first acute angle θ, which forms a tip structure in the corresponding first space R1. Due to the existence of this tip structure, the static electricity in the conductive connection part 64 and the constant voltage conductive ring 40 will be concentrated on the tip structure. This can easily lead to the problem of tip discharge in the first space R1.

[0175] Based on this, as shown in Figures 11 and 12 , the driving circuit layer 20 can also include a first compensation portion 70, which is placed on the same layer as the constant-voltage conductive ring 40. The first compensation portion 70 is located within the first space R1, and the first compensation portion 70 intersects with the first conductive connection portion 641 to form a first angle α1, and the first compensation portion 70 intersects with the constant-voltage conductive ring 40 to form a second angle α2. Both the first angle α1 and the second angle α2 are greater than or equal to 90°.

[0176] As shown above, a first compensating portion 70 is added to the driving circuit layer 20, on the same layer as the conductive connecting portion 64 and the constant-voltage conductive ring 40. The first compensating portion 70 fills the first space R1. Specifically, the first compensating portion 70 is placed at the location of the spike structure within the first space R1 to disrupt the spike structure formed by the intersection of the first conductive connecting portion 641 and the constant-voltage conductive ring 40. This can alleviate the problem of spike discharge within the first space R1 using the first compensating portion 70.

[0177] In some examples, the first compensation portion 70 may be shaped like a triangle. "Triangle-like" may be understood as meaning that the sides of the triangle adjacent to the first conductive connection portion 641 are aligned with the edges of the first conductive connection portion 641. That is, the sides of the triangle adjacent to the first conductive connection portion 641 can completely fit with the edges of the first conductive connection portion 641. Furthermore, the sides of the triangle adjacent to the constant-voltage conductive ring 40 are aligned with the edges of the constant-voltage conductive ring 40. That is, the sides of the triangle adjacent to the constant-voltage conductive ring 40 can completely fit with the edges of the constant-voltage conductive ring 40.

[0178] In some examples, along the circumference of the constant voltage conductive ring 40 , the length of the first compensation portion 70 ranges from 2.5 μm to 20 μm.

[0179] When the length of the first compensating portion 70 is within the range of 2.5 μm to 20 μm, the first compensating portion 70 can fill the position of the sharp structure in the first space R1 and destroy the sharp structure formed by the intersection of the first conductive connecting portion 641 and the constant voltage conductive ring 40, thereby improving the problem of sharp discharge in the first space R1. It can also prevent the first compensating portion 70 from being too long, resulting in excessive space occupied by the array substrate 100 and affecting the layout flexibility of the array substrate 100.

[0180] In other examples, along the circumference of the constant-voltage conductive ring 40 , the length of the first compensation portion 70 ranges from 5 μm to 10 μm.

[0181] When the length of the first compensation portion 70 is within the range of 5 μm to 10 μm, the first compensation portion 70 can not only improve the problem of tip discharge in the first space R1 , but also meet the layout requirements of the array substrate 100 .

[0182] For example, the length of the first compensation portion 70 is approximately 2.5 μm, 4 μm, 5 μm, 8 μm, 10 μm, 15 μm, 18 μm, or 20 μm, but the present disclosure is not limited thereto.

[0183] Taking the length of the first compensation portion 70 of about 5 μm as an example, the first compensation portion 70 can not only improve the problem of tip discharge in the first space R1 , but also meet the layout requirements of the array substrate 100 .

[0184] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the length of the first compensation part 70 fluctuates within the range of 10%×5μm, it can also be considered that the length of the first compensation part 70 satisfies the requirement of being equal to 5μm.

[0185] In other embodiments, the first conductive connection portion 641 may be directly connected to the constant voltage conductive ring 40. That is, the first conductive connection portion 641 is connected to the edge of the constant voltage conductive ring 40 close to the opening area W2 and away from the opening area W2.

[0186] At this time, the conductive connecting portion 64 and the constant-voltage conductive ring 40 do not form a relatively obvious tip structure, which can prevent the problem of electrostatic breakdown at the connection position between the conductive connecting portion 64 and the constant-voltage conductive ring 40.

[0187] In some other embodiments, when there is sufficient space in the opening peripheral area S1 , the end of the conductive connection portion 64 close to the opening area W2 may be arranged to directly contact and connect with the constant voltage conductive ring 40 .

[0188] At this time, the conductive connecting portion 64 and the constant-voltage conductive ring 40 do not form a relatively obvious tip structure, which can prevent the problem of electrostatic breakdown at the connection position between the conductive connecting portion 64 and the constant-voltage conductive ring 40.

[0189] The above mainly introduces the structures of the constant voltage conductive ring 40 and the bottom shielding layer 60 . The following will introduce the types of multiple target signal lines 30A and how to layout them in the via peripheral area S1 in conjunction with relevant drawings.

[0190] In some embodiments, as shown in FIG10 , the winding portions L2 of the plurality of target signal lines 30A surround the opening area W2 and are located in the opening peripheral area S1. If the winding portions L2 of the plurality of target signal lines 30A are all disposed in the opening peripheral area S1 located on one side of the opening area W2, the size of the opening peripheral area S1 will be increased, thereby reducing the display quality of the display panel 200.

[0191] Based on this, the plurality of target signal lines 30A can be divided into a first portion of target signal lines and a second portion of target signal lines. Along the direction in which the plurality of target signal lines 30A are arranged, the winding portion L2 of the first portion of target signal lines and the winding portion L2 of the second portion of target signal lines are respectively located on both sides of the opening area W2.

[0192] This arrangement allows the winding portions L2 of the plurality of target signal lines 30A to be dispersed within the aperture peripheral regions S1 on both sides of the aperture region W2, thereby preventing an excessive number of winding portions L2 within the aperture peripheral region S1 on one side of the aperture region W2. This helps reduce the size of the aperture peripheral region S1 and improves the display quality of the display panel 200.

[0193] In some embodiments, as shown in FIG. 10 , the plurality of target signal lines 30A include a plurality of first signal lines 31 . The lead portions L1 of the plurality of first signal lines 31 extend along the first direction X and are arranged in the second direction Y.

[0194] The plurality of first signal lines 31 in the plurality of target signal lines 30A can be divided into a first portion of signal lines 311 and a second portion of signal lines 312. Along the second direction Y, the winding portion L2 of the first portion of signal lines 311 and the winding portion L2 of the second portion of signal lines 312 are respectively disposed within the opening peripheral area S1 on both sides of the opening area W2.

[0195] Based on this, the winding portions L2 of the plurality of first signal lines 31 corresponding to the opening area W2 can be dispersed in the opening peripheral area S1 on both sides of the opening area W2, which is beneficial to reducing the size of the opening peripheral area S1.

[0196] In some examples, the number of the first portion of signal lines 311 and the number of the second portion of signal lines 312 are substantially equal.

[0197] This arrangement allows the winding portions L2 of the plurality of first signal lines 31 in the plurality of target signal lines 30A to be evenly distributed within the aperture peripheral area S1 on both sides of the aperture area W2. This not only facilitates the layout of the plurality of winding portions L2 within the aperture peripheral area S1, but also further reduces the size of the aperture peripheral area S1, thereby improving the display quality of the display panel.

[0198] It should be noted that, since the number of the multiple first signal lines 31 is not necessarily an even number, or due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the difference between the number of the first part signal lines 311 and the number of the second part signal lines 312 fluctuates within 10% of the total number of the first part signal lines 311 or the total number of the second part signal lines 312, it can also be considered that the number of the first part signal lines 311 and the number of the second part signal lines 312 are equal.

[0199] FIG13 is a cross-sectional view taken along line II' in FIG10 .

[0200] In some embodiments, as shown in conjunction with FIG10 and FIG13 , the driving circuit layer 20 includes a plurality of metal conductive layers 21 stacked on the substrate 10. In a direction away from the substrate 10, the plurality of metal conductive layers 21 are respectively a first gate metal layer Gate1, a second gate metal layer Gate2, a first routing metal layer SD1, and a second routing metal layer SD2.

[0201] The first gate metal layer Gate1 may include a portion of the plurality of first signal lines 31 , and the second gate metal layer Gate2 may include another portion of the plurality of first signal lines 31 .

[0202] That is, the multiple first signal lines 31 are dispersed and formed in different metal conductive layers 21. This prevents short circuits that can occur when multiple first signal lines 31 are located on the same layer due to the limited space in the aperture peripheral area S1. This facilitates the layout of the first signal lines 31 in the aperture peripheral area S1, improving the quality of the array substrate 100. Furthermore, this arrangement reduces the space occupied by the winding portions L2 of the multiple target signal lines 30A in the aperture peripheral area S1, thereby reducing the size of the aperture peripheral area S1.

[0203] In some examples, when the plurality of metal conductive layers 21 further include a third metal layer, the plurality of first signal lines 31 may be disposed on the first gate metal layer Gate1, the second gate metal layer Gate2, and the third metal layer, respectively, to facilitate a better layout of the first signal lines 31 and reduce the size of the aperture peripheral area S1.

[0204] In some examples, along the second direction, among two adjacent first signal lines 31 projected on the substrate 10 , one first signal line 31 is located in the first gate metal layer Gate, and the other first signal line 31 is located in the second gate metal layer Gate2.

[0205] This arrangement increases the distance between two adjacent first signal lines 31 in the same metal conductive layer 21, thereby preventing short circuits between the two adjacent first signal lines 31 in the same metal conductive layer 21. Furthermore, since the distance between two adjacent first signal lines 31 in the same metal conductive layer 21 is increased, crosstalk between the two first signal lines 31 can be reduced, thereby improving the quality of the array substrate 100.

[0206] In some examples, a plurality of first signal lines 31 are dispersedly formed on the basis of different metal conductive layers 21 , and a gap exists between orthographic projections of two adjacent first signal lines 31 on the substrate 10 .

[0207] Such an arrangement is equivalent to staggering the first signal lines 31 located on different metal conductive layers 21, which can increase the distance between two adjacent first signal lines 31 projected on the substrate 10 along the second direction, reduce the mutual crosstalk between the two first signal lines 31, and improve the quality of the array substrate 100.

[0208] In some embodiments, as shown in FIG. 10 , the plurality of target signal lines 30A include a plurality of second signal lines 32 , the lead portions L1 of the plurality of second signal lines 32 extend along the second direction Y, and are arranged in the first direction X.

[0209] The plurality of second signal lines 32 can be divided into a third portion of signal lines 321 and a fourth portion of signal lines 322. Along the first direction X, the winding portion L2 of the third portion of signal lines 321 and the winding portion L2 of the fourth portion of signal lines 322 are respectively disposed in the opening peripheral area S1 on both sides of the opening area W2.

[0210] Based on this, the winding portions L2 of the plurality of second signal lines 32 can be dispersed in the opening peripheral area S1 on both sides of the opening area W2 , which is beneficial for reducing the size of the opening peripheral area S1 .

[0211] In some examples, the number of the third portion of signal lines 321 is substantially equal to the number of the fourth portion of signal lines 322 .

[0212] This arrangement allows the winding portions L2 of the plurality of second signal lines 32 in the plurality of target signal lines 30A to be evenly distributed within the aperture peripheral area S1 on both sides of the aperture area W2. This not only facilitates the layout of the plurality of winding portions L2 within the aperture peripheral area S1, but also further reduces the size of the aperture peripheral area S1, thereby improving the display quality of the display panel.

[0213] It should be noted that, since the number of the plurality of second signal lines 32 is not necessarily an even number, or, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the difference between the number of the third part signal lines 321 and the number of the fourth part signal lines 322 fluctuates within 10% of the total number of the third part signal lines 321 or the total number of the fourth part signal lines 322, it can also be considered that the number of the third part signal lines 321 and the number of the fourth part signal lines 322 are equal.

[0214] In some embodiments, as shown in FIG10 and FIG13 , the second signal line 32 can be a data signal line, and multiple second signal lines 32 can be located in the second routing metal layer SD2. In this case, the winding portions L2 of the multiple second signal lines 32 are located in the same layer, and the multiple winding portions L2 are arranged relatively compactly within the opening peripheral area S1. This not only easily causes crosstalk between adjacent winding portions L2, but also easily leads to short circuits.

[0215] Based on this, the lead portions L1 of the plurality of second signal lines 32 can be all located in the second routing metal layer SD2, while the winding portions L2 of the plurality of second signal lines 32 within the aperture peripheral area S1 can be arranged in different layers. Specifically, the first routing metal layer SD1 can include the winding portions L2 of a portion of the plurality of second signal lines 32, and the second routing metal layer SD2 can include the winding portions L2 of another portion of the plurality of second signal lines 32.

[0216] In this case, the plurality of second signal lines 32 are disposed on the plurality of metal conductive layers 21. This facilitates the layout of the second signal lines 32 in the aperture perimeter area S1, preventing short circuits that would otherwise occur if all second signal lines 32 were located on the same layer. Furthermore, this arrangement reduces the space occupied by the winding portions L2 of the plurality of target signal lines 30A in the aperture perimeter area S1, thereby reducing the size of the aperture perimeter area S1.

[0217] In some examples, along the first direction X, among two second signal lines 32 that are adjacent to each other in orthographic projection on the substrate 10 , one second signal line 32 is located in the first routing metal layer SD1 , and the other second signal line 32 is located in the second routing metal layer SD2 .

[0218] This arrangement increases the distance between two adjacent second signal lines 32 in the same metal conductive layer 21, thereby preventing short circuits between the two adjacent second signal lines 32 in the same metal conductive layer 21. Furthermore, since the distance between two adjacent second signal lines 32 in the same metal conductive layer 21 is increased, crosstalk between the two second signal lines 32 can be reduced, thereby improving the quality of the array substrate 100.

[0219] In some examples, a plurality of second signal lines 32 are dispersedly formed on the basis of different metal conductive layers 21 , and a gap exists between orthographic projections of two adjacent second signal lines 32 on the substrate 10 .

[0220] Such an arrangement is equivalent to staggering the second signal lines 32 located on different metal conductive layers 21, which can increase the distance between two adjacent second signal lines 32 projected on the substrate 10 along the second direction, reduce the mutual crosstalk between the two second signal lines 32, and improve the quality of the array substrate 100.

[0221] The above mainly introduces how to layout the winding portions L2 of multiple target signal lines 30A in the opening peripheral area S. The following will introduce the relevant design of the winding portion L2 structure of multiple target signal lines 30A with reference to relevant drawings.

[0222] The inventors discovered that the side of the outer winding portion L2A near the aperture area W2 has multiple winding portions L2, while the side of the outer winding portion L2A near the display area AA has no other winding portions. Consequently, the side of the outer winding portion L2A near the display area AA is a blank area. Of the multiple winding portions L2, the winding portion L2 farthest from the aperture area W2 in its orthographic projection on the substrate 10 is the outer winding portion L2A.

[0223] Based on this, when forming multiple winding sections L2 through etching, the different density and number of winding sections L2 on either side of the outer winding section L2A can lead to a loading effect during the etching process, resulting in uneven development and etching. Areas with less loading will have a greater amount of etching, leading to reduced line width or even line breakage. In other words, the significant difference in pattern density on either side of the outer winding section L2A can easily cause reduced line width and even line breakage on the outer winding section L2A.

[0224] FIG14 is another partially enlarged view of N3 in FIG10 , and FIG15 is a cross-sectional view taken along line H1 - H1 ′ in FIG14 .

[0225] Based on this, in some embodiments, in combination with Figures 14 and 15, the winding portion L2 farthest from the hole area W2 in the positive projection of the multiple winding portions L2 on the substrate 10 is the outer winding portion L2A, and the remaining winding portions L2 in the multiple winding portions L2 are the first inner winding portion L2B.

[0226] In a direction V from the opening area W2 to the display area AA, a width d1 of the outer winding portion L2A is greater than a width d2 of the first inner winding portion L2B.

[0227] This is equivalent to widening the outer winding portion L2A, so that the widened portion of the outer winding portion L2A can be used to compensate for the problem of narrow line width or even line breakage in the outer winding portion L2A caused by different etching rates on both sides of the outer winding portion L2A, thereby improving the quality of the array substrate 100.

[0228] In some examples, 1.1d2≤d1≤1.15d2. That is, the outer winding portion L2A can be widened by 10% to 15% d2 to achieve a width d1 of the outer winding portion L2A within the range of 1.1d2 to 1.15d2. Based on this, when forming the first inner winding portion L2B with a width of d2 and the outer winding portion L2A with a width of d1, the etching rate at the outer winding portion L2A is faster than the etching rate at the first inner winding portion L2B. As a result, the width of the resulting outer winding portion L2A will be smaller than d1.

[0229] That is, the widened width of 10% to 15% d2 can be used to compensate for the problem of different etching rates. This makes the width of the outer winding portion L2A formed in the end roughly equal to the width d2 of the first inner winding portion L2B. This prevents the problem of the outer winding portion L2A having a narrow line width or even broken lines due to the different etching rates on both sides of the outer winding portion L2A. In addition, widening the outer winding portion L2A by 10% to 15% d2 can also prevent the outer winding portion L2A from being too wide, which would cause the load of the outer winding portion L2A to be different from that of the first inner winding portion L2B.

[0230] In some examples, d1 is approximately equal to 1.3d2.

[0231] When the width d1 of the outer winding portion L2A is approximately equal to 1.3d2, the increased width of 13% d2 can be used to compensate for the difference in etching rates. This ensures that the width of the resulting outer winding portion L2A is roughly equal to the width d2 of the first inner winding portion L2B, thereby alleviating the problem of narrow wire width or even wire breakage in the outer winding portion L2A. Furthermore, this prevents the excessive width of the outer winding portion L2A from affecting load. However, the present disclosure is not limited to this.

[0232] Illustratively, d1 is approximately equal to any one of d2, 1.1d2, 1.2d2, 1.3d2, 1.4d2, or 1.5d2.

[0233] Illustratively, the width d2 of the first inner winding portion L2B is approximately 2.3 μm, and the width d1 of the outer winding portion L2A is approximately 2.6 μm.

[0234] At this time, widening the outer winding portion L2A can not only improve the problem of narrow line width or even wire breakage in the outer winding portion L2A, but also prevent the problem of different loads affecting each winding portion L2.

[0235] The inventors have discovered that due to the different density and number of winding parts L2 on both sides of the outer winding part L2A, not only will the outer winding part L2A be prone to narrow line width or even broken wires, but the load of the outer winding part L2A will also be different from the load of other winding parts L2, affecting the display effect of the display panel.

[0236] FIG16 is another partially enlarged view of N3 in FIG10 , and FIG17 is a cross-sectional view taken along line H2 - H2 ′ in FIG16 .

[0237] Based on this, in some embodiments, another method can be used to simultaneously improve the above two problems. As shown in Figures 16 and 17, the driving circuit layer 20 also includes a dummy winding portion 51. The dummy winding portion 51 is located between the outer winding portion L2A and the display area AA, and the dummy winding portion 51 is on the same layer as the outer winding portion L2.

[0238] Regardless of whether the multiple winding portions L2 are arranged on different layers or the same layer, only the outer winding portion L2A closest to the display area AA along the direction V from the opening area W2 to the display area AA is processed. A dummy winding portion 51 is provided on the side of the outer winding portion L2A closest to the display area AA, and the dummy winding portion 51 is placed on the same layer as the outer winding portion L2.

[0239] In the above structure, since the dummy winding portion 51 is on the same layer as the outer winding portion L2, the dummy winding portion 51 can be used to balance the difference in pattern density on both sides of the outer winding portion L2A, reducing the problem of different etching rates on both sides of the outer winding portion L2A. This prevents the outer winding portion L2 from narrowing the line width or breaking the line, thereby improving the quality of the array substrate 100. In addition, the dummy winding portion 51 can also be used to balance the difference in load between the outer winding portion L2A and the other winding portions L2, thereby improving the display effect of the display panel.

[0240] In addition, the dummy winding portion 51 and the outer winding portion L2A are in the same layer, so that the dummy winding portion 51 and the outer winding portion L2A can be formed through one patterning process, which can simplify the process of the array substrate 100.

[0241] In some examples, the dummy winding portion 51 is located between the outer winding portion L2A and the constant voltage conductive ring 40. This prevents the constant voltage conductive ring 40 from affecting the load of the dummy winding portion 51, thereby affecting the load of the outer winding portion L2, which may again cause the load of the outer winding portion L2A to be different from the load of other winding portions L2.

[0242] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0243] In some embodiments, as shown in Figures 16 and 17 , along the direction V from the opening area W2 toward the display area AA, the spacing C1 between the dummy winding portion 51 and the outer winding portion L2A is substantially equal to the spacing C2 between any two adjacent winding portions L2. This facilitates the simultaneous formation of the dummy winding portion 51 and multiple winding portions L2, simplifying the fabrication of the array substrate 100. Furthermore, this can help reduce the layout complexity of the array substrate 100 and improve the regularity of the array substrate 100.

[0244] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the difference between the spacing C1 between the virtual winding portion 51 and the outer winding portion L2A and the spacing C2 between any two adjacent winding portions L2 fluctuates within the range of 10% C1 or 10% C2, it can also be considered that the spacing C1 between the virtual winding portion 51 and the outer winding portion L2A is equal to the spacing C2 between any two adjacent winding portions L2.

[0245] In some embodiments, as shown in Figures 16 and 17 , along the direction V from the opening area W2 toward the display area AA, the width of the dummy winding portion 51 is equal to the width of the winding portion L2. This facilitates the simultaneous formation of the dummy winding portion 51 and multiple winding portions L2, simplifying the manufacturing of the array substrate 100. Furthermore, this can help reduce the layout difficulty of the array substrate 100 and improve the regularity of the array substrate 100.

[0246] In summary, the dummy winding portion 51, except for not needing to be electrically connected to the pixel driving circuit, can have the same specifications and parameters as the multiple winding portions L2. This facilitates the simultaneous formation of the dummy winding portion 51 and the multiple winding portions L2, simplifies the manufacturing process of the array substrate 100, and improves the regularity of the array substrate 100.

[0247] The inventors have discovered that, because the multiple winding portions L2 are disposed in different layers, taking the example of multiple target signal lines 30A including first signal lines 31, the winding portions L2 of the multiple first signal lines 31 are disposed in the first gate metal layer Gate1 and the second gate metal layer Gate2, respectively. Furthermore, taking the example of multiple target signal lines 30A including second signal lines 32, the winding portions L2 of the multiple second signal lines 32 are disposed in the first routing metal layer SD1 and the second routing metal layer SD2, respectively.

[0248] Based on this, each metal conductive layer 21 provided with a winding portion L2 has an edge winding portion L2C that is farthest from the hole area W2. Each edge winding portion L2C has multiple winding portions L2 on the side close to the opening area W2, while each edge winding portion L2C has no other winding portions on the side close to the display area AA. Furthermore, the side of each edge winding portion L2C close to the display area AA is a blank area. In other words, not only is the outer winding portion L2A prone to the problem of reduced line width or even broken lines, but each edge winding portion L2C is also prone to the problem of reduced line width or even broken lines.

[0249] FIG18 is another partially enlarged view of N3 in FIG10 , and FIG19 is a cross-sectional view taken along line H3 - H3 ' in FIG18 .

[0250] Based on this, in some embodiments, as shown in conjunction with Figures 18 and 19 , among the multiple winding portions L2 located in the same metal conductive layer 21, the winding portion L2 farthest from the aperture area W2 is referred to as the edge winding portion L2C, and the remaining winding portions L2 in the same layer excluding the edge winding portion L2C are referred to as the second inner winding portion L2D. Along the direction V from the aperture area W2 toward the display area AA, the width d1 of the edge winding portion L2C is greater than the width d2 of the winding portion L2.

[0251] The difference from the array substrate 100 shown in FIG. 14 and FIG. 15 is that not only the outer winding portion L2A is widened, but also the edge winding portion L2C closest to the display area AA in each metal conductive layer 21 is widened.

[0252] This configuration can utilize the widened edge winding portion L2C to compensate for the problem of narrow line width or even line breakage of the edge winding portion L2C caused by different etching rates on both sides of the edge winding portion L2C, thereby improving the quality of the array substrate 100.

[0253] In some examples, 1.1d2≤d1≤1.15d2. That is, each edge winding portion L2C can be widened by 10% to 15% d2 to achieve a width d1 of each edge winding portion L2C that satisfies the range of 1.1d2 to 1.15d2. Based on this, when forming the second inner winding portion L2D with a width of d2 and each edge winding portion L2C with a width of d1 in the same metal conductive layer 21, since the etching rate at the edge winding portion L2C is faster than the etching rate at the second inner winding portion L2D, the width of each edge winding portion L2C finally formed will be smaller than d1.

[0254] In other words, the increased width d2, by 10% to 15%, can be used to compensate for the varying etching rates. This ensures that the width of each edge winding portion L2C is approximately equal to the width d2 of the second inner winding portion L2D on the same layer. This prevents the narrowing or even breakage of each edge winding portion L2C caused by the varying etching rates on both sides of the edge winding portion L2C.

[0255] In addition, widening each edge winding portion L2C by 10% to 15% d2 can also prevent the width of each edge winding portion L2C from being too wide, which would cause the load of each edge winding portion L2C to be different from the load of the second inner winding portion L2D arranged on the same layer.

[0256] In some examples, d1 is approximately equal to 1.3d2.

[0257] When the width d1 of each edge winding portion L2C is approximately equal to 1.3d2, the increased width of 13% d2 can be used to compensate for the varying etching rates. This ensures that the width of each edge winding portion L2C is roughly equal to the width d2 of the second inner winding portion L2D, thereby alleviating the problem of narrow line widths or even line breakage in each edge winding portion L2C. Furthermore, this prevents the excessive width of each edge winding portion L2C from affecting load. However, the present disclosure is not limited to this.

[0258] Illustratively, d1 is approximately equal to any one of d2, 1.1d2, 1.2d2, 1.3d2, 1.4d2, or 1.5d2.

[0259] Illustratively, the width d2 of the second inner winding portion L2D is approximately 2.3 μm, and the width d1 of each edge winding portion L2C is approximately 2.6 μm.

[0260] At this time, widening each edge winding portion L2C can not only improve the problem of narrow line width or even wire breakage in each edge winding portion L2C, but also prevent the problem of different loads affecting each winding portion L2.

[0261] The inventors have discovered that due to the different density and number of winding parts L2 on both sides of each edge winding part L2C, not only will the edge winding part L2C be prone to narrow line width or even broken wires, but the load of the edge winding part L2C will also be different from the load of other winding parts L2, affecting the display effect of the display panel.

[0262] FIG20 is another partially enlarged view of N3 in FIG10 , and FIG21 is a cross-sectional view taken along line H4 - H4 ′ in FIG20 .

[0263] Based on this, in some embodiments, another method can be used to simultaneously improve the above two problems. As shown in Figures 20 and 21, among the multiple winding portions L2 located in the same metal conductive layer 21, the winding portion L2 farthest from the hole area W2 is the edge winding portion L2C. A virtual winding portion 51 can be set to correspond to the edge winding portion L2C one by one. The virtual winding portion 51 is located between the edge winding portion L2C and the display area AA, and the virtual winding portion 51 is on the same layer as the corresponding edge winding portion L2C.

[0264] The difference from the array substrate 100 shown in FIG18 and FIG19 is that not only the outer winding portion L2A closest to the display area AA in the direction from the display area AA to the opening area W2 is processed, but also the edge winding portion L2C closest to the display area AA in each metal conductive layer 21 is processed accordingly.

[0265] As shown in the above structure, since the virtual winding portion 51 corresponds to the edge winding portion L2C one-to-one, the virtual winding portion 51 can be used to balance the difference in pattern density on both sides of the edge winding portion L2C in each metal conductive layer 21 provided with the winding portion L2, thereby reducing the problem of different etching rates on both sides of each edge winding portion L2C. This prevents any edge winding portion L2C from having a narrowed line width or broken line, thereby improving the quality of the array substrate 100. In addition, the virtual winding portion 51 can also be used to balance the difference in load between each edge winding portion L2C and the load of other winding portions L2, thereby improving the display effect of the display panel.

[0266] In addition, the dummy winding portion 51 and the edge winding portion L2C are in the same layer, so that the dummy winding portion 51 and the edge winding portion L2C can be formed through one patterning process, which can simplify the manufacturing process of the array substrate 100 .

[0267] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0268] In some embodiments, as shown in Figures 20 and 21 , along the direction V from the opening area W2 toward the display area AA, the spacing C1 between the dummy winding portion 51 and its adjacent edge winding portion L2C is substantially equal to the spacing C2 between any two adjacent winding portions L2. This facilitates the simultaneous formation of the dummy winding portion 51 and multiple winding portions L2, simplifying the fabrication of the array substrate 100. Furthermore, this can help reduce the layout complexity of the array substrate 100 and improve the regularity of the array substrate 100.

[0269] In addition, along the direction V from the opening area W2 to the display area AA, the distance between two adjacent virtual winding portions 51 is substantially equal to the distance C2 between any two adjacent winding portions L2.

[0270] It is more convenient to form the dummy winding portion 51 and the plurality of winding portions L2 at the same time, thereby simplifying the manufacturing difficulty of the array substrate 100 and improving the regularity of the array substrate 100 .

[0271] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the difference between the spacing C1 between the virtual winding portion 51 and the edge winding portion L2C and the spacing C2 between any two adjacent winding portions L2 fluctuates within the range of 10% C1 or 10% C2, it can also be considered that the spacing C1 between the virtual winding portion 51 and the edge winding portion L2C is equal to the spacing C2 between any two adjacent winding portions L2.

[0272] In some embodiments, as shown in Figures 20 and 21 , along the direction V from the opening area W2 toward the display area AA, the width of the dummy winding portion 51 is equal to the width of the winding portion L2. This facilitates the simultaneous formation of the dummy winding portion 51 and multiple winding portions L2, simplifying the manufacturing of the array substrate 100. Furthermore, it can help reduce the layout difficulty of the array substrate 100 and improve the regularity of the array substrate 100.

[0273] In summary, the dummy winding portion 51, except for not needing to be electrically connected to the pixel driving circuit, can have the same specifications and parameters as the multiple winding portions L2. This facilitates the simultaneous formation of the dummy winding portion 51 and the multiple winding portions L2, simplifies the manufacturing process of the array substrate 100, and improves the regularity of the array substrate 100.

[0274] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: An opening area, a display area surrounding the opening area, and an opening peripheral area between the opening area and the display area; The array substrate comprises: a substrate and a driving circuit layer located on the substrate; The driving circuit layer includes: a constant voltage conductive ring and a plurality of signal lines; The plurality of signal lines include a plurality of target signal lines, the target signal lines include a lead portion and a winding portion connected to each other, the lead portion extends from the opening peripheral area to the display area, the winding portion is located in the opening peripheral area and is arranged along the edge of the opening area; The constant voltage conductive ring is located in the peripheral area of ​​the opening and is arranged around the opening area. In the direction from the display area to the opening area, the orthographic projection of the winding part on the substrate is located between the orthographic projection of the constant voltage conductive ring on the substrate and the opening area.

2. The array substrate according to claim 1, wherein: The lead portion includes a first overlapping portion, the orthographic projection of the first overlapping portion on the substrate overlaps with the orthographic projection of the constant voltage conductive ring on the substrate, and the areas of the first overlapping portions of the lead portions of the plurality of target signal lines are equal.

3. The array substrate according to claim 1 or 2, wherein: The plurality of target signal lines include a plurality of first signal lines, the lead portions of the plurality of first signal lines extend along a first direction and are arranged in a second direction, and the first direction intersects with the second direction; The plurality of first signal lines are divided into a first portion of signal lines and a second portion of signal lines. Along the second direction, the lead portions of the first portion of signal lines and the lead portions of the second portion of signal lines are respectively located at two sides of the opening area.

4. The array substrate according to claim 3, wherein: The plurality of target signal lines further include a plurality of second signal lines, the lead portions of the plurality of second signal lines extend along the second direction, and are arranged in the first direction; The plurality of second signal lines are divided into a third portion of signal lines and a fourth portion of signal lines. Along the first direction, the lead portions of the third portion of signal lines and the lead portions of the fourth portion of signal lines are respectively located at two sides of the opening area.

5. The array substrate according to claim 4, wherein: The first signal line includes a gate control signal line, and the second signal line includes a data signal line.

6. The array substrate according to claim 4 or 5, wherein: The driving circuit layer includes a plurality of metal conductive layers stacked on the substrate; Along the direction away from the substrate, the plurality of metal conductive layers are respectively a first gate metal layer, a second gate metal layer, a first routing metal layer, and a second routing metal layer; Among the plurality of first signal lines: a portion of the first signal lines has winding portions located at the first gate metal layer, and another portion of the first signal lines has winding portions located at the second gate metal layer; Among the plurality of second signal lines, winding portions of a portion of the second signal lines are located in the first routing metal layer, and winding portions of another portion of the second signal lines are located in the second routing metal layer.

7. The array substrate according to any one of claims 1 to 6, wherein: The winding portion farthest from the opening area among the orthographic projections of the plurality of winding portions on the substrate is an outer winding portion; The driving circuit layer also includes: A virtual winding portion is located between the outer winding portion and the display area, and the virtual winding portion is in the same layer as the outer winding portion.

8. The array substrate according to claim 6, wherein: The winding portion farthest from the opening area among the plurality of winding portions located in the same metal conductive layer is an edge winding portion; The driving circuit layer also includes: A virtual winding portion, wherein the virtual winding portion corresponds to the edge winding portion one by one, the virtual winding portion is located between the edge winding portion and the display area, and the virtual winding portion and the corresponding edge winding portion are in the same layer.

9. The array substrate according to claim 7 or 8, wherein: Along the direction from the opening area to the display area, the width of the virtual winding portion is equal to the width of the winding portion.

10. The array substrate according to any one of claims 7 to 9, wherein: In the direction from the opening area to the display area, the spacing between the virtual winding portion and the adjacent winding portion is equal to the spacing between any two adjacent winding portions.

11. The array substrate according to any one of claims 1 to 6, wherein: The winding portion farthest from the opening area among the orthographic projections of the plurality of winding portions on the substrate is an outer winding portion, and the winding portion other than the outer winding portion among the plurality of winding portions is a first inner winding portion; In a direction from the opening area to the display area, a width d1 of the outer winding portion is greater than a width d2 of the first inner winding portion.

12. The array substrate according to claim 6, wherein: The winding portion farthest from the opening area among the plurality of winding portions located in the same metal conductive layer is an edge winding portion, and the winding portions other than the edge winding portion among the plurality of winding portions are second inner winding portions; In a direction from the opening area to the display area, a width d1 of the edge winding portion is greater than a width d2 of the second inner winding portion.

13. The array substrate according to claim 10 or 11, wherein: 1.1d2≤d1≤1.15d2.

14. The array substrate according to any one of claims 11 to 13, wherein: d1=1.3d2.

15. The array substrate according to any one of claims 1 to 14, wherein: The driving circuit layer further includes a plurality of pixel driving circuits, each of which includes a driving transistor, and the plurality of pixel driving circuits are located in the display area; The driving circuit layer also includes: A bottom shielding layer is located between the pixel driving circuit and the substrate, and the constant voltage conductive ring is electrically connected to the bottom shielding layer; the bottom shielding layer includes a plurality of shielding patterns, and the orthographic projections of the shielding patterns on the substrate cover the orthographic projections of the driving transistor on the substrate, and two adjacent shielding patterns are connected to each other.

16. The array substrate according to claim 15, wherein: The constant voltage conductive ring is in the same layer as the bottom shielding layer.

17. The array substrate according to claim 16, wherein: The bottom shielding layer further comprises a conductive connection portion, wherein the conductive connection portion is used to connect the constant voltage conductive ring and the shielding pattern; The driving circuit layer further includes a plurality of connecting through holes, and the orthographic projection of the conductive connecting portion on the substrate does not overlap with the orthographic projection of the connecting through holes on the substrate.

18. The array substrate according to claim 17, wherein: A minimum distance between an orthographic projection of the conductive connection portion on the substrate and an orthographic projection of the connecting through hole on the substrate is greater than or equal to 3 μm.

19. The array substrate according to claim 17 or 18, wherein: The conductive connection portion and the constant voltage conductive ring are in the same layer; The conductive connection portion includes a first conductive connection portion, the first conductive connection portion intersects with the constant voltage conductive ring to form a first acute angle, and the first conductive connection portion intersects with the constant voltage conductive ring to form a first space; The driving circuit layer also includes a first compensation part, which is in the same layer as the constant-voltage conductive ring; the first compensation part is located in the first space, the first compensation part intersects with the first conductive connection part to form a first angle, and the first compensation part intersects with the constant-voltage conductive ring to form a second angle; wherein the first angle and the second angle are both greater than or equal to 90°.

20. A display panel, comprising: The array substrate according to any one of claims 1 to 19; and, The light emitting device layer is located on a side of the array substrate away from the substrate.

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