PLC ladder diagram compilation method, device, computer equipment and medium

Abstract

The present disclosure provides a PLC ladder diagram compilation method, apparatus, computer equipment, and medium, comprising: obtaining an original PLC ladder diagram and optimizing the original PLC ladder diagram to obtain a target PLC ladder diagram; splitting the target PLC ladder diagram based on the link relationship between each identified bus in the target PLC ladder diagram to obtain a local ladder diagram between the starting node bus and the intermediate node bus, and a local ladder diagram between the intermediate node bus and the ending node bus; compiling the local ladder diagram between the starting node bus and the intermediate node bus based on the flow direction branch set corresponding to the starting node bus to obtain an intermediate node compilation result; and compiling the local ladder diagram between the intermediate node bus and the ending node bus based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus to obtain a PLC ladder diagram compilation result. Thus, the ladder diagram compilation efficiency is effectively improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of ladder diagram compilation, and in particular, to a method, apparatus, computer equipment, and medium applicable to compiling a PLC ladder diagram. Background Art

[0002] The ladder diagram of a PLC (Programmable Logic Controller) needs to be compiled into machine-executable code before it can be run on the PLC hardware. By automating the compilation process, the time and error rate of manual programming can be reduced, thereby improving programming efficiency.

[0003] In related technologies, most ladder diagram compilation algorithms first convert the ladder diagram into a directed acyclic graph (AVO), and then convert it into a binary tree. During the overall compilation process, they only focus on the previous and next link relationships of instructions, but ignore the importance of the bus.

[0004] However, using existing technologies, the compilation process is complicated, resulting in low compilation efficiency. Summary of the Invention

[0005] The embodiments described herein provide a method, apparatus, computer device, and medium for compiling a PLC ladder diagram, which overcome the above-mentioned problems.

[0006] In a first aspect, according to the present disclosure, a method for compiling a PLC ladder diagram is provided, comprising:

[0007] Obtaining an original PLC ladder diagram, and optimizing the diagram structure of the original PLC ladder diagram to obtain a target PLC ladder diagram, wherein the original PLC ladder diagram includes: a ladder diagram bus and a ladder diagram instruction, and the target PLC ladder diagram includes: an identification bus, an identification instruction, and an optimized structure, wherein the identification bus is obtained by encoding the ladder diagram bus, the identification instruction is obtained by encoding the ladder diagram instruction, and the optimized structure is used to describe a connecting line segment between the identification bus and the identification instruction;

[0008] Based on the link relationship between each of the identified buses in the target PLC ladder diagram, the target PLC ladder diagram is split into a graph structure to obtain a local ladder diagram between a starting node bus and an intermediate node bus and a local ladder diagram between the intermediate node bus and an ending node bus, wherein the starting node bus is directly linked to the intermediate node bus;

[0009] Compiling a local ladder diagram between the starting node bus and the intermediate node bus based on the flow direction branch set corresponding to the starting node bus to obtain an intermediate node compilation result;

[0010] Based on the intermediate node compilation result and the flow branch set corresponding to the intermediate node bus, the local ladder diagram between the intermediate node bus and the end node bus is program compiled to obtain a PLC ladder diagram compilation result.

[0011] In a second aspect, according to the present disclosure, a device for compiling a PLC ladder diagram is provided, comprising:

[0012] An acquisition and optimization module is used to acquire an original PLC ladder diagram and optimize the diagram structure of the original PLC ladder diagram to obtain a target PLC ladder diagram, wherein the original PLC ladder diagram includes: a ladder diagram bus and a ladder diagram instruction; the target PLC ladder diagram includes: an identification bus, an identification instruction, and an optimized structure, wherein the identification bus is obtained by encoding the ladder diagram bus, the identification instruction is obtained by encoding the ladder diagram instruction, and the optimized structure is used to describe the connecting line segment between the identification bus and the identification instruction;

[0013] A splitting module is used to split the target PLC ladder diagram into a graph structure based on the link relationship between each of the identified buses in the target PLC ladder diagram to obtain a local ladder diagram between the starting node bus and the intermediate node bus and a local ladder diagram between the intermediate node bus and the ending node bus, wherein the starting node bus is directly linked to the intermediate node bus;

[0014] A first compiling module is configured to compile a local ladder diagram between the starting node bus and the intermediate node bus based on a flow direction branch set corresponding to the starting node bus, to obtain an intermediate node compilation result;

[0015] The second compilation module is used to compile the local ladder diagram between the intermediate node bus and the end node bus based on the intermediate node compilation result and the flow branch set corresponding to the intermediate node bus to obtain a PLC ladder diagram compilation result.

[0016] In a third aspect, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of the PLC ladder diagram compilation method in any of the above embodiments are implemented.

[0017] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for compiling a PLC ladder diagram in any of the above embodiments are implemented.

[0018] The compiling method of the PLC ladder diagram provided by the embodiment of the present application obtains the original PLC ladder diagram and optimizes the diagram structure of the original PLC ladder diagram to obtain the target PLC ladder diagram. The original PLC ladder diagram includes: ladder bus and ladder instructions. The target PLC ladder diagram includes: identification bus, identification instruction and optimized structure. The identification bus is obtained by encoding the ladder bus, and the identification instruction is obtained by encoding the ladder instruction. The optimized structure is used to describe the connecting line segment between the identification bus and the identification instruction; based on the link relationship between the identification buses in the target PLC ladder diagram, the target The PLC ladder diagram is structured and split to obtain the local ladder diagram between the starting node bus and the intermediate node bus, as well as the local ladder diagram between the intermediate node bus and the ending node bus. The starting node bus is directly linked to the intermediate node bus. Based on the flow branch set corresponding to the starting node bus, the local ladder diagram between the starting node bus and the intermediate node bus is compiled to obtain the intermediate node compilation result. Based on the intermediate node compilation result and the flow branch set corresponding to the intermediate node bus, the local ladder diagram between the intermediate node bus and the ending node bus is compiled to obtain the PLC ladder diagram compilation result. In this way, by structurally optimizing the original PLC ladder diagram to obtain the target PLC ladder diagram, it is convenient to compile directly on the target PLC ladder diagram without performing other structural diagram conversions on the PLC ladder diagram, effectively reducing the compilation complexity of the PLC ladder diagram and improving the ladder diagram compilation efficiency.

[0019] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0021] Figure 1 It is a flow chart of a method for compiling a PLC ladder diagram provided by the present disclosure.

[0022] Figure 2 It is a structural schematic diagram of an original PLC ladder diagram provided by the present disclosure.

[0023] Figure 3 It is a structural schematic diagram of a target PLC ladder diagram provided by the present disclosure.

[0024] Figure 4It is a structural diagram of a PLC ladder diagram compiling device provided by the present disclosure.

[0025] Figure 5 It is a structural diagram of a computer device provided by the present disclosure.

[0026] It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0029] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it necessarily refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0030] The term "and / or" in this document simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists, A and B exist simultaneously, and B exists. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship. Terms such as "first" and "second" are used solely to distinguish one component (or portion of a component) from another component (or portion of a component).

[0031] In the description of this application, unless otherwise specified, “plurality” means two or more (including two), and similarly, “multiple groups” means two or more (including two).

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0033] Figure 1 This is a flow chart of a method for compiling a PLC ladder diagram provided by an embodiment of the present disclosure, such as Figure 1 As shown, the specific process of the PLC ladder diagram compilation method includes:

[0034] S110 , obtaining an original PLC ladder diagram, and optimizing the structure of the original PLC ladder diagram to obtain a target PLC ladder diagram.

[0035] Among them, the original PLC ladder diagram includes: ladder bus and ladder instructions. Figure 2 As shown, the ladder diagram bus is represented by a long vertical line in area 210 , and the ladder diagram instructions can be represented by two short vertical lines in area 220 .

[0036] The target PLC ladder diagram includes: identification bus, identification instruction and optimization structure. The identification bus is obtained by encoding the ladder diagram bus, the identification instruction is obtained by encoding the ladder diagram instruction, and the optimization structure is used to describe the connection line segment between the identification bus and the identification instruction. Figure 3 As shown, the identification bus is represented by a long vertical line with a number in area 310; the identification instruction can be represented by two short vertical lines with a number in area 320 to distinguish different ladder diagram instructions; the optimized structure is represented by a bold line segment to supplement the missing connecting line segments in the original PLC ladder diagram. Figure 3 In the , busbar can be regarded as a special instruction. Instructions and buses are associated through branches. Instructions have a front-and-back link relationship, and buses have a branch-merge relationship.

[0037] This embodiment uses object-oriented programming to abstract the instruction base class described in the following C# pseudocode. Each instruction is identified by a unique integer value, namely an ID (Identity Document). The IDs of the previous and next instructions are also stored, indicating the link relationship between adjacent instructions.

[0038] A busbar has multiple input and output branches, which manage branching and merging. Input branches describe input merging relationships, while output branches describe output branching relationships. The pseudocode definition for a busbar is as follows.

[0039] ------------------------------------------------

[0040] class Bus: InsBase

[0041] {

[0042] / / Branch

[0043] class Branch

[0044] {

[0045] int InsID; / / The first instruction of the branch link

[0046] List <int>buslist; / / bus list

[0047] }

[0048] List <branch>input; / / input branch

[0049] List <branch>output; / / output branch

[0050] }

[0051] ------------------------------------------------

[0052] The entire ladder diagram consists of busbars and instructions, and the busbars are special instructions, so the pseudo code description of the ladder diagram is as follows.

[0053] --------------------------------------------------

[0054] class Graph{

[0055] Map<int,InsBase> InsMap; / / Mapping of ID to instruction instance

[0056] }

[0057] -------------------------------------------------------

[0058] This embodiment uses the defined ID numbering rules as an example. Specifically, the ID number of the starting bus of the target PLC ladder diagram is always 1; the ID number of the ending bus is always -1; and the ID numbers of other instruction instances are not 0. After loading into memory, the code structure uses the structure described above, and the original PLC ladder diagram is numbered and segmented to obtain the target PLC ladder diagram.

[0059] A complete ladder diagram link logic can be described in code data using the above structure. Through the ID number and mapping table, specific instruction instances can be found, and the link relationship between instructions can also be described using the ID number.

[0060] S120. Based on the link relationship between the identified buses in the target PLC ladder diagram, the target PLC ladder diagram is split into a graph structure to obtain a local ladder diagram between the start node bus and the intermediate node bus and a local ladder diagram between the intermediate node bus and the end node bus.

[0061] The graph structure splitting in this embodiment is implemented by adopting a binary splitting idea, that is, first splitting a large range into several small ranges required by the symbols in sequence until it cannot be split any more.

[0062] The starting node bus is directly linked to the intermediate node bus. It can be understood that direct link means that there is no other identified bus between the starting node bus and the intermediate node bus. Figure 3 The identification bus 1 in the middle node bus is as follows Figure 3 Identify busbar 4 in the.

[0063] Based on the link relationship between each identification bus in the target PLC ladder diagram, the target PLC ladder diagram is split into a graph structure to obtain a local ladder diagram between the starting node bus and the intermediate node bus, as well as a local ladder diagram between the intermediate node bus and the ending node bus. This may include: taking the first identification bus in the target PLC ladder diagram as the starting node bus, the last identification bus as the ending node bus, and taking the identification bus (i.e., the intermediate node bus) that has a direct link relationship with the starting node bus as the graph structure splitting line to obtain a local ladder diagram between the starting node bus and the intermediate node bus, as well as a local ladder diagram between the intermediate node bus and the ending node bus.

[0064] For example, Figure 3 The target PLC ladder diagram shown in is split, with identification bus 1 as the starting node bus and the end identification bus-1 as the ending node bus. The identification bus 4, which has a direct link relationship with the starting node bus 1, is used as the graph structure splitting line to obtain the local ladder diagram between identification bus 1 and identification bus 4, and the local ladder diagram between identification bus 4 and identification bus-1.

[0065] In some embodiments, before compiling the local ladder diagram between the starting node bus and the intermediate node bus based on the flow direction branch set corresponding to the starting node bus, the method further includes:

[0066] Obtain a bus list corresponding to different branch flow directions of the starting node bus, wherein the bus list corresponding to different branch flow directions of the starting node bus includes: other identified buses having a flow direction relationship with the starting node bus; perform branch type identification on the bus list corresponding to different branch flow directions of the starting node bus to obtain a flow direction branch set corresponding to the starting node bus.

[0067] In the above example, the busbar identified as bus 1 (i.e., the starting node busbar) includes three branches: branch 1-1, branch 1-2, and branch 1-3. The busbar list corresponding to the flow direction of branch 1-1 for bus 1 is <4, 13, 15, -1>; the busbar list corresponding to the flow direction of branch 1-2 for bus 1 is <4> ; The busbar list corresponding to the flow direction of branches 1-3 is marked as <-1>.

[0068] The flow branches corresponding to the start node bus include: merged branches and / or single branches. A merged branch consists of flow branches corresponding to at least two bus lists. A merged branch is a branch that has multiple branches merged together to form multiple branches in the final result; a single branch is a branch that does not merge with other branches.

[0069] The flow branches corresponding to ID bus 1 include merged branches and single branches. If the largest merged branch bus of branches 1-1 and 1-2 is ID bus 4, branches 1-1 and 1-2 form a merged branch; branch 1-3 is a single branch. It should be noted that the first branch in a merged branch serves as the overall flow path of the merged branch, meaning that branch 1-1 serves as the overall flow path of the merged branch.

[0070] S130 , compiling a local ladder diagram between the starting node bus and the intermediate node bus based on the flow direction branch set corresponding to the starting node bus to obtain an intermediate node compilation result.

[0071] When compiling the local ladder diagram between the starting node bus and the intermediate node bus, it is necessary to compile the merged branches and single branches in the flow branch set corresponding to the starting node bus separately.

[0072] In some embodiments, a local ladder diagram between the starting node bus and the intermediate node bus is program-compiled based on the flow direction branch set corresponding to the starting node bus to obtain the intermediate node compilation result, including:

[0073] If the flow branch set corresponding to the starting node bus is used to describe the merged branch, the identification instruction corresponding to each branch in the merged branch is logically converted to obtain the execution logic data of the identification instruction corresponding to each branch, and the first logical operation is performed on the execution logic data of the identification instruction corresponding to each branch to obtain the intermediate node compilation result; if the flow branch set corresponding to the starting node bus is used to describe the single branch, the identification instruction corresponding to the single branch is logically converted to obtain the intermediate node compilation result; if the flow branch set corresponding to the starting node bus is used to describe the merged branch and the single branch, the intermediate node compilation result is obtained based on the logical conversion result of the identification instruction corresponding to each branch in the merged branch and the logical conversion result of the identification instruction corresponding to the single branch.

[0074] By converting a high-level language like LAD into an intermediate language (IR), and then analyzing and optimizing the IR, it can be directly converted into bytecode or C language code. The IR can be designed with reference to the STL language. This embodiment uses the "normally open contact instruction" as an example to illustrate IR conversion.

[0075] -----------------------------------------------------------

[0076] void Visit(NOC ins){

[0077] If the preceding instruction is bus&&

[0078] (In the merge branch, the || preceding instruction is the starting bus 1)

[0079] {

[0080] Generate a load instruction to get the value of the normally open contact operand,

[0081] Similar to STL's LD instruction

[0082] }

[0083] Else

[0084] Generate a bit and load instruction to get the value of the normally open contact operand,

[0085] Similar to STL's A instruction

[0086] }

[0087] }

[0088] -------------------------------------------------------------

[0089] In the above example, the flow branches corresponding to identification bus 1 include merged branches and single branches. Branches 1-1 and 1-2 form a merged branch; branch 1-3 is a single branch. When compiling the local ladder diagram between identification bus 1 and identification bus 4, identification instructions 2 and 3 are IR-converted to obtain the IR corresponding to identification instruction 2 (i.e., the logical conversion result of the identification instruction corresponding to branch 1-1) and the IR corresponding to identification instruction 3 (i.e., the logical conversion result of the identification instruction corresponding to branch 1-2). An OR operation (i.e., the first logical operation) is performed on the IRs corresponding to identification instruction 2 and 3, with the result being recorded as Q1. Identification instructions 20 and 21 are then IR-converted to obtain the IR corresponding to identification instruction 20 and the IR corresponding to identification instruction 21. An AND operation (i.e., the second logical operation referred to below) is performed on the IRs corresponding to identification instruction 20 and 21, with the result being recorded as Q2 (i.e., the logical conversion result of the identification instructions corresponding to single branches 1-3). The intermediate node compilation result is thus composed of Q1 and Q2.

[0090] S140 , based on the intermediate node compilation result and the flow branch set corresponding to the intermediate node bus, compile the local ladder diagram between the intermediate node bus and the end node bus to obtain a PLC ladder diagram compilation result.

[0091] When compiling the local ladder diagram between the intermediate node bus and the end node bus, it is necessary to compile the merged branches and single branches in the flow branch set corresponding to the intermediate node bus separately.

[0092] In some embodiments, based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus, a local ladder diagram between the intermediate node bus and the end node bus is program compiled to obtain a PLC ladder diagram compilation result, including:

[0093] If the intermediate node bus is directly linked to the end node bus, the flow direction branch set corresponding to the intermediate node bus is obtained; based on the flow direction branch set corresponding to the intermediate node bus, the local ladder diagram between the intermediate node bus and the end node bus is program compiled to obtain the end node compilation result; a second logical operation is performed on the intermediate node compilation result and the end node compilation result to obtain the PLC ladder diagram compilation result.

[0094] In some other embodiments, based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus, a local ladder diagram between the intermediate node bus and the end node bus is program compiled to obtain a PLC ladder diagram compilation result, including:

[0095] If the intermediate node bus is indirectly linked to the end node bus, the local ladder diagram between the intermediate node bus and the end node bus is split into a graph structure to obtain a local ladder diagram between the intermediate node bus and the lower-level node bus and a local ladder diagram between the lower-level node bus and the end node bus, and the intermediate node bus is directly linked to the lower-level node bus; the flow direction branch set corresponding to the intermediate node bus is obtained, and based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus, the local ladder diagram between the intermediate node bus and the lower-level node bus is compiled to obtain the lower-level node compilation result; based on the lower node compilation result and the flow direction branch set corresponding to the lower node bus, the local ladder diagram between the lower node bus and the end node bus is compiled to obtain the PLC ladder diagram compilation result.

[0096] Among them, the intermediate node bus is indirectly linked to the end node bus. It can be understood that the indirect link means that there are one or more other identified buses between the intermediate node bus and the end node bus. Figure 3 The identification bus 4 in the end node bus is as follows Figure 3 There are identification busbars 13 and 15 between identification busbars -1, 4 and -1.

[0097] The graph structure of the local ladder diagram between the intermediate node bus and the end node bus is split to obtain the local ladder diagram between the intermediate node bus and the lower-level node bus, and the local ladder diagram between the lower-level node bus and the end node bus, such as the local ladder diagram between the identification bus 4 and the identification bus 13 (i.e., the lower-level node bus), and the local ladder diagram between the identification bus 13 and the identification bus -1; the identification bus 4 is directly linked to the identification bus 13.

[0098] See also Figure 3 As shown, the busbar 4 includes three branches, namely: branch 4-1, branch 4-2 and branch 4-3. The busbar list corresponding to the flow direction of branch 4-1 is <13,15,-1>; the busbar list corresponding to the flow direction of branch 4-2 is <19,13>; the busbar list corresponding to the flow direction of branch 4-3 is <9> If the widest combined branch bus of branches 4-1, 4-2, and 4-3 is identification bus 13, then the flow branch set corresponding to identification bus 4 only includes the combined branch consisting of branches 4-1, 4-2, and 4-3. When compiling the local ladder diagram between identification bus 4 and identification bus 13, this can be achieved by combining the flow branch set corresponding to identification bus 4 and the logical conversion result Q1 in the intermediate node compilation result.

[0099] In some embodiments, based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus, a local ladder diagram between the intermediate node bus and the lower-level node bus is program-compiled to obtain the lower-level node compilation result, including:

[0100] Based on the flow branch set corresponding to the intermediate node bus, the local ladder diagram between the intermediate node bus and the lower-level node bus is program compiled to obtain the branch node compilation result; the second logical operation is performed on the intermediate node compilation result and the branch node compilation result to obtain the lower-level node compilation result.

[0101] In combination with the above example, when compiling the local ladder diagram between identification bus 4 and identification bus 13, IR conversion is performed on identification instruction 5 to obtain the IR corresponding to identification instruction 5, which is recorded as Q3; IR conversion is performed on identification instruction 6 to obtain the IR corresponding to identification instruction 6, and IR conversion is performed on identification instruction 7 to obtain the IR corresponding to identification instruction 7, and an "AND" operation is performed on the IR corresponding to identification instruction 6 and the IR corresponding to identification instruction 7, and the operation result is recorded as Q4; IR conversion is performed on identification instruction 8 to obtain the IR corresponding to identification instruction 8, which is recorded as Q5, and an "OR" operation is performed on Q4 and Q5, and the operation result is recorded as Q6; Perform IR conversion on identification instruction 10 to obtain the IR corresponding to identification instruction 10, denoted as Q7; perform IR conversion on identification instruction 11 to obtain the IR corresponding to identification instruction 11, perform IR conversion on identification instruction 12 to obtain the IR corresponding to identification instruction 12, and perform an "AND" operation on the IR corresponding to identification instruction 11 and the IR corresponding to identification instruction 12, with the result denoted as Q8; perform an "OR" operation on Q7 and Q8, with the result denoted as Q9; perform an "AND" operation on Q6 and Q9, with the result denoted as Q10; perform an "OR" operation on Q3 and Q10, with the result denoted as Q11, and the branch node compilation result is obtained. By performing an "AND" operation on the branch node compilation result Q11 and Q1 in the intermediate node compilation result, the result is denoted as Q12, and the lower-level node compilation result is obtained.

[0102] In some embodiments, based on the lower-level node compilation result and the flow direction branch set corresponding to the lower-level node bus, a local ladder diagram between the lower-level node bus and the end node bus is program compiled to obtain a PLC ladder diagram compilation result, including:

[0103] If the lower-level node bus is indirectly linked to the end node bus, the local ladder diagram between the lower-level node bus and the end node bus is further split until the node bus is directly linked to the end node bus after splitting; the PLC ladder diagram compilation result is obtained based on the lower-level node compilation result, the intermediate node compilation result, and the local ladder diagram compilation result of the lower-level node bus and the end node bus.

[0104] Among them, the lower-level node bus is indirectly connected to the end node bus. Figure 3 The identification bus 13 in the end node bus is as follows Figure 3 In the example, there is a busbar 15 between busbar 13 and busbar 1. Further splitting the local ladder diagram between busbars 13 and 13 yields a local ladder diagram between busbars 13 and 15, and a local ladder diagram between busbars 15 and busbar 13. Since there are no other busbars between busbars 15 and 13, busbar 15 becomes the node busbar after splitting.

[0105] The local ladder diagram compilation results of the lower-level node bus and the end node bus are the local ladder diagram compilation results of the identification bus 13 and the identification bus -1. The local ladder diagram compilation results of the identification bus 13 and the identification bus -1 are obtained by the local ladder diagram compilation results of the identification bus 13 (i.e., the lower-level node bus) and the identification bus 15 (i.e., the node bus after splitting) and the local ladder diagram compilation results of the identification bus 15 and the identification bus -1 (i.e., the end node bus).

[0106] Specifically, when compiling the local ladder diagram between the identified bus 13 and the identified bus 15, the local ladder diagram between the identified bus 13 and the identified bus 15 is compiled using the flow direction branch set corresponding to the identified bus 13. The identified bus 13 has two branches, namely, branch 13-1 and branch 13-2. The bus list corresponding to the flow direction of branch 13-1 for the identified bus 13 is <15, -1>; the bus list corresponding to the flow direction of branch 13-2 for the identified bus 13 is <-1>; and both branches 13-1 and 13-2 are single branches.

[0107] Based on the above example, the identification instruction 14 is IR-converted to obtain the IR corresponding to the identification instruction 14, which is recorded as Q13; the identification instruction 18 is IR-converted to obtain the IR corresponding to the identification instruction 18, and the identification instruction 19 is IR-converted to obtain the IR corresponding to the identification instruction 19, and the IR corresponding to the identification instruction 18 and the IR corresponding to the identification instruction 19 are ANDed, and the result of the operation is recorded as Q14.

[0108] When compiling the local ladder diagram between bus 15 and bus -1, the local ladder diagram between bus 15 and bus -1 is compiled based on the compilation result of the local ladder diagram between bus 13 and bus 15 and the flow direction branch set corresponding to bus 15. Bus 15 has two branches: branch 15-1 and branch 15-2. The bus list for bus 15 corresponding to the flow direction of branch 15-1 is <-1>; the bus list for bus 15 corresponding to the flow direction of branch 15-2 is <-1>. Both branches 15-1 and 15-2 are single branches.

[0109] In combination with the above example, the identification instruction 16 is IR-converted to obtain the IR corresponding to the identification instruction 16, the identification instruction 17 is IR-converted to obtain the IR corresponding to the identification instruction 17, and the IR corresponding to the identification instruction 16 and the IR corresponding to the identification instruction 17 are "OR"-operated, and the operation result is recorded as Q15; then the "AND" operation is performed on Q13 and Q15, and the operation result is recorded as Q16, and the local ladder diagram compilation result of the identification bus 15 and the identification bus-1 is obtained, that is, the local ladder diagram compilation result of the node bus and the end node bus after splitting; then the "OR" operation is performed on Q14 and Q16, and the operation result is recorded as Q17, and the local ladder diagram compilation result of the identification bus 13 and the identification bus-1 is obtained, that is, the local ladder diagram compilation result of the lower-level node bus and the end node bus.

[0110] Obtaining a PLC ladder diagram compilation result based on the lower-level node compilation result, the intermediate node compilation result, and the local ladder diagram compilation results of the lower-level node bus and the end node bus may include: performing a second logical operation on the lower-level node compilation result and the local ladder diagram compilation results of the lower-level node bus and the end node bus to obtain an operation result; and then performing a first logical operation on the operation result and the intermediate node compilation result to obtain a PLC ladder diagram compilation result.

[0111] Based on the above example, perform an "AND" operation on Q12 and Q17, and record the result as Q18. Then perform an "OR" operation on Q18 and Q2 in the intermediate node compilation result, and record the result as Q19. This will give the ladder diagram compilation result of bus 1 and bus -1, that is, the PLC ladder diagram compilation result.

[0112] In this embodiment, an original PLC ladder diagram is obtained, and the original PLC ladder diagram is optimized to obtain a target PLC ladder diagram. The original PLC ladder diagram includes: ladder bus and ladder instructions. The target PLC ladder diagram includes: identification bus, identification instruction and optimized structure. The identification bus is obtained by encoding the ladder bus, and the identification instruction is obtained by encoding the ladder instruction. The optimized structure is used to describe the connecting line segment between the identification bus and the identification instruction. Based on the link relationship between the identification buses in the target PLC ladder diagram, the target PLC ladder diagram is optimized. The line diagram structure is split to obtain the local ladder diagram between the starting node bus and the intermediate node bus, as well as the local ladder diagram between the intermediate node bus and the ending node bus. The starting node bus is directly linked to the intermediate node bus. Based on the flow branch set corresponding to the starting node bus, the local ladder diagram between the starting node bus and the intermediate node bus is compiled to obtain the intermediate node compilation result. Based on the intermediate node compilation result and the flow branch set corresponding to the intermediate node bus, the local ladder diagram between the intermediate node bus and the ending node bus is compiled to obtain the PLC ladder diagram compilation result. In this way, by structurally optimizing the original PLC ladder diagram to obtain the target PLC ladder diagram, it is convenient to compile directly on the target PLC ladder diagram without performing other structural diagram conversions on the PLC ladder diagram, effectively reducing the compilation complexity of the PLC ladder diagram and improving the ladder diagram compilation efficiency.

[0113] In summary, the method of this embodiment does not require additional conversion of the ladder diagram during the ladder diagram compilation process, but directly performs split analysis on the ladder diagram description structure, effectively reducing the intermediate structure process of structure conversion; by paying attention to the role of the bus, the reconstruction of branch merging relationships during the analysis process is avoided, further speeding up the compilation process.

[0114] Figure 4 This is a schematic diagram of the structure of a PLC ladder diagram compiling device provided in this embodiment. The PLC ladder diagram compiling device may include:

[0115] The acquisition and optimization module 410 is used to acquire the original PLC ladder diagram and optimize the diagram structure of the original PLC ladder diagram to obtain the target PLC ladder diagram. The original PLC ladder diagram includes: ladder bus and ladder instructions. The target PLC ladder diagram includes: identification bus, identification instruction and optimized structure. The identification bus is obtained by encoding the ladder bus, and the identification instruction is obtained by encoding the ladder instruction. The optimized structure is used to describe the connecting line segment between the identification bus and the identification instruction.

[0116] The splitting module 420 is used to split the target PLC ladder diagram based on the link relationship between the identified buses in the target PLC ladder diagram, and obtain the local ladder diagram between the starting node bus and the intermediate node bus and the local ladder diagram between the intermediate node bus and the ending node bus. The starting node bus is directly linked to the intermediate node bus.

[0117] The first compiling module 430 is configured to compile a local ladder diagram between the starting node bus and the intermediate node bus based on the flow direction branch set corresponding to the starting node bus to obtain an intermediate node compilation result.

[0118] The second compilation module 440 is used to compile the local ladder diagram between the intermediate node bus and the end node bus based on the intermediate node compilation result and the flow branch set corresponding to the intermediate node bus to obtain a PLC ladder diagram compilation result.

[0119] In this embodiment, optionally, it further includes: an acquisition module and an identification module.

[0120] The acquisition module is used to obtain a bus list corresponding to different branch flow directions of the starting node bus, wherein the bus list corresponding to different branch flow directions of the starting node bus includes: other identified buses having a flow direction relationship with the starting node bus.

[0121] An identification module is used to identify the branch type of the bus list corresponding to the starting node bus with different branch flow directions, and obtain a flow direction branch set corresponding to the starting node bus. The flow direction branch set corresponding to the starting node bus includes: a merged branch, and / or a single branch. The merged branch is composed of flow direction branches corresponding to at least two bus lists.

[0122] In this embodiment, optionally, the first compiling module 430 is specifically configured to:

[0123] If the flow branch set corresponding to the starting node bus is used to describe the merged branch, the identification instruction corresponding to each branch in the merged branch is logically converted to obtain the execution logic data of the identification instruction corresponding to each branch, and the first logical operation is performed on the execution logic data of the identification instruction corresponding to each branch to obtain the intermediate node compilation result; if the flow branch set corresponding to the starting node bus is used to describe the single branch, the identification instruction corresponding to the single branch is logically converted to obtain the intermediate node compilation result; if the flow branch set corresponding to the starting node bus is used to describe the merged branch and the single branch, the intermediate node compilation result is obtained based on the logical conversion result of the identification instruction corresponding to each branch in the merged branch and the logical conversion result of the identification instruction corresponding to the single branch.

[0124] In this embodiment, optionally, the second compiling module 440 includes: a splitting component, a first compiling component, and a second compiling component.

[0125] The splitting component is used to split the graph structure of the local ladder diagram between the intermediate node bus and the end node bus if the intermediate node bus is indirectly linked to the end node bus, so as to obtain the local ladder diagram between the intermediate node bus and the lower-level node bus and the local ladder diagram between the lower-level node bus and the end node bus. The intermediate node bus is directly linked to the lower-level node bus.

[0126] The first compilation component is used to obtain the flow branch set corresponding to the intermediate node bus, and based on the intermediate node compilation result and the flow branch set corresponding to the intermediate node bus, compile the local ladder diagram between the intermediate node bus and the lower-level node bus to obtain the lower-level node compilation result.

[0127] The second compilation component is used to compile the local ladder diagram between the lower-level node bus and the end node bus based on the lower-level node compilation result and the flow branch set corresponding to the lower-level node bus to obtain the PLC ladder diagram compilation result.

[0128] In this embodiment, optionally, the first compilation component is specifically configured to:

[0129] Based on the flow branch set corresponding to the intermediate node bus, the local ladder diagram between the intermediate node bus and the lower-level node bus is program compiled to obtain the branch node compilation result; the second logical operation is performed on the intermediate node compilation result and the branch node compilation result to obtain the lower-level node compilation result.

[0130] In this embodiment, the second compilation component is optionally configured to:

[0131] If the lower-level node bus is indirectly linked to the end node bus, the local ladder diagram between the lower-level node bus and the end node bus is further split until the node bus is directly linked to the end node bus after splitting; the PLC ladder diagram compilation result is obtained based on the lower-level node compilation result, the intermediate node compilation result, and the local ladder diagram compilation result of the lower-level node bus and the end node bus.

[0132] In this embodiment, optionally, the second compiling module 440 includes: an acquisition component, a third compiling component, and a calculation component.

[0133] Get component, used to get the flow branch set corresponding to the intermediate node bus if the intermediate node bus is directly linked to the end node bus.

[0134] The third compilation component is used to compile the local ladder diagram between the intermediate node bus and the end node bus based on the flow branch set corresponding to the intermediate node bus to obtain the end node compilation result.

[0135] The operation component is used to perform a second logic operation on the intermediate node compilation result and the end node compilation result to obtain the PLC ladder diagram compilation result.

[0136] The PLC ladder diagram compilation device provided by the present disclosure can execute the above method embodiments. Its specific implementation principles and technical effects can be found in the above method embodiments, and the present disclosure will not repeat them here.

[0137] The present application also provides a computer device. Figure 5 , Figure 5 This is a basic structural block diagram of the computer device in this embodiment.

[0138] The computer device includes a memory 510 and a processor 520 that are interconnected and communicate with each other via a system bus. It should be noted that the figure only shows a computer device with a memory 510 and a processor 520, but it should be understood that it is not required to implement all the components shown, and more or fewer components can be implemented instead. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to a microprocessor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), an embedded device, etc.

[0139] Computer devices can be desktop computers, laptops, PDAs, cloud servers, etc. Computer devices can interact with users through keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0140] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, a hard disk, a multimedia card, card-type memory (such as SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic storage, a magnetic disk, an optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of the computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, or a flash card equipped with the computer device. Of course, the memory 510 may also include both an internal storage unit of the computer device and an external storage device thereof. In this embodiment, the memory 510 is generally used to store an operating system and various application software installed on the computer device, such as the program code of the above-mentioned method. In addition, the memory 510 may also be used to temporarily store various types of data that have been output or are about to be output.

[0141] The processor 520 is generally used to perform the overall operation of the computer device. In this embodiment, the memory 510 is used to store program code or instructions, which include computer operating instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or process data, such as the program code for running the above method.

[0142] In this article, a bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. This bus system can be divided into address buses, data buses, control buses, and so on. For ease of illustration, the diagram uses only a single thick line, but this does not imply that there is only one bus or only one type of bus.

[0143] Another embodiment of the present application further provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads the computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method, and to generate a device that implements the functional actions specified in each block or combination of blocks in the block diagram.

[0144] Computer-readable media include but are not limited to electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any appropriate combination of the foregoing, the memory is used to store program codes or instructions, the program codes include computer operating instructions, and the processor is used to execute the program codes or instructions of the above-mentioned methods stored in the memory.

[0145] For the definitions of memory and processor, please refer to the description of the aforementioned computer device embodiment and will not be repeated here.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0147] Each functional unit or module in each embodiment of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software functional units.

[0148] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0149] In the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" described in the present application does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application can be implemented with the aid of hardware comprising several different elements and with the aid of a suitably programmed computer. In a unit claim that lists several devices, several units of these devices may be embodied by the same hardware item. The use of first, second, and third etc. does not indicate any order and these words may be interpreted as names. The steps in the above embodiments should not be understood as limiting the order of execution unless otherwise specified.

[0150] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.< / branch> < / branch> < / int>

Claims

1. A method for compiling a PLC ladder diagram, characterized in that: include: Obtaining an original PLC ladder diagram, and optimizing the diagram structure of the original PLC ladder diagram to obtain a target PLC ladder diagram, wherein the original PLC ladder diagram includes: a ladder diagram bus and a ladder diagram instruction, and the target PLC ladder diagram includes: an identification bus, an identification instruction, and an optimized structure, wherein the identification bus is obtained by encoding the ladder diagram bus, the identification instruction is obtained by encoding the ladder diagram instruction, and the optimized structure is used to describe a connecting line segment between the identification bus and the identification instruction; Based on the link relationship between each of the identified buses in the target PLC ladder diagram, the target PLC ladder diagram is split into a graph structure to obtain a local ladder diagram between a starting node bus and an intermediate node bus and a local ladder diagram between the intermediate node bus and an ending node bus, wherein the starting node bus is directly linked to the intermediate node bus; Compiling a local ladder diagram between the starting node bus and the intermediate node bus based on the flow direction branch set corresponding to the starting node bus to obtain an intermediate node compilation result; Based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus, a local ladder diagram between the intermediate node bus and the end node bus is program compiled to obtain a PLC ladder diagram compilation result; The step of compiling a local ladder diagram between the intermediate node bus and the end node bus based on the intermediate node compilation result and the flow branch set corresponding to the intermediate node bus to obtain a PLC ladder diagram compilation result includes: If the intermediate node bus is indirectly linked to the end node bus, the local ladder diagram between the intermediate node bus and the end node bus is split into a graph structure to obtain a local ladder diagram between the intermediate node bus and the lower-level node bus and a local ladder diagram between the lower-level node bus and the end node bus, and the intermediate node bus is directly linked to the lower-level node bus; Obtaining a flow direction branch set corresponding to the intermediate node bus, and based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus, compiling a local ladder diagram between the intermediate node bus and the lower-level node bus to obtain a lower-level node compilation result; Based on the lower-level node compilation result and the flow branch set corresponding to the lower-level node bus, the local ladder diagram between the lower-level node bus and the end node bus is program compiled to obtain the PLC ladder diagram compilation result.

2. The method according to claim 1, characterized in that Before compiling the local ladder diagram between the starting node bus and the intermediate node bus based on the flow direction branch set corresponding to the starting node bus, the method further includes: Obtaining a busbar list corresponding to different branch flow directions of the starting node busbar, wherein the busbar list corresponding to different branch flow directions of the starting node busbar includes: other identified buses having a flow direction relationship with the starting node busbar; The branch type is identified on the bus list corresponding to different branch flow directions of the starting node bus to obtain a flow direction branch set corresponding to the starting node bus. The flow direction branch set corresponding to the starting node bus includes: a merged branch, and / or a single branch, and the merged branch is composed of flow direction branches corresponding to at least two bus lists.

3. The method according to claim 2, characterized in that The program compiling of the local ladder diagram between the starting node bus and the intermediate node bus based on the flow direction branch set corresponding to the starting node bus to obtain the intermediate node compilation result includes: If the flow branch set corresponding to the starting node bus is used to describe the merged branch, logical conversion is performed on the identification instruction corresponding to each branch in the merged branch to obtain execution logic data of the identification instruction corresponding to each branch, and a first logical operation is performed on the execution logic data of the identification instruction corresponding to each branch to obtain the intermediate node compilation result; If the flow direction branch set corresponding to the starting node bus is used to describe the single branch, performing a logical conversion on the identification instruction corresponding to the single branch to obtain the intermediate node compilation result; If the flow branch set corresponding to the starting node bus is used to describe the merged branch and the single branch, the intermediate node compilation result is obtained based on the logical conversion result of the identification instruction corresponding to each branch in the merged branch and the logical conversion result of the identification instruction corresponding to the single branch.

4. The method according to claim 1, wherein The method of compiling a local ladder diagram between the intermediate node bus and the lower-level node bus based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus to obtain the lower-level node compilation result includes: Based on the flow direction branch set corresponding to the intermediate node bus, a local ladder diagram between the intermediate node bus and the lower-level node bus is program-compiled to obtain a branch node compilation result; A second logical operation is performed on the intermediate node compilation result and the branch node compilation result to obtain the lower-level node compilation result.

5. The method according to claim 1, wherein The method of compiling a local ladder diagram between the lower-level node bus and the end node bus based on the lower-level node compilation result and the flow branch set corresponding to the lower-level node bus to obtain the PLC ladder diagram compilation result includes: If the lower-level node bus is indirectly linked to the end node bus, the local ladder diagram between the lower-level node bus and the end node bus is further split until the node bus after splitting is directly linked to the end node bus; The PLC ladder diagram compilation result is obtained according to the lower-level node compilation result, the intermediate node compilation result, and the local ladder diagram compilation results of the lower-level node bus and the end node bus.

6. The method according to claim 3, characterized in that The method of compiling a local ladder diagram between the intermediate node bus and the end node bus based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus to obtain a PLC ladder diagram compilation result includes: If the intermediate node bus is directly connected to the end node bus, then obtaining the flow direction branch set corresponding to the intermediate node bus; Based on the flow direction branch set corresponding to the intermediate node bus, a local ladder diagram between the intermediate node bus and the end node bus is program compiled to obtain an end node compilation result; A second logic operation is performed on the intermediate node compilation result and the end node compilation result to obtain the PLC ladder diagram compilation result.

7. A PLC ladder diagram compiling device, characterized in that: include: An acquisition and optimization module is used to acquire an original PLC ladder diagram and optimize the diagram structure of the original PLC ladder diagram to obtain a target PLC ladder diagram, wherein the original PLC ladder diagram includes: a ladder diagram bus and a ladder diagram instruction; the target PLC ladder diagram includes: an identification bus, an identification instruction, and an optimized structure, wherein the identification bus is obtained by encoding the ladder diagram bus, the identification instruction is obtained by encoding the ladder diagram instruction, and the optimized structure is used to describe the connecting line segment between the identification bus and the identification instruction; A splitting module is used to split the target PLC ladder diagram into a graph structure based on the link relationship between each of the identified buses in the target PLC ladder diagram to obtain a local ladder diagram between the starting node bus and the intermediate node bus and a local ladder diagram between the intermediate node bus and the ending node bus, wherein the starting node bus is directly linked to the intermediate node bus; A first compiling module is configured to compile a local ladder diagram between the starting node bus and the intermediate node bus based on a flow direction branch set corresponding to the starting node bus, to obtain an intermediate node compilation result; A second compiling module is configured to compile a local ladder diagram between the intermediate node bus and the end node bus based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus to obtain a PLC ladder diagram compilation result; The second compilation module includes: a split component, a first compilation component, and a second compilation component; The splitting component is configured to split the local ladder diagram between the intermediate node bus and the end node bus if the intermediate node bus is indirectly linked to the end node bus, thereby obtaining a local ladder diagram between the intermediate node bus and the lower-level node bus and a local ladder diagram between the lower-level node bus and the end node bus, and the intermediate node bus is directly linked to the lower-level node bus; The first compilation component is configured to obtain a flow direction branch set corresponding to the intermediate node bus, and based on the intermediate node compilation result and the flow direction branch set corresponding to the intermediate node bus, compile a local ladder diagram between the intermediate node bus and the lower-level node bus to obtain a lower-level node compilation result; The second compilation component is used to compile the local ladder diagram between the lower-level node bus and the end node bus based on the lower-level node compilation result and the flow branch set corresponding to the lower-level node bus to obtain the PLC ladder diagram compilation result.

8. A computer device, characterized in that: The method comprises a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the method for compiling a PLC ladder diagram as claimed in any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for compiling a PLC ladder diagram as described in any one of claims 1 to 6 is implemented.

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