Binary translation method, translator, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: carrying out binary translation on a first code block to obtain a first translated code block, and determining a target state tag corresponding to the first code block during translation; when an indirect jump instruction in the first translation code block is executed, querying a quick lookup table according to a jump target address of the indirect jump instruction; when the quick lookup table is not hit, querying a first hash table corresponding to the target state tag according to a jump target address of the indirect jump instruction; the first hash table is used for recording a pointer of the translation code block matched with the target state tag, and the pointer points to an entry address of the translation code block. According to the embodiment of the invention, the code block searching efficiency can be improved, so that the execution efficiency of the indirect jump instruction is improved, and the performance of the system-level binary translator is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and particularly to a binary translation method, a translator, an electronic device, and a readable storage medium. Background Art

[0002] Binary translation can convert binary code of one ISA (Instruction Set Architecture) into binary code of another instruction set architecture. Through binary translation technology, an application program of one ISA (source architecture) can run on another ISA (target architecture).

[0003] Generally, the client is used to represent the platform to which the program to be emulated belongs, and the host is used to represent the platform on which the binary translation system runs, that is, the binary translation system can emulate and run the client program on the host. According to the level where the emulated program is located, it can be classified into user-level binary translation and system-level binary translation. User-level binary translation supports running client application programs, and system-level binary translation supports running a complete client operating system, so as to realize the running of any client application program.

[0004] The jump target address of an indirect jump instruction does not give a fixed address, but is determined by a value in a register or memory during the running process. In system-level binary translation, to find the translated code block to which the indirect jump instruction is to jump, it is necessary to dynamically parse the jump target address and verify its validity, and this process usually requires a relatively high cost, which affects the program execution efficiency. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a binary translation method that can overcome the above problems or at least partially solve the above problems, which can improve the code block search efficiency, and further improve the execution efficiency of indirect jump instructions and the performance of the system-level binary translator.

[0006] Correspondingly, embodiments of the present invention also provide a binary translator, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, embodiments of the present invention disclose a binary translation method, which is applied to a system-level binary translator, and the method includes: Performing binary translation on a first code block to obtain a first translated code block, and determining a target state tag of the first translated code block; the target state tag is used to identify the processor state corresponding to the first code block during translation; When executing the indirect jump instruction in the first translation code block, query the fast lookup table according to the jump target address of the indirect jump instruction; the fast lookup table is used to record pointers to translation code blocks corresponding to recently used jump target addresses; the pointer points to the entry address of the translation code block. In the case of a miss in the fast lookup table, query the first hash table corresponding to the target status label according to the jump target address of the indirect jump instruction; the first hash table is used to record pointers to translation code blocks that match the target status label.

[0008] In a second aspect, an embodiment of the present invention discloses a system-level binary translator, which includes: A status label determination module, configured to perform binary translation on a first code block to obtain a first translation code block, and determine a target status label of the first translation code block; the target status label is used to identify the processor status corresponding to the first code block during translation. A first-level lookup module, configured to query a fast lookup table according to the jump target address of the indirect jump instruction when executing the indirect jump instruction in the first translation code block; the fast lookup table is used to record pointers to translation code blocks corresponding to recently used jump target addresses; the pointer points to the entry address of the translation code block. A second-level lookup module, configured to query the first hash table corresponding to the target status label according to the jump target address of the indirect jump instruction in the case of a miss in the fast lookup table; the first hash table is used to record pointers to translation code blocks that match the target status label.

[0009] In a third aspect, an embodiment of the present invention discloses an electronic device, including: a processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the binary translation method as described in any one of the foregoing.

[0010] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, it can implement the binary translation method as described in any one of the foregoing.

[0011] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, and when the computer program is executed by a processor, it is the steps of the binary translation method as described in any one of the foregoing.

[0012] The embodiments of the present invention have the following advantages: In the embodiment of the present invention, the target status label of the first translation code block is determined during the translation stage. When an indirect jump instruction in the first translation code block is executed, a hierarchical search is performed on the second translation code block to which the jump is to be made. The first-level search queries a fast lookup table according to the jump target address of the indirect jump instruction. In the case where the fast lookup table is not hit, a second-level search is executed. The second-level search queries a first hash table corresponding to the target status label according to the jump target address of the indirect jump instruction. If the first hash table is hit, a direct jump can be made. The target status label is determined during translation. Thus, during the code block search process, it is not necessary to detect the status label of the translation code block, thereby eliminating the overhead of dynamically detecting the status label during runtime, improving the code block search efficiency, further improving the execution efficiency of the indirect jump instruction, and enhancing the performance of the system-level binary translator. Description of the Drawings

[0013] Figure 1 is a flowchart of the steps of an embodiment of a binary translation method of the present invention; Figure 2 is a schematic diagram of the overall architecture of code block search in an embodiment of the present invention; Figure 3 is a schematic diagram of the process of the second-level search in an example of the present invention; Figure 4 is a schematic diagram of the address conversion of a software instruction TLB in an example of the present invention; Figure 5 is a block diagram of the structure of an embodiment of a system-level binary translator of the present invention; Figure 6 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed Embodiments

[0014] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] The terms "first", "second", etc. in the description and claims of the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the description and claims is used to describe the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally means that the associated objects before and after are in an "or" relationship. In the embodiments of the present invention, the term "plural" means two or more, and other quantifiers are similar.

[0016] First, some concepts involved in the embodiments of the present invention will be explained.

[0017] A code block refers to a continuous sequence of instructions (composed of guest instructions) extracted from the executable binary code of a guest program, and it is the basic processing unit of binary translation. A code block is also called a basic block, which has only one entry (the entry is the first instruction) and one exit (the exit is the last instruction), and there will be no jump instructions in the middle. Except for the last instruction (such as a jump instruction, a call instruction, a return instruction), other instructions are executed sequentially, without jumping out or being jumped in.

[0018] A translated code block refers to a code block after binary translation, that is, the guest instructions in the code block are translated into host instructions. Translated code blocks are usually cached in the code cache for subsequent direct execution to avoid repeated translation.

[0019] A guest virtual address (GVA) is the virtual memory address used by a guest program, that is, the logical address of program code and data.

[0020] A guest physical address (GPA) is the address obtained by the guest operating system after converting the GVA through its memory management unit (MMU), and it is the "physical address" considered by the guest operating system or the runtime environment. The guest operating system maps the GVA to the GPA, but these addresses are not real physical addresses, but are further mapped to the host address space by the binary translator or the virtualization layer.

[0021] A page is the basic unit of operating system memory management and is usually a memory block of a fixed size (such as 4KB). In the memory management of an operating system, to effectively manage memory, the memory (virtual memory or physical memory) is divided into pages of a fixed size.

[0022] A virtual page is a division unit of the virtual memory space and is mapped to a physical page through a page table.

[0023] A physical page is a division unit of the physical memory space and is the memory block that actually stores data.

[0024] The guest virtual address GVA consists of a virtual page number (VPN) and an offset within the page. The virtual page number VPN is used to locate the virtual page, and the offset within the page is used to locate the specific byte within the virtual page.

[0025] The guest physical address GPA consists of a page frame number (PFN) and an offset within the page. The page frame number PFN is used to locate the physical page, and the offset within the page is used to locate the specific byte within the physical page, which is exactly the same as the offset within the virtual page (because the virtual page and the physical page have the same size).

[0026] The guest virtual address GVA can obtain the corresponding page frame number PFN through page table mapping, and then combine it with the offset within the page to generate the GPA, realizing the conversion from virtual memory to physical memory.

[0027] Binary translation mainly includes the following three steps: code block search, code block translation, and code block execution. The code block translation process is to translate guest instructions into host instructions through binary translation technology, which is the key to achieving cross-architecture operation. Usually, the translation result is called a translated code block, and the translated code block is stored in the code cache after translation. The code block search process is to search for existing translated code blocks in the code cache. If the required translated code block is found, it can be directly obtained, which can avoid repeated translation and reduce overhead. The code block execution process is to switch the translated code block to be executed to the host processor for execution, thereby realizing the simulated execution of guest instructions. The efficiency of a binary translation system is closely related to the operating efficiency of these three parts.

[0028] Refer to Figure 1 , which shows the flowchart of the steps of an embodiment of a binary translation method of the present invention. The method is applied to a system-level binary translator, and the method may include the following steps: Step 101: Perform binary translation on the first code block to obtain a first translated code block, and determine the target status label of the first translated code block; the target status label is used to identify the processor status corresponding to the first code block during translation. Step 102: When an indirect jump instruction in the first translated code block is executed, query a fast lookup table according to the jump target address of the indirect jump instruction; the fast lookup table is used to record pointers to translated code blocks corresponding to the most recently used jump target addresses; the pointer points to the entry address of the translated code block. Step 103: In the case of a miss in the fast lookup table, query a first hash table corresponding to the target status label according to the jump target address of the indirect jump instruction; the first hash table is used to record pointers to translated code blocks that match the target status label.

[0029] The binary translation method provided by the embodiments of the present invention can be applied to a system-level binary translator to optimize the execution efficiency of indirect jump instructions during binary translation. The jump target address of an indirect jump instruction does not give a fixed address, but is determined by the value in a register or memory during operation.

[0030] In the embodiments of the present invention, the first code block refers to a code block ending with an indirect jump instruction. The first translated code block refers to the translation result obtained by performing binary translation on the first code block. The second code block refers to the target code block to which the indirect jump instruction in the first code block jumps. The second translated code block refers to the translation result obtained by performing binary translation on the second code block.

[0031] In system-level binary translation, a client virtual address, a client physical address, and a status label are required to uniquely identify a code block. The status label is used to represent the processor status of the code block during translation, and the code block can run only when the simulated client processor status matches it.

[0032] The processor status (client status) refers to the hardware or software environment in which the client processor is located when executing an instruction, and these statuses will affect the execution semantics of the instruction. The processor status includes, but is not limited to, the following: privilege levels, such as Ring0 (kernel mode) and Ring3 (user mode) in the x86 architecture, or EL0 (user mode), EL1 (kernel mode), etc. in the ARM architecture; memory management statuses, such as paging mechanisms, address spaces, TLB (Translation Lookaside Buffer) statuses, etc.; interrupt / exception statuses, such as interrupt masking (EFLAGS.IF), deferred exception handling, etc.

[0033] For example, when an indirect jump instruction in the first translated code block is executed, the indirect jump instruction is to jump to the second code block. If the second code block has been translated and the second translated code block is stored in the code cache, and the client virtual address, client physical address, and status tag of the second translated code block all match the current client processor state, then it can directly jump to the entry address of the second translated code block for execution.

[0034] In the embodiments of the present invention, the client virtual address of the translated code block refers to the client virtual address of the first instruction in the translated code block. The client physical address of the translated code block refers to the client physical address corresponding to the client virtual address of the first instruction under the address mapping relationship during translation. The status tag of the translated code block represents the client processor state during translation. In the system-level binary translation system, the code block search process needs to check that the client virtual address, client physical address, and status tag of the translated code block are all correct to determine that the found translated code block is the translated code block to be executed.

[0035] When an indirect jump instruction in the first translated code block is executed, it is necessary to search for the translated code block to be executed according to the jump target address of the indirect jump instruction, and this process is called the code block search process. The code block search process needs to compare the client virtual address, client physical address, and status tag of the translated code block. For example, when a second translated code block is found according to the jump target address of the indirect jump instruction, it is necessary to detect whether the client virtual address of the second translated code block is the same as the jump target address of the indirect jump instruction, whether the client physical address of the second translated code block is the same as the physical address corresponding to the jump target address of the indirect jump instruction under the current address mapping relationship, and whether the status tag of the second translated code block matches the current client processor state, resulting in a relatively high search cost and affecting the search efficiency.

[0036] To improve the code block search efficiency and thus improve the execution efficiency of the indirect jump instruction, the embodiments of the present invention determine the status tag of the code block during the translation stage and propose a hierarchical search method. The first-level search is to query the fast search table according to the jump target address of the indirect jump instruction. In the case of a miss in the fast search table, the second-level search is executed. The second-level search is to query the first hash table corresponding to the target status tag according to the jump target address of the indirect jump instruction. If the first hash table is hit, it can directly jump; otherwise, it can continue to execute the next-level search. Among them, the target status tag is determined during translation. Therefore, during the code block search process, the status tag comparison operation does not need to be executed, which can improve the search efficiency, and further improve the execution efficiency of the indirect jump instruction and the performance of the system-level binary translator.

[0037] In the process of binary translation of the first code block in an embodiment of the present invention, a target status tag corresponding to the first code block during translation is determined, and this target status tag is the status tag of the first translated code block. Since an indirect jump does not change the state of the client processor, the state of the client processor during the translation of the first code block is the same as that during the translation of the second code block. That is, the status tag of the first translated code block is the same as the status tag of the second translated code block.

[0038] After the first translated code block is obtained by completing the translation of the first code block, the first translated code block is executed. When an indirect jump instruction is executed, a first-level search is first performed, and a fast lookup table is queried according to the jump target address of the indirect jump instruction.

[0039] The jump target address of the indirect jump instruction is the address of the first client instruction of the second code block, and this address is a client virtual address. The fast lookup table is a cache structure with a small capacity and is private. For example, it can be a hash table, which is used to store pointers to recently used translated code blocks and is indexed by the jump target address (or the low bits of the jump target address). Each table entry contains a key and a value. The key is the client virtual address, that is, the jump target address; the value is the pointer to the translated code block corresponding to this client virtual address. In this way, when the same jump target address is encountered again, by querying the fast lookup table with this jump target address, the corresponding translated code block can be directly obtained from the fast lookup table, avoiding repeated translation and improving execution efficiency.

[0040] It should be noted that since the fast lookup table does not distinguish status flags, when querying the fast lookup table with the jump target address of the indirect jump instruction, it is necessary to determine whether the status tag of the translated code block pointed to by the found table entry is consistent with the target status tag of the first translated code block. When the two are consistent, it is determined that the fast lookup table hits and a direct jump can be made.

[0041] The fast lookup table is private to the processor core and is indexed by the client virtual address, without the need for address conversion or hash calculation. Therefore, it has the characteristics of fast lookup speed and low latency. In the case of multiple processor cores, each processor core has its own private fast lookup table. The fast lookup table can be an array or a hash table of a fixed size. The capacity of the fast lookup table can be set according to actual needs. Usually, the capacity of the fast lookup table is small and is only used to record frequently accessed translated code blocks. When a new entry needs to be inserted when the capacity of the fast lookup table is full or there is an index value conflict, it can be directly replaced at the position of the corresponding index value, avoiding the efficiency impact brought by using a replacement algorithm.

[0042] In one example, assume that the index value calculated based on the lower bits of the jump target address is 12. Then, the 12th entry in the fast lookup table is searched. Assume that the entry stores a pointer to the translation code block TB1. If the search misses, the next-level search is performed. When the next-level search hits, the pointer to the found translation code block, such as TB2, is filled back into the 12th entry of the fast lookup table, and the pointer to the translation code block TB1 in this entry is directly replaced with the pointer to the translation code block TB2.

[0043] In the case where the fast lookup table misses, a second-level search is performed, and the first hash table corresponding to the target status label is queried according to the jump target address of the indirect jump instruction. The fast lookup table misses means that in the fast lookup table, no entry corresponding to the jump target address of the indirect jump instruction is found, or the status label of the translation code block pointed to by the found entry is inconsistent with the target status label of the first translation code block, or the client virtual address of the translation code block pointed to by the found entry is inconsistent with the jump target address.

[0044] Embodiments of the present invention can establish first hash tables corresponding to different status labels, and each first hash table is initially empty. In the case where the first hash table misses, the next-level search is performed, and when the next-level search hits, the first hash table is filled back. Among them, the same first hash table is used to record pointers to translation code blocks with the same status label, and different first hash tables correspond to different status labels.

[0045] Embodiments of the present invention can eliminate the overhead of dynamically detecting status labels at runtime and improve the code block search efficiency by constructing first hash tables corresponding to different status labels and completing the matching of status labels during translation.

[0046] It can be understood that embodiments of the present invention do not limit the types of status labels, nor the number of constructed first hash tables. In specific implementations, preset status labels can be set according to actual needs, and first hash tables are established for each preset status label respectively. Exemplarily, embodiments of the present invention set the preset status labels to include Fa and Fb, then a first hash table corresponding to the status label Fa and a first hash table corresponding to the status label Fb are established. Among them, the first hash table corresponding to the status label Fa records pointers to translation code blocks with the status label Fa. The first hash table corresponding to the status label Fb records pointers to translation code blocks with the status label Fb.

[0047] Among them, the pointer to the translation code block points to the entry address of the translation code block, so that it can directly jump to the entry address of the translation code block to execute the translation code block.

[0048] In one example, during the translation phase, it has been determined that the target status label of the first translation code block is Fa. Then, when executing the indirect jump instruction in the first translation code block and the first-level lookup fails, directly query the first hash table corresponding to the status label Fa according to the jump target address of the indirect jump instruction. Since the first hash table corresponding to the status label Fa records only the pointers of the translation code blocks with the status label Fa, and the first translation code block and the second translation code block have the same status label, during the process of querying the first hash table, there is no need to compare the status labels, and it is only necessary to ensure that the client virtual address and the client physical address match, which can eliminate the overhead of dynamically detecting the status label during runtime and improve the code block lookup efficiency.

[0049] In the case of a hit in the first hash table, the hit table entry contains the pointer to the second translation code block to which the indirect jump instruction is to jump, so that it can directly jump to the entry address of the second translation code block for execution.

[0050] In the code block lookup process of the embodiments of the present invention, a hierarchical lookup method is used. In the case where the first-level fast lookup table fails to hit, a second-level lookup method based on the status label is proposed, and the status label matching is completed during translation. The second-level lookup process does not need to detect the status label, which can improve the efficiency of the second-level lookup. In the case where the second-level lookup (first hash table lookup) fails to hit, a more comprehensive and slower third-level lookup is then performed.

[0051] The embodiments of the present invention do not limit the specific manner of the third-level lookup. The third-level lookup may include: querying a second hash table according to the jump target address; the second hash table is used to record the correspondence between the client virtual address, the client physical address, and the status label of the translation code block. The second hash table may be a global hash table for recording all translation code blocks to ensure global coverage.

[0052] Exemplarily, the third-level lookup process can be as follows: perform address translation on the jump target address (denoted as PC1 for example) to obtain the corresponding client physical address (denoted as physPC1 for example); comprehensively calculate the target hash value based on the jump target address PC1, the client physical address physPC1, and the current client processor status flags1; query the second hash table according to the target hash value; compare the client virtual address (denoted as PC2 for example), the client physical address (denoted as physPC2 for example), and the status label (denoted as flags2 for example) recorded in the found table entry; if PC2 is consistent with PC1, physPC2 is consistent with physPC1, and flags2 is consistent with flags1, it is determined that the second hash table is hit, and directly jump to the entry address of the translated code block recorded in the hit table entry for execution.

[0053] Refer to Figure 2 , which shows the overall architecture diagram of code block lookup in an embodiment of the present invention. As Figure 2 shown, the code lookup process in the embodiment of the present invention includes three levels of lookup. The first level is based on a fast lookup table for lookup, the second level is based on a first hash table for lookup, and the third level is based on a second hash table for lookup. When each level of lookup is hit, it can jump to the found translated code block for execution. When the third-level lookup fails, it means that the required translated code block has not been generated yet, and it is necessary to exit the code block execution process and enter the code block translation process.

[0054] In a specific implementation, the lookup tables of the first level (fast lookup table) and the second level (first hash table) are used to cache the pointers of the translated code blocks that are frequently accessed recently, so as to accelerate the access speed of the most recently used translated code blocks. The capacities of the fast lookup table and the first hash table can be set according to actual needs. The lookup table of the third level (second hash table) is used to record all translated code blocks and manage the global status of all translated code blocks. The capacity of the second hash table needs to cover the maximum number of translated code blocks that may be generated during the system operation.

[0055] Refer to Figure 3 , which shows the flowchart of the second-level lookup in an example of the present invention. As Figure 3 shown, assume that a first hash table corresponding to the status label Fa (denoted as the first hash table Fa for example) and a first hash table corresponding to the status label Fb (denoted as the first hash table Fb for example) are established. The first hash table Fa and the first hash table Fb respectively store the pointers of the translated code blocks with the status labels Fa and Fb.

[0056] For all translation code blocks with the target state label Fa, such as translation code block A, its indirect jump instruction will jump to the first lookup code for the state label Fa for execution. The first lookup code is used to perform a three-level lookup. The first level is based on a fast lookup table for lookup, the second level is based on the first hash table Fa for lookup, and the third level is based on the second hash table for lookup.

[0057] For all translation code blocks with the target state label Fb, such as translation code block B, its indirect jump instruction will jump to the second lookup code for the state label Fb for execution. The second lookup code is used to perform a three-level lookup. The first level is based on a fast lookup table for lookup, the second level is based on the first hash table Fb for lookup, and the third level is based on the second hash table for lookup.

[0058] In a specific implementation, for a target state label for which the first hash table is not established, it is called the default state label. In the case where the target state label of the first translation code block is the default state label, a two-level lookup can be performed. The first level is based on a fast lookup table for lookup, and the second level is based on the second hash table for lookup, so as to ensure that the code block lookup process can be correctly executed even when there is no first hash table corresponding to the target state label.

[0059] For example, for translation code block C with the state label Fc, its indirect jump instruction will jump to the third lookup code for the default state label for execution. The third lookup code is used to perform a two-level lookup. The first level is based on a fast lookup table for lookup, and the second level is based on the second hash table for lookup.

[0060] In this example, there are three types of lookup codes in total, namely the first lookup code for the state label Fa, the second lookup code for the state label Fb, and the third lookup code for the default state label. Two first hash tables are established in total, which respectively store the pointers of the translation code blocks of the state label Fa and the state label Fb. In a specific implementation, according to the types and quantities of the preset state labels, the types and quantities of the established first hash tables can be different, and the corresponding lookup codes can also be different. The embodiments of the present invention do not limit this.

[0061] Since the state label of the translation code block can be determined during translation, the lookup code corresponding to its indirect jump instruction can also be determined during translation. Therefore, an instruction to jump to the corresponding lookup code can be generated during translation, so as to jump to the corresponding lookup code for execution when the indirect jump instruction is executed.

[0062] It should be noted that the types and quantities of the preset status tags (such as Fa and Fb) can be determined according to the client system. For example, for client system A, 90% of the code blocks have the status tag Fa, and the distribution of the status tags of the remaining code blocks is relatively scattered. Only one first hash table with the status tag Fa needs to be established to cover the lookups of 90% of the code blocks. Therefore, Fa can be used as the preset status tag. For another client system B, 50% of the code blocks have the status tag Fa, and 40% of the code blocks have the status tag Fb. Then, a first hash table corresponding to the status tag Fa and a first hash table corresponding to the status tag Fb need to be established. A total of two first hash tables need to be established to cover the lookups of 90% of the code blocks. Therefore, Fa and Fb can be used as the preset status tags. The specific selection can be set by itself according to the differences of the client systems, and the coverage ratio is not limited to 90%.

[0063] In an alternative embodiment of the present invention, the querying of the first hash table corresponding to the target status tag according to the jump target address of the indirect jump instruction may include: Step S11: Perform address conversion on the jump target address to obtain a first physical address; Step S12: Calculate a first index value according to the jump target address and the first physical address; Step S13: Query the first hash table corresponding to the target status tag based on the first index value. If a first table entry is found, and the client virtual address of the second translated code block pointed to by the first table entry is the same as the jump target address, and the second physical address of the second translated code block is the same as the first physical address, it is determined that the first hash table hits.

[0064] The second-level lookup (lookup based on the first hash table) in the embodiment of the present invention includes three stages. In the first stage, perform address conversion on the jump target address to obtain the first physical address under the current address mapping relationship. In the second stage, calculate a first index value according to the jump target address and the first physical address, and query the first hash table corresponding to the target status tag based on the first index value. In the third stage, if a first table entry is found, compare whether the client virtual address of the second translated code block pointed to by the first table entry is the same as the jump target address, and whether the second physical address of the second translated code block is the same as the first physical address. Only when both are the same is it considered that the first hash table lookup hits.

[0065] In the embodiments of the present invention, the code block search process of the indirect jump instruction includes three-level search. The first level is to search the fast search table. If a hit occurs, jump to the found second translation code block; if no hit occurs, perform the next-level search. The second level is to search the first hash table corresponding to the target status tag. First, perform address conversion on the jump target address to obtain the first physical address; perform hash calculation based on the jump target address and the first physical address to obtain the first index value; search the first hash table based on the first index value; if a hit occurs, jump to the found second translation code block; if no hit occurs, perform the next-level search. The third level is to search the second hash table, which requires comparing the client virtual address, the client physical address, and the status tag. If a hit occurs, jump to the found second translation code block; if no hit occurs, exit the code block execution process and enter the code block translation process.

[0066] Among them, the first-level search directly searches based on the jump target address, and it is necessary to compare the client virtual address and the status tag of the translation code block, without the need for address conversion. The second-level search requires address conversion, and calculates the index value of the first hash table according to the jump target address and the first physical address to search for the corresponding table entry in the first hash table. If the corresponding table entry is not found, or the second translation code block pointed to by the found table entry fails the detection, it is determined that the second-level search misses. Among them, the second translation code block fails the detection, which means that the client virtual address of the second translation code block is different from the jump target address, and / or the second physical address of the second translation code block is different from the first physical address. When the second-level search hits, first backfill the hit table entry into the search table of the first level to ensure the hit rate of the first level, and then continue to execute. The second-level search does not need to compare the status tag of the translation code block. The third-level search requires address conversion, and calculates the index value of the second hash table according to the jump target address, the converted physical address, and the status tag to search for the corresponding table entry in the second hash table. If the corresponding table entry is not found, or the second translation code block pointed to by the found table entry fails the detection, both are determined that the third-level search misses. When the third-level search hits, first backfill the hit table entry into the search tables of the first level and the second level respectively to ensure the hit rates of the first level and the second level, and then continue to execute. The third-level search needs to compare the client virtual address, the client physical address, and the status tag of the translation code block.

[0067] The first-level search is the fastest search, the third-level search is the slowest but the most comprehensive search, the second-level search is between the two, and the three-level searches cooperate with each other to improve the execution efficiency of the indirect jump instruction.

[0068] In an alternative embodiment of the present invention, the performing address conversion on the jump target address to obtain the first physical address may include: Step S21: Extract the first preset bit of the virtual page number of the jump target address to obtain a second index value; Step S22: Query the address translation table based on the second index value; the address translation table is used to record the correspondence between the virtual page number of the client virtual address and the physical page frame number of the client physical address; Step S23: If a second entry is found and the virtual page number of the client virtual address stored in the second entry is the same as the virtual page number of the jump target address, determine a first physical address according to the physical page frame number of the client physical address stored in the second entry and the page offset within the jump target address.

[0069] The second-level lookup in the embodiments of the present invention includes three stages. To further improve the efficiency of the second-level lookup, each stage of the second-level lookup in the embodiments of the present invention is further optimized to improve the execution efficiency of each stage.

[0070] TLB (Translation Lookaside Buffer) is a cache in the computer memory management unit (MMU) used to accelerate the virtual address to physical address conversion process.

[0071] For the first stage, perform address conversion on the jump target address to obtain a first physical address. To improve the address conversion efficiency, the embodiments of the present invention propose a software instruction TLB with a simpler structure, which is called an address translation table in the embodiments of the present invention, to simulate the address conversion of the client instruction fetch behavior, thereby accelerating the jump target address conversion process of the indirect jump instruction. Further, the address translation table is private to the processor core, that is, in the case of multiple processor cores, each processor core has its own private address translation table.

[0072] In a computer system, a page is the basic unit of operating system memory management, usually a memory block of a fixed size (such as 4KB). A virtual address includes two parts: a virtual page number and a page offset within the page. The high-order part of the virtual address is the virtual page number, which is used to locate the virtual page. The low-order part of the virtual address is the page offset within the page, which is used to locate the specific byte within the virtual page. Taking a 4KB-sized page as an example, bits 12 - 47 of the virtual address are the virtual page number, and bits 0 - 11 are the page offset within the page.

[0073] Refer to Figure 4 , which shows the address conversion schematic diagram of the software instruction TLB in an example of the present invention. As Figure 4As shown, each entry of the software instruction TLB is used to record the correspondence between the virtual page and the physical page, that is, the recording unit is a page rather than a specific address. Specifically, each entry of the software instruction TLB stores the correspondence between the virtual page number of the guest virtual address and the physical page frame number of the guest physical address. Since the software instruction TLB only records the correspondence between the virtual page and the physical page, the page offset is 0. For the jump target address of the indirect jump instruction, the embodiment of the present invention uses Figure 4 the software instruction TLB shown to convert this jump target address into a physical address to accelerate the address conversion process.

[0074] In the embodiment of the present invention, the first preset bits in the virtual page number of the virtual address are used as the index value to query the address translation table. For example, taking a page with a size of 4KB as an example, bits 12-47 of the virtual address are the virtual page number, and bits 12-19 can be used as the first preset bits. Specifically, bits 12-19 of the virtual page number of the jump target address are extracted to obtain a second index value. The address translation table is queried with this second index value. If a second entry is queried, it is necessary to compare the virtual page number of the guest virtual address stored in the queried second entry with the virtual page number of the jump target address to determine whether they are the same to avoid hash conflicts. If the virtual page number of the guest virtual address stored in the queried second entry is the same as the virtual page number of the jump target address, the address translation table hits.

[0075] Since the address translation table stores the correspondence between the virtual page number of the guest virtual address and the physical page frame number of the guest physical address, therefore, the physical page frame number of the guest physical address corresponding to the virtual page number of the jump target address can be read from the queried second entry. Then, based on the physical page frame number of the guest physical address read and the page offset of the jump target address, the first physical address can be determined. For example, performing an or operation on the physical page frame number of the guest physical address read and the page offset of the jump target address can obtain the first physical address, and this first physical address is the guest physical address obtained by performing address conversion on the jump target address.

[0076] In one example, assume that the jump target address is 0x456ab123. Then the virtual page number of the jump target address 0x456ab123 is 0x456ab000, and the offset within the page is 0x00000123. Extract the first preset bits (such as bits 12 - 19) of the virtual page number to obtain a second index value of 0xab, which corresponds to the 0xabth entry in the address translation table. Therefore, based on the second index value 0xab, query the address translation table, and the second table entry found is the 0xabth entry. Assume that the virtual page number of the client virtual address stored in the 0xabth entry is 0x456ab000. Since the virtual page number of the client virtual address of the jump target address 0x456ab123 is also 0x456ab000. Therefore, the address translation table lookup hits, and the physical page frame number of the client physical address recorded in this second table entry is obtained, assumed to be 0x123cd000. Perform an OR operation on the physical page frame number 0x123cd000 of the queried client physical address and the offset within the page (0x00000123) of the jump target address, and the first physical address obtained is 0x123cd123.

[0077] It should be noted that taking bits 12 - 19 of the virtual page number of the virtual address as the first preset bits is only for illustrative purposes, and the scope of the first preset bits is not limited in the embodiments of the present invention. The first preset bits should be within the range of the virtual page address. For example, for a 4KB - sized virtual page, the first preset bits should be above 12 bits; for a 16KB - sized virtual page, the first preset bits should be above 14 bits.

[0078] In an alternative embodiment of the present invention, the method may further include: If the address translation table lookup misses, then after performing address translation on the jump target address in the next - level lookup, write the correspondence between the physical page frame number of the converted first physical address and the virtual page number of the jump target address into the address translation table.

[0079] The address translation table lookup miss means that when querying the address translation table based on the second index value, the second table entry corresponding to the second index value is not found, or the second table entry is found, but the virtual page number of the client virtual address stored in this second table entry is different from the virtual page number of the jump target address.

[0080] In the case where the address translation table lookup misses, it will cause the second - level lookup to miss, and then perform the next - level lookup, that is, perform the third - level lookup. During the third - level lookup, the jump target address will be address - translated to obtain the corresponding first physical address. At this time, the correspondence between the physical page frame number of this first physical address and the virtual page number of the jump target address can be written into the address translation table to update the address translation table, and then continue to execute.

[0081] In the embodiment of the present invention, by adding a second-level lookup for the first hash table corresponding to the target status tag and performing address translation in the second-level lookup, an address translation table with a simpler structure is used, so that the second-level lookup is not affected by the switching of the client address space. When the client address space switches, the mapping relationship between the virtual address and the physical address may change. Therefore, for the first-level lookup, since the first-level lookup does not perform address translation and only relies on the client virtual address for lookup, when the client address space switches, the translation code blocks stored in the fast lookup table can no longer be used and need to be cleared, resulting in the need to repeatedly rebuild the fast lookup table and increasing the overhead of refreshing the fast lookup table. For the second-level lookup, since the second-level lookup needs to perform address translation, when the client address space switches, the client physical addresses of the translation code blocks stored in the first hash table are correct and not affected, and there is no need to clear the first hash table, which can avoid repeatedly rebuilding the first hash table, reduce the overhead of refreshing the first hash table, and thus improve the performance of the translator.

[0082] In the embodiment of the present invention, at each level except the first level, when the lookup hits, the lookup result can be backfilled into the lookup table of the previous level to achieve lookup acceleration.

[0083] Specifically, when the first-level lookup misses, the second-level lookup will be executed; if the second-level lookup hits, before continuing to execute, the pointer of the found translation code block can be backfilled into the entry of the first-level lookup table (such as the fast lookup table). In this way, when looking up this translation code block next time, the first-level lookup will hit this entry, thus improving the lookup efficiency. Correspondingly, if the second-level lookup misses, the third-level lookup will be executed; if the third-level lookup hits, before continuing to execute, the pointer of the found translation code block can be backfilled into the entry of the first-level lookup table (such as the fast lookup table), and backfilled into the entry of the second-level lookup table (such as the first hash table).

[0084] In the embodiment of the present invention, the fast lookup table is private to each processor core, and the first hash table and the second hash table are shared by multiple processor cores. In the case of multiple processor cores, multiple processor cores can share a first hash table and a second hash table, which can save memory space.

[0085] When the client address space switches, such as when a process running on a certain processor core switches to another process, the mapping relationship between the virtual address and the physical address of the new process may change. At this time, the fast lookup table and the software instruction TLB (address translation table) need to be refreshed, such as clearing the original fast lookup table and software instruction TLB (address translation table) and rebuilding them.

[0086] In one example, assume that it is necessary to find the second translation code block A corresponding to the jump target address (such as 0xab123) of an indirect jump instruction. In the case of a client address space switch, since the fast lookup table and the software instruction TLB (address translation table) have been cleared, the first-level lookup misses. The second-level lookup also misses because the address translation table misses. Assume that the third-level lookup hits. Then, the jump target address (such as 0xab123) and the pointer to the found second translation code block A are filled back into the first-level fast lookup table as table entries. And the virtual page number (such as 0xab000) of the jump target address (such as 0xab123) and the physical page number of the corresponding client physical address are written into the software instruction TLB (address translation table); and the jump target address (such as 0xab123), the corresponding client physical address, and the pointer to the second translation code block A are filled back into the first hash table of the second level as table entries.

[0087] In this way, the next time it is necessary to find the second translation code block B corresponding to the jump target address (such as 0xab456) of an indirect jump instruction, since the first-level fast lookup table only contains the table entry corresponding to the jump target address 0xab123, the first-level lookup misses. The second-level lookup is executed. Since each table entry of the software instruction TLB (address translation table) used for address translation in the second-level lookup is recorded in units of pages, at this time, there is already a table entry corresponding to the virtual page number (such as 0xab000) in the software instruction TLB (address translation table). The jump target address 0xab456 and the jump target address 0xab123 are on the same virtual page. Therefore, their virtual page numbers are the same, both 0xab000. Therefore, the table entry corresponding to the jump target address (such as 0xab456) can be found in the software instruction TLB (address translation table), and then the first physical address corresponding to the jump target address (such as 0xab456) can be obtained. Based on the jump target address 0xab456 and the first physical address, the first index value can be calculated, and then the first hash table can be queried. If the first hash table hits, the first-level fast lookup table is filled back and the jump is directly executed.

[0088] In the embodiments of the present invention, each table entry of the software instruction TLB (address translation table) records the correspondence between the virtual page and the physical page, with pages as the recording unit. Therefore, each time a table entry is updated, it includes the correspondence between all the client virtual addresses and the client physical addresses on that page. In the case of a client address space switch, although the first-level fast lookup table fails, the first hash table of the second level is still valid and can still perform a fast lookup, avoiding the situation where only the slowest third-level lookup can be executed when the first-level lookup misses, which can improve the lookup hit rate and thus improve the lookup efficiency.

[0089] It should be noted that for the first-level fast lookup table and the first hash table of the second level, when a new entry needs to be inserted when the table capacity is full or the index values conflict, it can be directly replaced at the position of the corresponding index value, avoiding the efficiency impact brought by the replacement algorithm.

[0090] In an alternative embodiment of the present invention, calculating the first index value according to the jump target address and the first physical address may include: Step S31: Perform a preset hash calculation on the jump target address and the first physical address to obtain an intermediate result; Step S32: Extract the second preset bits of the intermediate result to obtain the first index value.

[0091] For the second stage of the second-level lookup, perform a preset hash calculation according to the jump target address and the first physical address to obtain the first index value, and query the first hash table corresponding to the target status label based on the first index value. The embodiments of the present invention optimize the process of calculating the first index value and reading the first hash table entry to further improve the efficiency of the second-level lookup.

[0092] In the embodiments of the present invention, the first index value of the first hash table is obtained by performing a preset hash calculation based on the jump target address and the first physical address, without calculating the first index value in combination with the status label. Therefore, the preset hash calculation may be to perform a preset shift and exclusive OR operation on the jump target address and the first physical address to calculate the first index value, without performing a complex hash calculation, thereby saving the overhead of calculating the first index value and improving the efficiency of calculating the first index value. After the first index value is calculated, the first index value can be directly used to read the first hash table corresponding to the target status label to obtain the first table entry, and its content is the second translation code block to be confirmed. Subsequently, the third stage can be executed to confirm whether the client virtual address and the client physical address of the second translation code block are the same as the jump target address and the first physical address; only when the client virtual address of the second translation code block is the same as the jump target address and the client physical address of the second translation code block is the same as the first physical address, it is considered that the first hash table lookup hits. The second-level lookup only needs to perform two comparisons of the virtual address and the physical address to complete the detection, without judging the status label, which can further improve the lookup efficiency.

[0093] It should be noted that the preset hash calculation may be a preset shift and exclusive OR operation. In one example, the first index value hash = GVA ^ (GPA >> 12), where GVA represents the jump target address and GPA represents the first physical address. "^" represents the bitwise exclusive OR operation, and ">>" represents the shift operation. Of course, the embodiments of the present invention do not limit the manner of the preset hash calculation.

[0094] Further, a preset shift and exclusive OR operation is performed on the jump target address and the first physical address to obtain an intermediate result, and this intermediate result can be directly used as the first index value. Alternatively, the second preset bit can be determined according to the capacity of the first hash table, and the second preset bit of the intermediate result can be extracted to obtain the first index value. For example, when the capacity of the first hash table is 1024 items, the second preset bit can be the lower 10 bits of the intermediate result (2 10 = 1024). If the lower 10 bits of the intermediate result are 100, then the 100th entry of the first hash table is read. The capacity of the first hash table can be set according to the specific situation of the client system, and the embodiments of the present invention do not limit this.

[0095] In summary, in the embodiments of the present invention, the target state label of the first translation code block is determined during the translation stage. When an indirect jump instruction in the first translation code block is executed, a hierarchical search is performed on the second translation code block to be jumped to. The first-level search is to query the fast lookup table according to the jump target address of the indirect jump instruction. In the case where the fast lookup table is not hit, the second-level search is executed. The second-level search is to query the first hash table corresponding to the target state label according to the jump target address of the indirect jump instruction. If the first hash table is hit, a direct jump can be made. The target state label is determined during translation. Thus, during the code block search process, it is not necessary to detect the state label of the translation code block, thereby eliminating the overhead of dynamically detecting the state label during runtime, improving the code block search efficiency, further improving the execution efficiency of the indirect jump instruction, and improving the performance of the system-level binary translator.

[0096] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present invention.

[0097] Refer to Figure 5 , which shows a structural block diagram of an embodiment of a system-level binary translator of the present invention. The system-level binary translator may include: A status label determination module 501 is configured to perform binary translation on a first code block to obtain a first translated code block, and determine a target status label of the first translated code block; the target status label is used to identify the processor status corresponding to the first code block during translation. A first-level lookup module 502 is configured to query a fast lookup table according to a jump target address of an indirect jump instruction when the indirect jump instruction in the first translated code block is executed; the fast lookup table is used to record pointers of translated code blocks corresponding to recently used jump target addresses; the pointer points to the entry address of the translated code block. A second-level lookup module 503 is configured to query a first hash table corresponding to the target status label according to the jump target address of the indirect jump instruction when the fast lookup table misses; the first hash table is used to record pointers of translated code blocks that match the target status label.

[0098] Optionally, the second-level lookup module includes: An address conversion sub-module is configured to perform address conversion on the jump target address to obtain a first physical address. A first index calculation sub-module is configured to calculate a first index value according to the jump target address and the first physical address. A first query sub-module is configured to query the first hash table corresponding to the target status label based on the first index value. If a first table entry is queried, and the client virtual address of the second translated code block pointed to by the first table entry is the same as the jump target address, and the second physical address of the second translated code block is the same as the first physical address, it is determined that the first hash table hits.

[0099] Optionally, the address conversion sub-module includes: A second index calculation unit is configured to extract a first preset bit of the virtual page number of the jump target address to obtain a second index value. A second query unit is configured to query an address conversion table based on the second index value; the address conversion table is used to record the correspondence between the virtual page number of the client virtual address and the physical page frame number of the client physical address. An address determination unit is configured to, if a second table entry is queried, and the virtual page number of the client virtual address stored in the second table entry is the same as the virtual page number of the jump target address, determine the first physical address according to the physical page frame number of the client physical address stored in the second table entry and the page offset within the jump target address.

[0100] Optionally, the system-level binary translator further includes: An address translation table update module, which is used to, if the address translation table is not hit, perform address translation on the jump target address in the next-level lookup, and then write the correspondence between the physical page frame number of the first physical address obtained by the translation and the virtual page number of the jump target address into the address translation table.

[0101] Optionally, the first index calculation sub-module is specifically used for: Perform a preset hash calculation on the jump target address and the first physical address to obtain an intermediate result; extract a second preset bit of the intermediate result to obtain a first index value.

[0102] Optionally, the system-level binary translator further includes: A first hash table establishment module, which is used to establish first hash tables respectively corresponding to different status tags, and each first hash table is initially empty; the same first hash table is used to record pointers of translation code blocks with the same status tag, and different first hash tables correspond to different status tags.

[0103] Optionally, the system-level binary translator further includes: A third-level lookup module, which is used to, if the first hash table is not hit, perform a next-level lookup according to the jump target address; the next-level lookup includes querying a second hash table according to the jump target address; the second hash table is used to record the correspondence between the client virtual address, the client physical address, and the status tag of the translation code block.

[0104] In the system-level binary translator according to the embodiments of the present invention, the target status tag of the first translation code block is determined during the translation stage. When an indirect jump instruction in the first translation code block is executed, a hierarchical lookup is performed on the second translation code block to which the jump is to be made. The first-level lookup is to query a fast lookup table according to the jump target address of the indirect jump instruction. When the fast lookup table is not hit, the second-level lookup is executed. The second-level lookup is to query the first hash table corresponding to the target status tag according to the jump target address of the indirect jump instruction. If the first hash table is hit, a direct jump can be made. Among them, the target status tag is determined during translation. Therefore, during the code block lookup process, the status tag of the translation code block does not need to be detected, thereby eliminating the overhead of dynamically detecting the status tag during runtime, improving the code block lookup efficiency, further improving the execution efficiency of the indirect jump instruction, and improving the performance of the system-level binary translator.

[0105] For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For related parts, please refer to the partial description of the method embodiments.

[0106] Refer to Figure 6, which is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. As Figure 6 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the binary translation method in the foregoing embodiment.

[0107] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by a program or a processor of a terminal, the terminal can execute the steps of the binary translation method in the foregoing embodiment. Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0108] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a binary translator, or a computer program product. Therefore, the embodiments of the present invention can take the form of an all-hardware embodiment, an all-software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0109] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of processes and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0110] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal devices to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0111] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one process or multiple processes and / or boxes Figure 1 one process or multiple processes and / or boxes Figure 1 or steps for implementing the functions specified in one box or multiple boxes.

[0112] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the said element.

[0113] Specific examples are used in this article to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation on the present invention.

Claims

1. A binary translation method, characterized in that, Applied to a system-level binary translator, the method includes: Performing binary translation on a first code block to obtain a first translated code block, and determining a target status tag for the first translated code block; the target status tag is used to identify the processor status corresponding to the first code block during translation. When an indirect jump instruction in the first translated code block is executed, querying a fast lookup table according to the jump target address of the indirect jump instruction; the fast lookup table is used to record pointers to translated code blocks corresponding to recently used jump target addresses; the pointer points to the entry address of the translated code block. In the case of a miss in the fast lookup table, querying a first hash table corresponding to the target status tag according to the jump target address of the indirect jump instruction; the first hash table is used to record pointers to translated code blocks that match the target status tag.

2. The method according to claim 1, characterized in that, The querying the first hash table corresponding to the target status tag according to the jump target address of the indirect jump instruction includes: Performing address conversion on the jump target address to obtain a first physical address. Calculating a first index value according to the jump target address and the first physical address. Querying the first hash table corresponding to the target status tag based on the first index value. If a first table entry is found, and the client virtual address of the second translated code block pointed to by the first table entry is the same as the jump target address, and the second physical address of the second translated code block is the same as the first physical address, it is determined that the first hash table hits.

3. The method according to claim 2, wherein The performing address conversion on the jump target address to obtain a first physical address includes: Extracting a first preset bit of the virtual page number of the jump target address to obtain a second index value. Querying an address conversion table based on the second index value; the address conversion table is used to record the correspondence between the virtual page numbers of client virtual addresses and the physical page frames of client physical addresses. If a second table entry is found, and the virtual page number of the client virtual address stored in the second table entry is the same as the virtual page number of the jump target address, then determine the first physical address according to the physical page frame number of the client physical address stored in the second table entry and the page offset within the jump target address.

4. The method according to claim 3, characterized in that, The method further includes: If the address conversion table misses, after performing address conversion on the jump target address in the next-level lookup, writing the correspondence between the physical page frame number of the converted first physical address and the virtual page number of the jump target address into the address conversion table.

5. The method according to claim 2, wherein The calculating a first index value according to the jump target address and the first physical address includes: Performing a preset hash calculation on the jump target address and the first physical address to obtain an intermediate result. Extracting a second preset bit of the intermediate result to obtain a first index value.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: Establishing first hash tables respectively corresponding to different status tags, each first hash table is initially empty; the same first hash table is used to record pointers to translated code blocks with the same status tag, and different first hash tables correspond to different status tags.

7. The method according to any one of claims 1 to 5, characterized in that The method further includes: If the first hash table lookup fails, perform a next-level lookup based on the jump target address; the next-level lookup includes querying a second hash table based on the jump target address; the second hash table is used to record the correspondence between the client virtual address, client physical address, and status label of the translated code block.

8. A system-level binary translator, characterized in that, The system-level binary translator includes: A status label determination module, configured to perform binary translation on a first code block to obtain a first translated code block, and determine a target status label of the first translated code block; the target status label is used to identify the processor status corresponding to the first code block during translation. A first-level lookup module, configured to, when an indirect jump instruction in the first translated code block is executed, query a fast lookup table based on the jump target address of the indirect jump instruction; the fast lookup table is used to record pointers to the translated code blocks corresponding to the most recently used jump target addresses; the pointer points to the entry address of the translated code block. A second-level lookup module, configured to, when the fast lookup table lookup fails, query a first hash table corresponding to the target status label based on the jump target address of the indirect jump instruction; the first hash table is used to record pointers to the translated code blocks that match the target status label.

9. The system-level binary translator according to claim 8, wherein The second-level lookup module includes: An address conversion sub-module, configured to perform address conversion on the jump target address to obtain a first physical address. A first index calculation sub-module, configured to calculate a first index value based on the jump target address and the first physical address. A first query sub-module, configured to query the first hash table corresponding to the target status label based on the first index value. If a first table entry is found, and the client virtual address of the second translated code block pointed to by the first table entry is the same as the jump target address, and the second physical address of the second translated code block is the same as the first physical address, it is determined that the first hash table lookup is successful.

10. The system-level binary translator according to claim 9, characterized in that The address conversion sub-module includes: A second index calculation unit, configured to extract a first preset bit of the virtual page number of the jump target address to obtain a second index value. A second query unit, configured to query an address conversion table based on the second index value; the address conversion table is used to record the correspondence between the virtual page number of the client virtual address and the physical page frame number of the client physical address. An address determination unit, configured to, if a second table entry is found, and the virtual page number of the client virtual address stored in the second table entry is the same as the virtual page number of the jump target address, determine the first physical address based on the physical page frame number of the client physical address stored in the second table entry and the page offset within the jump target address.

11. The system-level binary translator according to claim 10, characterized in that, The system-level binary translator further includes: An address conversion table update module, configured to, when the address conversion table lookup fails, write the correspondence between the physical page frame number of the first physical address obtained after address conversion of the jump target address in the next-level lookup and the virtual page number of the jump target address into the address conversion table.

12. The system-level binary translator according to claim 9, wherein The first index calculation sub-module is specifically configured to: Perform a preset hash calculation on the jump target address and the first physical address to obtain an intermediate result; extract the second preset bits of the intermediate result to obtain a first index value.

13. The system-level binary translator according to any one of claims 8 to 12, characterized in that The system-level binary translator further includes: A first hash table building module, configured to build first hash tables respectively corresponding to different state tags, each first hash table being initially empty; the same first hash table is used to record pointers of translation code blocks with the same state tag, and different first hash tables correspond to different state tags.

14. The system-level binary translator according to any one of claims 8 to 12, characterized in that The system-level binary translator further includes: A third-level lookup module, configured to perform a next-level lookup according to the jump target address if the first hash table is not hit; the next-level lookup includes querying a second hash table according to the jump target address; the second hash table is used to record the correspondence between the client virtual address, the client physical address, and the state tag of the translation code block.

15. An electronic device, characterized in that, Includes: A processor, a memory, a communication interface, and a communication bus, where the processor, the memory, and the communication interface complete mutual communication through the communication bus; The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the binary translation method according to any one of claims 1 to 7.

16. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium, and when the program or instruction is executed by the processor, the steps of the binary translation method according to any one of claims 1 to 7 are implemented.

17. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, the steps of the binary translation method according to any one of claims 1 to 7 are implemented.

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