A verification method based on a storage-computing integrated chip network-on-chip (NOC) system

Abstract

The present invention belongs to the technical field of storage and computing integrated chips, and particularly relates to a verification method based on a storage and computing integrated chip network on chip (NOC) system. The method comprises: image data is written into the NOC system via an AXI bus; weight data is directly written into the FLASH digital model of each node in the NOC system through initialization; the configuration information of the register is configured for each node in the NOC system via the APB bus; during the simulation of the NOC system, the final data read through the AXI bus, the output result of each node involved in the calculation, and the intermediate results of each step of the operator after convolution, bias addition, quantization, activation and pooling in each node are simultaneously saved and output. The present invention can quickly and effectively map the neural network calculations under different models performed by the software to the NOC system hardware circuit, thereby realizing the hardware circuit function verification of the storage and computing integrated chip NOC system.

Description

Technical Field

[0001] The present invention belongs to the technical field of storage-computing integrated chips, and in particular relates to a verification method based on a storage-computing integrated chip network on chip (NOC) system. Background Art

[0002] With the rapid development of computing science and information technology in recent years, as well as the rise of fields such as big data, artificial intelligence, and deep learning, the demand for high-performance computing platforms has increased significantly. The core concept of in-memory computing is to integrate computing functions with data storage. Computational operations are performed directly in memory, greatly reducing the need for data transmission, thereby reducing the burden on memory bandwidth and significantly improving computing efficiency. Based on this, in-memory computing opens up new possibilities for large-scale data processing in applications such as neural network computing, medical image processing, and the Internet of Things.

[0003] While computer performance continues to improve with advances in semiconductor technology, the widening speed gap between memory and processors has led to data transfer becoming a performance bottleneck. This memory wall limitation is widely known as the von Neumann bottleneck. The von Neumann computing architecture inherently faces both "memory wall" and "power wall" bottlenecks, and the recent slowdown of Moore's Law has further exacerbated these bottlenecks. New integrated memory and computing chip technology, through collaborative innovations in devices, architecture, circuits, and processes, integrates data storage and computing, significantly reducing data transfer costs and is considered a key technological direction for breaking through the von Neumann architecture bottleneck in the post-Moore era. Furthermore, integrated memory and computing chips achieve high computing power through massively parallel processing, which can alleviate process scaling pressures to a certain extent. This holds significant strategic significance and application value for my country's efforts to overcome the computing power bottleneck in the new round of artificial intelligence revolution. Summary of the Invention

[0004] The purpose of the present invention is to provide a verification method based on a storage-computing integrated chip on-chip network (NOC) system. The present invention can quickly and effectively map the neural network calculations under different models performed by software to the NOC system hardware circuit, thereby realizing the hardware circuit function verification of the storage-computing integrated chip NOC system.

[0005] To solve the above technical problems, the present invention provides a verification method based on a storage-computing integrated chip network-on-chip (NOC) system, comprising:

[0006] Inputting image data, and writing the image data into the NOC system via the AXI bus;

[0007] Input weight data, which is directly written into the FLASH digital model of each node in the NOC system through initialization;

[0008] Write the configuration information of the register, and the configuration information of the register is used to configure each node in the NOC system through the APB bus;

[0009] Compare the intermediate results and final output results. During the NOC system simulation, the final data read through the AXI bus, the output results of each node involved in the calculation, and the intermediate results of each node after convolution, bias addition, quantization, activation, and pooling are saved and output simultaneously.

[0010] Preferably, the process of inputting the image data includes:

[0011] Train the neural network algorithm model;

[0012] After training is completed, print out the used image data and save it to a text file; the format of the text file is width times height rows of image data, and each row is a combination of 8-bit data of 16 channels;

[0013] Declare an array at the top level of the verification environment. Using the language features of System Verilog, read the text file into the array, generate the corresponding AXI timing in the verification environment, and write the image data to the NOC system through the AXI bus.

[0014] Preferably, the weight data initialization process includes:

[0015] Train the neural network algorithm model;

[0016] After training is completed, the weight information used by each node is printed, which corresponds to the different convolutional layers in the neural network calculation. The number of weights used is related to the data width and height of the current convolutional layer and the number of input and output channels.

[0017] Preferably, each node Node includes a FLASH digital model for simulating the behavior of the FLASH device. The scale of the FLASH digital model is 256 rows and 1152 columns, and the weight value is 8 bits.

[0018] Preferably, the training of the neural network algorithm model includes:

[0019] The neural network algorithm model is trained in the software platform MapTools; the neural network algorithm model includes ResNet, MobileNet and target detection.

[0020] Preferably, according to the neural network algorithm model in the software platform MapTools, the weight information is directly initialized into the corresponding FLASH digital model, that is, the row and column positions for placing the weights.

[0021] Preferably, the register configuration process includes:

[0022] The configuration information of the register is written through the APB bus. Each node is assigned a corresponding base address, and each register has its own corresponding offset address. The base address and offset address are used to determine the location and corresponding value of the register of each node.

[0023] Through the script and software platform MapTools, the key information of the neural network algorithm model used by the software platform MapTools is mapped to the corresponding registers to generate two text files, which are an address file and a register value file, and the two correspond one to one.

[0024] Preferably, by declaring an array at the top level of the verification environment, utilizing the language characteristics of System Verilog, reading the text file into the array, generating the corresponding APB control timing in the verification environment, and writing the register configuration information into each corresponding node Node, the mapping of the neural network algorithm model is realized.

[0025] Preferably, the key information includes: image size, direction path of routing network, data flow type, input and output channels, sliding window size and sliding window step size.

[0026] Preferably, there are 30 nodes Node inside the NoC system, with 6 nodes Node in each row, for a total of 5 rows, and the register configuration of each node Node occupies 32KB of space.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The method of the present invention is directed to the design of the NOC system of the in-memory computing chip, and a verification platform is built including the four major components of image data input, weight data input, register information writing, intermediate results and final output result comparison. The image data is written via the AXI bus, and the weight data is directly written into the FLASH digital model of each node Node in the NOC system by initialization, and the register configuration information is configured to each node Node in the NOC system respectively via the APB bus. The method can complete the mapping of different neural network algorithm models by transforming different inputs, weights and register configuration information in the hardware circuit architecture of the storage and computing integrated chip NOC system, and can achieve comprehensive coverage function and effectively improve verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a flow chart of a verification method based on a storage-computing integrated chip network on chip (NOC) system provided by the present invention.

[0030] Figure 2 It is a schematic diagram of the node interconnection array in the NOC system provided by the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0032] like Figure 1 As shown, the embodiment of the present invention specifically provides a verification method based on a storage-computing integrated chip on-chip network NOC system. The present invention is aimed at the design of the NOC system of the in-memory computing chip, and builds a verification platform including four major components: image data input, weight data input, register information writing, intermediate results and final output result comparison. The image data is written through the AXI bus, and the weight data is directly written into the FLASH digital model of each node Node in the NOC system through initialization. The register configuration information is configured for each Node in the NOC system separately through the APB bus. Take the input image data of 32*32 as an example for detailed description.

[0033] The image data input process is as follows: After the trained ResNet, MobileNet, target detection and other neural network algorithm models are trained in the self-developed software platform MapTools, 32*32 or 1024 lines of image data are saved. Each line is a combination of 16 channels of 8-bit data, that is, 128-bit data per line, and 1024 lines of 128-bit data. Figure 2 The AXI input shown is converted by an AXI bridge (using an XBridge chip) and then input to the first node in the upper left corner of the NOC system. Once the data input meets the requirements of a sliding window, the window begins the corresponding convolution calculation, supporting up to 16 channels of convolution sliding windows simultaneously.

[0034] The weight initialization process involves training neural network algorithm models such as ResNet, MobileNet, and object detection using the independently developed MapTools software platform. The weight information used for each node is then printed. This corresponds to the different convolutional layers in the neural network calculation. The number of weights used is related to the data width and height of the current layer, as well as the number of input and output channels. To improve simulation speed and efficiency, each node contains a 256-row, 1152-column FLASH digital model to simulate the behavior of the FLASH device. Therefore, weight initialization is performed based on the software algorithm model, directly initializing the weight information to the corresponding node and the corresponding FLASH digital model at the weight placement row and column positions.

[0035] Register configuration via Figure 2As shown in the figure, there are 30 Nodes in the NoC, 6 Nodes in a row, and 5 rows in total. Each Node has an APB0 interface, and each Node configuration register occupies 32KB of space. The specific operation of APB0 configuration is: divide the corresponding address space for each Node external output selection circuit Output_Port, and connect the output signals of distributor 1 and distributor 2 to each Node in turn through the APB0 bus. The distributor 1 has a 1-way input and 2-way output structure, and the distributor 2 has a 1-way input and 30-way output structure. The register configuration is responsible for the APB0 interface, and the registers of each Node are written one by one. Nodes are assigned corresponding base addresses, and each register has its own corresponding offset address. The base address + offset address can determine the location and corresponding value of each register of each Node. The calculation results of the NoC system are output by selecting the three Nodes in the lower right corner. The registers in the output selection circuit Output_Port outside the NoC are responsible for determining the output information (i.e., which Node and which virtual channel to select). The APB0 bus outputs another signal to the register configuration circuit CFG_RF_NOC through the distributor 1. The registers in the output selection circuit Output_Port are configured through the register configuration circuit CFG_RF_NOC. Each register in the Output_Port circuit is also assigned a corresponding address space. Through the script and the independently developed MapTools tool, the key information of the algorithm model used by the software tool, such as image size, direction path of the routing network, data flow type, input and output channels, sliding window size, sliding window step, etc., can be mapped to the corresponding register, generating two text files, one for address information and the other for register value information, which correspond one to one. By declaring an array at the top level of the verification environment and utilizing the language features of System Verilog, the text file is read into the array, the corresponding APB control timing is generated in the environment, and the value of the configuration register is written to each corresponding Node to realize the mapping of the network model.

[0036] To confirm the correctness of the circuit calculation results, the output results need to be recorded and compared. The comparison process is to save and output the final data read through AXI during the NOC system simulation, the output results of each Node involved in the calculation, and the intermediate results of each step of the operator after convolution, bias addition, quantization, activation, and pooling in each Node. This greatly improves debugging efficiency and increases the location of problem locations.

[0037] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A verification method based on a storage and computing integrated chip network on chip NOC system, characterized in that: include: Inputting image data, and writing the image data into the NOC system via the AXI bus; Input weight data, which is directly written into the FLASH digital model of each node in the NOC system through initialization; Write the configuration information of the register, and the configuration information of the register configures each node Node in the NOC system and the NOC system output gating circuit through the APB bus; Compare the intermediate results and final output results. During the NOC system simulation, the final data read through the AXI bus, the output results of each node involved in the calculation, and the intermediate results of each node after convolution, bias addition, quantization, activation, and pooling are saved and output simultaneously.

2. A verification method based on a storage-computing integrated chip network on chip (NOC) system according to claim 1, characterized in that: The process of inputting the image data includes: Train the neural network algorithm model; After training is completed, print out the used image data and save it to a text file; the format of the text file is width times height rows of image data, and each row is a combination of 8-bit data of 16 channels; Declare an array at the top level of the verification environment. Using the language features of System Verilog, read the text file into the array, generate the corresponding AXI timing in the verification environment, and write the image data to the NOC system through the AXI bus.

3. A verification method based on a storage-computing integrated chip network on chip (NOC) system according to claim 2, characterized in that: The initialization process of the weight data includes: Train the neural network algorithm model; After training is completed, the weight information used by each node is printed, which corresponds to the different convolutional layers in the neural network calculation. The number of weights used is related to the data width and height of the current convolutional layer and the number of input and output channels.

4. A verification method based on a storage-computing integrated chip network on chip (NOC) system according to claim 3, characterized in that: Each node Node includes a FLASH digital model for simulating the behavior of the FLASH device. The scale of the FLASH digital model is 256 rows and 1152 columns, and the weight value is 8 bits.

5. A verification method based on a storage-computing integrated chip network on chip (NOC) system according to claim 3, characterized in that: The training of the neural network algorithm model includes: The neural network algorithm model is trained in the software platform MapTools; the neural network algorithm model includes ResNet, MobileNet and target detection.

6. A verification method based on a storage-computing integrated chip network on chip (NOC) system according to claim 5, characterized in that: According to the neural network algorithm model in the software platform MapTools, the weight information is directly initialized to the corresponding FLASH digital model, that is, the row and column positions for placing the weights.

7. A verification method based on a storage-computing integrated chip network on chip (NOC) system according to claim 5, characterized in that: The register configuration process includes: The configuration information of the register is written through the APB bus. Each node is assigned a corresponding base address, and each register has its own corresponding offset address. The base address and offset address are used to determine the location and corresponding value of the register of each node. Through the script and software platform MapTools, the key information of the neural network algorithm model used by the software platform MapTools is mapped to the corresponding registers to generate two text files, which are an address file and a register value file, and the two correspond one to one.

8. A verification method based on a storage-computing integrated chip network on chip (NOC) system according to claim 7, characterized in that: By declaring an array at the top level of the verification environment and utilizing the language features of System Verilog, the text file is read into the array, the corresponding APB control timing is generated in the verification environment, and the register configuration information is written into each corresponding node to realize the mapping of the neural network algorithm model.

9. A verification method based on a storage-computing integrated chip network on chip (NOC) system according to claim 7, characterized in that: The key information includes: image size, direction path of routing network, data flow type, input and output channels, sliding window size and sliding window step size.

10. A verification method based on a storage-computing integrated chip network on chip (NOC) system according to any one of claims 1 to 9, characterized in that: There are 30 nodes in the NOC system, with 6 nodes in each row, for a total of 5 rows. The register configuration of each node occupies 32KB of space.

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