OCC synchronous control system for cross-clock domain path scan test

Abstract

An OCC synchronization control system for cross-clock domain path scan testing is disclosed. The system comprises a first OCC and a second OCC, the first OCC is used for controlling test clock output of a first clock domain before frequency division, the second OCC is used for controlling test clock output of a second clock domain after frequency division, the first OCC receives a first high-speed clock signal, and the second OCC receives a second high-speed clock signal; the first OCC and the second OCC share the same group of trigger synchronization logic and are used for processing the synchronous trigger signal crossing the clock domain and providing synchronous control input for respective clock gating units, so that the first OCC and the second OCC generate respective test clock output under the same trigger reference. According to the OCC synchronous control system disclosed by the invention, in a circuit with a clock frequency divider, at least two OCCs are fused to share the same capture to trigger synchronous logic, so that synchronous clock pulse generation of clock domains before and after frequency division is realized, and the test coverage rate of a cross-clock path is improved.

Description

Technical Field

[0001] The present application relates to the technical field of design for testability, and in particular to an OCC synchronization control system for cross-clock domain path scan testing. Background Art

[0002] In the testability design of the chip, the test coverage of the functional logic can be achieved through the scan chain structure combined with the on-chip clock controller (OCC). However, in a circuit with a clock divider, the frequency difference and trigger timing difference between different clock domains will have a significant impact on the test coverage. In the prior art, possible problems include: the time of generating high-frequency test pulses cannot be accurately controlled, resulting in the difficulty in effectively covering the paths between the clock domains before and after the frequency division; or a longer timing check cycle is used during the test process, which is much higher than the normal timing in the functional mode. Although the test can be completed, it is equivalent to a frequency reduction test, which cannot truly reflect the operating status of the high-speed logic and affects the effectiveness of the test. Especially when there are a large number of cross-clock domain paths, this problem will be further aggravated, resulting in a significant decrease in test coverage, affecting the overall testability design goals of the chip.

[0003] Therefore, how to improve the test coverage of cross-clock paths is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, the present application discloses an OCC synchronization control system for cross-clock domain path scanning testing. In a circuit with a clock divider, at least two OCCs are merged to share the same capture trigger synchronization logic, thereby realizing the generation of synchronous clock pulses in the clock domains before and after the division, so as to improve the test coverage across clock paths.

[0005] The system includes at least two on-chip clock controllers (OCCs). The at least two OCCs include a first OCC and a second OCC. The first OCC is used to control the test clock output of the first clock domain before frequency division, and the second OCC is used to control the test clock output of the second clock domain after frequency division. Wherein: both the first OCC and the second OCC include a shift register, a clock gating unit, and a clock selector. The shift register is used to receive a control bit sequence during the shift phase of the scan chain to configure the clock pulse pattern of the corresponding clock domain during the test phase. The clock gating unit is used to receive a high-speed clock signal and control the on / off of the output of the high-speed clock signal based on the combination of the output of the shift register and a synchronization trigger signal. The high-speed clock signal includes a first high-speed clock signal and a second high-speed clock signal. The first OCC receives the first high-speed clock signal, and the second OCC receives the second high-speed clock signal. The clock selector is used to select a low-speed clock signal during the shift phase and select the high-speed clock signal from the clock gating unit as the output during the test phase. The first OCC and the second OCC share the same set of trigger synchronization logic, which is used to process the cross-clock-domain synchronization trigger signal and provide a synchronization control input to their respective clock gating units, so that the first OCC and the second OCC generate their respective test clock outputs under the same trigger reference.

[0006] Optionally, the system further includes a clock divider. The input end of the clock divider receives the first high-speed clock signal, and the output end of the clock divider outputs the second high-speed clock signal, so that the frequency of the first high-speed clock signal is an integer multiple of the frequency of the second high-speed clock signal.

[0007] Optionally, the frequency of the first high-speed clock signal is twice the frequency of the second high-speed clock signal; the frequency of the test clock signal of the first clock domain is twice the frequency of the test clock signal of the second clock domain.

[0008] Optionally, the clock pulses of the test clock signal of the first clock domain and the test clock signal of the second clock domain are determined by the control bit sequence shifted in during the shift phase of the scan chain. The control bit sequence is respectively loaded into the shift registers of the first OCC and the second OCC to configure the output clock pulse timing of the corresponding OCC during the test phase.

[0009] Optionally, the system includes a set of scan chain ports. The scan input port of the system is connected to the scan input port of the first OCC. The scan output port of the first OCC is connected to the scan input port of the second OCC. The scan output port of the second OCC is connected to the scan output port of the system, so that the shift registers of the first OCC and the second OCC are connected in series to form a continuous scan chain, realizing the sequential loading and output of the control bit sequence.

[0010] Optionally, the scan_en ports of the first OCC and the second OCC are both connected to the scan_en port of the system to receive the same enable control signal; the first OCC and the second OCC also uniformly receive the high-speed capture control signal, the test mode control signal, and the low-speed clock signal of the system; the system further includes a synchronization logic unit for synchronizing the scan_en signal in the low-speed clock domain to the high-speed clock domain, and the output end of the synchronization logic unit is connected to the clock gating units of the first OCC and the second OCC for uniformly controlling the enabling of the high-speed clock, so that the first OCC and the second OCC share the same set of trigger synchronization logic and achieve clock control under the same synchronization trigger reference.

[0011] Optionally, the system test paths include paths inside the functional logic circuits in the first clock domain and paths inside the functional logic circuits in the second clock domain. The control bit sequence is set such that only one OCC outputs high-speed clock pulses during the test phase, and the other OCC remains in a clockless output state, thereby realizing the test of the paths inside the corresponding clock domain.

[0012] Optionally, when the test path is the path inside the functional logic circuit in the first clock domain, during the shift phase of the scan chain, load the control bit sequence 0b0011 into the shift register of the first OCC and load the control bit sequence 0b0000 into the shift register of the second OCC; when the test path is the path inside the functional logic circuit in the second clock domain, during the shift phase, load the control bit sequence 0b0000 into the shift register of the first OCC and load the control bit sequence 0b0011 into the shift register of the second OCC; wherein, each bit in the control bit sequence is used to control whether the high-speed capture clock pulse is output in the corresponding clock cycle.

[0013] Optionally, the system test paths further include paths from the first clock domain to the second clock domain and paths from the second clock domain to the first clock domain. The control bit sequence is used to make the first OCC and the second OCC output high-speed clock pulses in different test clock cycles respectively to form a controllable pulse timing relationship.

[0014] Optionally, when the test path is from the first clock domain to the second clock domain, during the shift phase of the scan chain, load the shift register of the first OCC with the control bit sequence 0b0001 and load the shift register of the second OCC with the control bit sequence 0b0001, so that in the high-speed capture phase, the test clock signal of the first clock domain outputs a pulse first, and then the test clock signal of the second clock domain outputs a pulse; when the test path is from the second clock domain to the first clock domain, during the shift phase, load the shift register of the first OCC with the control bit sequence 0b0100 and load the shift register of the second OCC with the control bit sequence 0b0001, so that in the high-speed capture phase, the test clock signal of the second clock domain outputs a pulse first, and then the test clock signal of the first clock domain outputs a pulse.

[0015] In summary, an OCC synchronization control system for cross-clock-domain path scan testing disclosed in this application has at least the following beneficial effects: (1) By setting at least two on-chip clock controllers in the system and making them share the same set of trigger synchronization logics, the synchronization trigger signals across clock domains are uniformly processed, and the trigger reference is simultaneously transmitted to multiple clock gating units, so that the OCCs belonging to different frequency clock domains can output test clock signals with a consistent timing reference during the test phase. This structure avoids the clock deviation caused by independent triggering of each clock domain, realizes the collaborative control of cross-clock-domain OCCs, and is beneficial to ensuring the timing consistency and synchronization of system-level scan testing.

[0016] (2) By loading the control bit sequence into the shift register of each OCC during the shift phase of the scan chain, the number of pulses and output timing of each test clock signal are controlled, so that it is possible to configure a certain OCC to output clock pulses while the other OCC remains silent as needed under different test objectives, realizing the selective test control of the internal paths of each clock domain, making the test control more flexible, supporting the domain-by-domain testing of functional logics and the fine configuration of pulse timing, and improving the test efficiency and adaptability.

[0017] (3) On the premise of setting a clock divider, using the frequency doubling relationship between the first high-speed clock signal and the second high-speed clock signal, combined with the control bit sequence loaded by each OCC, by regulating the relative time sequence of the test pulses in the two clock domains, the controllable scan testing of cross-clock-domain paths (including paths from the high-frequency domain to the low-frequency domain and from the low-frequency domain to the high-frequency domain) is realized, breaking through the limitation that the traditional OCC structure can only test local paths, realizing the test coverage of logical paths between asynchronous domains or domains with inconsistent frequencies, and being beneficial to improving the path coverage integrity of DFT in multi-clock chips. Description of the Drawings

[0018] A brief introduction to the accompanying drawings used in the description of the embodiments of the present application will be given below.

[0019] Figure 1 Fig. shows a structural example diagram of an OCC provided by an embodiment of the present application.

[0020] Figure 2 Fig. shows a signal waveform diagram provided by an embodiment of the present application.

[0021] Figure 3 Fig. shows another signal waveform diagram provided by an embodiment of the present application.

[0022] Figure 4 Fig. shows a frequency division circuit provided by an embodiment of the present application.

[0023] Figure 5 For Figure 4 the waveform diagram corresponding to the frequency division circuit shown.

[0024] Figure 6 Fig. shows a frequency division circuit provided by an embodiment of the present application.

[0025] Figure 7 For Figure 6 the waveform diagram corresponding to the frequency division circuit shown.

[0026] Figure 8 Fig. shows a cross-clock domain solution provided by an embodiment of the present application.

[0027] Figure 9 For Figure 8 the waveform diagram of the solution shown.

[0028] Figure 10 Fig. shows another cross-clock domain solution provided by an embodiment of the present application.

[0029] Figure 11 For Figure 10 the waveform diagram of the solution shown.

[0030] Figure 12 Fig. shows an OCC synchronization control system for cross-clock domain path scan testing provided by an embodiment of the present application.

[0031] Figure 13 Fig. shows another OCC synchronization control system for cross-clock domain path scan testing provided by an embodiment of the present application.

[0032] Figure 14 Fig. shows a waveform diagram in a certain situation provided by an embodiment of the present application (corresponding to Figure 13 ).

[0033] Figure 15Shows a waveform diagram in another case provided by the embodiments of the present application (corresponding to Figure 13 ).

[0034] Figure 16 Shows a waveform diagram in yet another case provided by the embodiments of the present application (corresponding to Figure 13 ).

[0035] Figure 17 Shows a waveform diagram in yet another case provided by the embodiments of the present application (corresponding to Figure 13 ). Detailed implementation manners

[0036] To more clearly illustrate the technical solutions of the embodiments of the present application, the specific implementation manners of the present application will be described below with reference to the accompanying drawings. The accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other implementation manners can be obtained. Adjustments and improvements made without departing from the concept of the present application fall within the protection scope of the present application.

[0037] To make the drawings concise, only the parts related to the corresponding embodiments are schematically shown in each drawing, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, only some of the components with the same structure or function are schematically shown, and there may actually be more or fewer components with the same structure or function.

[0038] In the present application, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe related objects, and cannot be understood as indicating or implying the relative importance or order between related objects; in addition, they do not represent the quantity of related objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between related objects, which represents the "or" relationship between related objects. "And / or" is used to describe the relationship between related objects, which includes any combination relationship between related objects. For example, "a and / or b" includes: "a alone", "b alone", or "a and b". "One or more" or "at least one" among multiple objects refers to any object or any combination of multiple objects. For example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "a1 alone", "a2 alone", "a3 alone", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0039] Please refer to Figure 1 , which shows a structural example diagram of an OCC provided by the embodiments of the present application. As Figure 1As shown, an OCC includes an OCC controller occ_control, a fast clock gater, a slow clock gater, and a clock selector MUX. The fast clock gater and the slow clock gater can be collectively referred to as a clock gating unit. The OCC controller includes a shift register shift_reg, which is used to receive a control bit sequence during the shift phase of the scan chain to configure the clock pulse pattern of the corresponding clock domain during the test phase; the clock selector is used for switching between the fast clock and the slow clock. The slow clock signal slow_clock provides the clock in the shift mode (also referred to as the shift mode) and the slow capture mode (also referred to as slow capture), and the fast clock signal fast_clock is a free-running high-speed clock. In the high-speed capture (also referred to as high-speed capture) mode, the OCC controller generates a corresponding fast_clock_gater enable signal according to the value of shift_reg and the synchronized enable signal scan_en, so that the clock output clock_out can have a high-speed clock pulse with the expected waveform. Among them, scan_en is a signal in the slow clock domain and needs to be processed by a synchronization logic unit sync_cell before being used by fast_clock_gater. Exemplarily, the synchronization of the high-speed clock can be completed through the last two stages (i.e., the second stage and the third stage) in sync_cell because the clock ports of the last two stages receive the high-speed clock signal.

[0040] The registers in shift_reg are on the scan chain of the entire chip. The ATPG (automatic test pattern generation) tool can write data through the scan input scan_in port. During the shift phase, test_mode = 1 and scan_en = 1. Scan_in sends the values corresponding to the pulse waveforms to be generated in the subsequent high-speed capture phase to shift_reg. The rightmost MUX selects the output of slow_clock_gater. The enable terminal of slow_clock_gater is always 1, and the clock_out output is slow_clock. The clock of the subsequent driving logic is driven by slow_clock and is in the shift state.

[0041] During the high-speed clock capture phase, test_mode = 1, fast_capture_mode = 1, scan_en = 0. The MUX on the far right selects the output of the fast_clock_gater. The clock of the registers in the shift_reg comes from the output of the shift_reg_gater. When scan_en is synchronized to the output of the sync_cell by the slow_clock and the fast_clock, if there is a 1 in the registers of the shift_reg, the enable of the shift_reg_gater is 1. At this time, there is a fast_clock pulse on the clock of the shift_reg registers, and a shift operation will be performed.

[0042] At this time, the enable port of the fast_clock_gater is controlled by the 0th bit of the shift_reg. The high-speed capture clock pulse generated by clock_out is determined by the values shifted in during the shift phase. If you want to generate two consecutive pulses, you can shift the 0th and 1st bits in the shift_reg to 1 and the rest to 0 during the shift phase. In this way, clock pulses can be generated at the 0th and 1st beats during the capture phase. The signal diagram can be referred to Figure 2 . If you want to generate two spaced pulses, you can shift the 0th and 2nd bits in the shift_reg to 1 and the rest to 0 during the shift phase. In this way, clock pulses can be generated at the 0th and 2nd beats during the capture phase. For details, see Figure 3 .

[0043] The clock divider can divide the clock frequency. Figure 4 And Figure 5 respectively show a divide-by-two circuit and its waveform diagram provided by an embodiment of the present application. There can be a timing path between clocks of different frequencies. The arrow on the left is the timing check period from the rising edge of clk2x to the rising edge of clk1x, and the arrow on the right is the timing check period from the rising edge of clk1x to the rising edge of clk2x, which need to be covered by scan testing.

[0044] It should be noted that in the present application, in addition to the divide-by-two circuit mentioned above, the clock divider can also be a divide-by-four circuit. The relevant circuits and waveform diagrams are as shown in Figure 6 And Figure 7 . In addition, the clock divider can also be other types of frequency-dividing circuits, which will not be elaborated one by one in the present application.

[0045] The technical problem to be solved by the present application is how to improve the test coverage of the cross-clock path, and the circuit with a clock divider is a typical form of cross-clock domain performance.

[0046] In one implementation, completely independent OCCs can be inserted on different clock paths, and different clock domains are tested independently. The structural example diagram is as Figure 8 shown. However, independent OCCs result in complete independence during clock domain testing, making it impossible to control the generation time of high-frequency test pulses, and the paths between clock domains cannot be measured. If there are many paths across clock domains, it will lead to a significant decrease in coverage. As Figure 9 can be seen, the interval between clock_out2x and clock_out1x is large, and the paths between clock domains cannot be measured.

[0047] In another implementation, a circuit as Figure 10 shown is adopted. In the functional mode, the MUX selects path 0, and in the scan test, the MUX selects path 1. When the clk2x port is given a 2x-frequency clock, the clock gater of the clk1x logic is turned off, so that the paths inside the clk2x logic can be measured. At the same time, the clk1x logic having no clock will not cause a test failure; when the clk2x port is given a 1x-frequency clock, the clock gater is turned on, and the paths inside the clk1x logic and the paths between clk2x and clk1x can be measured. However, Figure 11 shown is the waveform diagram when the clk2x port is given a 1x-frequency clock as the high-speed capture clock. The arrows are the timing check periods of the clock rising edges, and the paths from clk1x to clk1x, from clk1x to clk2x, and from clk2x to clk1x are all covered hereby. Comparing Figure 5 it can be seen that the timing check period during testing is longer than that during the functional mode operation. Although this will not cause a test failure, it is equivalent to a frequency-down test and cannot achieve the desired test purpose.

[0048] In view of the deficiencies of the above two implementations, the present invention mainly solves the problem that the scan test coverage of the cross-clock-domain timing paths in a circuit with divided-frequency clocks is not achieved, enabling the OCC before frequency division and the OCC after frequency division to generate synchronous capture clock pulses and improving the scan test coverage.

[0049] Please refer to Figure 12 which shows an OCC synchronization control system for cross-clock-domain path scan testing provided by an embodiment of the present application. As Figure 12As shown in the figure, an OCC synchronization control system for cross-clock domain path scan testing includes at least two on-chip clock controllers OCC. The at least two OCCs include a first OCC and a second OCC. The first OCC is used to control the test clock output of the first clock domain before frequency division, and the second OCC is used to control the test clock output of the second clock domain after frequency division. Among them: both the first OCC and the second OCC include a shift register, a clock gating unit, and a clock selector. The shift register is used to receive a control bit sequence during the shift stage of the scan chain to configure the clock pulse pattern of the corresponding clock domain during the test stage. The clock gating unit is used to receive a high-speed clock signal and control the on-off of the output of the high-speed clock signal based on the combination of the output of the shift register and a synchronization trigger signal. The high-speed clock signal includes a first high-speed clock signal and a second high-speed clock signal. The first OCC receives the first high-speed clock signal, and the second OCC receives the second high-speed clock signal. The clock selector is used to select a low-speed clock signal during the shift stage and select the high-speed clock signal from the clock gating unit as the output during the test stage. The first OCC and the second OCC share the same set of trigger synchronization logic, which is used to process the cross-clock domain synchronization trigger signal and provide a synchronization control input to their respective clock gating units, so that the first OCC and the second OCC generate their respective test clock outputs under the same trigger reference.

[0050] By setting at least two on-chip clock controllers corresponding to the clock domains before and after frequency division respectively, and configuring a shift register, a clock gating unit, and a clock selector in each OCC, the system can load a control bit sequence during the shift stage of the scan chain and selectively output the corresponding test clock signal during the test stage. At the same time, the two OCCs share the same set of trigger synchronization logic, which is used to process the cross-clock domain synchronization trigger signal and provide a unified control input to their respective clock gating units, thereby ensuring that each OCC outputs test pulses under the same synchronization reference. This structural design enables the system to achieve synchronous control and clock coordination of each functional logic in a multi-clock domain environment, effectively avoiding test timing deviations caused by independent triggering of each clock domain, improving the collaborative controllability between clock domains, and providing a basic guarantee for the test coverage of cross-domain paths. It should be noted that the present solution is not limited to the two on-chip clock controllers listed in the above embodiments. In actual applications, it can be extended to three or more OCC units according to the complexity of the chip structure and clock domain division. The multiple OCCs can all achieve unified control and synchronous test clock output across multiple clock domains by sharing a set of trigger synchronization logic.

[0051] In Figure 12 , the first functional logic module corresponds to the first clock domain, and the second functional logic module corresponds to the second clock domain. Comparing Figure 12 with Figure 1 canFigure 12 The first OCC and the second OCC in are regarded as an overall OCC: they share the scan_en, fast_capture_mode, test_mode, and slow_clock ports, and the scan_out port of the first OCC is connected to the scan_in port of the second OCC, thereby realizing the hardware basis for cross-clock-domain testing.

[0052] In some embodiments of the present application, the system further includes a clock divider. The input end of the clock divider receives a first high-speed clock signal, and the output end of the clock divider outputs a second high-speed clock signal, so that the frequency of the first high-speed clock signal is an integer multiple of the frequency of the second high-speed clock signal. Exemplarily, the frequency of the first high-speed clock signal is twice the frequency of the second high-speed clock signal; the frequency of the test clock signal in the first clock domain is twice the frequency of the test clock signal in the second clock domain.

[0053] That is to say, the clock divider can be the frequency divider circuit mentioned above (as Figure 4 shown). The input end of the clock divider receives the first high-speed clock signal, that is, Figure 12 the fast_clock_2x in Figure 12 and outputs the second high-speed clock signal, that is, Figure 12 the fast_clock_1x in

[0054] When the clock divider is a frequency divider circuit, the frequency of the first high-speed clock signal is twice the frequency of the second high-speed clock signal; when the clock divider is a four-frequency divider circuit, the frequency of the first high-speed clock signal is four times the frequency of the second high-speed clock signal, and so on. For the sake of understanding, the following will take the frequency divider circuit as an example for description. At this time, the frequency of the test clock signal clock_out_2x in the first clock domain output by the first OCC is equivalent to twice the frequency of the test clock signal clock_out_1x in the second clock domain output by the second OCC.

[0054] In some embodiments of the present application, the clock pulses of the test clock signal in the first clock domain and the test clock signal in the second clock domain are determined by the control bit sequence shifted in during the shift stage of the scan chain. The control bit sequences are respectively loaded into the shift registers of the first OCC and the second OCC, and are used to configure the output clock pulse timing of the corresponding OCC during the test stage.

[0055] Please refer to Figure 13 which shows another OCC synchronization control system for cross-clock-domain path scan testing provided by the embodiments of the present application. Figure 13 It can also be understood as Figure 12 the specific structure diagram of Figure 13As shown, when the system is in the shift phase, test_mode = 1 and scan_en = 1. scan_in sends the values corresponding to the pulse waveforms desired in the subsequent high-speed capture phase to shift_reg. The rightmost MUX selects the output of slow_clock_gater. The enable terminal of slow_clock_gater is always 1, and clock_out outputs slow_clock. The subsequent clk2x logic and clk1x logic clocks are both driven by slow_clock and are in the shift state.

[0056] When the system is in the high-speed clock capture phase, test_mode = 1, fast_capture_mode = 1, scan_en = 0. The rightmost MUX selects the output of fast_clock_gater. The clocks of the registers in shift_reg come from the output of shift_reg_gater. When scan_en is synchronized to the output of sync_cell by slow_clock and fast_clock, if there is a 1 in the registers of shift_reg, the enable of shift_reg_gater is 1. At this time, there are fast_clock pulses on the clocks of the shift_reg registers, and the shift operation continues. The high-speed capture clock pulses generated by clock_out_2x and clock_out_1x are determined by the values shifted in during the shift phase.

[0057] In some embodiments of the present application, the system includes a group of scan chain ports. The scan input port of the system is connected to the scan input port of the first OCC. The scan output port of the first OCC is connected to the scan input port of the second OCC. The scan output port of the second OCC is connected to the scan output port of the system, so that the shift registers of the first OCC and the second OCC are connected in series to form a continuous scan chain, realizing the sequential loading and output of the control bit sequence.

[0058] This structure brings many beneficial effects at the test control level. First, it can reduce the occupation of scan chain port resources, avoid configuring a separate scan path for each OCC, and thus simplify the system structure. Second, the loading order of the control bit sequence is clear, which helps to accurately configure the output pulse behavior of each OCC during the test phase. Third, it is beneficial for the ATPG tool to uniformly generate test vectors and improve the automation degree of test strategy formulation. Generally speaking, this series structure improves the integration degree, control consistency and test predictability of the scan chain.

[0059] In the present application, the first OCC and the second OCC share the same capture logic. It can be understood that multiple on-chip clock controllers receive a unified scan_en signal through a shared set of synchronization logic units. After this signal is synchronized from the low-speed clock domain to the high-speed clock domain, it is respectively transmitted to their respective clock gating units as the trigger basis for capturing clock pulses, thereby controlling the output of the test clock under the same timing reference. This sharing mechanism is specifically embodied in that each OCC is uniformly connected to the same synchronization trigger path, and control signals such as test_mode, high-speed capture control signal, and slow_clock received are kept consistent, enabling the OCCs in different clock domains to output clock pulses in a coordinated manner during the test phase, achieving cross-clock-domain collaborative test control, and improving the timing consistency and coverage accuracy of the scan chain test. Specifically, the scan_en ports of the first OCC and the second OCC are both connected to the scan_en port of the system to receive the same enable control signal; the first OCC and the second OCC also uniformly receive the high-speed capture control signal, test mode control signal, and low-speed clock signal of the system; the system also includes a synchronization logic unit for synchronizing the scan_en signal in the low-speed clock domain to the high-speed clock domain, and the output end of the synchronization logic unit is connected to the clock gating units of the first OCC and the second OCC for uniformly controlling the enabling of the high-speed clock, so that the first OCC and the second OCC share the same set of trigger synchronization logic and achieve clock control under the same synchronization trigger reference.

[0060] In some embodiments of the present application, the system for the test path includes paths inside the functional logic circuits located in the first clock domain and paths inside the functional logic circuits located in the second clock domain. The setting of the control bit sequence is such that only one OCC outputs high-speed clock pulses during the test phase, and the other OCC remains in a clockless output state, thereby realizing the test of the paths inside the corresponding clock domain.

[0061] In some embodiments of the present application, as Figure 14 shown, when the test path is a path inside the functional logic circuit of the first clock domain, during the shift phase of the scan chain, the shift register of the first OCC is loaded with the control bit sequence 0b0011, and the shift register of the second OCC is loaded with the control bit sequence 0b0000; as Figure 15 shown, when the test path is a path inside the functional logic circuit of the second clock domain, during the shift phase, the shift register of the first OCC is loaded with the control bit sequence 0b0000, and the shift register of the second OCC is loaded with the control bit sequence 0b0011; wherein, each bit in the control bit sequence is used to control whether the high-speed capture clock pulse is output in the corresponding clock cycle.

[0062] That is to say, when testing the internal path of the clk2x clock domain logic, during the shift operation, 0b0011 can be shifted into shift_reg[3:0] of the OCC corresponding to clk2x, and 0b0000 can be shifted into shift_reg[3:0] of the OCC corresponding to clk1x. In this way, two high-speed capture clock pulses will be generated on clock_out_2x during high-speed capture, while no high-speed capture clock pulse will be generated on clock_out_1x. Similarly, when testing the internal path of the clk1x clock domain logic, during the shift operation, 0b0000 can be shifted into shift_reg[3:0] of the OCC corresponding to clk2x, and 0b0011 can be shifted into shift_reg[3:0] of the OCC corresponding to clk1x. In this way, two high-speed capture clock pulses will be generated on clock_out_1x during high-speed capture, while no high-speed capture clock pulse will be generated on clock_out_2x.

[0063] In some embodiments of the present application, the system for testing paths further includes a path from the first clock domain to the second clock domain and a path from the second clock domain to the first clock domain. The control bit sequence is used to cause the first OCC and the second OCC to output high-speed clock pulses respectively in different test clock cycles, so as to form a controllable pulse timing relationship.

[0064] In some embodiments of the present application, as Figure 16 shown, when the test path is from the first clock domain to the second clock domain, during the shift stage of the scan chain, the shift register of the first OCC is loaded with the control bit sequence 0b0001, and the shift register of the second OCC is loaded with the control bit sequence 0b0001, so that a pulse is first output by the test clock signal of the first clock domain during the high-speed capture stage, and then a pulse is output by the test clock signal of the second clock domain; as Figure 17 shown, when the test path is from the second clock domain to the first clock domain, during the shift stage, the shift register of the first OCC is loaded with the control bit sequence 0b0100, and the shift register of the second OCC is loaded with the control bit sequence 0b0001, so that a pulse is first output by the test clock signal of the second clock domain during the high-speed capture stage, and then a pulse is output by the test clock signal of the first clock domain.

[0065] That is to say, when testing the clk2x-to-clk1x cross-clock domain path, during the shift operation, 0b0001 can be loaded into shift_reg[3:0] of the OCC corresponding to clk2x, and 0b0001 can be loaded into shift_reg[3:0] of the OCC corresponding to clk1x. In this way, during the high-speed capture, a high-speed capture clock pulse will be generated first on clock_out_2x and a high-speed capture clock pulse will be generated on clock_out_1x in the next cycle, thereby covering the clk2x-to-clk1x path. Similarly, when testing the clk1x-to-clk2x cross-clock domain path, during the shift operation, 0b0100 can be loaded into shift_reg[3:0] of the OCC corresponding to clk2x, and 0b0001 can be loaded into shift_reg[3:0] of the OCC corresponding to clk1x. In this way, during the high-speed capture, a high-speed capture clock pulse will be generated first on clock_out_1x and a high-speed capture clock pulse will be generated on clock_out_2x in the next cycle, thereby covering the clk1x-to-clk2x path. In this way, the cross-clock domain test is achieved. It can be seen from the figure that compared with the previous implementation method, the technical solution corresponding to this embodiment has a higher test coverage rate.

[0066] In the above Figure 16 and Figure 17 example, in the circuit with a frequency divider, by introducing the synchronous OCC mechanism and improving the specific structure of the OCC, multiple OCCs can share a capture trigger synchronization logic, thereby achieving the synchronization of multiple OCCs. In addition, by controlling the values of the registers on the shift_reg during the shift stage, capture clocks with different waveforms can be generated during the capture stage. In this way, the paths between cross-clock domains can be detected under scan testing, significantly improving the test coverage rate.

[0067] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not described in detail or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. An OCC synchronization control system for cross-clock domain path scan testing, characterized in that, It includes at least two on-chip clock controllers (OCCs). The at least two OCCs include a first OCC and a second OCC. The first OCC is used to control the test clock output of the first clock domain before frequency division, and the second OCC is used to control the test clock output of the second clock domain after frequency division, where: Both the first OCC and the second OCC include a shift register, a clock gating unit, and a clock selector. The shift register is used to receive a control bit sequence during the shift stage of the scan chain to configure the clock pulse pattern of the corresponding clock domain during the test stage. The clock gating unit is used to receive a high-speed clock signal and control the on / off of the output of the high-speed clock signal based on the combination of the output of the shift register and a synchronization trigger signal. The high-speed clock signal includes a first high-speed clock signal and a second high-speed clock signal. The first OCC receives the first high-speed clock signal, and the second OCC receives the second high-speed clock signal. The clock selector is used to select a low-speed clock signal during the shift stage and select the high-speed clock signal from the clock gating unit as the output during the test stage. The first OCC and the second OCC share the same set of trigger synchronization logic, which is used to process the cross-clock-domain synchronization trigger signal and provide a synchronization control input to their respective clock gating units, so that the first OCC and the second OCC generate their respective test clock outputs under the same trigger reference.

2. The OCC synchronization control system for cross-clock domain path scan testing according to claim 1, wherein It further includes a clock divider. The input end of the clock divider receives the first high-speed clock signal, and the output end of the clock divider outputs the second high-speed clock signal, so that the frequency of the first high-speed clock signal is an integer multiple of the frequency of the second high-speed clock signal.

3. The OCC synchronization control system for cross-clock domain path scan test according to claim 1 or 2, characterized in that, The frequency of the first high-speed clock signal is twice the frequency of the second high-speed clock signal; The frequency of the test clock signal of the first clock domain is twice the frequency of the test clock signal of the second clock domain.

4. The OCC synchronization control system for cross-clock domain path scan test according to claim 1 or 2, characterized in that The clock pulses of the test clock signal of the first clock domain and the test clock signal of the second clock domain are determined by the control bit sequence shifted in during the shift stage of the scan chain. The control bit sequence is respectively loaded into the shift registers of the first OCC and the second OCC to configure the output clock pulse timing of the corresponding OCC during the test stage.

5. The OCC synchronization control system for cross-clock domain path scan test according to claim 1, characterized in that, The system includes a set of scan chain ports. The scan input port of the system is connected to the scan input port of the first OCC. The scan output port of the first OCC is connected to the scan input port of the second OCC. The scan output port of the second OCC is connected to the scan output port of the system, so that the shift registers of the first OCC and the second OCC are connected in series to form a continuous scan chain, realizing the sequential loading and output of the control bit sequence.

6. The OCC synchronization control system for cross-clock-domain path scan testing according to claim 1, wherein, The scan_en ports of the first OCC and the second OCC are both connected to the scan_en port of the system, and are used to receive the same enable control signal; The first OCC and the second OCC also uniformly receive the high-speed capture control signal, the test mode control signal, and the low-speed clock signal of the system; The system further includes a synchronization logic unit, which is used to synchronize the scan_en signal in the low-speed clock domain to the high-speed clock domain. The output end of the synchronization logic unit is connected to the clock gating units of the first OCC and the second OCC, and is used to uniformly control the enabling of the high-speed clock, so that the first OCC and the second OCC share the same set of trigger synchronization logic and achieve clock control under the same synchronization trigger reference.

7. The OCC synchronization control system for cross-clock domain path scan test according to claim 1, characterized in that, The test path of the system includes the paths inside the functional logic circuits in the first clock domain and the paths inside the functional logic circuits in the second clock domain. The setting of the control bit sequence enables only one OCC to output high-speed clock pulses during the test phase, and the other OCC remains in a clockless output state, so as to realize the test of the paths inside the corresponding clock domain.

8. The OCC synchronization control system for cross-clock domain path scan testing according to claim 7, wherein When the test path is the path inside the functional logic circuit in the first clock domain, during the shift stage of the scan chain, the shift register of the first OCC is loaded with the control bit sequence 0b0011, and the shift register of the second OCC is loaded with the control bit sequence 0b0000; When the test path is the path inside the functional logic circuit in the second clock domain, during the shift stage, the shift register of the first OCC is loaded with the control bit sequence 0b0000, and the shift register of the second OCC is loaded with the control bit sequence 0b0011; Among them, each bit in the control bit sequence is used to control whether the high-speed capture clock pulse is output in the corresponding clock cycle.

9. The OCC synchronization control system for cross-clock domain path scan test according to claim 1, characterized in that, The test path of the system also includes the path from the first clock domain to the second clock domain and the path from the second clock domain to the first clock domain. The control bit sequence is used to enable the first OCC and the second OCC to output high-speed clock pulses respectively in different test clock cycles, so as to form a controllable pulse timing relationship.

10. The OCC synchronization control system for cross-clock domain path scan testing according to claim 9, characterized in that, When the test path is the path from the first clock domain to the second clock domain, during the shift stage of the scan chain, the shift register of the first OCC is loaded with the control bit sequence 0b0001, and the shift register of the second OCC is loaded with the control bit sequence 0b0001, so that the test clock signal in the first clock domain outputs a pulse first during the high-speed capture stage, and then the test clock signal in the second clock domain outputs a pulse; When the test path is from the second clock domain to the first clock domain, in the shift stage, load the shift register of the first OCC with the control bit sequence 0b0100 and load the shift register of the second OCC with the control bit sequence 0b0001, so that in the high-speed capture stage, the test clock signal of the second clock domain outputs a pulse first, and then the test clock signal of the first clock domain outputs a pulse.

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