Shift register unit, shift register circuit and display panel

Abstract

The invention discloses a shift register unit, a shift register circuit and a display panel. The shift register unit comprises at least one shift register module and a plurality of output modules. The shift register module is configured to generate a control signal. The plurality of output modules are connected with the shift register module and are configured to generate a plurality of gate driving signals respectively. The number of the output modules is larger than that of the shift register modules. The number of the output modules is greater than that of the shift register modules, so that one shift register module controls more than one output module to output corresponding gate driving signals, the number of the shift register modules is reduced, the number of circuits of the shift register unit is reduced, and a narrow frame is realized.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a shift register unit, a shift register circuit, and a display panel. Background Art

[0002] A display panel includes a plurality of sub-pixels arranged in an array. When the display panel displays a frame of image, gate driving signals corresponding to respective scanning signal lines of the display panel are sequentially input, so that data signals can be written into corresponding sub-pixels in a display area through corresponding data signal lines, and the gate driving signals input to the gates of respective pixels are provided by a shift register unit.

[0003] In related technologies, a display panel includes multiple groups of shift register units, and each group of shift register units provides a gate driving signal. The multiple groups of shift register units make the size of the edge of the display panel large, which is not conducive to the realization of a narrow bezel. Summary of the Invention

[0004] The purpose of the present application is to provide a shift register unit, a shift register circuit, and a display panel with a small occupied area.

[0005] The present application discloses a shift register unit, which includes:

[0006] At least one shift register module, configured to generate a control signal;

[0007] A plurality of output modules, connected to the shift register module, configured to respectively generate a plurality of gate driving signals;

[0008] The number of the output modules is greater than the number of the shift register modules.

[0009] Optionally, the shift register module includes a first node and a second node, and the shift register module is configured to output a first control signal through the first node and output a second control signal through the second node.

[0010] Optionally, the number of the shift register modules is one;

[0011] The plurality of output modules at least include:

[0012] A first output module, connected to the second node, configured to generate a first gate driving signal according to the second control signal, and further configured to generate a third control signal according to the second control signal;

[0013] A second output module, connected to the first output module, configured to generate a second gate driving signal and a fifth gate driving signal according to the third control signal.

[0014] Optionally, the plurality of output modules further includes:

[0015] A third output module, connected to the second output module, configured to generate a third gate driving signal according to the second gate driving signal.

[0016] Optionally, the plurality of output modules further includes:

[0017] A fourth output module, connected to the second node, configured to generate a fourth gate driving signal according to the second control signal.

[0018] Optionally, the shift register unit further includes a plurality of clock signal terminals and a plurality of output signal terminals;

[0019] The first output module includes:

[0020] A first NAND gate, the first input terminal of the first NAND gate is connected to the second node, the second input terminal is connected to the clock signal terminal, and the output terminal is connected to the third node;

[0021] A third NOT gate, the input terminal of the third NOT gate is connected to the third node, and the output terminal is connected to the first output signal terminal;

[0022] The second output module includes:

[0023] A second NOR gate, the first input terminal of the second NOR gate is connected to the third node, the second input terminal is connected to the clock signal terminal, and the output terminal is connected to the input terminal of the fourth NOT gate;

[0024] The output terminal of the fourth NOT gate is connected to the input terminal of the fifth NOT gate;

[0025] The output terminal of the fifth NOT gate is connected to the input terminal of the sixth NOT gate;

[0026] The output terminal of the sixth NOT gate is connected to the second output signal terminal and the fifth output signal terminal.

[0027] Optionally, the third output module includes:

[0028] A third NOR gate, the first input terminal of the third NOR gate is connected to the second output signal terminal, the second input terminal is connected to the clock signal terminal, and the output terminal is connected to the input terminal of the seventh NOT gate;

[0029] The output terminal of the seventh NOT gate is connected to the input terminal of the eighth NOT gate;

[0030] The output terminal of the eighth NOT gate is connected to the input terminal of the ninth NOT gate;

[0031] The output terminal of the ninth NOT gate is connected to the third output signal terminal;

[0032] The fourth output module includes:

[0033] A tenth NOT gate, the input end of the tenth NOT gate is connected to the second node, and the output end is connected to the input end of an eleventh NOT gate;

[0034] The output end of the eleventh NOT gate is connected to the fourth output signal terminal.

[0035] Optionally, the number of the shift register modules is two, namely a first shift register module and a second shift register module; the multiple output modules at least include a first output module, a second output module, a third output module, a fourth output module and a fifth output module;

[0036] The first output module, the second output module, the third output module and the fifth output module are connected to the first shift register module and are configured to respectively generate a first gate driving signal, a second gate driving signal, a third gate driving signal and a fifth gate driving signal according to the control signal;

[0037] The fourth output module is connected to the second shift register module and is configured to generate a fourth gate driving signal according to the control signal.

[0038] Optionally, the first output module is connected to the second node of the first shift register module; the second output module is connected to the first node of the first shift register module; the third output module is connected to the first node of the first shift register module; the fifth output module is connected to the first node of the first shift register module; the fourth output module is connected to the second node of the second shift register module.

[0039] Optionally, the shift register unit further includes a plurality of clock signal terminals and a plurality of output signal terminals;

[0040] The first output module includes:

[0041] A third NOT gate, the input end of the third NOT gate is connected to the second node of the first shift register module, and the output end is connected to the input end of a fourth NOT gate;

[0042] The output end of the fourth NOT gate is connected to the first output signal terminal;

[0043] The second output module includes:

[0044] A fifth NOT gate, the input end of the fifth NOT gate is connected to the first node of the first shift register module, and the output end is connected to the input end of a sixth NOT gate;

[0045] The output terminal of the sixth NOT gate is connected to the second output signal terminal;

[0046] The third output module includes:

[0047] A second NOR gate, the first input terminal of the second NOR gate is connected to the first node of the first shift register module, the second input terminal is connected to the clock signal terminal, and the output terminal is connected to the input terminal of the seventh NOT gate;

[0048] The output terminal of the seventh NOT gate is connected to the input terminal of the eighth NOT gate;

[0049] The output terminal of the eighth NOT gate is connected to the input terminal of the ninth NOT gate;

[0050] The output terminal of the ninth NOT gate is connected to the third output signal terminal;

[0051] The fifth output module includes:

[0052] A tenth NOT gate, the input terminal of the tenth NOT gate is connected to the first node of the first shift register module, and the output terminal is connected to the input terminal of the eleventh NOT gate;

[0053] The output terminal of the eleventh NOT gate is connected to the fifth output signal terminal;

[0054] The fourth output module includes:

[0055] A twelfth NOT gate, the input terminal of the twelfth NOT gate is connected to the second node of the second shift register module, and the output terminal is connected to the input terminal of the thirteenth NOT gate;

[0056] The output terminal of the thirteenth NOT gate is connected to the fourth output signal terminal.

[0057] Optionally, the shift register unit further includes an input signal terminal and a reset signal terminal;

[0058] The shift register module further includes:

[0059] A first transmission gate, the first end of the first transmission gate is connected to the input signal terminal, and the second end is connected to the fourth node;

[0060] A first NOR gate, the first input terminal of the first NOR gate is connected to the fourth node, the second input terminal is connected to the reset signal terminal, and the output terminal is connected to the first node;

[0061] A first NOT gate, the input terminal of the first NOT gate is connected to the first node, and the output terminal is connected to the second node;

[0062] A second NOT gate, the input terminal of the second NOT gate is connected to the first node, and the output terminal is connected to the first end of the second transmission gate;

[0063] The second end of the second transmission gate is connected to the fourth node.

[0064] Optionally, the shift register unit further includes a plurality of reference signal terminals;

[0065] The first NOR gate is connected to the first reference signal terminal and the second reference signal terminal;

[0066] The first NOT gate is connected to the third reference signal terminal and the fourth reference signal terminal;

[0067] The first reference signal terminal and the third reference signal terminal are configured to provide a constant high potential signal, wherein the potential of the third reference signal terminal is greater than or equal to the potential of the first reference signal terminal; the second reference signal terminal and the fourth reference signal terminal are configured to provide a constant low potential signal, wherein the potential of the fourth reference signal terminal is less than or equal to the potential of the second reference signal terminal.

[0068] Optionally, the valid period of the third gate driving signal is within the valid periods of the second gate driving signal and the fifth gate driving signal; the valid periods of the second gate driving signal and the fifth gate driving signal are within the valid period of the first gate driving signal; the valid period of the first gate driving signal is within the valid period of the fourth gate driving signal.

[0069] Optionally, the shift register unit further includes:

[0070] A chopping module, connected to the output module, configured to receive the gate driving signal and generate a gate driving sub-signal with a valid period being half of the received gate driving signal.

[0071] Optionally, the shift register unit further includes a plurality of clock signal terminals;

[0072] The chopping module includes a fifth NOR gate and a fourteenth NOT gate. The first input terminal of the fifth NOR gate is connected to the output module, the second input terminal is connected to the clock signal terminal, and the output terminal is connected to the input terminal of the fourteenth NOT gate.

[0073] The present application also discloses a shift register circuit, which includes a plurality of the above-mentioned shift register units; a plurality of the shift register units are cascaded.

[0074] The present application also discloses a display panel, which includes a plurality of the above-mentioned shift register circuits and a pixel driving circuit; the gate driving signal output by the shift register circuit is used to drive the gate of the transistor in the pixel driving circuit.

[0075] Compared with the related art, the number of output modules in the present application is greater than the number of shift register modules, enabling one shift register module to control more than one output module to output corresponding gate driving signals, reducing the number of shift register modules, thereby reducing the number of circuits of the shift register cells, and thus achieving a narrow border.

[0076] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this specification. Brief Description of the Drawings

[0077] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with this specification, and are used together with the specification to explain the principles of this specification.

[0078] Figure 1 It is a schematic structural diagram of a display panel in an embodiment of the present application.

[0079] Figure 2 It is a schematic circuit diagram of a pixel driving circuit in an embodiment of the present application.

[0080] Figure 3 It is a schematic circuit diagram of a pixel driving circuit in an embodiment of the present application.

[0081] Figure 4 It is a schematic diagram of circuit modules of a display panel in the related art.

[0082] Figure 5 It is a schematic diagram of circuit modules of a shift register unit in an embodiment of the present application.

[0083] Figure 6 It is a schematic diagram of circuit modules of a display panel in an embodiment of the present application.

[0084] Figure 7 In one embodiment Figure 5 Specific logic circuit diagram of the circuit module diagram

[0085] Figure 8 In one embodiment Figure 7 Specific circuit diagram of the logic circuit diagram

[0086] Figure 9 In one embodiment Figure 8 Timing diagram of the circuit diagram

[0087] Figure 10 In one embodiment, several Figure 8 Connection diagram of the shift register circuit corresponding to the shown shift register unit

[0088] Figure 11Schematic diagram of a circuit module of a shift register unit in an embodiment of the present application.

[0089] Figure 12 Schematic diagram of a circuit module of a shift register unit in an embodiment of the present application.

[0090] Figure 13 Schematic diagram of a circuit module of a display panel in an embodiment of the present application.

[0091] Figure 14 In an embodiment Figure 11 Specific logic circuit diagram of the circuit module diagram.

[0092] Figure 15 In an embodiment Figure 12 Specific logic circuit diagram of the circuit module diagram.

[0093] Figure 16 In an embodiment Figure 14 Specific circuit diagram of the logic circuit diagram.

[0094] Figure 17 In an embodiment Figure 15 Specific circuit diagram of the logic circuit diagram.

[0095] Figure 18 In an embodiment Figure 16 、 Figure 17 Timing diagram of the circuit diagram.

[0096] Figure 19 In an embodiment, several Figure 16 、 Figure 17 Connection diagram of the shift register circuit corresponding to the shift register unit shown.

[0097] Figure 20 Circuit connection diagram of a chopper module in an embodiment.

[0098] Figure 21 In an embodiment Figure 20 Timing diagram of the circuit diagram. Specific embodiments

[0099] Here, the technical solutions in the embodiments (or "embodiment modes") of the present application will be clearly and completely described in conjunction with the accompanying drawings. When the following description involves the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0100] If there are terms related to directional indication or positional relationship in the embodiments of the present application (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture (as shown in the drawings); if the specific posture changes, the directional indication or positional relationship will also change accordingly. In addition, the terms "first", "second", etc. involved in the embodiments of the present application are only for the purpose of convenient description and cannot be construed as indicating or implying relative importance.

[0101] As Figure 1 shown, in the related art, a display panel generally includes a display area 1000 and a non-display area 2000 located on the peripheral side of the display area 1000.

[0102] The display area 1000 generally includes sub-pixels 1100 arranged in an array, and the sub-pixels 1100 can be red sub-pixels, green sub-pixels, or blue sub-pixels, etc. The sub-pixels 1100 include corresponding pixel driving circuits, and the pixel driving circuits drive the corresponding sub-pixels 1100 to emit light.

[0103] The non-display area 2000 generally includes a source driving circuit 2100 and a gate driving circuit 2200. Among them, the source driving circuit 2100 is connected to data signal lines (D1, D2, D3...), and the data signal lines (D1, D2, D3...) are connected to the pixel driving circuits. The source driving circuit 2100 is configured to provide data signals to the pixel circuits. The gate driving circuit 2200 is connected to scan signal lines (G1, G2, G3...), and the scan signal lines (G1, G2, G3...) are connected to the pixel driving circuits. The gate driving circuit 2200 is configured to provide gate driving signals to the pixel circuits. Usually, one shift register unit drives one row of pixels through one scan signal line. The pixel driving circuits receive the gate driving signals and data signals, and control the sub-pixels 1100 to emit light under the control of the gate driving signals and data signals.

[0104] As Figure 2 and Figure 3 shown, Figure 2 With Figure 3A circuit diagram of a pixel driving circuit is provided respectively. Among them, a data signal terminal provides a data signal to be written into the pixel driving circuit. Part of the gate driving signal controls the second transistor T2 and the fourth transistor T4 to control the data signal to be written into the gate of the third transistor T3. Part of the gate driving signal controls the fifth transistor T5 and the sixth transistor T6 to control whether the light-emitting unit emits light. Part of the gate driving signal controls the first transistor T1, the seventh transistor T7, and the eighth transistor T8 to reset the pixel driving circuit. In other embodiments, the display panel may adopt pixel driving circuits of other specifications.

[0105] As Figure 4 shown, in the related art, most display panels use a PMOS (P-type Metal-Oxide-Semiconductor) circuit to implement the function of the gate driving circuit and output the gate driving signal. Due to the existence of the coupling capacitance between circuits and the insufficient switching of the TFT (Thin Film Transistor) at the high and low level transitions of the output of the PMOS circuit in the related art, there will be steps in the output waveform. For example, the output pulse of the PMOS circuit cannot directly jump from the high level to the low level, but first jumps from the high level to a level around 0V, and then jumps from the level around 0V to the low level. The level around 0V may last for one or two clock signal widths, which is called the output step. Although the PMOS circuit has been continuously evolved and optimized, it is difficult to completely eliminate the steps of the existing PMOS circuit. Since the high and low level output transistors of the CMOS (Complementary Metal-Oxide-Semiconductor) circuit are composed of a PMOS and an NMOS (N-type Metal-Oxide-Semiconductor), the PMOS outputs a high level and the NMOS outputs a low level, the output ability is relatively high, and the low level output ability is greatly enhanced compared with the LTPS circuit, and the output waveform can be free of steps. In addition, the combination of the high speed (high electron mobility) of the NMOS and the low leakage current of the PMOS enables the CMOS circuit to achieve a balance between high-speed operation and low power consumption. However, since the implementation of the output signal of the current CMOS circuit requires the assistance of a shift register module ( Figure 4 the shift register therein) and an output module ( Figure 4 ResetH, ResetN, GateP, GateN, EM therein) for output, in order to ensure the output stability, the TFT size of the output module is generally large. After being applied to the OLED display panel, it occupies a large border space. When all five groups of gate driving circuits use CMOS circuits in the existing design, the required space is large, which is not conducive to the design concept of narrow borders.

[0106] As Figure 5 and Figure 6 shown, to solve the above problems, the present application provides a shift register unit, which includes at least one shift register module 100 and a plurality of output modules. Among them, the shift register module 100 is configured to generate a control signal. The plurality of output modules are connected to the shift register module 100 and are configured to generate a plurality of gate driving signals respectively. Among them, the number of output modules is greater than the number of shift register modules 100.

[0107] In the present application, the number of output modules is greater than the number of shift register modules, so that one shift register module controls more than one output module to output corresponding gate driving signals, reducing the number of shift register modules, thereby reducing the number of circuits of the shift register unit, and thus achieving a narrow border.

[0108] The following will detail each embodiment of the present application that conforms to the above creative concept.

[0109] In an embodiment of the present application, the shift register unit includes an input signal terminal STV, a reset signal terminal RST, a first reference signal terminal VREF1, a second reference signal terminal VREF2, a third reference signal terminal VREF3, a fourth reference signal terminal VREF4, a first clock signal terminal CK, a second clock signal terminal CKn, a third clock signal terminal CB, a fourth clock signal terminal CBn, a fifth clock signal terminal NCK, a sixth clock signal terminal RCK, a seventh clock signal terminal GCK, a first output signal terminal NOUT, a second output signal terminal RPOUT, a third output signal terminal GOUT, a fourth output signal terminal EOUT, a fifth output signal terminal RHOUT, and a cascade signal terminal.

[0110] Among them, the input signal terminal STV is configured to provide an input signal. The reset signal terminal RST is configured to provide a reset signal. The first reference signal terminal VREF1 is configured to provide a constant high-potential signal, the second reference signal terminal VREF2 is configured to provide a constant low-potential signal, the third reference signal terminal VREF3 is configured to provide a constant high-potential signal, and the fourth reference signal terminal VREF4 is configured to provide a constant low-potential signal. Optionally, the potential of the third reference signal terminal VREF3 can be higher than the potential of the first reference signal terminal VREF1, and the potential of the fourth reference signal terminal VREF4 can be lower than the potential of the second reference signal terminal VREF2. Optionally, the potential of the third reference signal terminal VREF3 can be equal to the potential of the first reference signal terminal VREF1, and the potential of the fourth reference signal terminal VREF4 can be equal to the potential of the second reference signal terminal VREF2. The first clock signal terminal CK and the fourth clock signal terminal CBn are configured to provide clock signals with opposite phases, the third clock signal terminal CB and the second clock signal terminal CKn are configured to provide clock signals with opposite phases, and the fifth clock signal terminal NCK is configured to provide one of the clock signals NCK1 to NCK7, where the clock signals NCK1 to NCK7 are clock signals that shift one by one, and the width of the shift one by one between the clock signals NCK1 to NCK7 is set according to the actual requirements of the circuit. The sixth clock signal terminal RCK is configured to provide one of the clock signals RCK1 to RCK3, where the clock signals RCK1 to RCK3 are clock signals that shift one by one, and the width of the shift one by one between the clock signals RCK1 to RCK3 is set according to the actual requirements of the circuit. The seventh clock signal terminal GCK is configured to provide one of the clock signals GCK1 to GCK4 or GCK and GCB, where the clock signals GCK1 to GCK4 are clock signals that shift one by one, the width of the shift one by one between the clock signals GCK1 to GCK4 is set according to the actual requirements of the circuit, and the clock signals GCK and GCB are clock signals with opposite phases. Please refer to Figure 3 , the first output signal terminal NOUT is configured to output a first gate drive signal to drive the second transistor T2, the second output signal terminal RPOUT is configured to output a second gate drive signal to drive the first transistor T1, the third output signal terminal GOUT is configured to output a third gate drive signal to drive the fourth transistor T4, the fourth output signal terminal EOUT is configured to output a fourth gate drive signal to drive the fifth transistor T5 and the sixth transistor T6, and the fifth output signal terminal RHOUT is configured to output a fifth gate drive signal to drive the seventh transistor T7 and the eighth transistor T8. The cascade signal terminal is configured to output a cascade signal.

[0111] Such as Figure 5As shown, in an alternative embodiment, the shift register unit includes a shift register module 100, a first output module 200, a second output module 300, a third output module 400, and a fourth output module 500.

[0112] Among them, the shift register module 100 is configured to generate a first control signal and a second control signal. The first output module 200 is connected to the shift register module 100. The first output module 200 is configured to generate a first gate driving signal according to the second control signal, and is also configured to generate a third control signal according to the second control signal. The second output module 300 is connected to the first output module 200. The second output module 300 is configured to generate a second gate driving signal and a fifth gate driving signal according to the third control signal. The third output module 400 is connected to the second output module 300. The third output module 400 is configured to generate a third gate driving signal according to the second gate driving signal. The fourth output module 500 is connected to the shift register module 100. The fourth output module 500 is configured to generate a fourth gate driving signal according to the second control signal. Please refer to Figure 4 and Figure 6 , so that 4 shift register modules can be reduced in one row of the shift register circuit, which can greatly reduce the width of the display panel border.

[0113] As Figure 5 and as Figure 7 shown, in an alternative embodiment, the shift register module 100 includes a first transmission gate Tg1, a first NOR gate NOR1, a first inverter INV1, a second inverter INV2, and a second transmission gate Tg2. Among them, the first end of the first transmission gate Tg1 is connected to the input signal terminal STV, and the second end is connected to the fourth node N4. The first input terminal of the first NOR gate NOR1 is connected to the fourth node N4, the second input terminal is connected to the reset signal terminal RST, and the output terminal is connected to the first node N1. The reset signal of the reset signal terminal RST is a constant low-potential signal in the normal state, and only switches to a high-potential signal when the device is turned on or the device needs to be reset to reset the circuit. The input terminal of the first inverter INV1 is connected to the first node N1, and the output terminal is connected to the second node N2. The input terminal of the second inverter INV2 is connected to the first node N1, and the output terminal is connected to the first end of the second transmission gate Tg2. The second end of the second transmission gate Tg2 is connected to the fourth node N4. The second inverter INV2 and the second transmission gate Tg2 can lock the signal of the fourth node N4 according to the signal of the first node N1 until the input signal of the input signal terminal STV changes. Among them, the signal of the first node N1 is the first control signal, and the signal of the second node N2 is the second control signal. The second node N2 is also connected to the cascaded signal terminal STVn+1.

[0114] The first output module 200 includes a first NAND gate NAND1 and a third inverter INV3. Among them, the first input terminal of the first NAND gate NAND1 is connected to the second node N2, the second input terminal is connected to the fifth clock signal terminal NCK, and the output terminal is connected to the third node N3. The input terminal of the third inverter INV3 is connected to the third node N3, and the output terminal is connected to the first output signal terminal NOUT.

[0115] The second output module 300 includes a second NOR gate NOR2, a fourth inverter INV4, a fifth inverter INV5, and a sixth inverter INV6. The first input terminal of the second NOR gate NOR2 is connected to the third node N3, the second input terminal is connected to the sixth clock signal terminal RCK, and the output terminal is connected to the input terminal of the fourth inverter INV4. The output terminal of the fourth inverter INV4 is connected to the input terminal of the fifth inverter INV5. The output terminal of the fifth inverter INV5 is connected to the input terminal of the sixth inverter INV6. The output terminal of the sixth inverter INV6 is connected to the second output signal terminal RPOUT and the fifth output signal terminal RHOUT.

[0116] The third output module 400 includes a third NOR gate NOR3, a seventh inverter INV7, an eighth inverter INV8, and a ninth inverter INV9. The first input terminal of the third NOR gate NOR3 is connected to the second output signal terminal RPOUT, the second input terminal is connected to the seventh clock signal terminal GCK, and the output terminal is connected to the input terminal of the seventh inverter INV7. The output terminal of the seventh inverter INV7 is connected to the input terminal of the eighth inverter INV8. The output terminal of the eighth inverter INV8 is connected to the input terminal of the ninth inverter INV9. The output terminal of the ninth inverter INV9 is connected to the third output signal terminal GOUT.

[0117] The fourth output module 500 includes a tenth inverter INV10 and an eleventh inverter INV11. The input terminal of the tenth inverter INV10 is connected to the second node N2, and the output terminal is connected to the input terminal of the eleventh inverter INV11. The output terminal of the eleventh inverter INV11 is connected to the fourth output signal terminal EOUT.

[0118] Optionally, as Figure 8 shown, Figure 8 in an optional embodiment Figure 7 is the specific circuit diagram of the logic gate circuit shown. The transmission gate may include an N-type transistor and a P-type transistor, and the N-type transistor and the P-type transistor of the transmission gate are connected in parallel. Among them, the gate of the N-type transistor in the first transmission gate Tg1 may be connected to the second clock signal terminal CKn, and the gate of the P-type transistor may be connected to the third clock signal terminal CB. The gate of the N-type transistor in the second transmission gate Tg2 may be connected to the fourth clock signal terminal CBn, and the gate of the P-type transistor may be connected to the first clock signal terminal CK.

[0119] The NOT gate may include an N-type transistor and a P-type transistor. The gates of the N-type transistor and the P-type transistor of the NOT gate are connected to the same node, and the second poles of the N-type transistor and the P-type transistor of the NOT gate are connected to the same node. Among them, the first pole of the N-type transistor in the second NOT gate INV2 may be connected to the second reference signal terminal VREF2, and the first pole of the P-type transistor in the second NOT gate INV2 may be connected to the first reference signal terminal VREF1. The first poles of the N-type transistors in the remaining NOT gates may be connected to the fourth reference signal terminal VREF4, and the first poles of the P-type transistors may be connected to the third reference signal terminal VREF3. Among them, when the potential of the third reference signal terminal VREF3 is higher than the potential of the first reference signal terminal VREF1, and the potential of the fourth reference signal terminal VREF4 is lower than the potential of the second reference signal terminal VREF2. There is a potential difference between the potential of the first node N1 and the source voltage of the transistor of the first NOT gate INV1, and the transistor of the first NOT gate INV1 will conduct more fully.

[0120] The NOR gate may include two N-type transistors and two P-type transistors. The two N-type transistors in the NOR gate are connected in parallel, and the two P-type transistors in the NOR gate are connected in series. The second poles of the two series-connected P-type transistors are connected to the second poles of the parallel-connected N-type transistors at the same node. The gates of one P-type transistor and the N-type transistor are connected to the same node, and the gates of the other P-type transistor and the N-type transistor are connected to another same node. Among them, the first poles of the two series-connected P-type transistors in the first NOR gate NOR1 are connected to the first reference signal terminal VREF1, the first poles of the parallel-connected N-type transistors are connected to the second reference signal terminal VREF2, the gates of one P-type transistor and the N-type transistor are connected to the fourth node N4, and the gates of the other P-type transistor and the N-type transistor are connected to the reset signal terminal RST. The first poles of the two series-connected P-type transistors in the second NOR gate NOR2 are connected to the third reference signal terminal VREF3, the first poles of the parallel-connected N-type transistors are connected to the fourth reference signal terminal VREF4, the gates of one P-type transistor and the N-type transistor are connected to the third node N3, and the gates of the other P-type transistor and the N-type transistor are connected to the sixth clock signal terminal RCK. The first poles of the two series-connected P-type transistors in the third NOR gate NOR3 are connected to the third reference signal terminal VREF3, the first poles of the parallel-connected N-type transistors are connected to the fourth reference signal terminal VREF4, the gates of one P-type transistor and the N-type transistor are connected to the second output signal terminal RPOUT, and the gates of the other P-type transistor and the N-type transistor are connected to the seventh clock signal terminal GCK.

[0121] The NAND gate may include two N-type transistors and two P-type transistors. The two P-type transistors in the NAND gate are connected in parallel, and the two N-type transistors in the NAND gate are connected in series. The second poles of the two series-connected N-type transistors are connected to the second poles of the parallel-connected P-type transistors at the same node. The gates of one of the P-type transistors and the N-type transistor are connected to the same node, and the gates of the other P-type transistor and the N-type transistor are connected to another same node. Among them, the first poles of the two series-connected N-type transistors in the first NAND gate NAND1 are connected to the fourth reference signal terminal VREF4, and the first poles of the parallel-connected P-type transistors are connected to the third reference signal terminal VREF3. The gates of one of the P-type transistors and the N-type transistor are connected to the second node N2, and the gates of the other P-type transistor and the N-type transistor are connected to the fifth clock signal terminal NCK.

[0122] As Figure 7 , Figure 8 and Figure 9 shown, Figure 9 is a timing diagram of the circuit shown in an alternative embodiment. In this embodiment, the fifth clock signal terminal NCK provides the fifth clock signal NCK1, the sixth clock signal terminal RCK provides the sixth clock signal RCK1, and the seventh clock signal terminal GCK provides the seventh clock signal GCK1. Figure 8 When the signal at the input signal terminal STV is at a high potential, the signal at the second clock signal terminal CKn switches to a high potential, and the signal at the third clock signal terminal CB switches to a low potential, through the first transmission gate Tg1, the first NOR gate NOR1, and the first inverter INV1, the first node N1 is written with a low potential, and the second node N2 is written with a high potential. The signal of the second node N2 is output to the input signal terminal STV of the next row of shift register units through the cascade signal terminal STVn+1.

[0123] When the second node N2 is at a high potential and the fifth clock signal NCK1 switches to a high potential, through the first NAND gate NAND1, the third node N3 is written with a low potential, and then through the third inverter INV3, the first output signal terminal NOUT outputs a high potential until the fifth clock signal NCK1 switches to a low potential.

[0124] When the third node N3 is at a low potential and the sixth clock signal RCK1 switches to a low potential, through the second NOR gate NOR2, the fourth inverter INV4, the fifth inverter INV5, and the sixth inverter INV6, the second output signal terminal RPOUT and the fifth output signal terminal RHOUT output low potentials.

[0125] When the third node N3 is at a low potential and the sixth clock signal RCK1 switches to a low potential, through the second NOR gate NOR2, the fourth inverter INV4, the fifth inverter INV5, and the sixth inverter INV6, the second output signal terminal RPOUT and the fifth output signal terminal RHOUT output low potentials.

[0126] When the second output signal terminal RPOUT outputs a low potential and the seventh clock signal GCK1 switches to a low potential, the third output signal terminal GOUT outputs a low potential through the third NOR gate NOR3, the seventh inverter INV7, the eighth inverter INV8, and the ninth inverter INV9.

[0127] When the second node N2 is at a high potential, the fourth output signal terminal EOUT outputs a high potential through the tenth inverter INV10 and the eleventh inverter INV11.

[0128] In the related art, five shift register modules and five output modules are required to output five gate driving signals. In this embodiment, all the gate driving signals required by the pixel driving circuit can be output by one shift register module 100 and four output modules, saving the width of four shift register modules for the border of the display panel, which is beneficial to realizing a narrow border. The output modules of the present application are not limited to five. When the display panel adopts a pixel driving circuit with other specifications and the pixel driving circuit requires other numbers of gate driving signals, the output modules of the present application can be correspondingly adjusted to other numbers.

[0129] In this embodiment, the valid period of the third gate driving signal is within the valid periods of the second gate driving signal and the fifth gate driving signal. The valid periods of the second gate driving signal and the fifth gate driving signal are within the valid period of the first gate driving signal. The valid period of the first gate driving signal is within the valid period of the fourth gate driving signal. Therefore, the third gate driving signal can be processed based on the second gate driving signal and the fifth gate driving signal, and the second gate driving signal and the fifth gate driving signal can be processed based on the first gate driving signal.

[0130] In this embodiment, the first output module 200 and the fourth output module 500 are directly connected to the shift register module 100. The second output module 300 is connected to the first output module 200, and the third output module 400 is connected to the second output module 300. The fourth output module 500 generates a fourth gate driving signal based on the signal of the second node N2 of the shift register module 100. The first output module 200 generates a first gate driving signal based on the signal of the second node N2 of the shift register module 100 and the signal of the fifth clock signal terminal NCK. The second output module 300 generates a second gate driving signal based on the signal of the third node N3 of the first output module 200 and the signal of the sixth clock signal terminal RCK. The third output module 400 generates a third gate driving signal based on the signal output by the second output module 300 and the signal of the seventh clock signal terminal GCK. Each level of signal is processed from the signal of the previous node, avoiding all output modules being connected to the same node, which may cause an excessive load on that node. At the same time, since the width of the signal gradually decreases from the second node to the third node to the output terminal of the second output module 300, the input signal of each output module is a signal wider than its output signal, which facilitates the design of the clock signal, reduces the number of clock signal lines, and further reduces the width of the display panel border.

[0131] As Figure 10 shown, Figure 10 Figure [X] is a schematic connection diagram of a shift register circuit corresponding to a plurality of Figure 8 shift register units in an embodiment. Only the connection lines of some shift register units are shown in the figure, and the other shift register units not shown are connected according to the connection rules of the shown shift register units. Among the cascaded shift register units, the fifth clock signal terminal NCK of the first-stage shift register unit can be configured to provide a clock signal NCK1, the sixth clock signal terminal RCK can be configured to provide a clock signal RCK1, and the seventh clock signal terminal GCK can be configured to provide a clock signal GCK1. The fifth clock signal terminal NCK of the second-stage shift register unit can be configured to provide a clock signal NCK2, the sixth clock signal terminal RCK can be configured to provide a clock signal RCK2, and the seventh clock signal terminal GCK can be configured to provide a clock signal GCK2. The subsequent shift register units are connected in this pattern in a cycle. For example, the fifth clock signal terminal NCK of the fourth-stage shift register unit can be configured to provide a clock signal NCK4, the sixth clock signal terminal RCK can be configured to provide a clock signal RCK1, and the seventh clock signal terminal GCK can be configured to provide a clock signal GCK4.

[0132] Among them, Figure 10 connecting the output signal terminal to the scan signal line Gj indicates that the signal output by the output signal terminal drives the pixels in the j-th row. Figure 10The connection between multiple output signal terminals and the scan signal line Gj indicates that the multiple output signal terminals are respectively and correspondingly connected to the gates of different transistors in the pixel driving circuit of the j-th row of pixels, and the multiple output signal terminals are not connected to each other.

[0133] In this embodiment, the signals output by the first output signal terminal NOUT, the second output signal terminal RPOUT, the fourth output signal terminal EOUT, and the fifth output signal terminal RHOUT of a single shift register unit drive two rows of pixels. That is, in a shift register unit, the first output signal terminal NOUT, the second output signal terminal RPOUT, the fourth output signal terminal EOUT, and the fifth output signal terminal RHOUT are correspondingly connected to a group of scan signal lines, and a group of scan signal lines includes scan signal lines for driving two rows of pixels. Among them, the first output signal terminal NOUT, the second output signal terminal RPOUT, and the fourth output signal terminal EOUT are connected to a group of scan signal lines corresponding to the current-stage shift register unit, and the fifth output signal terminal RHOUT is connected to a group of scan signal lines corresponding to the shift register unit of the first eight stages before the current-stage shift register unit.

[0134] The signal output by the third output signal terminal GOUT of a single shift register unit drives one row of pixels. That is, in a shift register unit, the third output signal terminal GOUT is correspondingly connected to one row of scan signal lines. Among them, the third output signal terminal GOUT is connected to one row of scan signal lines corresponding to the shift register unit of the first two stages before the current-stage shift register unit.

[0135] As Figure 11 and Figure 12 shown, in an alternative embodiment, the shift register unit includes two shift register modules 100, a first output module 200, a second output module 300, a third output module 400, and a fourth output module 500. The two shift register modules 100 are respectively the first shift register module 100 and the second shift register module 100. Among them, the first output module 200, the second output module 300, the third output module 400, and the fifth output module 600 are connected to the first shift register module 100 and are configured to generate a first gate driving signal, a second gate driving signal, a third gate driving signal, and a fifth gate driving signal respectively according to a control signal. The fourth output module 500 is connected to the second shift register module 100 and is configured to generate a fourth gate driving signal according to a control signal.

[0136] Please refer to Figure 4 and Figure 13 , so that three shift register modules can be reduced in the setting of one row of the shift register circuit, and the width of the border of the display panel can be greatly reduced.

[0137] As Figure 14 and as Figure 15As shown, in an optional embodiment, the structures of the first shift register module 100 and the second shift register module 100 are substantially the same as those of the Figure 7 embodiment shown, and will not be elaborated here.

[0138] Please refer Figure 15 to. The first output module 200 may include a third NOT gate INV3 and a fourth NOT gate INV4. Among them, the input terminal of the third NOT gate INV3 is connected to the second node N2 of the first shift register module 100, and the output terminal is connected to the input terminal of the fourth NOT gate INV4. The output terminal of the fourth NOT gate INV4 is connected to the first output signal terminal NOUT.

[0139] The second output module 300 may include a fifth NOT gate INV5 and a sixth NOT gate INV6. Among them, the input terminal of the fifth NOT gate INV5 is connected to the first node N1 of the first shift register module 100, and the output terminal is connected to the input terminal of the sixth NOT gate INV6. The output terminal of the sixth NOT gate INV6 is connected to the second output signal terminal RPOUT.

[0140] The third output module 400 may include a second NOR gate NOR2, a seventh NOT gate INV7, an eighth NOT gate INV8, and a ninth NOT gate INV9. Among them, the first input terminal of the second NOR gate NOR2 is connected to the first node N1 of the first shift register module 100, the second input terminal is connected to the seventh clock signal terminal GCK, and the output terminal is connected to the input terminal of the seventh NOT gate INV7. The output terminal of the seventh NOT gate INV7 is connected to the input terminal of the eighth NOT gate INV8. The output terminal of the eighth NOT gate INV8 is connected to the input terminal of the ninth NOT gate INV9. The output terminal of the ninth NOT gate INV9 is connected to the third output signal terminal GOUT.

[0141] The fifth output module 600 may include a tenth NOT gate INV10 and an eleventh NOT gate INV11. Among them, the input terminal of the tenth NOT gate INV10 is connected to the first node N1 of the first shift register module 100, and the output terminal is connected to the input terminal of the eleventh NOT gate INV11. The output terminal of the eleventh NOT gate INV11 is connected to the fifth output signal terminal RHOUT.

[0142] Please refer Figure 14 to. The fourth output module 500 may include a twelfth NOT gate INV12 and a thirteenth NOT gate INV13. Among them, the input terminal of the twelfth NOT gate INV12 is connected to the second node N2 of the second shift register module 100, and the output terminal is connected to the input terminal of the thirteenth NOT gate INV13. The output terminal of the thirteenth NOT gate INV13 is connected to the fourth output signal terminal EOUT.

[0143] Optionally, as Figure 16 well as Figure 17 shown.Figure 16 In an alternative embodiment Figure 14 is the specific circuit diagram of the logic gate circuit shown Figure 17 In an alternative embodiment Figure 15 is the specific circuit diagram of the logic gate circuit shown. Among them, the structures of the first shift register module 100 and the second shift register module 100 are Figure 8 substantially the same as those in the embodiment shown, and will not be elaborated here

[0144] The NOT gate may include an N-type transistor and a P-type transistor. The gates of the N-type transistor and the P-type transistor of the NOT gate are connected to the same node, and the second poles of the N-type transistor and the P-type transistor of the NOT gate are connected to the same node. Among them, the first pole of the N-type transistor in the second NOT gate INV2 may be connected to the second reference signal terminal VREF2, and the first pole of the P-type transistor in the second NOT gate INV2 may be connected to the first reference signal terminal VREF1. The first poles of the N-type transistors in the remaining NOT gates may be connected to the fourth reference signal terminal VREF4, and the first pole of the P-type transistor in the second NOT gate INV2 may be connected to the third reference signal terminal VREF3

[0145] The NOR gate may include two N-type transistors and two P-type transistors. The two N-type transistors in the NOR gate are connected in parallel, and the two P-type transistors in the NOR gate are connected in series. The second poles of the two series-connected P-type transistors are connected to the second poles of the parallel-connected N-type transistors at the same node. The gates of one P-type transistor and the N-type transistor are connected to the same node, and the gates of the other P-type transistor and the N-type transistor are connected to another same node Figure 17 In the second NOR gate NOR2, the first poles of the two series-connected P-type transistors are connected to the third reference signal terminal VREF3, the first poles of the parallel-connected N-type transistors are connected to the fourth reference signal terminal VREF4, the gates of one P-type transistor and the N-type transistor are connected to the first node N1 of the first shift register module 100, and the gates of the other P-type transistor and the N-type transistor are connected to the seventh clock signal terminal GCK

[0146] As Figures 14 to 18 shown Figure 18 In an alternative embodiment Figure 16 and Figure 17 is the timing schematic diagram of the circuit shown. In this embodiment, the seventh clock signal terminal GCK provides the seventh clock signal GCK. Among them, the output timing process of the fourth output signal terminal EOUT is Figure 8 and Figure 9 substantially the same as the output timing process of the fourth output signal terminal EOUT in, and will not be elaborated here

[0147] Please refer to Figure 15 ,17 and Figure 18 When the signal at the input signal terminal STV is at a high potential, the signal at the second clock signal terminal CKn switches to a high potential, and the signal at the third clock signal terminal CB switches to a low potential, the first node N1 is written with a low potential and the second node N2 is written with a high potential through the first transmission gate Tg1, the first NOR gate NOR1, and the first inverter INV1. The signal of the second node N2 is output to the input signal terminal STV of the next row of shift register units through the cascaded signal terminal STVn+1.

[0148] When the second node N2 is at a high potential, the first output signal terminal NOUT outputs a high potential through the third inverter INV3 and the fourth inverter INV4.

[0149] When the first node N1 is at a low potential, the second output signal terminal RPOUT outputs a low potential through the fifth inverter INV5 and the sixth inverter INV6.

[0150] When the first node N1 is at a low potential and the seventh clock signal terminal GCK switches to a low potential, the third output signal terminal GOUT outputs a low potential through the second NOR gate NOR2, the seventh inverter INV7, the eighth inverter INV8, and the ninth inverter INV9.

[0151] When the first node N1 is at a low potential, the fifth output signal terminal RHOUT outputs a low potential through the tenth inverter INV10 and the eleventh inverter INV11.

[0152] In the related art, five shift register modules and five output modules are required to output five gate driving signals. In this embodiment, all the gate driving signals required by the pixel driving circuit can be output through two shift register modules 100 and five output modules, saving the width of three shift register modules for the border of the display panel, which is beneficial to realizing a narrow border. The output modules of the present application are not limited to five. When the display panel adopts a pixel driving circuit with other specifications and the pixel driving circuit requires other numbers of gate driving signals, the output modules of the present application can be correspondingly adjusted to other numbers, and the number of shift register modules of the present application can also be correspondingly adjusted.

[0153] In this embodiment, the first output module 200, the second output module 300, the third output module 400, and the fifth output module 600 are connected to the first shift register module 100 and are configured to generate a first gate driving signal, a second gate driving signal, a third gate driving signal, and a fifth gate driving signal respectively according to a control signal. The fourth output module 500 is connected to the second shift register module 100 and is configured to generate a fourth gate driving signal according to the control signal. The width of the output signal of the fourth output module 500 is much larger than the width of the output signals of the first output module 200, the second output module 300, the third output module 400, and the fifth output module 600, so that the width requirement of the input signal of the fourth output module 500 is also much larger than that of other output modules. The fourth output module 500 is separately connected to the second shift register module 100, so that the effective segment of the signal output by the first shift register module 100 can be set to be relatively narrow, so that the first output module 200, the second output module 300, and the fifth output module 600 do not require a clock signal, and the third output module 400 requires fewer clock signals, thus greatly reducing the number of clock signals, and further reducing the width of the display panel border.

[0154] As Figure 19 shown, in this embodiment, the gate driving signals output by the first output signal terminal NOUT, the third output signal terminal GOUT, and the fourth output signal terminal EOUT can be connected to the corresponding scan signal lines of this row to drive the sub-pixels of this row, and the gate driving signal output by the second output signal terminal RPOUT can be connected to the scan signal lines two rows forward from this row to drive the sub-pixels of the corresponding row, and the gate driving signal output by the fifth output signal terminal RHOUT can be connected to the scan signal lines two rows backward from this row to drive the sub-pixels of the corresponding row.

[0155] As Figure 19 shown, Figure 19 is a connection schematic diagram of a shift register circuit corresponding to several Figure 16 , Figure 17 shown shift register units in an embodiment. Only the connection lines of some shift register units are shown in the figure, and the other shift register units not shown are connected according to the connection rules of the shown shift register units. Among several cascaded shift register units, the seventh clock signal terminal GCK of the first-stage shift register unit can be configured to provide the clock signal GCK. The seventh clock signal terminal GCK of the second-stage shift register unit can be configured to provide the clock signal GCB. The subsequent shift register units are connected in this rule in a cycle. For example, the seventh clock signal terminal GCK of the third-stage shift register unit can be configured to provide the clock signal GCK.

[0156] Among them, Figure 19The connection between the middle output signal terminal and the scanning signal line Gj indicates that the signal output by the output signal terminal drives the pixels in the j-th row. Figure 10 The connection between multiple output signal terminals and the scanning signal line Gj indicates that the multiple output signal terminals are respectively and correspondingly connected to the gates of different transistors in the pixel driving circuit of the pixels in the j-th row, and the multiple output signal terminals are not connected to each other.

[0157] In this embodiment, the signals output by the first output signal terminal NOUT, the second output signal terminal RPOUT, the fourth output signal terminal EOUT, and the fifth output signal terminal RHOUT of a single shift register unit drive two rows of pixels. That is, in a shift register unit, the first output signal terminal NOUT, the second output signal terminal RPOUT, the fourth output signal terminal EOUT, and the fifth output signal terminal RHOUT correspondingly connect to a group of scanning signal lines, and a group of scanning signal lines includes the scanning signal lines for driving two rows of pixels. Among them, the first output signal terminal NOUT and the fourth output signal terminal EOUT are connected to a group of scanning signal lines corresponding to the current-stage shift register unit, the second output signal terminal RPOUT is connected to a group of scanning signal lines corresponding to the shift register unit two stages before the current-stage shift register unit, and the fifth output signal terminal RHOUT is connected to a group of scanning signal lines corresponding to the shift register unit two stages after the current-stage shift register unit.

[0158] The signal output by the third output signal terminal GOUT of a single shift register unit drives one row of pixels. That is, in a shift register unit, the third output signal terminal GOUT correspondingly connects to one row of scanning signal lines. Among them, the third output signal terminal GOUT is connected to one row of scanning signal lines corresponding to the current-stage shift register unit.

[0159] Such as Figure 20 and Figure 21 As shown, in an alternative embodiment, the shift register unit further includes a chopping module 700. The chopping module 700 is connected to the output module and is configured to receive a gate driving signal and generate a gate driving sub-signal with an effective period being half of the received gate driving signal.

[0160] The chopping module may include a fifth NOR gate NOR5 and a fourteenth inverter INV14. The first input terminal in of the fifth NOR gate NOR5 is connected to the output module, the second input terminal is connected to the eighth clock signal terminal EN, the output terminal is connected to the input terminal of the fourteenth inverter INV14, and the output terminal of the fourteenth inverter INV14 is connected to the scanning signal line.

[0161] Specifically, as Figure 20 shown, the first input terminals in of two chopping modules 700 are both connected to the third output module 400, and the second input terminals are respectively connected to the eighth clock signal terminal EN1 and the eighth clock signal terminal EN2. Combining Figure 21, the eighth clock signal terminal EN1 and the eighth clock signal terminal EN2 are clock signals with opposite phases. When the signal output by the third output module 400 is at a low potential and the eighth clock signal terminal EN1 is at a low potential, the output signal terminal out1 outputs a low potential. When the signal output by the third output module 400 is at a low potential and the eighth clock signal terminal EN2 is at a low potential, the output signal terminal out2 outputs a low potential. Thus, the gate drive signal output by the third output module 400 is divided into gate drive sub-signals with an effective period of half. The effective period of the signal output by the third output module 400 is set to twice the original. By setting the circuit in the manner as Figure 20 shown, two effective gate drive sub-signals can be output through one output module. Thus, one third output module 400 can be connected to two scan signal lines through two chopping modules 700, so as to drive two rows of pixels simultaneously, thereby reducing the number of circuits in the shift register unit and realizing a narrow border. Of course, the chopping module 700 can also be set at the output end of other output modules, and only the timing of the eighth clock signal terminal EN needs to be adjusted according to the corresponding output module.

[0162] This application also discloses a shift register circuit, and the shift register circuit includes a plurality of the above-mentioned shift register units. The plurality of shift register units are cascaded.

[0163] This application also discloses a display panel, and the display panel includes a plurality of the above-mentioned shift register circuits and a pixel driving circuit. The gate drive signal output by the shift register circuit is used to drive the gates of the transistors in the pixel driving circuit.

[0164] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the drawings; any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included within the scope of protection of this application.

Claims

1. A shift register unit, characterized in that, Comprising: At least one shift register module configured to generate control signals; A plurality of output modules connected to the shift register module and configured to generate a plurality of gate driving signals respectively; The number of the output modules is greater than the number of the shift register modules.

2. The shift register unit according to claim 1, wherein The shift register module includes a first node and a second node, and the shift register module is configured to output a first control signal through the first node and a second control signal through the second node.

3. The shift register unit according to claim 2, characterized in that, The number of the shift register modules is one; The plurality of output modules at least include: A first output module connected to the second node and configured to generate a first gate driving signal according to the second control signal and further configured to generate a third control signal according to the second control signal; A second output module connected to the first output module and configured to generate a second gate driving signal and a fifth gate driving signal according to the third control signal.

4. The shift register unit according to claim 3, wherein The plurality of output modules further include: A third output module connected to the second output module and configured to generate a third gate driving signal according to the second gate driving signal.

5. The shift register unit according to claim 4, wherein The plurality of output modules further include: A fourth output module connected to the second node and configured to generate a fourth gate driving signal according to the second control signal.

6. The shift register unit according to claim 5, wherein The shift register unit further includes a plurality of clock signal terminals and a plurality of output signal terminals; The first output module includes: A first NAND gate, the first input terminal of the first NAND gate is connected to the second node, the second input terminal is connected to the clock signal terminal, and the output terminal is connected to the third node; A third NOT gate, the input terminal of the third NOT gate is connected to the third node, and the output terminal is connected to the first output signal terminal; The second output module includes: A second NOR gate, the first input terminal of the second NOR gate is connected to the third node, the second input terminal is connected to the clock signal terminal, and the output terminal is connected to the input terminal of the fourth NOT gate; The output terminal of the fourth NOT gate is connected to the input terminal of the fifth NOT gate; The output terminal of the fifth NOT gate is connected to the input terminal of the sixth NOT gate; The output terminal of the sixth NOT gate is connected to the second output signal terminal and the fifth output signal terminal.

7. The shift register unit according to claim 6, wherein The third output module includes: A third NOR gate, the first input terminal of the third NOR gate is connected to the second output signal terminal, the second input terminal is connected to the clock signal terminal, and the output terminal is connected to the input terminal of the seventh NOT gate; The output terminal of the seventh NOT gate is connected to the input terminal of the eighth NOT gate; The output terminal of the eighth NOT gate is connected to the input terminal of the ninth NOT gate; The output terminal of the ninth NOT gate is connected to the third output signal terminal; The fourth output module includes: A tenth NOT gate, the input terminal of the tenth NOT gate is connected to the second node, and the output terminal is connected to the input terminal of the eleventh NOT gate; The output terminal of the eleventh NOT gate is connected to the fourth output signal terminal.

8. The shift register unit according to claim 2, characterized in that, The number of the shift register modules is two, namely a first shift register module and a second shift register module; the plurality of output modules at least include a first output module, a second output module, a third output module, a fourth output module and a fifth output module; The first output module, the second output module, the third output module, and the fifth output module are connected to the first shift register module and are configured to generate a first gate driving signal, a second gate driving signal, a third gate driving signal, and a fifth gate driving signal respectively according to the control signal; The fourth output module is connected to the second shift register module and is configured to generate a fourth gate driving signal according to the control signal.

9. The shift register unit according to claim 8, wherein The first output module is connected to the second node of the first shift register module; the second output module is connected to the first node of the first shift register module; the third output module is connected to the first node of the first shift register module; the fifth output module is connected to the first node of the first shift register module; the fourth output module is connected to the second node of the second shift register module.

10. The shift register unit according to claim 9, wherein The shift register unit further includes a plurality of clock signal terminals and a plurality of output signal terminals; The first output module includes: A third NOT gate, the input terminal of the third NOT gate is connected to the second node of the first shift register module, and the output terminal is connected to the input terminal of the fourth NOT gate; The output terminal of the fourth NOT gate is connected to the first output signal terminal; The second output module includes: A fifth NOT gate, the input terminal of the fifth NOT gate is connected to the first node of the first shift register module, and the output terminal is connected to the input terminal of the sixth NOT gate; The output terminal of the sixth NOT gate is connected to the second output signal terminal; The third output module includes: A second NOR gate, the first input terminal of the second NOR gate is connected to the first node of the first shift register module, the second input terminal is connected to the clock signal terminal, and the output terminal is connected to the input terminal of the seventh NOT gate; The output terminal of the seventh NOT gate is connected to the input terminal of the eighth NOT gate; The output terminal of the eighth NOT gate is connected to the input terminal of the ninth NOT gate; The output terminal of the ninth NOT gate is connected to the third output signal terminal; The fifth output module includes: A tenth NOT gate, the input terminal of the tenth NOT gate is connected to the first node of the first shift register module, and the output terminal is connected to the input terminal of the eleventh NOT gate; The output terminal of the eleventh NOT gate is connected to the fifth output signal terminal; The fourth output module includes: A twelfth NOT gate, the input terminal of the twelfth NOT gate is connected to the second node of the second shift register module, and the output terminal is connected to the input terminal of the thirteenth NOT gate; The output terminal of the thirteenth NOT gate is connected to the fourth output signal terminal.

11. The shift register unit according to claim 2, wherein The shift register unit further includes an input signal terminal and a reset signal terminal; The shift register module further includes: A first transmission gate, the first end of the first transmission gate is connected to the input signal terminal, and the second end is connected to the fourth node; A first NOR gate, the first input terminal of the first NOR gate is connected to the fourth node, the second input terminal is connected to the reset signal terminal, and the output terminal is connected to the first node; A first NOT gate, the input terminal of the first NOT gate is connected to the first node, and the output terminal is connected to the second node; A second NOT gate, wherein an input end of the second NOT gate is connected to the first node, and an output end thereof is connected to a first end of a second transmission gate; A second end of the second transmission gate is connected to the fourth node.

12. The shift register unit according to claim 11, wherein The shift register unit further includes a plurality of reference signal terminals; A first NOR gate is connected to a first reference signal terminal and a second reference signal terminal; The first NOT gate is connected to a third reference signal terminal and a fourth reference signal terminal; The first reference signal terminal and the third reference signal terminal are configured to provide a constant high-potential signal, wherein a potential of the third reference signal terminal is greater than or equal to a potential of the first reference signal terminal; The second reference signal terminal and the fourth reference signal terminal are configured to provide a constant low-potential signal, wherein a potential of the fourth reference signal terminal is less than or equal to a potential of the second reference signal terminal.

13. The shift register unit according to any one of claims 5-7, characterized in that, An effective period of the third gate driving signal is within effective periods of the second gate driving signal and the fifth gate driving signal; the effective periods of the second gate driving signal and the fifth gate driving signal are within an effective period of the first gate driving signal; the effective period of the first gate driving signal is within an effective period of the fourth gate driving signal.

14. The shift register unit according to any one of claims 1-12, characterized in that, The shift register unit further includes: A chopping module, connected to the output module, and configured to receive the gate driving signal and generate a gate driving sub-signal with an effective period being half of the received gate driving signal.

15. The shift register unit according to claim 14, characterized in that, The shift register unit further includes a plurality of clock signal terminals; The chopping module includes a fifth NOR gate and a fourteenth NOT gate, wherein a first input end of the fifth NOR gate is connected to the output module, a second input end thereof is connected to the clock signal terminal, and an output end thereof is connected to an input end of the fourteenth NOT gate.

16. A shift register circuit, characterized in that, The shift register circuit includes a plurality of shift register units as described in any one of claims 1-15; and a plurality of the shift register units are cascaded.

17. A display panel, characterized in that, The display panel includes a plurality of pixel driving circuits and the shift register circuit as described in claim 16; and the gate driving signal output by the shift register circuit is used to drive a gate of a transistor in the pixel driving circuit.

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