Driving circuit and array substrate

Abstract

The invention provides a driving circuit and an array substrate, and relates to the technical field of display. The driving circuit comprises a plurality of shift registers which are arranged in a cascade mode, and one shift register is electrically connected with multiple rows (such as four rows) of sub-pixels in the display area so as to provide grid control signals for the multiple rows of sub-pixels at the same time. Due to the fact that the multiple output subunits in the same shifting register are independently arranged, signal interference does not exist between the grid control signals output to the corresponding subpixel rows by the multiple output subunits, and the output stability of the driving circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a driving circuit and an array substrate. Background Art

[0002] With the progress of display technologies, compared with traditional Liquid Crystal Display (LCD) devices, a new generation of Organic Light Emitting Diode (OLED) display devices have advantages such as lower manufacturing costs, faster response speeds, higher contrast ratios, wider viewing angles, larger operating temperature ranges, no need for a backlight unit, vivid colors, and being thin and light. Therefore, OLED display technology has become the fastest developing display technology currently.

[0003] In order to improve the process integration degree of the OLED panel and reduce costs, the Gate Driver on Array (GOA) technology is usually adopted to integrate the gate driving circuit of thin film transistors (TFTs) on the array substrate of the display panel to form a scanning drive for the display panel. This gate driving circuit integrated on the array substrate by using the GOA technology is also called a GOA unit or a shift register. The display device adopting the GOA circuit can reduce costs in terms of both material costs and manufacturing processes because the part of the bonding driving circuit is omitted. Summary of the Invention

[0004] The embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a driving circuit is provided, including: a plurality of cascaded shift registers, the m-th shift register is electrically connected to multiple rows of sub-pixels, and the m-th shift register includes:

[0006] An input sub-circuit, electrically connected to a plurality of first nodes, a signal input terminal, and a first cascaded signal input terminal respectively, and configured to input the signal transmitted by the signal input terminal into the plurality of first nodes under the control of the signal transmitted by the first cascaded signal input terminal;

[0007] An output sub-circuit, including a plurality of output sub-units, each output sub-unit is respectively connected to one of the first nodes, a clock signal line, and a gate control signal output terminal, and the output sub-unit is configured to output the clock signal transmitted by the clock signal line from the gate control signal output terminal under the control of the signal of the first node; each gate control signal output terminal is electrically connected to one row of the sub-pixels;

[0008] A pull-up sub-circuit, respectively electrically connected to the first power supply signal input line and the second node, is configured to pull up the voltage of the second node under the control of the first power supply signal input to the first power supply signal input line;

[0009] A first pull-down sub-circuit, respectively electrically connected to the pull-up sub-circuit, the second node, the low-level signal input line, and the output sub-circuit, is configured to pull down the voltage of the second node;

[0010] A second pull-down sub-circuit, respectively electrically connected to the second node, the low-level signal input line, and the multiple first nodes, is configured to pull down the voltage of the multiple first nodes under the control of the signal of the second node;

[0011] A reset sub-circuit, respectively electrically connected to the reset signal line, the low-level signal input line, and the multiple first nodes, is configured to reset the signals of the multiple first nodes under the control of the reset signal transmitted by the reset signal line;

[0012] A third pull-down sub-circuit, respectively electrically connected to the second node, the low-level signal input line, and multiple gate control signal output ends, is configured to reduce the noise of the signals output by the gate control signal output ends under the control of the signal of the second node; m is a positive integer.

[0013] In some driving circuits provided by the embodiments of the present application, the low-level signal input line includes a first level signal line and a second level signal line;

[0014] The first pull-down sub-circuit, the second pull-down sub-circuit, and the reset sub-circuit are all electrically connected to the first level signal, the third pull-down sub-circuit is electrically connected to the second level signal line, and the voltage of the first level signal transmitted by the first level signal line is different from the voltage of the second level signal transmitted by the second level signal line.

[0015] In some driving circuits provided by the embodiments of the present application, the voltage of the second level signal transmitted by the second level signal line is less than the voltage of the first level signal transmitted by the first level signal line.

[0016] In some driving circuits provided by the embodiments of the present application, the low-level signal input line includes a third level signal line, and the first pull-down sub-circuit, the second pull-down sub-circuit, the reset sub-circuit, and the third pull-down sub-circuit are all electrically connected to the third level signal.

[0017] In some driving circuits provided by the embodiments of the present application, the signal input end and the first cascaded signal input end are shared.

[0018] In some driving circuits provided by the embodiments of the present application, the signal input end is electrically connected to the second power supply signal input line.

[0019] In some driving circuits provided by the embodiments of the present application, the output sub-circuit includes a cascading unit, the input sub-circuit includes a first cascading transistor, the second pulling-down sub-circuit includes a second cascading transistor, the reset sub-circuit includes a third cascading transistor, and the third pulling-down sub-circuit includes a fourth cascading transistor;

[0020] The cascading unit is respectively electrically connected to the third node, the cascading clock signal line, and the cascading signal output end, and is configured to output the signal transmitted by the cascading clock signal line from the cascading signal output end under the control of the third node;

[0021] The first cascading transistor is respectively electrically connected to the third node, the signal input end, and the first cascading signal input end, and is configured to input the signal transmitted by the signal input end into the third node under the control of the first cascading signal transmitted by the first cascading signal input end;

[0022] The second cascading transistor is respectively electrically connected to the second node, the low-level signal input line, and the third node, and is configured to pull down the voltage of the third node under the control of the signal of the second node;

[0023] The third cascading transistor is respectively electrically connected to the reset signal line, the low-level signal input line, and the third node, and is configured to reset the signal of the third node under the control of the reset signal transmitted by the reset signal line;

[0024] The fourth cascading transistor is respectively electrically connected to the second node, the low-level signal input line, and the cascading signal output end, and is configured to reduce the noise of the signal output by the cascading signal output end under the control of the signal of the second node;

[0025] The first pulling-down sub-circuit is electrically connected to the output sub-circuit through the third node.

[0026] In some driving circuits provided by the embodiments of the present application, the cascading signal output end of the (m - 1)-th stage shift register serves as the first cascading signal input end of the m-th stage shift register, where m > 2;

[0027] The first pulling-down sub-circuit is also respectively electrically connected to the cascading signal output end of the (m - 1)-th stage shift register and the cascading signal output end of the (m + 2)-th stage shift register.

[0028] In some driving circuits provided by the embodiments of the present application, in the m-th stage of the shift register, the output sub-circuit includes the n-th gate control signal output terminal, the (n + 1)-th gate control signal output terminal, the (n + 2)-th gate control signal output terminal, and the (n + 3)-th gate control signal output terminal;

[0029] The (n - 4)-th gate control signal output terminal serves as the first cascading signal input terminal of the m-th stage of the shift register, and the first pulling-down sub-circuit is also electrically connected to the (n - 4)-th gate control signal output terminal and the (n + 8)-th gate control signal output terminal respectively. n is a positive integer, and n > 4.

[0030] In some driving circuits provided by the embodiments of the present application, in the m-th stage of the shift register, the output sub-circuit includes the n-th gate control signal output terminal, the (n + 1)-th gate control signal output terminal, the (n + 2)-th gate control signal output terminal, and the (n + 3)-th gate control signal output terminal;

[0031] The (n - 3)-th gate control signal output terminal serves as the first cascading signal input terminal of the m-th stage of the shift register, and the first pulling-down sub-circuit is also electrically connected to the (n - 3)-th gate control signal output terminal and the (n + 9)-th gate control signal output terminal respectively. n is a positive integer, and n > 3.

[0032] In some driving circuits provided by the embodiments of the present application, the m-th stage of the shift register further includes a first anti-leakage electronic circuit, and the signal input terminal and the first cascading signal input terminal are shared;

[0033] The first anti-leakage electronic circuit is electrically connected to the input sub-circuit, the pulling-up sub-circuit, the first pulling-down sub-circuit, the third node, the second pulling-down sub-circuit, and the first power signal input line respectively, and is configured to prevent leakage between the third node and multiple first nodes under the control of the signal of the third node.

[0034] In some driving circuits provided by the embodiments of the present application, the m-th stage of the shift register further includes a first anti-leakage electronic circuit, and the signal input terminal is electrically connected to the second power signal input line;

[0035] The first anti-leakage electronic circuit is electrically connected to the pulling-up sub-circuit, the first pulling-down sub-circuit, the third node, the second pulling-down sub-circuit, and the first power signal input line respectively, and is configured to prevent leakage between the third node and multiple first nodes under the control of the signal of the third node.

[0036] In some driving circuits provided by the embodiments of the present application, the m-th stage of the shift register further includes a second anti-leakage electronic circuit, and the second anti-leakage electronic circuit is electrically connected to the second power signal input line and the input sub-circuit respectively; the second anti-leakage electronic circuit is configured to transmit a high-level signal to the third node and a plurality of the first nodes through the input sub-circuit when the input sub-circuit is turned on, so as to prevent the third node and the plurality of the first nodes from leaking electricity.

[0037] In some driving circuits provided by the embodiments of the present application, the clock signal transmitted in the clock signal line includes a first level signal, and the signal output by the gate control signal output terminal includes the first level signal;

[0038] The reset signal transmitted in the reset signal line includes a second level signal, the cascaded clock signal transmitted in the cascaded clock signal line includes the second level signal, and the signal output by the cascaded signal output terminal includes the second level signal;

[0039] The voltage of the second level signal is less than the voltage of the first level signal.

[0040] In some driving circuits provided by the embodiments of the present application, the input sub-circuit includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The gates of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the first cascaded signal input terminal. The sources of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the signal input terminal. The drain of the second transistor is electrically connected to the fourth first node, the drain of the third transistor is electrically connected to the third first node, the drain of the fourth transistor is electrically connected to the second first node, and the drain of the fifth transistor is electrically connected to the first first node.

[0041] In some driving circuits provided by the embodiments of the present application, the output sub-circuit includes a ninth transistor, an eleventh transistor, a thirteenth transistor, a fifteenth transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

[0042] The gate of the ninth transistor is electrically connected to the first first node, the source of the ninth transistor is electrically connected to the first clock signal line, the drain of the ninth transistor is electrically connected to the n-th gate control signal output terminal, and the first capacitor is electrically connected to the gate of the ninth transistor and the drain of the ninth transistor respectively;

[0043] The gate of the eleventh transistor is electrically connected to the second one of the first nodes, the source of the eleventh transistor is electrically connected to the second clock signal line, the drain of the eleventh transistor is electrically connected to the (n + 1)-th gate control signal output terminal, and the second capacitor is electrically connected to the gate and the drain of the eleventh transistor respectively;

[0044] The gate of the thirteenth transistor is electrically connected to the third one of the first nodes, the source of the thirteenth transistor is electrically connected to the third clock signal line, the drain of the thirteenth transistor is electrically connected to the (n + 2)-th gate control signal output terminal, and the third capacitor is electrically connected to the gate and the drain of the thirteenth transistor respectively;

[0045] The gate of the fifteenth transistor is electrically connected to the fourth one of the first nodes, the source of the fifteenth transistor is electrically connected to the fourth clock signal line, the drain of the fifteenth transistor is electrically connected to the (n + 3)-th gate control signal output terminal, and the fourth capacitor is electrically connected to the gate and the drain of the fifteenth transistor respectively, where n is a positive integer.

[0046] In some driving circuits provided by the embodiments of the present application, the pulling-up sub-circuit includes a twenty-fourth transistor and a twenty-sixth transistor, the first pulling-down sub-circuit includes a twenty-second transistor, a twenty-third transistor, a twenty-fifth transistor and a twenty-seventh transistor, and the second pulling-down sub-circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a twenty-first transistor;

[0047] The gate and the source of the twenty-fourth transistor are both electrically connected to the first power signal input line, the drain of the twenty-fourth transistor is electrically connected to the source of the twenty-fifth transistor and the gate of the twenty-sixth transistor respectively, the source of the twenty-sixth transistor is electrically connected to the first power signal input line, and the drain of the twenty-sixth transistor is electrically connected to the second node;

[0048] The drains of the twenty-third transistor and the twenty-seventh transistor are both electrically connected to the second node;

[0049] The gates of the eighteenth transistor, the nineteenth transistor, the twentieth transistor and the twenty-first transistor are all electrically connected to the second node, the drain of the eighteenth transistor is electrically connected to the first one of the first nodes, the drain of the nineteenth transistor is electrically connected to the second one of the first nodes, the drain of the twentieth transistor is electrically connected to the third one of the first nodes, and the drain of the twenty-first transistor is electrically connected to the fourth one of the first nodes;

[0050] The sources of the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fifth transistor, and the twenty-seventh transistor are all electrically connected to the low-level signal input line.

[0051] In some driving circuits provided by the embodiments of the present application, the third pulling-down sub-circuit includes a tenth transistor, a twelfth transistor, a fourteenth transistor, and a sixteenth transistor.

[0052] The gates of the tenth transistor, the twelfth transistor, the fourteenth transistor, and the sixteenth transistor are all electrically connected to the second node. The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, and the sixteenth transistor are all electrically connected to the low-level signal input line. The drain of the tenth transistor is electrically connected to the drain of the ninth transistor. The drain of the twelfth transistor is electrically connected to the drain of the eleventh transistor. The drain of the fourteenth transistor is electrically connected to the drain of the thirteenth transistor. The drain of the sixteenth transistor is electrically connected to the drain of the fifteenth transistor.

[0053] The reset sub-circuit includes four twenty-eighth transistors. The gates of the four twenty-eighth transistors are all electrically connected to the reset signal line. The drains of the four twenty-eighth transistors are respectively electrically connected to the first first node, the second first node, the third first node, and the fourth first node. The sources of the four twenty-eighth transistors are all electrically connected to the low-level signal input line.

[0054] In some driving circuits provided by the embodiments of the present application, the signal input end and the first cascaded signal input end are shared. The (n - 4)-th gate control signal output end serves as the first cascaded signal input end of the m-th stage of the shift register. The low-level signal input line includes a third-level signal line.

[0055] The gates and sources of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the (n - 4)-th gate control signal output end.

[0056] The gate of the twenty-second transistor is electrically connected to the (n + 8)-th gate control signal output end. The drain of the twenty-second transistor is electrically connected to the first first node. The gate of the twenty-third transistor is electrically connected to the (n - 4)-th gate control signal output end. The gates of the twenty-fifth transistor and the twenty-seventh transistor are both electrically connected to the first first node.

[0057] The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty - first transistor, the twenty - second transistor, the twenty - third transistor, the twenty - fifth transistor, the twenty - seventh transistor and the four twenty - eighth transistors are all electrically connected to the third - level signal line, where n>4.

[0058] In some driving circuits provided by the embodiments of the present application, the signal input terminal and the first cascaded signal input terminal are shared, and the (n - 3)th gate control signal output terminal serves as the first cascaded signal input terminal of the m - th shift register, and the low - level signal input line includes a third - level signal line;

[0059] The gates of the second transistor, the third transistor, the fourth transistor and the fifth transistor, and the sources of the second transistor, the third transistor, the fourth transistor and the fifth transistor are all electrically connected to the (n - 3)th gate control signal output terminal;

[0060] The gate of the twenty - second transistor is electrically connected to the (n + 9)th gate control signal output terminal, the drain of the twenty - second transistor is electrically connected to the first first node, the gate of the twenty - third transistor is electrically connected to the (n - 3)th gate control signal output terminal; the gates of the twenty - fifth transistor and the twenty - seventh transistor are both electrically connected to the first first node;

[0061] The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty - first transistor, the twenty - second transistor, the twenty - third transistor, the twenty - fifth transistor, the twenty - seventh transistor and the four twenty - eighth transistors are all electrically connected to the third - level signal line where n>3.

[0062] In some driving circuits provided by the embodiments of the present application, the signal input terminal includes a second power - supply signal input line, the (n - 4)th gate control signal output terminal serves as the first cascaded signal input terminal of the m - th shift register, and the low - level signal input line includes a third - level signal line;

[0063] The gates of the second transistor, the third transistor, the fourth transistor and the fifth transistor are all electrically connected to the (n - 4)th gate control signal output terminal, and the sources of the second transistor, the third transistor, the fourth transistor and the fifth transistor are all electrically connected to the second power - supply signal input line;

[0064] The gate of the twenty-second transistor is electrically connected to the (n + 8)-th gate control signal output terminal, the drain of the twenty-second transistor is electrically connected to the first first node, and the gate of the twenty-third transistor is electrically connected to the (n - 4)-th gate control signal output terminal; the gates of the twenty-fifth transistor and the twenty-seventh transistor are both electrically connected to the first first node;

[0065] The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fifth transistor, the twenty-seventh transistor, and the four twenty-eighth transistors are all electrically connected to the third-level signal line; where n > 4.

[0066] In some driving circuits provided by the embodiments of the present application, the signal input terminal includes a second power supply signal input line, the (n - 3)-th gate control signal output terminal serves as the first cascading signal input terminal of the m-th shift register, and the low-level signal input line includes a third-level signal line;

[0067] The gates of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the (n - 3)-th gate control signal output terminal, and the sources of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the second power supply signal input line;

[0068] The gate of the twenty-second transistor is electrically connected to the (n + 9)-th gate control signal output terminal, the drain of the twenty-second transistor is electrically connected to the first first node, and the gate of the twenty-third transistor is electrically connected to the (n - 3)-th gate control signal output terminal; the gates of the twenty-fifth transistor and the twenty-seventh transistor are both electrically connected to the first first node;

[0069] The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fifth transistor, the twenty-seventh transistor, and the four twenty-eighth transistors are all electrically connected to the third-level signal line; where n > 3.

[0070] In some driving circuits provided by the embodiments of the present application, the input sub-circuit further includes a sixth transistor, the output sub-circuit further includes a seventh transistor and a fifth capacitor, the third pulling-down sub-circuit further includes an eighth transistor, the second pulling-down sub-circuit further includes a seventeenth transistor, and the reset sub-circuit further includes a fifth one of the twenty-eighth transistors;

[0071] The drain of the sixth transistor is electrically connected to the third node, the gate of the seventh transistor is electrically connected to the third node, the source of the seventh transistor is electrically connected to the cascaded clock signal line, the drain of the seventh transistor is electrically connected to the cascaded signal output terminal, and the fifth capacitor is electrically connected to the gate and the drain of the seventh transistor respectively;

[0072] The gate of the eighth transistor is electrically connected to the second node, the drain of the eighth transistor is electrically connected to the cascaded signal output terminal, the gate of the seventeenth transistor is electrically connected to the second node, the drain of the seventeenth transistor is electrically connected to the third node, the gate of the fifth one of the twenty-eighth transistors is electrically connected to the reset signal line, and the drain of the fifth one of the twenty-eighth transistors is electrically connected to the third node;

[0073] The gate of the twenty-second transistor is electrically connected to the cascaded signal output terminal of the (m + 2)-th stage of the shift register, and the drain of the twenty-second transistor is electrically connected to the third node; the gate of the twenty-third transistor is electrically connected to the cascaded signal output terminal of the (m - 1)-th stage of the shift register, and the gates of the twenty-fifth transistor and the twenty-seventh transistor are both electrically connected to the third node, where m > 1.

[0074] In some driving circuits provided by the embodiments of the present application, the low-level signal input line includes a third-level signal line, and the sources of the transistors in the first pulling-down sub-circuit, the second pulling-down sub-circuit, the reset sub-circuit, and the third pulling-down sub-circuit are all electrically connected to the third-level signal line;

[0075] The gates and sources of the transistors in the input sub-circuit are both electrically connected to the cascaded signal output terminal of the (m - 1)-th stage of the shift register.

[0076] In some driving circuits provided by the embodiments of the present application, the low-level signal input line includes a third-level signal line, and the sources of the transistors in the first pulling-down sub-circuit, the second pulling-down sub-circuit, the reset sub-circuit, and the third pulling-down sub-circuit are all electrically connected to the third-level signal line;

[0077] The gates of the transistors in the input sub - circuit are all electrically connected to the cascade signal output terminal of the (m - 1)th stage of the shift register, and the sources of the transistors in the input sub - circuit are all electrically connected to the second power - signal input line.

[0078] In some driving circuits provided by the embodiments of the present application, the low - level signal input line includes a first - level signal line and a second - level signal line, and the voltage of the second - level signal transmitted by the second - level signal line is less than the voltage of the first - level signal transmitted by the first - level signal line;

[0079] The sources of the transistors in the first pulling - down sub - circuit, the second pulling - down sub - circuit, and the reset sub - circuit are all electrically connected to the first - level signal, and the sources of the transistors in the third pulling - down sub - circuit except the eighth transistor are electrically connected to the first - level signal line; the source of the eighth transistor is electrically connected to the second - level signal line;

[0080] The mth - stage shift register further includes a first transistor and a twenty - ninth transistor. The gate of the first transistor is electrically connected to the cascade signal output terminal of the (m - 1)th stage of the shift register, and the drain of the first transistor is electrically connected to the sources of the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor respectively;

[0081] The gate of the twenty - ninth transistor is electrically connected to the third node, the source of the twenty - ninth transistor is electrically connected to the first power - signal input line, and the drain of the twenty - ninth transistor is electrically connected to the fourth node;

[0082] The seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty - first transistor, the twenty - second transistor, the twenty - fourth transistor, five of the twenty - eighth transistors, and the twenty - ninth transistor each include two serially - connected sub - transistors, and the two sub - transistors in any one of the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, and the twenty - first transistor are connected through the fourth node.

[0083] In some driving circuits provided by the embodiments of the present application, the source of the first transistor is electrically connected to the cascade signal output terminal of the (m - 1)th stage of the shift register;

[0084] The drain of the twenty - ninth transistor is also electrically connected to the sources of the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor respectively.

[0085] In some driving circuits provided by embodiments of the present application, a source electrode of the first transistor is electrically connected to a second power signal input line.

[0086] In some driving circuits provided by embodiments of the present application, the m-th stage of the shift register further includes a thirtieth transistor. A gate electrode and a source electrode of the thirtieth transistor are both electrically connected to the second power signal input line. A drain electrode of the thirtieth transistor is further electrically connected to source electrodes of the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor respectively; wherein, the thirtieth transistor includes two sub-transistors.

[0087] In some driving circuits provided by embodiments of the present application, the first power signal input line and the second power signal input line are shared.

[0088] In some driving circuits provided by embodiments of the present application, gate control signals output from respective gate control signal output ends in the m-th stage of the shift register overlap with each other in sequence.

[0089] In some driving circuits provided by embodiments of the present application, a charging time of the sub-pixel is 2H, and an overlapping time between gate control signals of adjacent two rows of the sub-pixels is 1H.

[0090] In some driving circuits provided by embodiments of the present application, a charging time of the sub-pixel is 3H, and an overlapping time between gate control signals of adjacent two rows of the sub-pixels is 2H.

[0091] In some driving circuits provided by embodiments of the present application, a signal transmitted by the cascaded clock signal line has the same phase and period as a signal transmitted by the first clock signal line;

[0092] Alternatively, a signal transmitted by the cascaded clock signal line has the same phase and period as a signal transmitted by the second clock signal line.

[0093] In a second aspect, embodiments of the present application provide an array substrate, which includes the driving circuit according to any one of the first aspect.

[0094] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the description. And in order to make the above and other objects, features, and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically exemplified below. Description of the Drawings

[0095] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0096] Figures 1 to 4 Four shift register circuit structures without cascade units provided for the embodiments of the present application;

[0097] Figure 5 For Figure 1 And Figure 3 The corresponding cascade circuit architecture diagram;

[0098] Figure 6 For Figure 2 And Figure 4 The corresponding cascade circuit architecture diagram;

[0099] Figure 7 For Figure 1 And Figure 3 The corresponding timing signal diagram;

[0100] Figure 8 For Figure 2 And Figure 4 The corresponding timing signal diagram;

[0101] Figures 9 to 10 Two shift register circuit structures with cascade units provided for the embodiments of the present application;

[0102] Figure 11 For Figure 9 And Figure 10 The corresponding timing signal diagram;

[0103] Figures 12 to 14 Another three shift register circuit structures with cascade units provided for the embodiments of the present application;

[0104] Figure 15 For Figure 12 And Figure 14 The corresponding timing signal diagram;

[0105] Figure 16 For Figure 9 、 Figure 10 、 Figures 12 to 14 The corresponding cascade circuit architecture diagram;

[0106] Figure 17 For Figure 12 The shift register circuit shown in Figure 15 The output waveform diagrams of four gate control signals obtained by simulation under the shown timing;

[0107] Figure 18 For Figure 12 The output waveform diagram of four first nodes obtained by simulation when the low level of the clock signal is the second level signal and the threshold voltage of the transistor is 3V for the shift register circuit shown;

[0108] Figure 19 For Figure 18 The output waveform diagram of the corresponding four gate control signals;

[0109] Figure 20 For Figure 12 The output waveform diagram of four first nodes obtained by simulation when the low level of the clock signal is the second level signal and the threshold voltage of the transistor is 1.5V for the shift register circuit shown;

[0110] Figure 21 For Figure 20 The output waveform diagram of the corresponding four gate control signals. Detailed implementation manners

[0111] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0112] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" etc. are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the described specific features, structures, materials or characteristics can be included in any one or more embodiments or examples in any appropriate manner.

[0113] In the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using words such as "first" and "second" only for clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features.

[0114] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0115] In this application, a transistor refers to an element having at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel region, and the source. In this application, the channel region refers to the region where current mainly flows.

[0116] In this application, the transistor can be a thin-film transistor or a field-effect transistor, etc. This application will be described by taking a thin-film transistor as an example.

[0117] In this application, in the case of using transistors with opposite polarities or when the current direction changes during the operation of the circuit, etc., the functions of the "source" and "drain" sometimes swap with each other. Therefore, in this application, the "source" and "drain" can swap with each other.

[0118] In an embodiment of this application, the driving circuit is an integrated gate driving circuit (Gate Driver on Array, GOA). The GOA driving circuit technology directly manufactures the gate driving circuit on the array substrate to achieve a line-by-line scanning driving method and is used in various display devices. Since the GOA driving circuit can be directly made on the array substrate, the process of bonding the driving IC is omitted, the dependence of the array substrate on the relatively expensive driving IC is reduced, the cost is lowered, and at the same time, the design requirements of narrow borders and low power consumption of the display product can be achieved.

[0119] Embodiments of the present application provide a driving circuit and an array substrate. The driving circuit includes a plurality of cascaded shift registers. One shift register is electrically connected to multiple rows (e.g., four rows) of sub-pixels in the display area AA to simultaneously provide gate control signals to the multiple rows of sub-pixels. The shift register provided by the embodiments of the present application includes a plurality of output sub-units. Each output sub-unit is respectively connected to a first node, a clock signal line, and a gate control signal output terminal. The output sub-unit is configured to output the clock signal transmitted by the clock signal line from the gate control signal output terminal under the control of the signal of the first node; each gate control signal output terminal is electrically connected to one row of sub-pixels. Since the multiple output sub-units in the same shift register provided by the embodiments of the present application are independently arranged, there is no signal interference between the gate control signals output by the multiple output sub-units to the corresponding sub-pixel rows. In this way, on the one hand, compared with the driving circuit in the related art where one shift register is connected to one row of sub-pixels, the design of the GOA circuit is greatly simplified, saving design space; on the other hand, since there is no signal interference between the gate control signals output by the multiple output sub-units of the same shift register to the corresponding sub-pixel rows, the output stability of the driving circuit and the driving stability of the pixel circuit in the subsequent sub-pixels are improved, thereby improving the display performance and display effect of the array substrate.

[0120] The driving circuit provided by the embodiments of the present application will be specifically introduced and described below with reference to the drawings.

[0121] The present application provides a driving circuit, as Figure 5 、 Figure 6 and Figure 16 shown, including: a plurality of cascaded shift registers, and the m-th stage shift register GOA(m) is electrically connected to multiple rows of sub-pixels.

[0122] Among them, as Figures 1 to 4 、 Figure 9 、 Figure 10 、 Figure 12 、 Figure 13 and Figure 14 shown, the m-th stage shift register GOA(m) includes: an input sub-circuit 1, an output sub-circuit 2, a pull-up sub-circuit 3, a first pull-down sub-circuit 4, a second pull-down sub-circuit 5, a reset sub-circuit 6, and a third pull-down sub-circuit 7.

[0123] Among them, the input sub-circuit 1 is respectively connected to a plurality of first nodes (e.g., Q <n>, Q<n + 1>, Q<n + 2>, Q<n + 3>), the signal input terminal is electrically connected to the first cascaded signal input terminal, and is configured to input the signal transmitted by the signal input terminal to a plurality of first nodes under the control of the signal transmitted by the first cascaded signal input terminal.

[0124] In an exemplary embodiment, the signal input terminal refers to the signal terminal to which the sources of the transistors in the input sub - circuit 1 are electrically connected, and signals can be written into the input sub - circuit 1 through the signal input terminal; the first cascaded signal input terminal is used to receive the trigger signal (also called the STV signal) of the current - stage shift register.

[0125] Exemplarily, in Figure 1 , Figure 2 in, Figure 9 and Figure 12 in, the first cascaded signal input terminal serves as the signal input terminal, that is, the first cascaded signal input terminal and the signal input terminal are shared.

[0126] For example, Figure 1 in, the signal OUT output from the (n - 4)th gate control signal output terminal <n-4>, and simultaneously transmitted to the first cascade signal input terminal and the signal input terminal;

[0127] For example, Figure 2 the signal OUT output from the (n - 3)-th gate control signal output terminal in <n-3>, while being transmitted to the first cascaded signal input terminal and the signal input terminal simultaneously;

[0128] For example, Figure 9 and Figure 12 in, the signal CR output from the cascaded output terminal of the (m - 1)-th stage shift register <m-1>, and transmitted to the first cascaded signal input terminal and the signal input terminal simultaneously;

[0129] Exemplarily, such as Figure 3 , Figure 4 , Figure 10 , Figure 13 and Figure 14 As shown, the signal input terminal is used to connect the second power supply signal line GVDD2.

[0130] Exemplarily, the second power supply signal line GVDD2 is used to transmit a high-level signal with a constant voltage.

[0131] Among them, the output sub-circuit 2 includes a plurality of output sub-units. Each output sub-unit is respectively connected to a first node, a clock signal line, and a gate control signal output terminal. The output sub-unit is configured to output the clock signal transmitted by the clock signal line from the gate control signal output terminal under the control of the signal at the first node; each gate control signal output terminal is electrically connected to a row of sub-pixels;

[0132] Exemplarily, such as Figures 1 to 4 , Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 As shown, the output sub-circuit 2 includes 4 output sub-units. The first output sub-unit is respectively connected to the first first node Q <n>, the first clock signal line CLK1 and the first gate control signal output terminal OUT <n>; The second output sub-unit is respectively connected to the second first node Q<n+1>, the second clock signal line CLK2, and the second gate control signal output terminal OUT<n+1>; The third output sub-unit is respectively connected to the third first node Q<n+2>, the third clock signal line CLK3, and the third gate control signal output terminal OUT<n+2>; The fourth output sub-unit is respectively connected to the fourth first node Q<n+3>, the fourth clock signal line CLK4, and the fourth gate control signal output terminal OUT<n+3>.

[0133] Among them, the pull-up sub-circuit 3 is respectively connected to the first power supply signal input line GVDD1 and the second node QB <m>Electrically connected and configured to pull up the second node QB under the control of a first power supply signal input on a first power supply signal input line GVDD1 <m>voltage;

[0134] Exemplarily, the first power supply signal input line GVDD1 is used to transmit a high-level signal with a constant voltage. Among them, the voltages of the high-level signals transmitted by the first power supply signal input line GVDD1 and the second power supply signal line GVDD2 may be the same or different.

[0135] Among them, the first pulling-down sub-circuit 4 is respectively connected to the pulling-up sub-circuit 3 and the second node QB <m>is electrically connected to the low-level signal input line and the output sub-circuit 2, and is configured to pull down the second node QB <m>voltage;

[0136] Exemplarily, such as Figures 1 to 4 As shown, the first pull-down sub-circuit 4 passes through the first first node Q <n>Electrically connected to the output sub-circuit 2.

[0137] Exemplarily, such as Figure 9 、 Figure 10 、 Figures 12 to 14 As shown, the first pulling-down sub-circuit 4 passes through the third node QC <m>Electrically connected to the output sub-circuit 2.

[0138] Among them, the second pulling-down sub-circuit 5 is respectively connected to the second node QB <m>, low-level signal input line, and multiple first nodes (e.g., Q <n>, Q<n + 1>, Q<n + 2>, Q<n + 3>) are electrically connected and are configured to be at the second node QB <m>Under the control of the signal, pull down a plurality of first nodes (such as Q <n>, the voltages of Q<n+1>, Q<n+2>, Q<n+3>;

[0139] Wherein, the reset sub-circuit 6 is respectively electrically connected to the reset signal line TRST, the low-level signal input line and a plurality of first nodes, and is configured to reset the signals of the plurality of first nodes under the control of the reset signal transmitted on the reset signal line TRST;

[0140] Wherein, the third pulling-down sub-circuit 7 is respectively connected to the second node QB <m>, low-level signal input line and multiple gate control signal output terminals (such as OUT <n>, OUT<n+1>, OUT<n+2>, OUT<n+3>) are electrically connected and are configured to be at the second node QB <m>Under the control of the signal, noise reduction is performed on the signal output from the gate control signal output terminal; m is a positive integer.

[0141] In an exemplary embodiment, as Figure 12 , Figure 13 and Figure 14 shown, the low-level signal input line includes a first level signal line VGL1 and a second level signal line VGL2;

[0142] The first pulling-down sub-circuit 4, the second pulling-down sub-circuit 5, and the reset sub-circuit 6 are all electrically connected to the first level signal line VGL1, and the third pulling-down sub-circuit 7 is electrically connected to the second level signal line VGL2. The voltage of the first level signal transmitted by the first level signal line VGL1 is different from the voltage of the second level signal transmitted by the second level signal line VGL2. Among them, the third pulling-down sub-circuit 7 is also electrically connected to the first level signal line VGL1.

[0143] In some driving circuits provided in the embodiments of the present application, the voltage of the second level signal transmitted by the second level signal line VGL2 is less than the voltage of the first level signal transmitted by the first level signal line VGL1.

[0144] In the embodiments of the present application, as Figure 12 , Figure 13 and Figure 14 shown, by setting V VGL2 -V VGL1 < 0V, in this way, when each transistor except the eighth transistor T8 in the third pull-down sub-circuit 7 is turned off, the gate-source voltage Vgs of each transistor = QB <m>-Vs = V VGL2 -V VGL1 < 0V, which can make each transistor in the third pull-down sub-circuit 7 except the eighth transistor T8 turn off more completely, so as to prevent each gate control signal output terminal in the output sub-circuit 2 (such as OUT <n>, OUT<n+1>, OUT<n+2>, OUT<n+3>) leak through the third pull-down sub-circuit 7, improving the stability of the output signal at the gate control signal output terminal and enhancing the driving performance of the driving circuit.

[0145] In addition, it should be noted that the smaller V VGL2 is, the faster the voltage jumps when the second node and the third node are pulled low. Correspondingly, the transistors controlled by the second node and the third node turn off faster, and the leakage time is shorter.

[0146] Exemplarily, in the driving circuits such as Figure 12 , Figure 13 and Figure 14 shown, each transistor can be a depletion-type transistor.

[0147] For example, the threshold voltage Vth of some depletion-type transistors can be greater than or equal to 0, and the threshold voltage Vth of some depletion-type transistors can be less than or equal to 0.

[0148] The depletion-type transistors can include oxide transistors.

[0149] Exemplarily, in the driving circuits such as Figures 1 to 4 , Figure 9 and Figure 10 shown, each transistor can be an enhancement-type transistor.

[0150] The enhancement-type transistors can include polycrystalline silicon (Poly-Si) or amorphous silicon (a-Si) transistors.

[0151] In some driving circuits provided in the embodiments of the present application, such as Figures 1 to 4 , Figure 9 and Figure 10 shown, the low-level signal input line includes the third-level signal line VGL, and the first pull-down sub-circuit 4, the second pull-down sub-circuit 5, the reset sub-circuit 6, and the third pull-down sub-circuit 7 are all electrically connected to the third-level signal VGL.

[0152] Exemplarily, Figures 1 to 4 , Figure 9 and Figure 10 shown, when each transistor in the driving circuit is an enhancement-type transistor, it can be set that the first pull-down sub-circuit 4, the second pull-down sub-circuit 5, the reset sub-circuit 6, and the third pull-down sub-circuit 7 are all electrically connected to the third-level signal VGL.

[0153] Compared with oxide transistors, the leakage current of other types of transistors is small, and the influence on the driving circuit can be almost negligible. Therefore, the first pull-down sub-circuit 4, the second pull-down sub-circuit 5, the reset sub-circuit 6, and the third pull-down sub-circuit 7 can be set to be electrically connected to the third-level signal VGL, that is, a low-level signal line is set. In this way, the number of signal lines connected to the driving circuit can be reduced, thereby simplifying the design and reducing the cost.

[0154] In some driving circuits provided by the embodiments of the present application, such as Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 as shown, the output sub-circuit 2 includes a cascading unit (for example, including the seventh transistor T7 and the fifth capacitor CC), the input sub-circuit 1 includes a first cascading transistor (for example, including the sixth transistor T6), the second pull-down sub-circuit 5 includes a second cascading transistor (for example, including the seventeenth transistor T17), the reset sub-circuit 6 includes a third cascading transistor (for example, including the fifth twenty-eighth transistor T28-C), and the third pull-down sub-circuit 7 includes a fourth cascading transistor (for example, including the eighth transistor T8); the cascading unit is respectively connected to the third node QC <m>, cascaded clock signal line CLKD and cascaded signal output terminal CR <m>Electrically connected and configured at the third node QC <m>Under the control of, the signal transmitted on the cascaded clock signal line CLKD is output from the cascaded signal output terminal CR <m>Output; the first cascaded transistor is respectively connected to the third node QC <m>, The signal input terminal is electrically connected to the first cascaded signal input terminal, and is configured to input the signal transmitted by the signal input terminal to the third node QC under the control of the first cascaded signal transmitted by the first cascaded signal input terminal <m>; The second cascaded transistor is respectively connected to the second node QB <m>, low-level signal input line and third node QC <m>Electrically connected and configured at the second node QB <m>Under the control of the signal, pull down the third node QC <m>voltage; the third cascaded transistor is respectively connected to a reset signal line TRST, a low-level signal input line, and a third node QC <m>electrically connected and configured to, under the control of a reset signal transmitted on a reset signal line TRST, reset a third node QC <m>Reset the signal of; The fourth cascaded transistor is respectively connected to the second node QB <m>, low-level signal input line and cascaded signal output terminal CR <m>Electrically connected and configured at the second node QB <m>Under the control of the signal, the cascaded signal output terminal CR <m>The output signal is denoised; the first pull-down sub-circuit 4 passes through the third node QC <m>Electrically connected to the output sub-circuit 2.

[0155] In an exemplary embodiment, as Figures 1 to 4 shown, when the cascade unit, the first cascade transistor, the second cascade transistor, the third cascade transistor, and the fourth cascade transistor are not set in the shift register, the first pulling-down sub-circuit 4 passes through the first first node Q <n>Electrically connected to the output sub-circuit 2.

[0156] In an embodiment of the present application, when a cascading unit is provided in the output sub-circuit 2, the shift registers at all levels can be connected through the cascading signal output terminal CR <m>Electrically connected together. To avoid the cascaded signal output terminal CR <m>Connected to the gate control signal output terminal (e.g., OUT <n>) signal interference between, the input sub-circuit 1 is also provided with a first cascaded transistor (for example, including the sixth transistor T6), the second pull-down sub-circuit 5 includes a second cascaded transistor (for example, including the seventeenth transistor T17), the reset sub-circuit 6 includes a third cascaded transistor (for example, including the fifth twenty-eighth transistor T28-C), and the third pull-down sub-circuit 7 includes a fourth cascaded transistor (for example, including the eighth transistor T8) to separately implement signal input to the cascaded unit (implemented by the first cascaded transistor), signal pull-down of the third node (implemented by the second cascaded transistor), signal reset of the third node (implemented by the third cascaded transistor), and cascaded signal output terminal CR <m>Signal noise reduction (implemented by the fourth cascaded transistor).

[0157] In some driving circuits provided in the embodiments of the present application, such as Figure 16 as shown, the cascaded signal output terminal CR of the (m-1)-th stage shift register GOA(m-1) <m-1>As the first cascaded signal input terminal of the m-th stage shift register GOA(m), where m > 2; such as Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 shown, the first pull-down sub-circuit 4 is also respectively connected to the cascaded signal output terminal CR of the (m - 1)-th stage shift register <m-1>is electrically connected to the cascade signal output terminal CR<m+2> of the (m+2)-th shift register.

[0158] Among them, Figure 16 is as shown in Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 the cascade circuit diagram corresponding to the shift register shown. Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 all schematically show the specific circuit structure diagram of the m-th shift register GOA(m).

[0159] Exemplarily, in Figure 16 , the clock signal lines may include a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7, an eighth clock signal line CLK8, a ninth clock signal line CLK9, a tenth clock signal line CLK10, an eleventh clock signal line CLK11, and a twelfth clock signal line CLK12, and the cascade clock signal lines may include a first cascade clock signal line CLKD1, a second cascade clock signal line CLKD2, and a third cascade clock signal line CLKD3; among them, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, and the first cascade clock signal line CLKD1 are correspondingly connected to the m-th shift register GOA(m), the fifth clock signal line CLK5, the sixth clock signal line CLK6, the seventh clock signal line CLK7, the eighth clock signal line CLK8, and the second cascade clock signal line CLKD2 are correspondingly connected to the (m+1)-th shift register GOA(m+1), and the ninth clock signal line CLK9, the tenth clock signal line CLK10, the eleventh clock signal line CLK11, the twelfth clock signal line CLK12, and the third cascade clock signal line CLKD3 are correspondingly connected to the (m-1)-th shift register GOA(m-1).

[0160] In Figure 16 , for the m-th shift register GOA(m), the cascade signal output terminal CR of the (m-1)-th shift register GOA(m-1) <m-1>As the first cascaded signal input terminal of the m-th stage shift register GOA(m), i.e., CR <m-1>As the enable signal STV of the m-th stage shift register GOA(m); the cascade signal output terminal CR<m+2> of the (m+2)-th stage shift register GOA(m+2) serves as the second cascade signal input terminal of the m-th stage shift register GOA(m), that is, CR<m+2> serves as the reset signal STD of the m-th stage shift register GOA(m).

[0161] In some driving circuits provided by the embodiments of the present application, in the m-th stage shift register, the output sub-circuit includes the n-th gate control signal output terminal OUT <n>, the (n + 1)-th gate control signal output terminal OUT<n + 1>, the (n + 2)-th gate control signal output terminal OUT<n + 2>, the (n + 3)-th gate control signal output terminal OUT<n + 3>;

[0162] Combined with Figure 1 , Figure 3 and Figure 5 As shown, the (n - 4)-th gate control signal output terminal serves as the first cascaded signal input terminal of the m-th stage shift register, and the first pull-down sub-circuit 4 is also electrically connected to the (n - 4)-th gate control signal output terminal and the (n + 8)-th gate control signal output terminal respectively. n is a positive integer, and n > 4. Among them, Figure 1 and Figure 3 are schematic circuit diagrams of two shift registers in the case where no cascaded unit, first cascaded transistor, second cascaded transistor, third cascaded transistor, and fourth cascaded transistor are provided. Figure 5 is Figure 1 and Figure 3 corresponding cascaded circuit diagram.

[0163] In Figure 5 , for the m-th stage shift register GOA(m), the gate control signal output terminal OUT of the (m - 1)-th stage shift register GOA(m - 1) <n-4>As the first cascaded signal input terminal of the m-th stage shift register, i.e., the gate control signal output terminal OUT <n-4>The output signal is used as the trigger signal STV of the m-th stage shift register; the gate control signal output terminal OUT<n + 8> of the (m + 2)-th stage shift register GOA(m + 2) is used as the second cascading signal input terminal of the m-th stage shift register, that is, the output signal of the gate control signal output terminal OUT<n + 8> is used as the reset signal STD of the m-th stage shift register. In Figure 5 the number and electrical connection manner of the clock signal line and the cascading clock signal line are the same as those described in the previous Figure 16 and will not be elaborated here.

[0164] Combined with Figure 2 、 Figure 4 and Figure 6 as shown, the (n - 3)-th gate control signal output terminal is used as the first cascading signal input terminal of the m-th stage shift register, and the first pull-down sub-circuit 4 is also electrically connected to the (n - 3)-th gate control signal output terminal and the (n + 9)-th gate control signal output terminal respectively, where n is a positive integer and n > 3.

[0165] In Figure 6 for the m-th stage shift register GOA(m), the gate control signal output terminal OUT of the (m - 1)-th stage shift register GOA(m - 1) <n-3>As the first cascaded signal input terminal of the m-th stage shift register, i.e., the gate control signal output terminal OUT <n-3>The output signal is used as the trigger signal STV of the m-th stage shift register; the gate control signal output terminal OUT<n+9> of the (m+2)-th stage shift register GOA(m+2) is used as the second cascading signal input terminal of the m-th stage shift register, that is, the output signal of the gate control signal output terminal OUT<n+9> is used as the reset signal STD of the m-th stage shift register. In Figure 6 the number and electrical connection manner of the clock signal line and the cascading clock signal line are the same as those described in the previous Figure 16 and will not be elaborated herein.

[0166] In some driving circuits provided by the embodiments of the present application, such as Figure 12 shown, the m-th stage shift register further includes a first anti-leakage electronic circuit 8, and the signal input terminal and the first cascading signal input terminal share CR <m-1>; The first leak-proof electronic circuit 8 is respectively connected to the input sub-circuit 1, the pull-up sub-circuit 3, the first pull-down sub-circuit 4, and the third node QC <m>, the second pull-down sub-circuit 5 is electrically connected to the first power supply signal input line GVDD1 and is configured to be at the third node QC <m>Under the control of the signal, prevent the third node QC <m>and a plurality of first nodes (e.g., Q <n>, Q<n+1>, Q<n+2>, Q<n+3>) leakage.

[0167] In an embodiment of the present application, as Figure 12 shown, by setting the first anti-leakage electronic circuit 8, at the third node QC <m>and a plurality of first nodes (e.g., Q <n>When Q<n+1>, Q<n+2>, and Q<n+3> hold high-level signals, a high-level signal from the first power supply signal input line GVDD1 can be transmitted to the third node and multiple first nodes through the first anti-leakage electronic circuit 8 and the input sub-circuit 1 to ensure that the third node and multiple first nodes maintain high-level signals and avoid leakage. Additionally, since the first anti-leakage electronic circuit 8 is electrically connected to the second pull-down sub-circuit 5, it can prevent the third node and multiple first nodes from leaking electricity from the second pull-down sub-circuit 5 to ensure that the third node and multiple first nodes maintain high-level signals.

[0168] In some driving circuits provided in the embodiments of the present application, such as Figure 13 shown, the m-th stage shift register further includes a first anti-leakage electronic circuit 8, and the signal input end is electrically connected to the second power supply signal input line GVDD2 (at the position indicated by the arrow); the first anti-leakage electronic circuit 8 is respectively connected to the pull-up sub-circuit 3, the first pull-down sub-circuit 4, and the third node QC <m>, the second pull-down sub-circuit 5 is electrically connected to the first power supply signal input line GVDD1 and is configured to be at the third node QC <m>Under the control of the signal, prevent the third node QC <m>and a plurality of first nodes (e.g., Q <n>, leakage of Q<n+1>, Q<n+2>, Q<n+3>).

[0169] Compared with Figure 12 , such as Figure 13 as indicated by the arrow near the first anti-leakage electronic circuit 8 in Figure 13 shown, the first anti-leakage electronic circuit 8 of the circuit shown is not electrically connected to the input sub-circuit 1. Since the signal input terminal is electrically connected to the second power supply signal input line GVDD2, when each transistor in the input sub-circuit 1 is turned on, the second power supply signal input line GVDD2 can transmit a high-level signal to the third node and multiple first nodes through the input sub-circuit to prevent leakage and ensure that the third node and multiple first nodes maintain a high-level signal.

[0170] In some driving circuits provided by the embodiments of the present application, such as Figure 14 shown, the m-th stage shift register further includes a second anti-leakage electronic circuit 9, and the second anti-leakage electronic circuit 9 is electrically connected to the second power supply signal input line GVDD2 and the input sub-circuit 1 respectively; the second anti-leakage electronic circuit 9 is configured to transmit a high-level signal to multiple third nodes and first nodes through the input sub-circuit 1 when the input sub-circuit 1 is turned on to prevent leakage of the third node and multiple first nodes. Among them, Figure 14 the circuit diagram shown is based on Figure 13 and the second anti-leakage electronic circuit 9 is added.

[0171] In the embodiments of the present application, such as Figure 14 shown, by providing the second anti-leakage electronic circuit 9, since the second anti-leakage electronic circuit 9 is connected to the second power supply signal input line GVDD2 and is always turned on, in this way, a high-level signal can be transmitted to the input sub-circuit 1 through the second anti-leakage electronic circuit 9, and multiple third nodes and first nodes will not leak through the input sub-circuit 1, thereby ensuring that the third node and multiple first nodes maintain a high-level signal.

[0172] In some driving circuits provided by the embodiments of the present application, such as Figure 15 shown, the clock signal transmitted in the clock signal line CLK (including CLK1 to CLK12) includes a first level signal VGL1, and the gate control signal output terminal OUT (such as OUT <n>, the signals output by OUT<n+1>, OUT<n+2>, OUT<n+3> include a first level signal VGL1; the reset signal transmitted in the reset signal line TRST includes a second level signal VGL2, and the cascaded clock signal transmitted in the cascaded clock signal line CLKD includes a second level signal VGL2, and the cascaded signal output terminal CR <m>The output signal includes a second-level signal VGL2; the voltage of the second-level signal VGL2 is less than the voltage of the first-level signal VGL2.

[0173] In some other embodiments, it may be set that the clock signal transmitted in the clock signal lines CLK (including CLK1 to CLK12) includes the second-level signal VGL2, and the gate control signal output terminal OUT (such as OUT <n>The signals output by OUT<n+1>, OUT<n+2>, OUT<n+3> include the second-level signal VGL2.

[0174] Figure 17 There is provided Figure 12 The circuit diagram shown in Figure 15 Under the timing of the clock signal shown (the low-level signal of CLK1 to CLK12 is VGL1), four gate control signal output terminals OUT (such as OUT <n>The output signals of (OUT<n+1>, OUT<n+2>, OUT<n+3>). It can be seen that there is no interference between the four gate control signals output by the same shift register, the waveforms are consistent, and there is a time overlap between adjacent two signals.

[0175] Figure 18 provides Figure 12 The waveform diagrams corresponding to the four first nodes of the circuit diagram shown in the case where the low-level signals of the clock signals CLK1 to CLK12 are VGL2 and the threshold voltage Vth of each transistor in the shift register circuit is 3V. Figure 19 are the signal waveforms output at the output ends of the four gate control signals in the same case.

[0176] Figure 20 provides Figure 12 The waveform diagrams corresponding to the four first nodes of the circuit diagram shown in the case where the low-level signals of the clock signals CLK1 to CLK12 are VGL2 and the threshold voltage Vth of each transistor in the shift register circuit is -1.5V. Figure 21 are the signal waveforms output at the output ends of the four gate control signals in the same case.

[0177] It can be seen from the above simulation waveform diagrams that whether the threshold voltage Vth is -1.5V or 3V, there is no voltage attenuation in the signal waveforms output at the four first nodes and the output ends of the four gate control signals, and there is no charge flow and mutual interference between the signals output at the output ends of the four gate control signals, and the waveforms are consistent. In addition, it can be seen from Figure 19 and Figure 21 that there are two voltages, VGL2 and VGL1, for the output low voltage. This is because the low voltage of the clock signal CLK is VGL2 and the pull-down voltage is VGL1. This is to increase the high-low voltage difference of the output pulse, which can reduce the pulse fall time and increase the bootstrap voltage of the first node.

[0178] Next, the specific structures of each circuit will be described in detail with reference to the drawings.

[0179] In some driving circuits provided in the embodiments of the present application, such as Figures 1 to 4 , Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 As shown, the input sub-circuit 1 includes a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The gates of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all electrically connected to the first cascaded signal input terminal. The sources of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all electrically connected to the signal input terminal. The drain of the second transistor T2 is electrically connected to the fourth first node Q<n+3>. The drain of the third transistor T3 is electrically connected to the third first node Q<n+2>. The drain of the fourth transistor T4 is electrically connected to the second first node Q<n+1>. The drain of the fifth transistor T5 is electrically connected to the first first node Q <n>Electrical connection.

[0180] In some driving circuits provided in the embodiments of the present application, such as Figures 1 to 4 , Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 shown, the output sub - circuit 2 includes a ninth transistor T9, an eleventh transistor T11, a thirteenth transistor T13, a fifteenth transistor T15, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4;

[0181] As Figures 1 to 4 , Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 shown, the gate of the ninth transistor T9 is connected to the first first node Q <n>electrically connected, the source of the ninth transistor T9 is electrically connected to the first clock signal line CLK1, and the drain of the ninth transistor T9 is connected to the nth gate control signal output terminal OUT <n>Electrically connected, the first capacitor C1 is electrically connected to the gate and the drain of the ninth transistor T9 respectively; the gate of the eleventh transistor T11 is electrically connected to the second first node Q<n+1>, the source of the eleventh transistor T11 is electrically connected to the second clock signal line CLK2, the drain of the eleventh transistor T11 is electrically connected to the (n+1)-th gate control signal output terminal OUT<n+1>, and the second capacitor C2 is electrically connected to the gate and the drain of the eleventh transistor T11 respectively; the gate of the thirteenth transistor T13 is electrically connected to the third first node Q<n+2>, the source of the thirteenth transistor T13 is electrically connected to the third clock signal line CLK3, the drain of the thirteenth transistor T13 is electrically connected to the (n+2)-th gate control signal output terminal OUT<n+2>, and the third capacitor C3 is electrically connected to the gate and the drain of the thirteenth transistor T13 respectively; the gate of the fifteenth transistor T15 is electrically connected to the fourth first node Q<n+3>, the source of the fifteenth transistor T15 is electrically connected to the fourth clock signal line CLK4, the drain of the fifteenth transistor T15 is electrically connected to the (n+3)-th gate control signal output terminal OUT<n+3>, and the fourth capacitor C4 is electrically connected to the gate and the drain of the fifteenth transistor T15 respectively, where n is a positive integer.

[0182] In an exemplary embodiment, a shift register needs to be electrically connected to four clock signal lines. In the case where the shift register includes cascade units, a shift register needs to be electrically connected to four clock signal lines and one cascade clock signal line. In the driving circuit, the total number of clock signal lines can be a multiple of 4. For example, the total number of clock signal lines in the driving circuit can be 12 (4CLK * 3). Additionally, for another example, in the case where the shift register includes cascade units, the total number of clock signal lines in the driving circuit can be 12 (4CLK * 3), and the total number of cascade clock signal lines can be 3 (1CLKD * 3).

[0183] In some driving circuits provided in the embodiments of the present application, such as Figures 1 to 4 , Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 shown, the pull-up sub-circuit 3 includes the twenty-fourth transistor T24 and the twenty-sixth transistor T26, the first pull-down sub-circuit 4 includes the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fifth transistor T25, and the twenty-seventh transistor T27, and the second pull-down sub-circuit 5 includes the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21;

[0184] wherein, as Figures 1 to 4 , Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 As shown in Figure 13 and Figure 14 , both the gate and the source of the twenty-fourth transistor T24 are electrically connected to the first power supply signal input line GVDD1. The drain of the twenty-fourth transistor T24 is electrically connected to the source of the twenty-fifth transistor T25 and the gate of the twenty-sixth transistor T26 respectively. The source of the twenty-sixth transistor T26 is electrically connected to the first power supply signal input line GVDD1, and the drain of the twenty-sixth transistor T26 is connected to the second node QB <m>Electrically connected; the drains of the twenty-third transistor T23 and the twenty-seventh transistor T27 are both connected to the second node QB <m>Electrically connected; the gates of the eighteenth transistor T28, the nineteenth transistor T29, the twentieth transistor T20, and the twenty-first transistor T21 are all connected to the second node QB <m>Electrically connected, the drain of the eighteenth transistor T18 is connected to the first first node Q <n>Electrically connected, the drain of the nineteenth transistor T19 is electrically connected to the second first node Q<n+1>, the drain of the twentieth transistor T20 is electrically connected to the third first node Q<n+2>, and the drain of the twenty-first transistor T21 is electrically connected to the fourth first node Q<n+3>; the sources of the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fifth transistor T25, and the twenty-seventh transistor T27 are all electrically connected to the low-level signal input line (such as VGL or VGL2).

[0185] In some driving circuits provided by the embodiments of the present application, such as Figures 1 to 4 , Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 shown, the third pulling-down sub-circuit 7 includes the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16. The gates of the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 are all connected to the second node QB <m>Electrically connected, the sources of the tenth transistor T10, the twelfth transistor T12, the fourteenth transistor T14, and the sixteenth transistor T16 are all electrically connected to a low-level signal input line (such as VGL1 or VGL). The drain of the tenth transistor T10 is electrically connected to the drain of the ninth transistor T9. The drain of the twelfth transistor T12 is electrically connected to the drain of the eleventh transistor T11. The drain of the fourteenth transistor T14 is electrically connected to the drain of the thirteenth transistor T13. The drain of the sixteenth transistor T16 is electrically connected to the drain of the fifteenth transistor T15;

[0186] The reset sub-circuit 6 includes four twenty-eighth transistors T28 (T18-1, T18-2, T18-3, T18-4). The gates of the four twenty-eighth transistors T28 are all electrically connected to the reset signal line TRST. The drains of the four twenty-eighth transistors T28 are respectively connected to the first first node Q <n>is electrically connected to the second first node Q<n+1>, the third first node Q<n+2>, and the fourth first node Q<n+3>. The sources of the four twenty-eighth transistors T28 are all electrically connected to the low-level signal input line (VGL or VGL2).

[0187] As Figures 1 to 4 , Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 shown, the specific structures of the shift registers will be described separately in combination with the differences in each circuit.

[0188] In some driving circuits provided in the embodiments of the present application, as Figure 1 shown, the signal input end and the first cascade signal input end are shared, and the (n-4)th gate control signal output end OUT <n-4>As the first cascaded signal input terminal of the m-th stage shift register, the low-level signal input line includes a third-level signal line VGL;

[0189] Specifically, as Figure 1 shown, the gates of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, as well as those of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, are all connected to the (n - 4)-th gate control signal output terminal OUT <n-4>Electrically connected; the gate of the twenty-second transistor T22 is electrically connected to the (n + 8)-th gate control signal output terminal OUT<n+8>, and the drain of the twenty-second transistor T22 is connected to the first first node Q <n>Electrically connected, the gate of the twenty-third transistor T23 is connected to the (n - 4)-th gate control signal output terminal OUT <n-4>Electrically connected; the gates of the twenty-fifth transistor T25 and the twenty-seventh transistor T27 are both connected to the first first node Q <n>Electrical connection; the sources of the tenth transistor T10, twelfth transistor T12, fourteenth transistor T14, sixteenth transistor T16, eighteenth transistor T18, nineteenth transistor T19, twentieth transistor T20, twenty - first transistor T21, twenty - second transistor T22, twenty - third transistor T23, twenty - fifth transistor T25, twenty - seventh transistor T27 and four twenty - eighth transistors T28 (T18 - 1, T18 - 2, T18 - 3, T18 - 4) are all electrically connected to the third - level signal line VGL, where n > 4.

[0190] It should be noted that Figure 5 is Figure 1 the cascade circuit diagram corresponding to the shift register of, in Figure 5 n is greater than 8. In Figure 1 the shift register circuit shown, by setting the gate control signal output terminal OUT <n-4>As the first cascaded signal input terminal of the m-th stage shift register, i.e., OUT <n-4>The signal serves as the trigger signal STV of the m-th stage shift register; the gate control signal output terminal OUT<n + 8> serves as the second cascading signal input terminal of the m-th stage shift register, that is, the OUT<n + 8> signal serves as the reset signal STD of the m-th stage shift register, eliminating the cascading unit, thereby simplifying the circuit, saving design space, and being applicable to the narrow border array substrate.

[0191] In some driving circuits provided in the embodiments of the present application, such as Figure 2 shown, the signal input terminal and the first cascading signal input terminal are shared, and the (n - 3)-th gate control signal output terminal OUT <n-3>As the first cascaded signal input terminal of the m-th stage shift register, the low-level signal input line includes a third-level signal line VGL;

[0192] Specifically, as Figure 2 shown, the gates of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all connected to the (n - 3)-th gate control signal output terminal OUT <n-3>Electrically connected; the gate of the twenty-second transistor T22 is electrically connected to the (n + 9)-th gate control signal output terminal OUT<n+9>, and the drain of the twenty-second transistor T22 is connected to the first first node Q <n>Electrically connected, the gate of the twenty-third transistor T23 is connected to the (n - 3)-th gate control signal output terminal OUT <n-3>Electrically connected; the gates of the twenty-fifth transistor T25 and the twenty-seventh transistor T27 are both connected to the first first node Q <n>Electrical connection; the sources of the tenth transistor T10, twelfth transistor T12, fourteenth transistor T14, sixteenth transistor T16, eighteenth transistor T18, nineteenth transistor T19, twentieth transistor T20, twenty - first transistor T21, twenty - second transistor T22, twenty - third transistor T23, twenty - fifth transistor T25, twenty - seventh transistor T27 and four twenty - eighth transistors T28 (T18 - 1, T18 - 2, T18 - 3, T18 - 4) are all electrically connected to the third - level signal line VGL, where n > 3.

[0193] It should be noted that Figure 6 is Figure 2 the cascade circuit diagram corresponding to the shift register of Figure 6 in which, n is greater than 7. In Figure 2 the shift register circuit shown, by setting the gate control signal output terminal OUT <n-3>As the first cascaded signal input terminal of the m-th stage shift register, i.e., OUT <n-3>The signal serves as the trigger signal STV of the m-th stage shift register; the gate control signal output terminal OUT<n + 9> serves as the second cascading signal input terminal of the m-th stage shift register, that is, the OUT<n + 9> signal serves as the reset signal STD of the m-th stage shift register, eliminating the cascading unit, thereby simplifying the circuit, saving design space, and being applicable to the narrow bezel array substrate.

[0194] In some driving circuits provided by the embodiments of the present application, such as Figure 3 shown, the signal input terminal includes the second power supply signal input line GVDD2, the (n - 4)-th gate control signal output terminal OUT <n-4>As the first cascaded signal input terminal of the m-th stage shift register, the low-level signal input line includes a third-level signal line VGL;

[0195] Specifically, as Figure 3 shown, the gates of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all connected to the (n - 4)-th gate control signal output terminal OUT <n-4>Electrically connected, the sources of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all electrically connected to the second power supply signal input line GVDD2; the gate of the twenty-second transistor T22 is electrically connected to the (n + 8)-th gate control signal output terminal OUT<n + 8>, and the drain of the twenty-second transistor T22 is connected to the first first node Q <n>Electrically connected, the gate of the twenty-third transistor is connected to the (n - 4)-th gate control signal output terminal OUT <n-4>Electrically connected; the gates of the twenty-fifth transistor T25 and the twenty-seventh transistor T27 are both connected to the first first node Q <n>Electrical connection; the sources of the tenth transistor T10, twelfth transistor T12, fourteenth transistor T14, sixteenth transistor T16, eighteenth transistor T18, nineteenth transistor T19, twentieth transistor T20, twenty-first transistor T21, twenty-second transistor T22, twenty-third transistor T23, twenty-fifth transistor T25, twenty-seventh transistor T27 and four twenty-eighth transistors T28 (T18-1, T18-2, T18-3, T18-4) are all electrically connected to the third-level signal line VGL; where n > 4.

[0196] Wherein, Figure 3 and Figure 1 The corresponding cascaded circuit diagrams of the shift registers shown are all Figure 5 .

[0197] Compared with Figure 1 , Figure 3 In the input sub-circuit 1 of the shift register shown, the sources of the second transistor T2, third transistor T3, fourth transistor T4 and fifth transistor T5 are all electrically connected to the second power signal input line GVDD2. Since the second power signal input line GVDD2 transmits a constant high-level signal, in this way, it is possible to prevent the four first nodes from leaking electricity when the second transistor T2, third transistor T3, fourth transistor T4 and fifth transistor T5 are turned on.

[0198] In some driving circuits provided in the embodiments of the present application, as Figure 4 shown, the signal input terminal includes the second power signal input line GVDD2, and the (n - 3)-th gate control signal output terminal OUT <n-3>As the first cascaded signal input terminal of the m-th stage shift register, the low-level signal input line includes a third-level signal line VGL;

[0199] Specifically, as Figure 4 shown, the gates of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all connected to the (n - 3)-th gate control signal output terminal OUT <n-3>Electrically connected, the sources of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all electrically connected to the second power supply signal input line GVDD2; the gate of the twenty-second transistor T22 is electrically connected to the (n + 9)-th gate control signal output terminal OUT<n + 9>, and the drain of the twenty-second transistor T22 is connected to the first first node Q <n>Electrically connected, the gate of the twenty-third transistor is connected to the (n - 3)-th gate control signal output terminal OUT <n-3>Electrically connected; the gates of the twenty-fifth transistor T25 and the twenty-seventh transistor T27 are both connected to the first first node Q <n>Electrical connection; the sources of the tenth transistor T10, twelfth transistor T12, fourteenth transistor T14, sixteenth transistor T16, eighteenth transistor T18, nineteenth transistor T19, twentieth transistor T20, twenty - first transistor T21, twenty - second transistor T22, twenty - third transistor T23, twenty - fifth transistor T25, twenty - seventh transistor T27 and four twenty - eighth transistors T28 (T18 - 1, T18 - 2, T18 - 3, T18 - 4) are all electrically connected to the third - level signal line VGL; where n > 3.

[0200] Wherein, Figure 2 and Figure 4 The corresponding cascade circuit diagrams of the shift registers shown are all Figure 6 .

[0201] Compared with Figure 2 , Figure 4 In the input sub - circuit 1 of the shift register shown, the sources of the second transistor T2, third transistor T3, fourth transistor T4 and fifth transistor T5 are all electrically connected to the second power - signal input line GVDD2. Since the second power - signal input line GVDD2 transmits a constant high - level signal, in this way, it is possible to prevent the four first nodes from leaking electricity when the second transistor T2, third transistor T3, fourth transistor T4 and fifth transistor T5 are turned on.

[0202] Next, on the basis of the above - mentioned shift - register circuit, a separate cascade unit is added to make the cascade signal CR <m>With the gate control signal OUT <n>Separate setting.

[0203] In some driving circuits provided by the embodiments of the present application, such as Figure 9 , Figure 10 , Figure 12 , Figure 13 and Figure 14 shown, the input sub-circuit 1 further includes a sixth transistor T6, the output sub-circuit 2 further includes a seventh transistor T7 and a fifth capacitor CC, the third pulling-down sub-circuit 7 further includes an eighth transistor T8, the second pulling-down sub-circuit 5 further includes a seventeenth transistor T17, and the reset sub-circuit 6 further includes a fifth twenty-eighth transistor T28-C; the drain of the sixth transistor is connected to the third node QC <m>electrically connected, the gate T7 of the seventh transistor to the third node QC <m>electrically connected, the source of the seventh transistor T7 is electrically connected to the cascaded clock signal line CLKD, and the drain of the seventh transistor T7 is connected to the cascaded signal output terminal CR <m>Electrically connected, the fifth capacitor CC is electrically connected to the gate and drain of the seventh transistor T7 respectively; the gate of the eighth transistor T8 is connected to the second node QB <m>Electrically connected, the drain of the eighth transistor T8 is connected to the cascade signal output terminal CR <m>Electrically connected, the gate of the seventeenth transistor T17 is connected to the second node QB <m>electrically connected, the drain of the seventeenth transistor T17 is connected to the third node QC <m>electrically connected, the gate of the fifth twenty-eighth transistor T28-C is electrically connected to the reset signal line TRST, and the drain of the fifth twenty-eighth transistor T28-C is connected to the third node QC <m>electrically connected; the gate of the twenty-second transistor T22 is electrically connected to the cascaded signal output terminal CR<m+2> of the (m+2)-th stage shift register, and the drain of the twenty-second transistor T22 is connected to the third node QC <m>Electric connection; the gate of the twenty-third transistor T23 is connected to the cascade signal output terminal CR of the (m - 1)-th stage shift register <m-1>Electrically connected, the gates of the twenty-fifth transistor T25 and the twenty-seventh transistor T27 are both connected to the third node QC <m>Electrically connected, m > 1.

[0204] In an embodiment of the present application, by adding a separate cascading unit to the shift register circuit, the cascading signal CR <m>With the gate control signal OUT <n>Set separately, so that the cascaded signal CR can be further improved <m>The signal output stability of the four gate control signals, thereby further improving the driving stability of the driving circuit and enhancing the driving performance of the array substrate.

[0205] In some driving circuits provided in the embodiments of the present application, such as Figure 9 shown, the low-level signal input line includes a third-level signal line VGL, and the sources of the transistors in the first pulling-down sub-circuit 4, the second pulling-down sub-circuit 5, the reset sub-circuit 6, and the third pulling-down sub-circuit 7 are all electrically connected to the third-level signal line VGL; the gates and sources of the transistors in the input sub-circuit 1 are both connected to the cascaded signal output terminal CR of the (m - 1)-th stage shift register <m-1>Electrical connection.

[0206] In some driving circuits provided by embodiments of the present application, such as Figure 10 shown, the low-level signal input line includes a third-level signal line VGL, and the sources of the transistors in the first pulling-down sub-circuit 4, the second pulling-down sub-circuit 5, the reset sub-circuit 6, and the third pulling-down sub-circuit 7 are all electrically connected to the third-level signal line VGL; the gates of the transistors in the input sub-circuit 1 are all connected to the cascaded signal output terminal CR of the (m-1)-th stage shift register <m-1>Electrically connected, the sources of the transistors in the input sub-circuit 1 are all electrically connected to the second power supply signal input line GVDD2.

[0207] It should be noted that as described above Figures 1 to 4 、 Figure 9 and Figure 10 The shift register circuit shown can be applied to the circuit of enhancement-mode transistors.

[0208] In the following Figure 12 、 Figure 13 and Figure 14 The shift register circuit shown can be applied to the circuit of depletion-mode transistors.

[0209] In some driving circuits provided in the embodiments of the present application, such as Figure 12 、 Figure 13 and Figure 14 shown, the low-level signal input line includes a first level signal line VGL1 and a second level signal line VGL2, and the voltage of the second level signal transmitted by the second level signal line VGL2 is less than the voltage of the first level signal transmitted by the first level signal line VGL1;

[0210] Specifically, as Figure 12 、 Figure 13 and Figure 14 shown, the sources of the transistors in the first pulling-down sub-circuit 4, the second pulling-down sub-circuit 5 and the reset sub-circuit 6 are all electrically connected to the second level signal line VGL2, and the sources of the transistors in the third pulling-down sub-circuit 7 except the eighth transistor T8 are electrically connected to the first level signal line VGL; the source of the eighth transistor T8 is electrically connected to the second level signal line VGL1. The m-th stage shift register further includes a first transistor T1 and a twenty-ninth transistor T29, and the gate of the first transistor T1 is connected to the cascade signal output terminal CR of the (m-1)-th stage shift register <m-1>Electrically connected, the drain of the first transistor T1 is electrically connected to the sources of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 respectively; the gate of the twenty-ninth transistor T29 is connected to the third node QC <m>electrically connected, the source of the twenty-ninth transistor T29 is electrically connected to the first power supply signal input line GVDD1, and the drain of the twenty-ninth transistor T29 is connected to the fourth node QD (or QD <m>)Electrically connected; wherein, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-fourth transistor T24, five twenty-eighth transistors T28 and the twenty-ninth transistor T29 each include two serially connected sub-transistors, and the two sub-transistors in any one of the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22 are connected through the fourth node QD.

[0211] In an embodiment of the present application, Figure 12 , Figure 13 and Figure 14 As shown in, by setting the drain of the twenty-ninth transistor T29 to be electrically connected to the fourth node QD, when the third node and a plurality of first nodes maintain a high voltage, the first power signal input line GVDD1 can transmit a high-level signal to the fourth node QD through the twenty-ninth transistor T29, so that the fourth node QD maintains a high level, avoiding leakage of the third node and a plurality of first nodes caused by incomplete turn-off of the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21.

[0212] In some driving circuits provided in an embodiment of the present application, such as Figure 12 shown, the source of the first transistor T1 is connected to the cascade signal output terminal CR of the (m - 1)-th stage shift register <m-1>Electric connection; the drain of the twenty-ninth transistor T29 is also electrically connected to the sources of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 respectively.

[0213] Similar to the principle of preventing leakage of transistors in the second pull-down sub-circuit 5 in the foregoing, by setting the drain of the twenty-ninth transistor T29 to be electrically connected to the sources of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 respectively, leakage of each transistor in the input sub-circuit 1 can be prevented, so as to ensure that the third node and multiple first nodes hold high-level signals.

[0214] It should be noted that in the following Figure 13 and Figure 14 , the twenty-ninth transistor T29 is not electrically connected to the sources of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, but other means are adopted to prevent leakage of the third node and multiple first nodes from the transistors in the input sub-circuit 1.

[0215] In some driving circuits provided by the embodiments of the present application, as Figure 13 shown, the source of the first transistor T1 is electrically connected to the second power supply signal input line GVDD2.

[0216] In the embodiments of the present application, by setting the source of the first transistor T1 to be electrically connected to the second power supply signal input line GVDD2, within a certain time period, high-level signals can also be transmitted to the sources of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 through the first transistor T1, so as to prevent leakage of each transistor in the input sub-circuit 1, and ensure that the third node and multiple first nodes hold high-level signals.

[0217] In some driving circuits provided by the embodiments of the present application, as Figure 14 shown, the m-th stage shift register further includes a thirtieth transistor T30. The gate and the source of the thirtieth transistor T30 are both electrically connected to the second power supply signal input line GVDD2, and the drain of the thirtieth transistor T30 is also electrically connected to the sources of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 respectively; wherein, the thirtieth transistor T30 includes two sub-transistors.

[0218] In the embodiments of the present application, as Figure 14 As shown, by providing the thirtieth transistor T30, since the thirtieth transistor T30 is connected to the second power supply signal input line GVDD2 and always remains conducting, in this way, a high-level signal can be transmitted to the input sub-circuit 1 through the thirtieth transistor T30, and multiple third nodes and the first node will not leak electricity through the input sub-circuit 1, thereby ensuring that the third node and the multiple first nodes maintain high-level signals.

[0219] Exemplarily, the size of the thirtieth transistor T30 is smaller than the sizes of the transistors in the input sub-circuit. Even if leakage occurs, the influence of the leakage degree on the driving circuit can be ignored.

[0220] In some driving circuits provided in the embodiments of the present application, the first power supply signal input line GVDD1 and the second power supply signal input line GVDD2 are shared. For example, when the first power supply signal input line GVDD1 and the second power supply signal input line GVDD2 are shared, the electrical signals of the constant voltages input by the two are the same. In this way, the number of signal lines can be reduced.

[0221] In some driving circuits provided in the embodiments of the present application, as Figure 7 、 Figure 8 and Figure 11 shown, at each gate control signal output terminal OUT (such as OUT <n>The gate control signals output by OUT<n+1>, OUT<n+2>, and OUT<n+3> overlap in sequence.

[0222] Exemplarily, OUT <n>OUT<n> controls the charging of sub-pixels in the n-th row, OUT<n + 1> controls the charging of sub-pixels in the (n + 1)-th row, OUT<n + 2> controls the charging of sub-pixels in the (n + 2)-th row, and OUT<n + 3> controls the charging of sub-pixels in the (n + 3)-th row.

[0223] In some driving circuits provided by the embodiments of the present application, such as Figure 7 , Figure 8 and Figure 11 shown, the charging time of the sub-pixels is 2H (i.e., the time of the gate control signal in the high-level stage is 2H), and the overlapping time between the gate control signals of adjacent two rows of sub-pixels is 1H.

[0224] Among them, the overlapping time between the gate control signals of adjacent two rows of sub-pixels is the pre-charging time of the sub-pixels in the subsequent row. In this way, the charging time of the sub-pixels in the display area AA can be provided to a great extent, thereby improving the brightness and display effect of the array substrate.

[0225] In some driving circuits provided by the embodiments of the present application, the charging time of the sub-pixels is 3H, and the overlapping time between the gate control signals of adjacent two rows of sub-pixels is 2H.

[0226] In an exemplary embodiment, the charging time of the sub-pixels can be controlled by controlling the pulse width of the clock signal line CLK in the high-pulse time period. For example, if the pulse width of the clock signal line CLK in the high-pulse time period is 2H, then the charging time of the sub-pixels is 2H. Another example, if the pulse width of the clock signal line CLK in the high-pulse time period is 3H, then the charging time of the sub-pixels is 3H.

[0227] In addition, the overlapping time between the gate control signals of adjacent two rows of sub-pixels can be adjusted by controlling the overlapping time of the clock signals transmitted by adjacent two clock signal lines in the high-pulse time period. For example, if the overlapping time of the clock signals transmitted by adjacent two clock signal lines in the high-pulse time period is 1H, then the overlapping time between the gate control signals of adjacent two rows of sub-pixels is 1H. For example, if the overlapping time of the clock signals transmitted by adjacent two clock signal lines in the high-pulse time period is 2H, then the overlapping time between the gate control signals of adjacent two rows of sub-pixels is 2H.

[0228] In some driving circuits provided by the embodiments of the present application, such as Figure 11 shown, the phase and period of the signal transmitted by the cascaded clock signal line CLKD are the same as those of the signal transmitted by the first clock signal line CLK1;

[0229] Or, in some other embodiments, it can be set that the phase and period of the signal transmitted by the cascaded clock signal line CLKD are the same as those of the signal transmitted by the second clock signal line CLK2.

[0230] In an embodiment of the present application, a cascaded clock signal line CLKD corresponds to four clock signal lines CLK. It is also possible to set the signals transmitted by the cascaded clock signal line CLKD to have the same phase and period as the signals transmitted by the third clock signal line CLK3.

[0231] Exemplarily, the periods of the signals transmitted by the cascaded clock signal line CLKD and the four clock signal lines CLK are all 12H.

[0232] In an exemplary embodiment, the types of all transistors are the same.

[0233] Taking the Figure 12 shown circuit as an example, and taking all transistors as N-type transistors as an example, combined with the Figure 15 shown timing, the driving process of the shift register will be described.

[0234] When all transistors are P-type transistors, the timing of the corresponding signal lines can be opposite to the Figure 15 shown timing, which will not be elaborated here.

[0235] Combined with the Figure 12 and Figure 15 shown, before the start of refreshing each frame of signals, a reset signal TRST is input to the reset signal line to reset the voltages of the third node and multiple first nodes;

[0236] In the first stage P1, the trigger signal CR of the m-th stage shift register <m-1>is at a high level, controlling the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to conduct, and writing the high-level signal to the third node QC through the respective transistors in the input sub-circuit 2 <m>and four first nodes, are conducted through the twenty-third transistor T23, the second node QB <m>Pulled down to V VGL2 , due to the third node QC <m>is at a high level, the twenty-fifth transistor T25 and the twenty-seventh transistor T27 are turned on, and the gate of the twenty-sixth transistor T26 is pulled low to V VGL2 , the twenty-sixth transistor T26 is turned off, and the connection from the first power supply signal input line GVDD1 through the twenty-sixth transistor T26 to the second node QB is closed <m>Charging path; at this time, in order to maintain the third node QC <m>and the high-level signals of the four first nodes, each transistor in the second pulling-down sub-circuit 5 is turned off, and through the twenty-ninth transistor T29, the third node QC can be prevented <m>and four first node leakages. At this time, since the signals output by the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, and the cascaded clock signal line CLKD are low levels (such as VGL1), the cascaded output terminal CR <m>and four gate control signal output terminals OUT <n>~OUT<n + 3> all output low-level signals.

[0237] In the second stage P2, the trigger signal CR of the m-th stage shift register <m-1>is at a low level, controlling the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to turn off, and the third node QC <m>Maintain the state of the previous stage (pre hold state) with the four first nodes.

[0238] In the third stage P3, at the rising edge of the high-level signals of the first clock signal line CLK1 and the cascaded clock signal line CLKD, the cascaded output CR <m>and the first gate control signal output terminal OUT <n>The output signal is pulled high, and the third node QC and the first first node Q <n>Due to the bootstrap effect of the fifth capacitor CC and the first capacitor C1, it is further pulled up, increasing the output capabilities of the seventh transistor T7 and the ninth transistor T9. Additionally, since the transistors in the input sub-circuit 2 have been turned off, there is no mutual influence among the potentials of the multiple first nodes.

[0239] In the fourth section P4, when the rising edge of the second clock signal line CLK2 arrives, the signal output by the second gate control signal output terminal OUT<n+1> is pulled up. Due to the bootstrap effect of the second capacitor C2, the second first node Q<n+1> is further pulled up, and the eleventh transistor T11 is fully turned on. The second gate control signal output terminal OUT<n+1> maintains the output of a high-level signal. At this time, when the falling edges of the high-level signals on the first clock signal line CLK1 and the cascaded clock signal line CLKD arrive, the output signal is pulled from high to low, and the third node QC and the first first node Q <n>is pulled down to the pre-hold potential, but the seventh transistor T7 and the ninth transistor T9 are in the on state, and the cascaded output terminal CR <m>and the first gate control signal output terminal OUT <n>The output low-level signal, for example, the cascaded output terminal CR <m>Outputs a low-level signal from the cascaded clock signal line CLKD, the first gate control signal output terminal OUT <n>Output a low-level signal from the first clock signal line CLK1.

[0240] In the fifth stage P5 to the seventh stage P7, the output processes of the third gate control signal output terminal OUT<n+2> and the fourth gate control signal output terminal OUT<n+3> are similar to those in the fourth stage P4, which will not be elaborated here.

[0241] In the eighth stage P8 to the tenth stage P10, the third node QC <m>and four first nodes Q <n>~Q<n+3> maintain the prehold state (maintain the high level state) and control the corresponding transistors T7, T9, T11, T13, and T15 to turn on; until the rising edge of the high pulse of the reset signal CR<m+2> arrives, the twenty-second transistor T22 conducts, and the third node QC <m>is pulled down, the seventh transistor T7 and the twenty-ninth transistor T29 are turned off; the third node QC <m>Further control the twenty-fifth transistor T25 and the twenty-seventh transistor T27 to turn off; the second node QB <m>is pulled high by pulling high T24 and T26 in sub-circuit 3, and the second node QB <m>Turn on each of the transistors T17 to T21 in the second pull-down sub-circuit 5, and the third node QC <m>and four first nodes Q <n>~Q<n + 3> is pulled low to V VGL2 ; all transistors in the output sub - circuit 2 are turned off, and each transistor in the third pull - down sub - circuit 7 is at the second node QB <m>conduct under the control of, and the four gate control signal output terminals OUT <n>~OUT<n + 3> is pulled low to V VGL1 , the third node QC <m>and four first nodes Q <n>~Q<n+3> are noise-reduced by VGL2, and four gate control signal output terminals OUT <n>~OUT<n+3> is noise-reduced by VGL1, maintaining the output stability of the m-th stage shift register.

[0242] Subsequently, the next-stage GOA(m+1) repeats the above process to achieve the functions of cascading stage by stage and turning on row by row.

[0243] For other shift register circuits such as Figures 1 to 4 , Figure 9 , Figure 10 , Figure 13 and Figure 14 shown, their driving processes are similar to those of the shift register circuit shown in Figure 12 , or their driving processes have some functions deleted on the basis of the driving process of the shift register circuit shown in Figure 12 . For the driving processes of each shift register circuit, reference can be made to the introduction of the driving circuit structure and functions in the foregoing text, and the driving processes of each shift register circuit will not be elaborated here.

[0244] An embodiment of the present application provides an array substrate, which includes a driving circuit as described in any one of the foregoing.

[0245] The array substrate provided by the embodiment of the present application has all the advantages of the above driving circuit.

[0246] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application, and all of them should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.< / n> < / n> < / m> < / n> < / m> < / n> < / m> < / m> < / m> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / n> < / n> < / n> < / m> < / m> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / m> < / m> < / m> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / n> < / m> < / m> < / m> < / n> < / m> < / n> < / m> < / m> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / m> < / m> < / n> < / m> < / n> < / m> < / n> < / m> < / m> < / n> < / m> < / m> < / m> < / m> < / n> < / n> < / n>

Claims

1. A driving circuit, wherein, Including: A plurality of cascaded shift registers, where the m-th stage of the shift register is electrically connected to multiple rows of sub-pixels. The m-th stage of the shift register includes: An input sub-circuit, electrically connected to a plurality of first nodes, a signal input terminal, and a first cascaded signal input terminal respectively, and configured to input the signal transmitted by the signal input terminal to the plurality of first nodes under the control of the signal transmitted by the first cascaded signal input terminal; An output sub-circuit, including a plurality of output sub-units, each output sub-unit is respectively connected to one of the first nodes, a clock signal line, and a gate control signal output terminal. The output sub-unit is configured to output the clock signal transmitted by the clock signal line from the gate control signal output terminal under the control of the signal of the first node; each gate control signal output terminal is electrically connected to one row of the sub-pixels; A voltage boosting sub-circuit, electrically connected to a first power signal input line and a second node respectively, and configured to boost the voltage of the second node under the control of the first power signal input by the first power signal input line; A first voltage pulling-down sub-circuit, electrically connected to the voltage boosting sub-circuit, the second node, a low-level signal input line, and the output sub-circuit respectively, and configured to pull down the voltage of the second node; A second voltage pulling-down sub-circuit, electrically connected to the second node, the low-level signal input line, and the plurality of first nodes respectively, and configured to pull down the voltages of the plurality of first nodes under the control of the signal of the second node; A reset sub-circuit, electrically connected to a reset signal line, the low-level signal input line, and the plurality of first nodes respectively, and configured to reset the signals of the plurality of first nodes under the control of the reset signal transmitted by the reset signal line; A third voltage pulling-down sub-circuit, electrically connected to the second node, the low-level signal input line, and a plurality of the gate control signal output terminals respectively, and configured to reduce the noise of the signals output by the gate control signal output terminals under the control of the signal of the second node; m is a positive integer.

2. The drive circuit according to claim 1, wherein The low-level signal input line includes a first level signal line and a second level signal line; The first voltage pulling-down sub-circuit, the second voltage pulling-down sub-circuit, and the reset sub-circuit are all electrically connected to the first level signal. The third voltage pulling-down sub-circuit is electrically connected to the second level signal line. The voltage of the first level signal transmitted by the first level signal line is different from the voltage of the second level signal transmitted by the second level signal line.

3. The drive circuit according to claim 2, wherein, The voltage of the second level signal transmitted by the second level signal line is less than the voltage of the first level signal transmitted by the first level signal line.

4. The drive circuit according to claim 1, wherein, The low-level signal input line includes a third level signal line. The first voltage pulling-down sub-circuit, the second voltage pulling-down sub-circuit, the reset sub-circuit, and the third voltage pulling-down sub-circuit are all electrically connected to the third level signal.

5. The drive circuit according to claim 1, wherein, The signal input terminal and the first cascaded signal input terminal are shared.

6. The drive circuit according to claim 1, wherein, The signal input terminal is electrically connected to a second power signal input line.

7. The drive circuit according to claim 5 or 6, wherein, The output sub-circuit includes a cascading unit, the input sub-circuit includes a first cascading transistor, the second pulling-down sub-circuit includes a second cascading transistor, the reset sub-circuit includes a third cascading transistor, and the third pulling-down sub-circuit includes a fourth cascading transistor; The cascading unit is respectively electrically connected to a third node, a cascading clock signal line, and a cascading signal output terminal, and is configured to output, under the control of the third node, the signal transmitted on the cascading clock signal line from the cascading signal output terminal; The first cascading transistor is respectively electrically connected to the third node, the signal input terminal, and the first cascading signal input terminal, and is configured to input, under the control of a first cascading signal transmitted on the first cascading signal input terminal, the signal transmitted on the signal input terminal into the third node; The second cascading transistor is respectively electrically connected to the second node, the low-level signal input line, and the third node, and is configured to pull down the voltage of the third node under the control of the signal of the second node; The third cascading transistor is respectively electrically connected to the reset signal line, the low-level signal input line, and the third node, and is configured to reset the signal of the third node under the control of a reset signal transmitted on the reset signal line; The fourth cascading transistor is respectively electrically connected to the second node, the low-level signal input line, and the cascading signal output terminal, and is configured to reduce noise of the signal output from the cascading signal output terminal under the control of the signal of the second node; The first pulling-down sub-circuit is electrically connected to the output sub-circuit through the third node.

8. The drive circuit according to claim 7, wherein, The cascading signal output terminal of the (m - 1)-th stage shift register serves as the first cascading signal input terminal of the m-th stage shift register, where m > 2; The first pulling-down sub-circuit is also respectively electrically connected to the cascading signal output terminal of the (m - 1)-th stage shift register and the cascading signal output terminal of the (m + 2)-th stage shift register.

9. The drive circuit according to claim 5 or 6, wherein In the m-th stage shift register, the output sub-circuit includes the n-th gate control signal output terminal, the (n + 1)-th gate control signal output terminal, the (n + 2)-th gate control signal output terminal, and the (n + 3)-th gate control signal output terminal; The (n - 4)-th gate control signal output terminal serves as the first cascading signal input terminal of the m-th stage shift register, and the first pulling-down sub-circuit is also respectively electrically connected to the (n - 4)-th gate control signal output terminal and the (n + 8)-th gate control signal output terminal, where n is a positive integer and n > 4.

10. The drive circuit according to claim 5 or 6, wherein In the m-th stage shift register, the output sub-circuit includes the n-th gate control signal output terminal, the (n + 1)-th gate control signal output terminal, the (n + 2)-th gate control signal output terminal, and the (n + 3)-th gate control signal output terminal; The (n - 3)-th gate control signal output terminal serves as the first cascaded signal input terminal of the m-th shift register, and the first pull-down sub-circuit is also electrically connected to the (n - 3)-th gate control signal output terminal and the (n + 9)-th gate control signal output terminal respectively, where n is a positive integer and n > 3.

11. The drive circuit according to claim 8, wherein, The m-th shift register further includes a first anti-leakage electronic circuit, and the signal input terminal and the first cascaded signal input terminal are shared; The first anti-leakage electronic circuit is electrically connected to the input sub-circuit, the pull-up sub-circuit, the first pull-down sub-circuit, the third node, the second pull-down sub-circuit and the first power signal input line respectively, and is configured to prevent leakage of the third node and multiple first nodes under the control of the signal of the third node.

12. The drive circuit according to claim 8, wherein, The m-th shift register further includes a first anti-leakage electronic circuit, and the signal input terminal is electrically connected to the second power signal input line; The first anti-leakage electronic circuit is electrically connected to the pull-up sub-circuit, the first pull-down sub-circuit, the third node, the second pull-down sub-circuit and the first power signal input line respectively, and is configured to prevent leakage of the third node and multiple first nodes under the control of the signal of the third node.

13. The drive circuit according to claim 12, wherein, The m-th shift register further includes a second anti-leakage electronic circuit, and the second anti-leakage electronic circuit is electrically connected to the second power signal input line and the input sub-circuit respectively; the second anti-leakage electronic circuit is configured to transmit a high-level signal to the third node and multiple first nodes through the input sub-circuit when the input sub-circuit is turned on, so as to prevent leakage of the third node and multiple first nodes.

14. The drive circuit according to claims 11 to 13, wherein, The clock signal transmitted in the clock signal line includes a first level signal, and the signal output from the gate control signal output terminal includes the first level signal; The reset signal transmitted in the reset signal line includes a second level signal, the cascaded clock signal transmitted in the cascaded clock signal line includes the second level signal, and the signal output from the cascaded signal output terminal includes the second level signal; The voltage of the second level signal is less than the voltage of the first level signal.

15. The drive circuit according to claim 1, wherein, The input sub-circuit includes a second transistor, a third transistor, a fourth transistor and a fifth transistor. The gates of the second transistor, the third transistor, the fourth transistor and the fifth transistor are all electrically connected to the first cascaded signal input terminal. The sources of the second transistor, the third transistor, the fourth transistor and the fifth transistor are all electrically connected to the signal input terminal. The drain of the second transistor is electrically connected to the fourth first node, the drain of the third transistor is electrically connected to the third first node, the drain of the fourth transistor is electrically connected to the second first node, and the drain of the fifth transistor is electrically connected to the first first node.

16. The drive circuit according to claim 15, wherein, The output sub-circuit includes a ninth transistor, an eleventh transistor, a thirteenth transistor, a fifteenth transistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; The gate of the ninth transistor is electrically connected to the first of the first nodes, the source of the ninth transistor is electrically connected to the first clock signal line, the drain of the ninth transistor is electrically connected to the nth gate control signal output terminal, and the first capacitor is electrically connected to the gate and the drain of the ninth transistor respectively; The gate of the eleventh transistor is electrically connected to the second of the first nodes, the source of the eleventh transistor is electrically connected to the second clock signal line, the drain of the eleventh transistor is electrically connected to the (n + 1)th gate control signal output terminal, and the second capacitor is electrically connected to the gate and the drain of the eleventh transistor respectively; The gate of the thirteenth transistor is electrically connected to the third of the first nodes, the source of the thirteenth transistor is electrically connected to the third clock signal line, the drain of the thirteenth transistor is electrically connected to the (n + 2)th gate control signal output terminal, and the third capacitor is electrically connected to the gate and the drain of the thirteenth transistor respectively; The gate of the fifteenth transistor is electrically connected to the fourth of the first nodes, the source of the fifteenth transistor is electrically connected to the fourth clock signal line, the drain of the fifteenth transistor is electrically connected to the (n + 3)th gate control signal output terminal, and the fourth capacitor is electrically connected to the gate and the drain of the fifteenth transistor respectively, where n is a positive integer.

17. The drive circuit according to claim 16, wherein, The pull-up sub-circuit includes a twenty-fourth transistor and a twenty-sixth transistor, the first pull-down sub-circuit includes a twenty-second transistor, a twenty-third transistor, a twenty-fifth transistor and a twenty-seventh transistor, and the second pull-down sub-circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a twenty-first transistor; The gate and the source of the twenty-fourth transistor are both electrically connected to the first power signal input line, the drain of the twenty-fourth transistor is electrically connected to the source of the twenty-fifth transistor and the gate of the twenty-sixth transistor respectively, the source of the twenty-sixth transistor is electrically connected to the first power signal input line, and the drain of the twenty-sixth transistor is electrically connected to the second node; The drains of the twenty-third transistor and the twenty-seventh transistor are both electrically connected to the second node; The gates of the eighteenth transistor, the nineteenth transistor, the twentieth transistor and the twenty-first transistor are all electrically connected to the second node, the drain of the eighteenth transistor is electrically connected to the first of the first nodes, the drain of the nineteenth transistor is electrically connected to the second of the first nodes, the drain of the twentieth transistor is electrically connected to the third of the first nodes, and the drain of the twenty-first transistor is electrically connected to the fourth of the first nodes; The sources of the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fifth transistor and the twenty-seventh transistor are all electrically connected to the low-level signal input line.

18. The drive circuit according to claim 17, wherein, The third pulling-down sub-circuit includes a tenth transistor, a twelfth transistor, a fourteenth transistor, and a sixteenth transistor. The gates of the tenth transistor, the twelfth transistor, the fourteenth transistor, and the sixteenth transistor are all electrically connected to the second node. The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, and the sixteenth transistor are all electrically connected to the low-level signal input line. The drain of the tenth transistor is electrically connected to the drain of the ninth transistor. The drain of the twelfth transistor is electrically connected to the drain of the eleventh transistor. The drain of the fourteenth transistor is electrically connected to the drain of the thirteenth transistor. The drain of the sixteenth transistor is electrically connected to the drain of the fifteenth transistor. The reset sub-circuit includes four twenty-eighth transistors. The gates of the four twenty-eighth transistors are all electrically connected to the reset signal line. The drains of the four twenty-eighth transistors are respectively electrically connected to the first first node, the second first node, the third first node, and the fourth first node. The sources of the four twenty-eighth transistors are all electrically connected to the low-level signal input line.

19. The drive circuit according to claim 18, wherein, The signal input terminal and the first cascaded signal input terminal are shared. The (n - 4)-th gate control signal output terminal serves as the first cascaded signal input terminal of the m-th stage of the shift register. The low-level signal input line includes a third-level signal line. The gates and the sources of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the (n - 4)-th gate control signal output terminal. The gate of the twenty-second transistor is electrically connected to the (n + 8)-th gate control signal output terminal. The drain of the twenty-second transistor is electrically connected to the first first node. The gate of the twenty-third transistor is electrically connected to the (n - 4)-th gate control signal output terminal. The gates of the twenty-fifth transistor and the twenty-seventh transistor are both electrically connected to the first first node. The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fifth transistor, the twenty-seventh transistor, and the four twenty-eighth transistors are all electrically connected to the third-level signal line, where n > 4.

20. The drive circuit according to claim 18, wherein, The signal input terminal and the first cascaded signal input terminal are shared. The (n - 3)-th gate control signal output terminal serves as the first cascaded signal input terminal of the m-th stage of the shift register. The low-level signal input line includes a third-level signal line. The gates of the second transistor, the third transistor, the fourth transistor, and the fifth transistor, as well as the sources of the second transistor, the third transistor, the fourth transistor, and the fifth transistor, are all electrically connected to the (n - 3)-th gate control signal output terminal; The gate of the twenty-second transistor is electrically connected to the (n + 9)-th gate control signal output terminal, the drain of the twenty-second transistor is electrically connected to the first first node, and the gate of the twenty-third transistor is electrically connected to the (n - 3)-th gate control signal output terminal; the gates of the twenty-fifth transistor and the twenty-seventh transistor are both electrically connected to the first first node; The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fifth transistor, the twenty-seventh transistor, and the four twenty-eighth transistors are all electrically connected to the third-level signal line. Here, n > 3.

21. The drive circuit according to claim 18, wherein The signal input terminal includes a second power supply signal input line, and the (n - 4)-th gate control signal output terminal serves as the first cascaded signal input terminal of the m-th shift register, and the low-level signal input line includes a third-level signal line; The gates of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the (n - 4)-th gate control signal output terminal, and the sources of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the second power supply signal input line; The gate of the twenty-second transistor is electrically connected to the (n + 8)-th gate control signal output terminal, the drain of the twenty-second transistor is electrically connected to the first first node, and the gate of the twenty-third transistor is electrically connected to the (n - 4)-th gate control signal output terminal; the gates of the twenty-fifth transistor and the twenty-seventh transistor are both electrically connected to the first first node; The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fifth transistor, the twenty-seventh transistor, and the four twenty-eighth transistors are all electrically connected to the third-level signal line; where n > 4.

22. The drive circuit according to claim 18, wherein, The signal input terminal includes a second power supply signal input line, and the (n - 3)-th gate control signal output terminal serves as the first cascaded signal input terminal of the m-th shift register, and the low-level signal input line includes a third-level signal line; The gates of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the (n - 3)-th gate control signal output terminal, and the sources of the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all electrically connected to the second power signal input line; The gate of the twenty-second transistor is electrically connected to the (n + 9)-th gate control signal output terminal, the drain of the twenty-second transistor is electrically connected to the first first node, the gate of the twenty-third transistor is electrically connected to the (n - 3)-th gate control signal output terminal; the gates of the twenty-fifth transistor and the twenty-seventh transistor are both electrically connected to the first first node; The sources of the tenth transistor, the twelfth transistor, the fourteenth transistor, the sixteenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, the twenty-fifth transistor, the twenty-seventh transistor, and the four twenty-eighth transistors are all electrically connected to the third-level signal line; where n > 3.

23. The drive circuit according to claim 18, wherein, The input sub-circuit further includes a sixth transistor, the output sub-circuit further includes a seventh transistor and a fifth capacitor, the third pull-down sub-circuit further includes an eighth transistor, the second pull-down sub-circuit further includes a seventeenth transistor, and the reset sub-circuit further includes the fifth twenty-eighth transistor; The drain of the sixth transistor is electrically connected to the third node, the gate of the seventh transistor is electrically connected to the third node, the source of the seventh transistor is electrically connected to the cascaded clock signal line, the drain of the seventh transistor is electrically connected to the cascaded signal output terminal, and the fifth capacitor is electrically connected to the gate and the drain of the seventh transistor respectively; The gate of the eighth transistor is electrically connected to the second node, the drain of the eighth transistor is electrically connected to the cascaded signal output terminal, the gate of the seventeenth transistor is electrically connected to the second node, the drain of the seventeenth transistor is electrically connected to the third node, the gate of the fifth twenty-eighth transistor is electrically connected to the reset signal line, and the drain of the fifth twenty-eighth transistor is electrically connected to the third node; The gate of the twenty-second transistor is electrically connected to the cascaded signal output terminal of the (m + 2)-th shift register, and the drain of the twenty-second transistor is electrically connected to the third node; the gate of the twenty-third transistor is electrically connected to the cascaded signal output terminal of the (m - 1)-th shift register, and the gates of the twenty-fifth transistor and the twenty-seventh transistor are both electrically connected to the third node, where m > 1.

24. The drive circuit according to claim 23, wherein, The low-level signal input line includes a third-level signal line, and the sources of the transistors in the first pull-down sub-circuit, the second pull-down sub-circuit, the reset sub-circuit, and the third pull-down sub-circuit are all electrically connected to the third-level signal line; The gates and sources of the transistors in the input sub-circuit are all electrically connected to the cascaded signal output terminal of the (m - 1)-th shift register.

25. The drive circuit according to claim 23, wherein, The low-level signal input line includes a third-level signal line, and the sources of the transistors in the first pulling-down sub-circuit, the second pulling-down sub-circuit, the reset sub-circuit, and the third pulling-down sub-circuit are all electrically connected to the third-level signal line; The gates of the transistors in the input sub-circuit are all electrically connected to the cascade signal output terminal of the (m-1)-th stage of the shift register, and the sources of the transistors in the input sub-circuit are all electrically connected to the second power supply signal input line.

26. The drive circuit according to claim 23, wherein, The low-level signal input line includes a first-level signal line and a second-level signal line, and the voltage of the second-level signal transmitted by the second-level signal line is less than the voltage of the first-level signal transmitted by the first-level signal line; The sources of the transistors in the first pulling-down sub-circuit, the second pulling-down sub-circuit, and the reset sub-circuit are all electrically connected to the second-level signal, and the sources of the transistors in the third pulling-down sub-circuit except the eighth transistor are electrically connected to the first-level signal line; the source of the eighth transistor is electrically connected to the second-level signal line; The m-th stage of the shift register further includes a first transistor and a twenty-ninth transistor. The gate of the first transistor is electrically connected to the cascade signal output terminal of the (m-1)-th stage of the shift register, and the drain of the first transistor is electrically connected to the sources of the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor respectively; The gate of the twenty-ninth transistor is electrically connected to the third node, the source of the twenty-ninth transistor is electrically connected to the first power supply signal input line, and the drain of the twenty-ninth transistor is electrically connected to the fourth node; The seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-fourth transistor, five of the twenty-eighth transistors, and the twenty-ninth transistor each include two serially connected sub-transistors. The two sub-transistors of any one of the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are connected through the fourth node.

27. The drive circuit according to claim 26, wherein, The source of the first transistor is electrically connected to the cascade signal output terminal of the (m-1)-th stage of the shift register; The drain of the twenty-ninth transistor is also electrically connected to the sources of the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor respectively.

28. The drive circuit according to claim 26, wherein, The source of the first transistor is electrically connected to the second power supply signal input line.

29. The drive circuit according to claim 28, wherein, The m-th stage of the shift register further includes a thirtieth transistor. The gate and the source of the thirtieth transistor are both electrically connected to the second power supply signal input line, and the drain of the thirtieth transistor is also electrically connected to the sources of the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor respectively; wherein, the thirtieth transistor includes two sub-transistors.

30. The drive circuit according to claim 29, wherein, The first power supply signal input line and the second power supply signal input line are shared.

31. The drive circuit according to claim 1, wherein, The gate control signals output from the respective gate control signal output ends in the m-th stage shift register overlap with each other in sequence.

32. The drive circuit according to claim 31, wherein, The charging time of the sub-pixel is 2H, and the overlap time between the gate control signals of adjacent two rows of sub-pixels is 1H.

33. The drive circuit according to claim 31, wherein, The charging time of the sub-pixel is 3H, and the overlap time between the gate control signals of adjacent two rows of sub-pixels is 2H.

34. The drive circuit according to claim 23, wherein, The signal transmitted by the cascaded clock signal line has the same phase and period as the signal transmitted by the first clock signal line; Alternatively, the signal transmitted by the cascaded clock signal line has the same phase and period as the signal transmitted by the second clock signal line.

35. An array substrate, wherein, It includes the driving circuit according to any one of claims 1 to 34.

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