Pixel scanning driving circuit, display panel and display device

Abstract

The embodiment of the invention relates to a pixel scanning driving circuit, a display panel and a display device. The pixel scanning driving circuit comprises a pixel unit array, a first preset number of scanning lines and a scanning driving module, each row of pixel units corresponds to two target scanning lines, a first group of pixel units in the row of pixel units are driven by a first target scanning line, and a second group of pixel units in the row of pixel units are driven by a second target scanning line; the scanning driving module is used for outputting a scanning driving signal to a first scanning line in the first preset number of scanning lines in response to starting scanning of a current frame of image; and for the nth scanning line and the (n + 1) th scanning line, a scanning driving signal is firstly output to the (n + 1) th scanning line, and then the scanning driving signal is output to the nth scanning line. According to the embodiment of the invention, the condition of inconsistent coupling during scanning line voltage change caused by different distances between the pixel electrodes and the scanning lines can be improved, so that the uniformity of the display brightness of the panel is improved.

Description

Technical Field

[0001] This application relates to the technical field of display panels, and in particular, to a pixel scanning driving circuit, a display panel, and a display device. Background Art

[0002] Currently, LCD (Liquid Crystal Display) monitors are evolving towards higher resolution, higher display quality, and larger sizes. When driving a TFT-LCD (Thin Film Transistor LCD), the driving method is Line-by-Line (progressive scanning), that is, when the scanning signal of a row is at a high level, the corresponding TFTs in this row are turned on, and data in the column direction can be written into the pixels. To reduce power consumption and cost, a dual-gate driving method can be adopted to reduce the resources required by the data driving IC. That is, for the pixels in the same row, they are driven by two scanning signals at different times, and one output terminal of the data driving IC is connected to two data lines.

[0003] However, due to the increase in the number of scanning lines, the number of parasitic capacitances generated between different scanning lines and the pixel electrodes will increase, and the distances between the scanning lines and the pixel electrodes result in different sizes of parasitic capacitances. Therefore, the liquid crystal panel driven by dual gates will generate bright and dark stripes, affecting the image display quality. Summary of the Invention

[0004] In view of this, to solve some or all of the above technical problems, embodiments of this application provide a pixel scanning driving circuit, a display panel, and a display device.

[0005] In a first aspect, embodiments of this application provide a pixel scanning driving circuit, which includes: a pixel unit array, a first preset number of scanning lines, and a scanning driving module; the scanning driving module is connected to the first preset number of scanning lines; for each row of pixel units in the pixel unit array, the pixel units in this row correspond to two target scanning lines, and the first group of pixel units in the pixel units in this row is driven by the first target scanning line among the two target scanning lines, and the second group of pixel units in the pixel units in this row is driven by the second target scanning line among the two target scanning lines; the scanning driving module is configured to: in response to starting to scan the current frame of image, output a scanning driving signal to the first scanning line among the first preset number of scanning lines; for the nth scanning line and the (n + 1)th scanning line, first output a scanning driving signal to the (n + 1)th scanning line, and then output a scanning driving signal to the nth scanning line, where n is an even number greater than 1.

[0006] In a possible implementation, the rising edge triggering moment of the scanning signal on the n-th scanning line is during the high level period of the scanning signal on the (n + 1)-th scanning line; the falling edge triggering moment of the scanning signal on the (n + 1)-th scanning line is during the high level period of the scanning signal on the n-th scanning line.

[0007] In a possible implementation, the scan driving module includes an output line switching unit, and the output line switching unit is configured to connect the n-th output line of the scan driving module to the (n + 1)-th scanning line.

[0008] In a possible implementation, two target scanning lines are located on the same side of the corresponding row of pixel units, and among the two target scanning lines, the serial number of the target scanning line closer to the corresponding row of pixel units is smaller than the serial number of the target scanning line farther from the corresponding row of pixel units.

[0009] In a possible implementation, the circuit further includes a compensation scanning line. The compensation scanning line and the first scanning line are respectively located on both sides of the first row of pixel units in the pixel unit array, and the distance between the compensation scanning line and the second scanning line among the first preset number of scanning lines is greater than the distance between the first scanning line and the second scanning line; the compensation scanning line is connected to the scan driving module, and the scan driving module is further configured to: in response to starting to scan the current frame of image, first output a scan driving signal to the first scanning line among the first preset number of scanning lines, and then output a scan driving signal to the compensation scanning line.

[0010] In a possible implementation, the scan driving module includes an output line switching unit. The output line switching unit is configured to connect the first output line of the scan driving module to the compensation scanning line, connect the 0-th output line of the scan driving module to the first scanning line, and connect the n-th output line of the scan driving module to the (n + 1)-th scanning line.

[0011] In a possible implementation, two target scanning lines are respectively located on both sides of the corresponding row of pixel units.

[0012] In a possible implementation, the circuit further includes a second preset number of data lines; each data line among the second preset number of data lines corresponds to a column of pixel units and is configured to transmit display data to the corresponding column of pixel units; each data line among the second preset number of data lines is connected to at least one corresponding target data line.

[0013] In a second aspect, an embodiment of the present application provides a display panel, which includes: a controller, a data driving module, and the above-mentioned pixel scan driving circuit, wherein the controller is connected to the data driving module and the scan driving module in the pixel scan driving circuit.

[0014] In a third aspect, an embodiment of the present application provides a display device, including: a display panel, a panel frame, a power module, and a data receiving module as described in the second aspect above; the display panel is mounted on the panel frame, the power supply terminal of the display panel is connected to the power module, and the signal receiving terminal of the display panel is connected to the data receiving module.

[0015] The pixel scanning driving circuit, display panel, and display device provided by the embodiments of the present application adjust the scanning order of each row of the pixel unit array when displaying an image, that is, when starting to scan the current frame of image, a scanning driving signal is output to the first scanning line among each scanning line. For the nth scanning line and the (n + 1)th scanning line, the scanning driving signal is first output to the (n + 1)th scanning line, and then the scanning driving signal is output to the nth scanning line, where n is an even number greater than 1. Thus, when the level of a certain scanning line changes, the distance between this scanning line and the pixel units driven by the scanning lines during the driving state increases, that is, the magnitude of the parasitic capacitance between this scanning line and the pixel units driven by the scanning lines during the driving state can be reduced. Furthermore, the voltage coupled to the pixel units by each scanning line is reduced, improving the inconsistent coupling during the voltage change of the scanning line caused by the different distances between the pixel electrodes and the scanning lines, thereby improving the uniformity of the panel display brightness. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0018] One or more embodiments are illustrated by way of example in the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the figures do not constitute a proportional limitation.

[0019] Figure 1 It is a schematic diagram of the architecture of a pixel array in the related art of the embodiments of the present application;

[0020] Figure 2 It is a schematic diagram of the difference in the distance between a scanning line and a pixel unit in the related art of the embodiments of the present application;

[0021] Figure 3 It is a timing diagram of a scanning driving signal in the related art of the embodiments of the present application;

[0022] Figure 4 Schematic diagram of a pixel scanning driving circuit provided by an embodiment of the present application;

[0023] Figure 5 Timing diagram of a scanning driving signal provided by an embodiment of the present application;

[0024] Figure 6 Circuit structure diagram of a scanning driving module provided by an embodiment of the present application;

[0025] Figure 7 Schematic diagram of another pixel scanning driving circuit provided by an embodiment of the present application;

[0026] Figure 8 Timing diagram of another scanning driving signal provided by an embodiment of the present application;

[0027] Figure 9 Circuit structure diagram of another scanning driving module provided by an embodiment of the present application;

[0028] Figure 10 Schematic diagram of yet another pixel scanning driving circuit provided by an embodiment of the present application;

[0029] Figure 11 Schematic diagram of yet another pixel scanning driving circuit provided by an embodiment of the present application;

[0030] Figure 12 Schematic diagram of a display panel provided by an embodiment of the present application;

[0031] Figure 13 Schematic diagram of a display device provided by an embodiment of the present application.

[0032] Reference numerals:

[0033] 400 - Pixel scanning driving circuit; 401 - Pixel unit array; 402 - First preset number of scanning lines; 403 - Scanning driving module; 4031 - Output line switching unit; 1200 - Display panel; 1201 - Controller; 1202 - Data driving module; 1300 - Display device; 1301 - Panel frame; 1302 - Power supply module; 1303 - Data receiving module. Detailed implementation manners

[0034] Now, various exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. It should be noted that: Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and values set forth in these embodiments do not limit the scope of the present application.

[0035] Those skilled in the art can understand that terms such as "first" and "second" in the embodiments of the present application are only used to distinguish different steps, devices, or modules, etc., and neither represent any specific technical meaning nor indicate the logical order between them.

[0036] It should also be understood that in this embodiment, "a plurality of" may refer to two or more, and "at least one" may refer to one, two, or more.

[0037] It should also be understood that for any component, data, or structure mentioned in the embodiments of the present application, in the absence of clear limitations or contrary implications in the context, it can generally be understood as one or more.

[0038] In addition, the term "and / or" in the present application is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present application generally represents an "or" relationship between the associated objects before and after.

[0039] It should also be understood that the description of each embodiment in the present application emphasizes the differences between the embodiments, and their similarities can be referred to each other. For the sake of brevity, they will not be elaborated one by one.

[0040] The following description of at least one exemplary embodiment is actually only illustrative and in no way limits the present application and its application or use.

[0041] Technologies, circuits, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the above technologies, circuits, and devices should be regarded as part of the specification.

[0042] It should be noted that: Similar reference numerals and letters denote similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0043] It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined with each other. For the convenience of understanding the embodiments of the present application, the present application will be described in detail below with reference to the drawings and in combination with the embodiments. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0044] Such as Figure 1As shown, it is a schematic diagram of the H-type architecture in the related art. Among them, Dn represents the distribution of data lines, L_n represents the distribution of scan lines, and G_n represents the received scan driving signal. From Figure 1 it can be seen that there are two scan lines between adjacent rows of pixel units, and the distances between the two scan lines and the same row of pixel units are different. As Figure 2 shown, for two different connection methods within the panel, it can be known that the distance between the L_1 scan line and one end of the pixel electrode of the TFT is d1, and the distance between the L_2 scan line and one end of the pixel electrode of the TFT is d2. Obviously, d2 > d1, and this distance will cause the parasitic capacitance C gs between the scan line and the pixel electrode to be different, that is, C gs1 > C gs2 . Different parasitic capacitances will cause different feedthrough voltages ΔV p = C gs / (C gs + C lc + C st ), that is, ΔV p1 > ΔV p2 . As a result, the positive polarity controlled by G_1 is darker, and the negative polarity controlled is brighter; the opposite is true for G_2 control. Therefore, there may be a situation where Figure 1 two columns of pixels are bright and two columns of pixels are dark.

[0045] As Figure 3 shown, it is the normal scan timing of each scan line. From Figure 3 and Figure 1 it can be seen that under the above architecture, the sub-pixels controlled by L_3 are too close to both the L_3 and L_2 scan lines. During the high level of L_3, the falling edge of L_2 will cause an increase in the voltage fed into the sub-pixels controlled by L_3, and the falling edge of L_3 itself will also cause an increase in the voltage fed into the sub-pixels controlled by L_3. Therefore, the sub-pixels controlled by L_3 will be greatly affected by L_2 and L_3 twice. For the sub-pixels controlled by L_4, since L_2 has been turned off during its driving period, only L_3 and L_4 itself have a great influence on the fed-in voltage, and L_4 is farther from the sub-pixel compared to L_2. Therefore, the fed-in voltage of the sub-pixels controlled by L_4 is lower. As a result, the brightness of the sub-pixels controlled by L_3 and L_4 is uneven.

[0046] To solve the above technical problems, as Figure 4As shown, an embodiment of the present application provides a pixel scanning driving circuit 400, which is generally applied to a display panel. The circuit 400 specifically includes: a pixel unit array 401, a first preset number of scanning lines 402, and a scanning driving module 403. The scanning driving module 403 is connected to the first preset number of scanning lines 402.

[0047] The above scanning driving module 403 can also be referred to as GOA (Gate on Array), which includes a plurality of scanning signal output lines, and each scanning signal output line is connected to a scanning line. As Figure 4 shown, the scanning signal output lines included in the scanning driving module 403 are represented by G_1 - G_M, and the first preset number of scanning lines 402 are represented by L_1 - L_M.

[0048] For each row of pixel units in the pixel unit array 401, the row of pixel units corresponds to two target scanning lines, and the first group of pixel units in the row of pixel units is driven by the first target scanning line among the two target scanning lines, and the second group of pixel units in the row of pixel units is driven by the second target scanning line among the two target scanning lines.

[0049] As Figure 4 shown, for the first row of pixel units, the scanning lines L_1 and L_2 are the corresponding target scanning lines. A part of the pixel units are connected to the scanning line L_1 through TFTs, and another part of the pixel units are connected to the scanning line L_2 through TFTs. The scanning signals received by L_1 and L_2 drive the pixel units at different positions in the same row respectively.

[0050] The scanning driving module 403 is used for: in response to starting the scanning of the current frame of image, outputting a scanning driving signal to the first scanning line among the first preset number of scanning lines 402; for the nth scanning line and the (n + 1)th scanning line, first outputting a scanning driving signal to the (n + 1)th scanning line, and then outputting a scanning driving signal to the nth scanning line. Wherein, n is an even number greater than 1.

[0051] That is, for the other scanning lines except the first scanning line, in order, for the scanning lines arranged in the even order positions and the scanning lines arranged in the odd order positions, the order of receiving the scanning driving signals is exchanged. Usually, the scanning driving module 403 can output scanning driving signals from the G_1 - G_M terminals respectively according to the timing under the control of the timing controller. The output order of the scanning driving module 403 is usually G_1, G_2,..., G_M. By adjusting the connection order with the scanning lines, the timing of the scanning driving signals received by each scanning line is as Figure 5 shown, that is, in the order of L_1, L_2,..., L_M, the order of receiving the scanning driving signals is G_1, G_3, G_2, G_5, G_4,..., G_M - 1, G_M.

[0052] The principle by which the embodiments of the present application can improve the brightness uniformity of the display screen is as follows:

[0053] Taking the sub-pixels controlled by L3 and L4 as an example, if the conventional driving timing as Figure 3 shown is adopted, since both L_2 and L_3 are adjacent to the sub-pixels corresponding to D1~D6, it can be known that the feeding voltage of L_2 to these sub-pixels is ΔV p2 =C Ls2 / (C Ls2 +C lc +C st )(-VLH + VLL), and the feeding voltage of L_3 to these sub-pixels is ΔV p3 =C Ls3 / (C Ls3 +C lc +C st )(-VLH + VLL), and the total influence is ΔV p2 +ΔV p3 .

[0054] For the sub-pixels controlled by L_4, according to the driving timing shown in Figure 3 , only the falling edges on L_3 and L_4 will affect its feeding voltage. Among them, since the distances between L_2 and L_3 and the sub-pixels controlled by L_4 are equal respectively, therefore, the influence of L_3 on the feeding voltage of the sub-pixels controlled by L_4 is also ΔV p2 =C Ls2 / (C Ls2 +C lc +C st )(-VLH + VLL), and then the influence of L_4 on its feeding voltage is ΔV p4 =C Ls4 / (C Ls4 +C lc +C st )(-VLH + VLL), and the total influence is ΔV p2 +ΔV p4 .

[0055] It can be known that the difference in the feeding voltages received by the sub-pixels controlled by L_3 and L_4 respectively is ΔV p3 -ΔV p4 , and because there is a difference in capacitance size due to the difference in distance between C Ls3 and C Ls4 , therefore, ΔV p3 >ΔV p4 , which further leads to uneven brightness and darkness of the pixels corresponding to the two scanning lines.

[0056] In the embodiments of the present application, other scan lines except the first scan line receive scan driving signals in a manner that the odd-order bits and the even-order bits are swapped. As Figure 4 and Figure 5 shown, for the sub-pixels controlled by L_3, L_3 drives the corresponding sub-pixels prior to L_2, and the falling edge of the scan driving signal received by L_3 is during the high level of L_2, and the distance between the sub-pixels controlled by L_3 and L_2 is relatively far, resulting in a relatively small parasitic capacitance generated by L_3 on the sub-pixels controlled by L_2, thereby reducing the voltage fed into the sub-pixels controlled by L_2 and improving the uniformity of the display screen.

[0057] The pixel scan driving circuit provided by the embodiments of the present application adjusts the scan order of each row of the pixel unit array when displaying an image, that is, when starting to scan the current frame of image, a scan driving signal is output to the first scan line among each scan line. For the nth scan line and the (n + 1)th scan line, the scan driving signal is first output to the (n + 1)th scan line, and then the scan driving signal is output to the nth scan line, where n is an even number greater than 1. Thus, when the level of a certain scan line changes, the distance between this scan line and the pixel units driven by the scan lines during the driving state increases, that is, the magnitude of the parasitic capacitance between this scan line and the pixel units driven by the scan lines during the driving state can be reduced, and further the voltage coupled by each scan line to the pixel unit is reduced, improving the inconsistent coupling during the voltage change of the scan line caused by the different distances between the pixel electrode and the scan line, thereby improving the uniformity of the panel display brightness.

[0058] In some optional implementation manners of this embodiment, as Figure 5 shown in the timing diagram, the rising edge trigger moment of the scan signal on the nth scan line is during the high level of the scan signal on the (n + 1)th scan line; the falling edge trigger moment of the scan signal on the (n + 1)th scan line is during the high level of the scan signal on the nth scan line.

[0059] From the reasons for generating bright and dark stripes described above, during the high level of the scan driving signal on a scan line a, if a falling edge occurs on another scan line b, it will cause voltage to be fed into the pixel units controlled by scan line a. Taking Figure 1 L_3 and L_4 in p3 as an example, ΔV p4 >ΔV . If there is a way to reduce the tendency of the voltage generated by the falling edge on L_3 to couple downward, then the fed voltages of the pixel units controlled by L_3 and L_4 can also be made to approach equality. And the downward coupling is all caused by the problem of the scan line being turned off. If the influence of the upward coupling of the voltage brought when the scan line is turned on can be fed into the pixel capacitance, the above problems can be solved.

[0060] Therefore, Figure 4 in the shown circuit, the rising edge trigger moment on L_2 needs to be during the high level of L_3, and the rising edge of L_2 cannot be when L_4 is high. As Figure 5 shown, reverse the order of the signals received by L_2 and L_3, so that the rising edge of the signal on L_2 is in the high level stage of the signal on L_3. For the sub-pixel controlled by L_3, when L_2 is turned on, its influence on it is to make ΔV p2′ rise upward, and when L_3 is turned off, its influence on it is to make ΔV p3 fall, that is, ΔV p3 = (-VGH + VGL) * C gs3 / (C gs3 + C lc + C st ), then the overall influence is ΔV p3′ = ΔV p3 + ΔV p2′ = (-VGH + VGL) * C gs3 / (C gs3 + C lc + C st ) + ΔV p2′ . Because |ΔV p3 | > |ΔV p2′ |, it can be known that after addition, the overall absolute value of ΔV p3′ decreases.

[0061] For the sub-pixel controlled by L_4, during its high level period, L_2 has been turned off and there is no rising or falling change, and only L_5 has a rising edge. And the physical position of L_5 is far from L_4, and its rising and falling have basically no influence on L_4.

[0062] Therefore, the fed-in voltage of the sub-pixel controlled by L_4 is ΔV p4 = C gs4 / (C gs4 + C lc + C st )(-VGH + VGL). Originally, both ΔV p3 and ΔV p4 pull the pixel voltage downward, and |ΔV p3 | > |ΔV p4 |. Here, because ΔV p3′ is lifted up a little, therefore, ΔV p3′ and ΔV p4 are closer, resulting in better brightness uniformity.

[0063] In this embodiment, during the high-level period of the scanning signal on the (n + 1)-th scanning line triggered by the rising edge of the scanning signal on the n-th scanning line, the absolute value of the feeding voltage of the (n + 1)-th scanning line to the pixel units it controls can be reduced, thereby achieving effective reduction of the difference in feeding voltages of pixels in different columns by adjusting the timing of the scanning lines and the positional relationship of the rising and falling edges, and improving the uniformity of the panel display brightness.

[0064] In some alternative implementation manners of this embodiment, as Figure 6 shown, the scanning driving module 403 includes an output line switching unit 4031, and the output line switching unit is used to connect the n-th output line of the scanning driving module 403 to the (n + 1)-th scanning line. That is, through the output line switching unit, other scanning lines except the first scanning line are cross-connected with the output lines of the scanning driving module 403.

[0065] The above output line switching unit can be a separate detachable connector, or can be solidified inside or outside the scanning driving module 403. By setting the output line switching unit in this embodiment, flexible adjustment of the timing of the scanning driving signals received by each scanning line is achieved, which helps to expand the application scenarios of this circuit.

[0066] In some alternative implementation manners of this embodiment, as Figure 4 shown in the circuit, two target scanning lines are located on the same side of the pixel units in the corresponding row, and among the two target scanning lines, the serial number of the target scanning line closer to the pixel units in the corresponding row is smaller than the serial number of the target scanning line farther from the pixel units in the corresponding row.

[0067] Specifically, as Figure 4 shown, for the pixel units in the first row, the scanning lines L_1 and L_2 are both located on the same side of the pixel units in the first row, and L_1 is closer to the pixel units in the first row than L2.

[0068] The circuit architecture provided in this embodiment can make full use of the adjusted timing to reduce the occurrence probability of bright and dark stripes in the display screen when the two scanning lines controlling the pixel units in the same row are located on the same side.

[0069] In some alternative implementation manners of this embodiment, as Figure 7 shown, the circuit further includes a compensation scanning line L_0. The compensation scanning line and the first scanning line L_1 are respectively located on both sides of the pixel units in the first row of the pixel unit array 401, and the distance between the compensation scanning line L_0 and the second scanning line L_2 among the first preset number of scanning lines 402 is greater than the distance between the first scanning line L_1 and the second scanning line L_2. That is Figure 7The shown L_0 is located above the first row of pixel units, and L_1 is located below the first row of pixel units.

[0070] The compensation scan line L_0 is connected to the scan driving module 403, and the scan driving module 403 is further configured to: in response to starting a scan of the current frame of image, first output a scan driving signal to the first scan line among the first preset number of scan lines 402, and then output a scan driving signal to the compensation scan line.

[0071] As Figure 8 shown, it shows a timing diagram of the scan driving signals received by the compensation scan line L_0 and the first preset number of scan lines 402. It can be seen that the scan driving module 403 can output a scan driving signal to L_1 through the output line G_0, and output a scan driving signal to L_0 through the output line G_1. The scan order of the scan lines L_0 and L_1 is swapped. The compensation scan line L_0 is not connected to any pixel units, and the change of the signal level thereon is only for compensating the feed-in voltage of the pixel units controlled by L_1.

[0072] Figure 8 In the shown timing diagram, the rising edge of the scan driving signal on L_0 is during the high level of the signal on L_1, and the falling edge is during the high level of the signal on L_3. And L_0 is far from the sub-pixels controlled by L_3 and has no influence on the sub-pixels controlled by L_3. Therefore, the scan driving signal on L_0 can reduce the feed-in voltage of the pixel units controlled by L1.

[0073] In this embodiment, by setting the compensation scan line, a compensation feed-in voltage can be generated for all pixel units controlled by scan lines, so as to reduce the difference in feed-in voltages of all pixel units on the panel and improve the overall display uniformity of the panel.

[0074] In some optional implementation manners of this embodiment, based on Figure 7 the shown circuit architecture, as Figure 9 shown, the scan driving module 403 includes an output line switching unit 4031. The output line switching unit 4031 is configured to connect the first output line G_1 of the scan driving module 403 to the compensation scan line L_0, connect the 0th output line G_0 of the scan driving module 403 to the first scan line L_1, and connect the nth output line of the scan driving module 403 to the (n + 1)th scan line.

[0075] In this embodiment, by setting the output line switching unit, the timing of the scan driving signals received by all scan lines including the compensation scan line is flexibly adjusted, which helps to expand the application scenarios of this circuit.

[0076] In some optional implementation manners of this embodiment, asFigure 10 As shown, it shows another schematic diagram of the circuit provided by this application. For the two target scan lines corresponding to each row of pixel units, these two target scan lines are respectively located on both sides of a corresponding row of pixel units.

[0077] Figure 10 In the architecture shown, the driving timings of the nth scan line L_n and the (n + 1)th scan line L_n+1 can also be swapped, that is, first output a scan driving signal to the (n + 1)th scan line L_n+1, and then output a scan driving signal to the nth scan line L_n. Wherein, n is an even number greater than 1.

[0078] In this embodiment, Figure 5 When outputting the scan driving signal according to the timing diagram shown, the falling edge of L_1 is during the high level of L_3. The distance between L_1 and the sub-pixel controlled by L_3 is relatively far. Therefore, the influence of the signal level change on L_1 on the feeding voltage of the sub-pixel controlled by L_3 can be reduced. The rising edge of L_2 is during the high level of L_3, and it can generate a voltage that lifts ΔV p3 upward, reducing the absolute value of ΔV p3 By analogy, the difference between the absolute values and of the feeding voltages of each column of pixel units will be reduced, thereby improving the uniformity of the panel display brightness.

[0079] In some optional implementation manners of this embodiment, as Figure 11 shown, the circuit further includes a second preset number of data lines (including D1 - DK).

[0080] Each data line among the second preset number of data lines corresponds to a column of pixel units and is used to transmit display data to the corresponding column of pixel units. Each data line among the second preset number of data lines is connected to at least one corresponding target data line.

[0081] As Figure 11 the circuit architecture shown, it is an H-type architecture, that is, one row of pixels is driven by two scan lines, and the same output terminal (including S1 - SJ) of the data driving IC is connected to two data lines, and at different times, different data signals are output to the two data lines.

[0082] This embodiment realizes implementing this pixel scan driving circuit on a panel with an H-type architecture, thereby solving the problem of bright and dark stripes on the panel with an H-type architecture.

[0083] Figure 12 It is a schematic structural diagram of a display panel 1200 provided by an embodiment of this application, as Figure 12As shown, the display panel 1200 specifically includes: a controller 1201, a data driving module 1202, and the above-mentioned pixel scanning driving circuit 400. Among them, the timing controller is connected to the data driving module and the scanning driving module in the pixel scanning driving circuit. The controller can configure the scanning driving module and the data driving module, and control the timing of the output signals.

[0084] For the display panel provided by the embodiment of the present application, by applying the above-mentioned pixel scanning driving circuit, the inconsistent coupling during the change of the scanning line voltage caused by the different distances between the pixel electrode and the scanning line can be improved, thereby improving the uniformity of the panel display brightness.

[0085] Figure 13 It is a schematic structural diagram of a display device 1300 provided by an embodiment of the present application. As Figure 13 shown, the display device 1300 includes:

[0086] a display panel 1200, a panel frame 1301, a power supply module 1302, and a data receiving module 1303;

[0087] Among them, the display panel 1200 can be Figure 12 the display panel 1200 as shown. The display panel 1200 is installed on the panel frame 1301.

[0088] The power supply end of the display panel 1200 is connected to the power supply module 1302, and the signal receiving end of the display panel 1200 is connected to the data receiving module 1303.

[0089] The power supply module 1302 can provide the electric energy required during the operation of the display panel 1200. The data receiving module 1303 can receive the input data, and the display panel 1200 drives the corresponding pixels to display corresponding colors according to the received data.

[0090] In addition, in addition to Figure 13 the various parts shown, the display device may further include a memory for storing data and programs, a processor for running application programs, a data transmission bus, various data interfaces (such as a network interface, a user interface), etc.

[0091] For the display device provided by the embodiment of the present application, by applying the above-mentioned display panel, the inconsistent coupling during the change of the scanning line voltage caused by the different distances between the pixel electrode and the scanning line on the panel can be improved, thereby improving the uniformity of the panel display brightness.

[0092] Those skilled in the art should also be able to further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different circuits to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0093] The steps of the circuits or algorithms described in combination with the embodiments disclosed herein can be implemented by hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0094] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" as used herein may also include the plural forms. The terms "comprising", "including", "containing", and "having" are inclusive and thus specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The steps, processes, and operations described herein are not to be construed as necessarily requiring them to be executed in the particular order described or illustrated, unless the order of execution is explicitly stated. It should also be understood that additional or alternative steps may be used.

[0095] The above description is only specific embodiments of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A pixel scanning driving circuit, characterized in that, The circuit includes: a pixel unit array, a first preset number of scan lines, and a scan driving module; The scan driving module is connected to the first preset number of scan lines; For each row of pixel units in the pixel unit array, the pixel units in this row correspond to two target scan lines, and the first group of pixel units in the pixel units of this row is driven by the first target scan line among the two target scan lines, and the second group of pixel units in the pixel units of this row is driven by the second target scan line among the two target scan lines; The scan driving module is configured to: in response to starting to scan the current frame of image, output a scan driving signal to the first scan line among the first preset number of scan lines; for the nth scan line and the (n + 1)th scan line, first output a scan driving signal to the (n + 1)th scan line, and then output a scan driving signal to the nth scan line, where n is an even number greater than 1.

2. The circuit according to claim 1, wherein The rising edge triggering moment of the scan signal on the nth scan line is located during the high level period of the scan signal on the (n + 1)th scan line; the falling edge triggering moment of the scan signal on the (n + 1)th scan line is located during the high level period of the scan signal on the nth scan line.

3. The circuit according to claim 1, wherein The scan driving module includes an output line switching unit, and the output line switching unit is configured to connect the nth output line of the scan driving module to the (n + 1)th scan line.

4. The circuit according to claim 1, characterized in that, The two target scan lines are located on the same side of the corresponding row of pixel units, and among the two target scan lines, the serial number of the target scan line closer to the corresponding row of pixel units is smaller than the serial number of the target scan line farther from the corresponding row of pixel units.

5. The circuit according to claim 4, wherein The circuit further includes a compensation scan line, the compensation scan line and the first scan line are respectively located on both sides of the first row of pixel units in the pixel unit array, and the distance between the compensation scan line and the second scan line among the first preset number of scan lines is greater than the distance between the first scan line and the second scan line; The compensation scan line is connected to the scan driving module, and the scan driving module is further configured to: in response to starting to scan the current frame of image, first output a scan driving signal to the first scan line among the first preset number of scan lines, and then output a scan driving signal to the compensation scan line.

6. The circuit according to claim 5, characterized in that, The scan driving module includes an output line switching unit, and the output line switching unit is configured to connect the first output line of the scan driving module to the compensation scan line, connect the 0th output line of the scan driving module to the first scan line, and connect the nth output line of the scan driving module to the (n + 1)th scan line.

7. The circuit according to claim 1, wherein The two target scan lines are respectively located on both sides of the corresponding row of pixel units.

8. The circuit according to claim 1, wherein The circuit further includes a second preset number of data lines; Each data line among the second preset number of data lines corresponds to a column of pixel units and is used to transmit display data to the corresponding column of pixel units; Each data line among the second preset number of data lines is connected to at least one corresponding target data line.

9. A display panel, characterized in that, Including: A controller, a data driving module, and the pixel scanning driving circuit according to any one of claims 1-8, wherein the controller is connected to the data driving module and the scanning driving module in the pixel scanning driving circuit.

10. A display device, characterized in that, Comprising: A display panel, a panel frame, a power supply module, and a data receiving module as claimed in claim 9; The display panel is mounted on the panel frame, a power supply terminal of the display panel is connected to the power supply module, and a signal receiving terminal of the display panel is connected to the data receiving module.

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