Display panel and display device

Abstract

The utility model provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate, a via hole formed in the substrate and located in a hole area, a first gate drive circuit located in a non-display area, a plurality of sub-pixels located in a display area and a plurality of first scanning signal lines extending from the display area to the non-display area. The first gate driving circuit is electrically connected with the sub-pixels through the first scanning signal lines; the plurality of first scanning signal lines comprise first scanning lines; the first scanning line comprises a first sub-scanning line and a second sub-scanning line which are laminated; the first sub-scanning line and the second sub-scanning line are connected in parallel; each first sub-scanning line comprises at least two sections of first extension parts and a first surrounding part connected with the adjacent first extension parts; the first surrounding part surrounds a part of contour of the via hole; the second sub-scanning line comprises at least two sections of second extension parts and a second surrounding part connected with the adjacent second extension parts; the second surrounding portion surrounds a part of the contour of the via hole.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Art

[0002] At present, the openings in display products come in various shapes, quantities, and positions, such as single-centered hole, single-offset hole, double-centered hole, three-centered hole, etc. Here, the holes in the display products are mainly used to accommodate various types of sensors or cameras, etc., so winding design is required for the wiring of the holes in the extension direction. For example, the scanning signal line used to drive the sub-pixels. However, as the number of holes increases, the winding path of the scanning signal line becomes longer, which leads to an increase in the resistance of the scanning signal line, and then the resistance of the scanning signal line near the hole area is quite different from the resistance of the scanning signal line with a non-winding layout in the display area. Ultimately, there is a significant difference in the display effect of the sub-pixels driven by winding and non-winding under the same display screen, affecting the product yield. Utility Model Content

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display panel and a display device.

[0004] In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a display panel having an aperture area, a display area surrounding the aperture area, and a non-display area surrounding the display area; the display panel includes a base substrate, a via hole provided on the base substrate and located in the aperture area, a first gate drive circuit located in the non-display area, a plurality of sub-pixels located in the display area, and a plurality of first scan signal lines extending from the display area to the non-display area; the first gate drive circuit is electrically connected to the sub-pixels via the first scan signal lines;

[0005] The plurality of first scan signal lines include a first scan line; the first scan line includes a first sub-scan line and a second sub-scan line that are stacked; the first sub-scan line is connected in parallel with the second sub-scan line;

[0006] The first sub-scan line includes at least two first extension sections and a first surrounding section connecting adjacent first extension sections; the first surrounding section surrounds a portion of the contour of the via hole; the second sub-scan line includes at least two second extension sections and a second surrounding section connecting adjacent second extension sections; the second surrounding section surrounds a portion of the contour of the via hole.

[0007] In some embodiments, the orthographic projections of the first surrounding portion and the second surrounding portion on the base substrate at least partially overlap.

[0008] In some embodiments, the first extension portion and the second extension portion overlap in orthographic projection on the base substrate.

[0009] In some embodiments, the plurality of first scan signal lines further include a second scan line; and an extending direction of the second scan line, an extending direction of the first extending portion, and an extending direction of the second extending portion are all the same.

[0010] In some embodiments, the second scan line includes a third sub-scan line and a fourth sub-scan line that are stacked; the third sub-scan line is connected in parallel with the fourth sub-scan line.

[0011] In some embodiments, the plurality of sub-pixels are divided into a plurality of rows; the plurality of first scanning signal lines are divided into a plurality of first scanning signal line groups; each first scanning signal line group includes at least two adjacent first scanning signal lines; different first scanning signal lines are electrically connected to the sub-pixels in different rows;

[0012] For any first scanning signal line group, first ends of the first scanning signal lines are electrically connected to each other, and second ends of the first scanning signal lines are electrically connected to each other;

[0013] An output end of the first gate driving circuit is electrically connected to a first end of each of the first scanning signal lines in a group of the first scanning signal lines.

[0014] In some embodiments, the display panel further includes a plurality of second scan signal lines, third scan signal lines, fourth scan signal lines, and fifth scan signal lines extending from the display area to the non-display area; the sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device;

[0015] The pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a storage capacitor;

[0016] The control electrode of the first transistor is electrically connected to the second scanning signal line, the first electrode is electrically connected to the first reference signal line, and the second electrode is electrically connected to the third node;

[0017] The control electrode of the second transistor is electrically connected to the first scanning signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node;

[0018] The control electrode of the third transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node;

[0019] The control electrode of the fourth transistor is electrically connected to the third scan signal line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the second node;

[0020] The control electrode of the fifth transistor is electrically connected to the fourth scan signal line, the first electrode is electrically connected to the first power signal line, and the second electrode is electrically connected to the second node;

[0021] The control electrode of the sixth transistor is electrically connected to the fourth scan signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the first electrode of the light emitting device;

[0022] The control electrode of the seventh transistor is electrically connected to the fifth scan signal line, the first electrode is electrically connected to the second reference signal line, and the second electrode is electrically connected to the first electrode of the light emitting device;

[0023] The control electrode of the eighth transistor is electrically connected to the fifth scan signal line, the first electrode is electrically connected to the third reference signal line, and the second electrode is electrically connected to the second node;

[0024] The first plate of the storage capacitor is electrically connected to the first power signal line, and the second plate is electrically connected to the first node.

[0025] In some embodiments, the display panel further includes a second gate driving circuit; the second gate driving circuit is electrically connected to the second scan signal line;

[0026] The plurality of second scanning signal lines include a third scanning line and a fourth scanning line; the third scanning line includes at least two third extension portions and a third surrounding portion connecting adjacent third extension portions; the third surrounding portion surrounds a portion of the contour of the via hole; the extension direction of the fourth scanning line is the same as the extension direction of the third extension portion.

[0027] In some embodiments, the plurality of sub-pixels are divided into a plurality of rows; the plurality of second scanning signal lines are divided into a plurality of second scanning signal line groups; each second scanning signal line group includes at least two adjacent second scanning signal lines; different second scanning signal lines are electrically connected to the sub-pixels in different rows;

[0028] For any second scanning signal line group, first ends of the second scanning signal lines are electrically connected to each other, and second ends of the second scanning signal lines are electrically connected to each other;

[0029] An output end of the second gate driving circuit is electrically connected to a first end of each second scanning signal line in a group of second scanning signal lines.

[0030] In some embodiments, the non-display area includes a first sub-frame area and a second sub-frame area disposed opposite to each other along a first direction; the display panel further includes two third gate driving circuits located in the first sub-frame area and the second sub-frame area, respectively; the two third gate driving circuits disposed opposite to each other along the first direction are electrically connected via one third scanning signal line; the plurality of sub-pixels are divided into a plurality of rows; and one third scanning signal line is electrically connected to one row of sub-pixels;

[0031] The plurality of third scan signal lines include a fifth scan line and a sixth scan line; the fifth scan line includes at least two fourth extension portions and a fourth surrounding portion connecting adjacent fourth extension portions; the fourth surrounding portion surrounds a portion of the contour of the via hole; the extension direction of the sixth scan line is the same as the extension direction of the fourth extension portion.

[0032] In some embodiments, the non-display area includes a first sub-frame area and a second sub-frame area disposed opposite to each other along a first direction; the display panel further includes a fourth gate driving circuit located in the second sub-frame area; the fourth gate driving circuit is electrically connected to the fourth scan signal line;

[0033] The plurality of fourth scan signal lines include a seventh scan line; the seventh scan line includes at least two fifth extensions and a fifth surrounding portion connecting adjacent fifth extensions; the fifth surrounding portion surrounds a portion of the contour of the via hole;

[0034] The plurality of seventh scan lines are divided into a plurality of third scan signal line groups; each of the third scan signal line groups includes at least two adjacent seventh scan lines; the plurality of sub-pixels are divided into a plurality of rows; different seventh scan lines are electrically connected to sub-pixels in different rows; for any third scan signal line group, the fifth surrounding portions of the seventh scan lines are shared, the first ends of the fifth extension portions of the seventh scan lines are electrically connected to each other, and the second ends of the fifth extension portions of the seventh scan lines are electrically connected to each other;

[0035] An output end of the fourth gate driving circuit is electrically connected to one end of each of the seventh scanning lines in a group of the third scanning signal lines.

[0036] In some embodiments, the plurality of fourth scan signal lines further include an eighth scan line; the plurality of eighth scan lines are divided into a plurality of fourth scan signal line groups; each of the fourth scan signal line groups includes at least two adjacent eighth scan lines; different eighth scan lines are electrically connected to different rows of sub-pixels;

[0037] For any of the fourth scan signal line groups, first ends of the eighth scan lines are electrically connected to each other, and second ends of the eighth scan lines are electrically connected to each other;

[0038] An output end of the fourth gate driving circuit is electrically connected to the first end of each of the eighth scan lines in a group of the fourth scan signal lines.

[0039] In some embodiments, the non-display area includes a first sub-frame area and a second sub-frame area arranged opposite to each other along a first direction; the display panel further includes a fifth gate driving circuit located in the second sub-frame area; the fifth gate driving circuit is electrically connected to the fifth scan signal line;

[0040] The plurality of fifth scan signal lines include a ninth scan line; the ninth scan line includes at least two sixth extensions and a sixth surrounding portion connecting adjacent sixth extensions; the sixth surrounding portion surrounds a portion of the contour of the via hole;

[0041] The plurality of ninth scan lines are divided into a plurality of fifth scan signal line groups; each of the fifth scan signal line groups includes at least two adjacent ninth scan lines; the plurality of sub-pixels are divided into a plurality of rows; different ninth scan lines are electrically connected to sub-pixels in different rows; for any fifth scan signal line group, the sixth surrounding portions of the ninth scan lines are shared, the first ends of the sixth extension portions of the ninth scan lines are electrically connected to each other, and the second ends of the sixth extension portions of the ninth scan lines are electrically connected to each other;

[0042] An output end of the fifth gate driving circuit is electrically connected to one end of each of the ninth scanning lines in a group of the fifth scanning signal lines.

[0043] In some embodiments, the plurality of fifth scan signal lines further include a tenth scan line; the plurality of tenth scan lines are divided into a plurality of sixth scan signal line groups; each of the sixth scan signal line groups includes at least two adjacent tenth scan lines; different tenth scan lines are electrically connected to different rows of sub-pixels;

[0044] For any of the sixth scan signal line groups, first ends of the tenth scan lines are electrically connected to each other, and second ends of the tenth scan lines are electrically connected to each other;

[0045] An output end of the fifth gate driving circuit is electrically connected to the first end of each of the tenth scan lines in a group of the sixth scan signal lines.

[0046] In some embodiments, the display panel includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer arranged in sequence along a direction away from the base substrate;

[0047] The first sub-scan line is located in the third conductive layer; the second sub-scan line is located in the fourth conductive layer; the second scan signal line is located in the first conductive layer; the third scan signal line is located in the second conductive layer; the fourth scan signal line and the fifth scan signal line are both located in the fifth conductive layer.

[0048] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes a display panel as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present disclosure;

[0050] Figure 2 A circuit diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0051] Figure 3 A schematic diagram of the routing layout of the first scan signal line provided in an embodiment of the present disclosure;

[0052] Figure 4 for Figure 3 Schematic diagram of the cross section along the A-A' direction;

[0053] Figure 5a A schematic diagram of the equivalent resistance of a single-layer routing of a first scan line provided in an embodiment of the present disclosure;

[0054] Figure 5b A schematic diagram of equivalent resistance of a double-layer routing of an extended portion and a single-layer routing of a surrounding portion of a first scan line provided by an embodiment of the present disclosure;

[0055] Figure 5c A schematic diagram of equivalent resistance of the extended portion and the surrounding portion of the first scan line provided by the embodiment of the present disclosure, both of which are double-layered;

[0056] Figure 5d A schematic diagram of the equivalent resistance of a single-layer routing of a second scan line provided in an embodiment of the present disclosure;

[0057] Figure 6 This is a poor display effect diagram showing a bright band on the right side of the hole area provided by an embodiment of the present disclosure;

[0058] Figure 7 A schematic diagram of the layout of each gate driving circuit in a display panel provided by an embodiment of the present disclosure;

[0059] Figure 8 A schematic diagram of the routing layout of the second scan signal line provided in an embodiment of the present disclosure;

[0060] Figure 9 A schematic diagram of the routing layout of the third scan signal line provided in an embodiment of the present disclosure;

[0061] Figure 10 A schematic diagram of the routing layout of the fourth scan signal line provided in an embodiment of the present disclosure;

[0062] Figure 11 A schematic diagram of the routing layout of the fifth scan signal line provided in an embodiment of the present disclosure;

[0063] Figure 12 for Figure 7 Schematic cross-section along the BB' direction. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0065] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0066] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0067] It should be noted that the transistors in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0068] It should be noted that thin film transistors can be either N-type or P-type thin film transistors; an N-type thin film transistor refers to a thin film transistor in which N-type ions are doped in its active layer; a P-type thin film transistor refers to a thin film transistor in which P-type ions are doped in its active layer. The operating voltage level of an N-type thin film transistor is a high-level voltage, meaning that when a high-level voltage is input to the gate of the N-type thin film transistor, the source and drain are conductive; the operating voltage level of a P-type thin film transistor is a low-level voltage, meaning that when a low-level voltage is input to the gate of the P-type thin film transistor, the source and drain are conductive.

[0069] It should also be noted that the light-emitting device in the embodiments of the present disclosure is a current-type light-emitting device, and further, can be a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro organic light-emitting diode (Micro-OLED), etc. In the embodiments of the present disclosure, the light-emitting device is an OLED as an example for description.

[0070] In the related art, the driving of each row of sub-pixels depends on the scanning signal provided by the gate driving circuit. Specifically, the gate driving circuit is electrically connected to the sub-pixels through the scanning signal line to provide the scanning signal to the sub-pixels. However, in the display area on the same horizontal direction as the hole area, the scanning signal line electrically connected to the sub-pixels is affected by the position of the hole and needs to be wound around the hole. As the number of holes increases, the winding path of the scanning signal line becomes longer, which leads to an increase in the resistance of the scanning signal line. As a result, the resistance of the scanning signal line near the hole area is significantly different from the resistance of the scanning signal line of the non-winding layout in the display area. Ultimately, there is a significant difference in the display effect of the sub-pixels driven by the winding and non-winding layouts under the same display screen, affecting the product yield.

[0071] In view of this, the embodiments of the present disclosure provide a display panel and a display device, which substantially reduce the difference between the resistance of the scanning signal line (first scanning line) near the hole area and the resistance of the scanning signal line (second scanning line) with a non-winding layout in the display area, thereby improving the difference in display effects of sub-pixels driven by winding and non-winding under the same display screen, and improving product yield.

[0072] In a first aspect, an embodiment of the present disclosure provides a display panel. Figure 1 A schematic plan view of a display panel provided in an embodiment of the present disclosure is shown. Figure 2 A circuit diagram of a pixel driving circuit provided in an embodiment of the present disclosure, Figure 3 A schematic diagram of the routing layout of the first scanning signal line provided in an embodiment of the present disclosure is provided. Figure 4 for Figure 3 The cross-sectional view along the A-A' direction is shown in the figure below. Figures 1 to 4 As shown, the display panel has a hole area, a display area AA surrounding the hole area, and a non-display area BB surrounding the display area AA. The display panel includes a base substrate 01, a via H provided on the base substrate 01 and located in the hole area, a first gate drive circuit 101 located in the non-display area BB, a plurality of sub-pixels Px located in the display area AA, and a plurality of first scan signal lines 1 extending from the display area AA to the non-display area BB; the first gate drive circuit 101 is electrically connected to the sub-pixel Px through the first scan signal line 1. Optionally, the first scan signal line 1 can be a transmission line for providing a first scan signal Gate_N to the sub-pixel Px; the first scan signal Gate_N can be a transmission line for driving a threshold compensation transistor (such as Figure 2The first gate drive circuit 101 is electrically connected to the first scan signal line 1, and is used to provide the first scan signal Gate_N to the first scan signal line 1. The first scan signal line 1 is mainly used to transmit the first scan signal Gate_N to each sub-pixel Px electrically connected thereto. Optionally, the multiple sub-pixels Px are divided into multiple rows, and one first scan signal line 1 is electrically connected to a row of sub-pixels Px. For the display area AA that is in the same first direction X (such as the horizontal direction) as the hole area, the first scan signal line 1 to which the sub-pixels Px are electrically connected is affected by the position of the hole and needs to be arranged around the hole. In this disclosure, the wound first scan signal line 1 is referred to as the first scan line 11.

[0073] Specifically, the plurality of first scan signal lines 1 include a first scan line 11; the first scan line 11 includes a stacked first sub-scan line 111 and a second sub-scan line 112; the first sub-scan line 111 and the second sub-scan line 112 are connected in parallel. In this embodiment, by providing a double-layered first scan line 11, with the first sub-scan line 111 and the second sub-scan line 112 connected in parallel, the resistance of the first scan line 11 is reduced compared to the prior art single-line arrangement.

[0074] The first sub-scanning line 111 includes at least two sections of first extension portions 1111 and a first surrounding portion 1112 connecting adjacent first extension portions 1111; the first surrounding portion 1112 surrounds a portion of the contour of the via H; the second sub-scanning line 112 includes at least two sections of second extension portions 1121 and a second surrounding portion 1122 connecting adjacent second extension portions 1121; the second surrounding portion 1122 surrounds a portion of the contour of the via H.

[0075] Among them, the first extension portion 1111 and the first surrounding portion 1112 connected thereto are connected as an integral structure, that is, the same routing line, and are prepared and formed by the same mask process. The extension direction of the first extension portion 1111 is the first direction X, and the extension line of the first extension portion 1111 along its extension direction passes through the via H. The first surrounding portion 1112 surrounds the via H along the contour edge of the via H, and the extension lines of each first extension portion 1111 in the same first sub-scan line 111 are collinear. Similarly, the second extension portion 1121 and the second surrounding portion 1122 connected thereto are connected as an integral structure, that is, the same routing line, and are prepared and formed by the same mask process. The extension direction of the second extension portion 1121 is the first direction X, and the extension line of the second extension portion 1121 along its extension direction passes through the via H. The second surrounding portion 1122 surrounds the via hole H along the contour edge of the via hole H, and the extension lines of the second extending portions 1121 in the same second sub-scan line 112 are collinear.

[0076] Exemplarily, the number of vias H is 1, the first sub-scan line 111 includes two first extensions 1111 and a first surrounding portion 1112 connecting the two; the second sub-scan line 112 includes two second extensions 1121 and a second surrounding portion 1122 connecting the two.

[0077] Exemplarily, the number of vias H is two, and the first sub-scan line 111 includes three first extension sections 1111 and two first surround sections 1112. A first surround section 1112 connects two adjacent first extension sections 1111; different first surround sections 1112 connect different adjacent first extension sections 1111. The second sub-scan line 112 includes three second extension sections 1121 and two second surround sections 1122. A second surround section 1122 connects two adjacent second extension sections 1121; different second surround sections 1122 connect different adjacent second extension sections 1121.

[0078] Exemplarily, the number of vias H is three, and the first sub-scan line 111 includes four first extensions 1111 and three first surrounds 1112. A first surround 1112 connects two adjacent first extensions 1111; different first surrounds 1112 connect different adjacent first extensions 1111. The second sub-scan line 112 includes four second extensions 1121 and three second surrounds 1122. A second surround 1122 connects two adjacent second extensions 1121; different second surrounds 1122 connect different adjacent second extensions 1121.

[0079] Figure 5a This is a schematic diagram of the equivalent resistance of a single-layer trace of the first scan line provided in an embodiment of the present disclosure. Figure 5b This is a schematic diagram of the equivalent resistance of the double-layer routing of the extension portion and the single-layer routing of the surrounding portion of the first scan line provided in an embodiment of the present disclosure. Figure 5c This is a schematic diagram of equivalent resistance of the first scan line provided by the embodiment of the present disclosure, in which both the extension portion and the surrounding portion are double-layered. Figure 5d This is a schematic diagram of the equivalent resistance of the second scan line single-layer routing provided by the embodiment of the present disclosure. Figure 5a to Figure 5c As shown, the resistance of the first extension portion 1111 is R1, and the resistance of the first surrounding portion 1112 is R2; the resistance of the second extension portion 1121 is R1, and the resistance of the second surrounding portion 1122 is R2. Taking three vias H as an example, Figure 5a The resistance of the first scan line 11 is 4×R1+3×R2. Figure 5b The resistance of the first scan line 11 is 4×R1+3×R2. Figure 5c The resistance of the first scanning line 11 is (4×R1+3×R2) / 2. That is, the resistance of the double-layer wiring of the extension part and the surrounding part is smaller than the resistance of the single-layer wiring. Figure 5dAs shown, the non-winding scan signal lines in the normal display area AA are arranged in a single-layer routing, such as the second scan line 12. The resistance corresponding to the horizontal length of the extended portion in the second scan line 12 (the single-layer third sub-scan line 121) is R1, and the resistance corresponding to the horizontal length of the surrounding portion (less than the total path length of the surrounding portion) is R3, and R3 < R2; the resistance of the second scan line 12 is 4×R1+3×R3 < 4×R1+3×R2, and because (4×R1+3×R2) / 2 < 4×R1+3×R2, the difference between the resistance of the second scan line 12 and the resistance of the first scan line 11 is reduced, thereby improving the difference in display effects of the sub-pixels Px driven by winding and non-winding under the same display screen, thereby improving product yield.

[0080] In some embodiments, as Figure 4 As shown, the orthographic projections of the first surrounding portion 1112 and the second surrounding portion 1122 on the base substrate 01 at least partially overlap.

[0081] Optionally, the orthographic projections of the first surrounding portion 1112 and the second surrounding portion 1122 on the base substrate 01 partially overlap, which can reduce the border of the via H and increase the display area near the via H, which is conducive to full-screen display.

[0082] Optionally, the orthographic projections of the first surrounding portion 1112 and the second surrounding portion 1122 on the base substrate 01 completely overlap, which can minimize the border of the via H, thereby maximizing the display area near the via H to achieve full-screen display.

[0083] In some embodiments, as Figure 4 As shown, the first extension portion 1111 and the second extension portion 1121 overlap in orthographic projection on the base substrate 01 . Here, “overlap” may be, for example, partial overlap or complete overlap, which can improve the transmittance of the screen body itself.

[0084] In some embodiments, the number of stacked first sub-scan lines 111 is greater than or equal to 2; the number of stacked second sub-scan lines 112 is greater than or equal to 2. By adding multiple layers of sub-scan lines, the resistance of the first scan line 11 is reduced, and the difference between the resistance of the first scan line 11 and the resistance of the second scan line 12 is reduced. In practical applications, the number of stacked sub-scan lines can be set according to the resistance of the second scan line 12 or the difference between the resistance of the first scan line 12 and the resistance of the second scan line 12. The specific number is not limited in this disclosure. This disclosure is described by taking a layer of first sub-scan lines 111 and a layer of second sub-scan lines 112 as an example. Figure 4 As shown, this does not constitute a limitation on the actual number of layers of the first sub-scanning lines 111 and the second sub-scanning lines 112 disclosed in the present invention.

[0085] In some embodiments, as Figure 3 and Figure 4As shown, the plurality of first scan signal lines 1 also include a second scan line 12; the extension direction of the second scan line 12 is the same as the extension direction of the first extension portion 1111 and the extension direction of the second extension portion 1121. Here, the tangent direction of any point on the second scan line 12 is the same, that is, the first direction X.

[0086] Alternatively, as Figure 3 As shown, a plurality of sub-pixels Px are divided into a plurality of rows; different first scan lines 11 are electrically connected to sub-pixels Px in different rows; and different second scan lines 12 are electrically connected to sub-pixels Px in different rows.

[0087] In some embodiments, the second scan line 12 may adopt a single-layer wiring layout, or a double-layer wiring layout.

[0088] Alternatively, as Figure 4 As shown, the second scan line 12 includes a third sub-scan line 121 and a fourth sub-scan line 122 that are stacked; the third sub-scan line 121 and the fourth sub-scan line 122 are connected in parallel, which can reduce the resistance of the second scan line 12, which is beneficial to increasing the transmission speed of the first scan signal Gate_N, thereby increasing the refresh rate.

[0089] Alternatively, as Figure 4 As shown, the first sub-scanning line 111 and the third sub-scanning line 121 are arranged on the same layer, and the second sub-scanning line 112 and the fourth sub-scanning line 122 are arranged on the same layer.

[0090] In some embodiments, an output terminal 101a of the first gate driving circuit 101 can be electrically connected to one first scanning signal line 1, or electrically connected to multiple first scanning signal lines 1 at the same time. Figure 3 As shown, one output terminal 101a of the first gate driving circuit 101 is electrically connected to two adjacent first scanning lines 11 at the same time. Figure 3 As shown, one output terminal 101a of the first gate driving circuit 101 is electrically connected to two adjacent second scan lines 12. For another example, one output terminal 101a of the first gate driving circuit 101 is electrically connected to one first scan line 11 and one second scan line 12 at the same time.

[0091] Alternatively, as Figure 3As shown, multiple first scan signal lines 1 are divided into multiple first scan signal line groups 10a; each first scan signal line group 10a includes at least two adjacent first scan signal lines 1; different first scan signal lines 1 are electrically connected to different rows of sub-pixels Px; for any first scan signal line group 10a, the first ends of the first scan signal lines 1 are electrically connected to each other, and the second ends of the first scan signal lines 1 are electrically connected to each other. An output end 101a of the first gate driver circuit 101 is electrically connected to the first ends of the first scan signal lines 1 in the first scan signal line group 10a, and is used to simultaneously provide the first scan signal Gate_N to each first scan signal line 1 in the first scan signal line group 10a, thereby achieving the effect of one first gate driver circuit 101 driving multiple (for example, one first gate driver circuit 101 simultaneously drives two rows of sub-pixels Px). Optionally, an output terminal 101 a of the first gate driving circuit 101 is electrically connected to the first end of each first scanning signal line 1 in a group of first scanning signal lines 10 a through a first connecting line 13 .

[0092] For example, Figure 3 As shown, each first scan signal line group 10a includes two first scan signal lines 1. For any first scan signal line group 10a, the first end of one first scan signal line 1 is electrically connected to the first end of another first scan signal line 1 via a first adapter line 14; and the second end of one first scan signal line 1 is electrically connected to the second end of another first scan signal line 1 via a second adapter line 15. Here, for any first scan signal line group 10a, the first end of each first scan signal line 1 is electrically connected to the first connection line 13.

[0093] Optionally, the first adapter line 14 and the second adapter line 15 are single-layer wiring. The first connecting line 13 is single-layer wiring.

[0094] Optionally, the first connecting line 13 , the first adapter line 14 and the second adapter line 15 are all double-layered, wherein the first layer is on the same layer as the first sub-scanning line 111 , and the second layer is on the same layer as the second sub-scanning line 112 .

[0095] This embodiment adopts a design scheme in which the first gate driving circuit 101 drives two gates, which can achieve a narrow frame.

[0096] In some embodiments, as Figure 2As shown, the sub-pixel Px includes a light-emitting device OLED and a pixel driving circuit 200 for driving the light-emitting device OLED. The display panel also includes a second scanning signal line 2, a third scanning signal line 3, a fourth scanning signal line 4 and a fifth scanning signal line 5; the second scanning signal line 2, the third scanning signal line 3, the fourth scanning signal line 4 and the fifth scanning signal line 5 all extend from the display area AA to the non-display area BB. The pixel driving circuit 200 in the embodiment of the present disclosure is described using an 8T1C structure as an example. The pixel driving circuit 200 may include 8 transistors (a first transistor T1 to an eighth transistor T8) and a storage capacitor Cst. The pixel driving circuit 200 may also be a 7T1C (i.e., 7 transistors and 1 storage capacitor Cst) structure, a 7T2C (i.e., 7 transistors and 2 storage capacitors Cst) structure or an 8T2C (i.e., 8 transistors and 2 storage capacitors Cst) structure, etc., which is not limited in this embodiment.

[0097] Specifically, the pixel driving circuit 200 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst. The control electrode of the first transistor T1 is electrically connected to the second scan signal line 2, the first electrode is electrically connected to the first reference signal line 6, and the second electrode is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the first scan signal line 1, the first electrode is electrically connected to the first node N1, and the second electrode is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal line 3, the first electrode is electrically connected to the data line 7, and the second electrode is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the fourth scan signal line 4, the first electrode is electrically connected to the first power signal line 8, and its second electrode is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the fourth scan signal line 4, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the first electrode of the light-emitting device OLED (i.e., the fourth node N4); the control electrode of the seventh transistor T7 is electrically connected to the fifth scan signal line 5, the first electrode is electrically connected to the second reference signal line 9, and the second electrode is electrically connected to the first electrode of the light-emitting device OLED; the control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal line 5 (RH), the first electrode is electrically connected to the third reference signal line 10, and the second electrode is electrically connected to the second node N2; the first plate of the storage capacitor Cst is electrically connected to the first power signal line 8, and the second plate is electrically connected to the first node N1. The first transistor T1 is turned on in response to the second scan signal Reset_P transmitted by the second scan signal line 2, and is used to write the first reference signal Vinit1 provided by the first reference signal line 6 into the first node N1 to reset the first node N1. The second transistor T2 is turned on in response to the first scan signal Gate_N transmitted by the first scan signal line 1, and is used to perform threshold compensation for the third transistor T3. The third transistor T3 is turned on in response to the voltage signal at the first node N1, thereby driving the light-emitting device OLED to emit light. The fourth transistor T4 is turned on in response to the third scan signal Gate_P transmitted by the third scan signal line 3, thereby writing the data voltage signal Data provided by the data line 7 to the second node N2. The fifth transistor T5 is turned on in response to the fourth scan signal EM transmitted by the fourth scan signal line 4, thereby writing the first power signal VDD provided by the first power signal line 8 to the second node N2. Simultaneously, the sixth transistor T6 is turned on in response to the fourth scan signal EM transmitted by the fourth scan signal line 4, thereby writing the voltage of the third node N3 to the fourth node N4, thereby driving the light-emitting device OLED to emit light.The seventh transistor T7 is responsive to the fifth scan signal Reset_H transmitted by the fifth scan signal line 5 and is configured to write the second reference signal Vinit2 provided by the second reference signal line 9 into the fourth node N4, thereby resetting the fourth node N4. The eighth transistor T8 is responsive to the fifth scan signal Reset_H transmitted by the fifth scan signal line 5 and is configured to write the third reference signal Vinit3 provided by the third reference signal line 10 into the second node N2, thereby resetting the second node N2. The second electrode of the light-emitting device OLED is electrically connected to the second power signal line VSS. The second reference signal Vinit2 and the third reference signal Vinit3 have different voltages; specifically, the second reference signal Vinit2 and the third reference signal Vinit3 have opposite potentials, with the second reference signal Vinit2 having a voltage of -5V and the third reference signal Vinit3 having a voltage of +5V.

[0098] Exemplarily, one of the first electrode and the second electrode of the light-emitting device OLED is an anode, and the other is a cathode. The embodiments of the present disclosure are described by taking the first electrode of the light-emitting device OLED as an anode and the second electrode as a cathode as an example.

[0099] Optionally, the first transistor T1 , the second transistor T2 , and the eighth transistor T8 are all N-type transistors, and the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 are all P-type transistors.

[0100] Optionally, the second transistor T2 may be an oxide thin film transistor; the active layer of the oxide thin film transistor uses an oxide semiconductor (Oxide), so that the second transistor T2 has the advantages of high mobility, large area uniformity, low preparation temperature, high transmittance and transparency.

[0101] Table 1 shows the capacitance and resistance parameters of each scanning signal line (first scanning signal line 1 to fifth scanning signal line 5) with and without winding, as well as the capacitance change rate and resistance change rate of winding compared to without winding. As can be seen from Table 1, the capacitance change of the first scanning signal line 1 (first scanning signal Gate_N) with winding (i.e., first scanning line 11) is not much compared to the first scanning signal line 1 without winding (second scanning line 12), but the resistance change is larger (i.e., the resistance difference is larger).

[0102] Table 1

[0103]

[0104] Figure 6This is a diagram of a poor display effect in which a bright band appears on the right side of the hole area provided in the embodiment of the present disclosure. In the related art, the first scan line 11 needs to be wound at the position of the via H compared to the second scan line 12, resulting in an increase in the resistance of the first scan line 11, thereby increasing the rise time (Tr) and fall time (Tf) of the waveform of the first scan signal Gate_N transmitted by the first scan line 11, which is different from the normal output waveform of the second scan line 12. The greater the difference between the two or the greater the winding load at the position of the via H, the longer the fall time (Tf), and thus the longer the time to pull down the first node N1, resulting in a negative bias of the first node N1, which in turn causes the driving transistor (that is, the third transistor T3) to turn on quickly, and the light-emitting device OLED produces a continuously bright display effect, that is, a bright band, as shown in FIG. Figure 6 In addition, it should be noted that the position of the bright band is related to the position of the first gate driver circuit 101. If the first gate driver circuit 101 is located in the non-display area BB of the left frame, the sub-pixels Px farther away from the first gate driver circuit 101 will be brighter due to the influence of the increased resistance value, that is, the bright band will be closer to the right. Similarly, if the first gate driver circuit 101 is located in the non-display area BB of the right frame, the sub-pixels Px farther away from the first gate driver circuit 101 will be brighter due to the influence of the increased resistance value, that is, the bright band will be closer to the left.

[0105] In the embodiment of the present disclosure, the resistance of the first scan line 11 for controlling the second transistor T2 is reduced, thereby shortening the fall time (Tf) of the output waveform. This reduces the difference between the resistance of the first scan line 11 and the resistance of the second scan line 12, thereby improving the difference between the output waveforms of the first scan line 11 and the second scan line 12, avoiding the negative bias phenomenon of the first node N1, and eliminating the bright band display.

[0106] Figure 7 A schematic diagram of the layout of each gate driving circuit in the display panel provided by the embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the display panel further includes a first gate driving circuit 101, a second gate driving circuit 102, a third gate driving circuit 103, a fourth gate driving circuit 104 and a fifth gate driving circuit 105. Figure 2As can be seen from the pixel driving circuit 200 shown, the first gate driving circuit 101 is electrically connected to the control electrode of the second transistor T2 via the first scan signal line 1, and is used to control the on / off of the second transistor T2. The second gate driving circuit 102 is electrically connected to the control electrode of the first transistor T1 via the second scan signal line 2, and is used to control the on / off of the first transistor T1. The third gate driving circuit 103 is electrically connected to the control electrode of the fourth transistor T4 via the third scan signal line 3, and is used to control the on / off of the fourth transistor T4. The fourth gate driving circuit 104 is electrically connected to the control electrodes of the fifth transistor T5 and the sixth transistor T6 via the fourth scan signal line 4, and is used to simultaneously control the on / off of the fifth transistor T5 and the sixth transistor T6. The fifth gate driving circuit 105 is electrically connected to the control electrodes of the seventh transistor T7 and the eighth transistor T8 via the fifth scan signal line 5, and is used to simultaneously control the on / off of the seventh transistor T7 and the eighth transistor T8.

[0107] Wherein, each gate driving circuit (the first gate driving circuit 101 to the fifth gate driving circuit 105) in the display panel is located in the non-display area BB. Figure 7 As shown, the non-display area BB includes a first sub-border area BB1 and a second sub-border area BB2 that are arranged opposite to each other along a first direction X. The first gate driving circuit 101 is located in the first sub-border area BB1; the second gate driving circuit 102 is located in the first sub-border area BB1 and is arranged on a side of the first gate driving circuit 101 away from the display area AA; the third gate driving circuit 103 includes two, which are located in the first sub-border area BB1 and the second sub-border area BB2 respectively, and the third gate driving circuit 103 located in the first sub-border area BB1 is arranged on a side of the first gate driving circuit 101 close to the display area AA; the fourth gate driving circuit 104 is located in the second sub-border area BB2 and is arranged on a side of the third gate driving circuit 103 located in the second sub-border area BB2 away from the display area AA; the fifth gate driving circuit 105 is located in the second sub-border area BB2 and is arranged between the fourth gate driving circuit 104 and the third gate driving circuit 103 located in the second sub-border area BB2.

[0108] In some embodiments, Figure 8 A schematic diagram of the routing layout of the second scan signal line provided in an embodiment of the present disclosure is shown in FIG. Figure 8As shown, the plurality of second scan signal lines 2 include a third scan line 21 and a fourth scan line 22. The third scan line 21 and the fourth scan line 22 are both used to transmit the second scan signal Reset_P to the first transistor T1 connected thereto. The difference between the third scan line 21 and the fourth scan line 22 is that the extension line of the third scan line 21 passes through the via H, so the third scan line 21 needs to be routed around the via H. Specifically, the third scan line 21 includes at least two third extension portions 211 and a third surrounding portion 212 connecting adjacent third extension portions 211; the third surrounding portion 212 surrounds a portion of the contour of the via H; the extension direction of the fourth scan line 22 is the same as the extension direction of the third extension portion 211. The extension direction of the third extension portion 211 is the first direction X.

[0109] Optionally, the third extension portion 211 and the third surrounding portion 212 are connected as an integral structure, i.e., are formed in the same routing and by the same mask process. The third surrounding portion 212 surrounds the via H along the contour edge of the via H, and the extension lines of the third extension portions 211 in the same third scan line 21 are collinear.

[0110] Exemplarily, the number of the via hole H is 1, and the third scan line 21 includes two third extending portions 211 and a third surrounding portion 212 connecting the two.

[0111] Exemplarily, the number of vias H is 2, and the third scan line 21 includes three third extensions 211 and two third surrounding portions 212. One third surrounding portion 212 connects two adjacent third extensions 211, and different third surrounding portions 212 connect different adjacent third extensions 211.

[0112] Exemplarily, the number of vias H is 3, and the third scan line 21 includes four third extensions 211 and three third surrounding portions 212. One third surrounding portion 212 connects two adjacent third extensions 211, and different third surrounding portions 212 connect different adjacent third extensions 211.

[0113] In some embodiments, the third scan line 21 and the fourth scan line 22 may be arranged in a single-layer layout, or in a double-layer layout. Optionally, both the third scan line 21 and the fourth scan line 22 may be arranged in a single-layer layout, thereby improving fabrication efficiency, reducing process costs, and avoiding signal interference in a multi-layer structure.

[0114] In some embodiments, an output terminal 102a of the second gate driving circuit 102 can be electrically connected to one second scanning signal line 2, or electrically connected to multiple second scanning signal lines 2 at the same time. Figure 8 As shown, one output terminal 102a of the second gate driving circuit 102 is electrically connected to two adjacent third scanning lines 21 at the same time. Figure 8 As shown, an output terminal 102a of the second gate driving circuit 102 is electrically connected to two adjacent fourth scan lines 22. For another example, an output terminal of the second gate driving circuit 102 is electrically connected to a third scan line 21 and a fourth scan line 22 at the same time.

[0115] Alternatively, as Figure 8 As shown, a plurality of second scan signal lines 2 are divided into a plurality of second scan signal line groups 20a; each second scan signal line group 20a includes at least two adjacent second scan signal lines 2; a plurality of sub-pixels Px are divided into a plurality of rows; different second scan signal lines 2 are electrically connected to sub-pixels Px in different rows; and for any second scan signal line group 20a, the first ends of the second scan signal lines 2 are electrically connected to each other, and the second ends of the second scan signal lines 2 are electrically connected to each other, i.e., each second scan signal line in the second scan signal line group 20a. An output terminal 102a of the second gate driver circuit 102 is electrically connected to the first ends of the second scan signal lines 2 in the second scan signal line group 20a, and is used to simultaneously provide the second scan signal Reset_P to each second scan signal line 2 in the second scan signal line group 20a, thereby achieving the effect of one second gate driver circuit 102 driving multiple sub-pixels (for example, one second gate driver circuit 102 simultaneously drives two rows of sub-pixels Px). Optionally, an output terminal 102 a of the second gate driving circuit 102 is electrically connected to the first end of each second scanning signal line 2 in a second scanning signal line group 20 a through a second connecting line 23 .

[0116] For example, Figure 8 As shown, each second scan signal line group 20a includes two second scan signal lines 2. For any second scan signal line group 20a, the first end of one second scan signal line 2 is electrically connected to the first end of another second scan signal line 2 via a third adapter line 24; and the second end of one second scan signal line 2 is electrically connected to the second end of another second scan signal line 2 via a fourth adapter line 25.

[0117] Optionally, the second connecting line 23 , the third adapter line 24 and the fourth adapter line 25 may all adopt a single-layer routing layout.

[0118] This embodiment adopts a design scheme in which the second gate driving circuit 102 drives two gates at a time, thereby achieving a narrow frame.

[0119] In some embodiments, Figure 9 A schematic diagram of the wiring layout of the third scan signal line provided in an embodiment of the present disclosure is shown in FIG. Figure 9As shown, two third gate drive circuits 103 arranged opposite each other along the first direction X are electrically connected via a third scan signal line 3; a plurality of sub-pixels Px are divided into a plurality of rows; and a third scan signal line 3 is electrically connected to a row of sub-pixels Px. The disclosed embodiment uses a dual-gate drive method to control the data writing transistors (fourth transistors T4) of a row of sub-pixels Px (in the pixel drive circuit 200) to improve the refresh rate of the screen.

[0120] Among them, the multiple third scan signal lines 3 include a fifth scan line 31 and a sixth scan line 32. The fifth scan line 31 and the sixth scan line 32 are both used to transmit the third scan signal Gate_P to the fourth transistor T4 connected thereto. The difference between the fifth scan line 31 and the sixth scan line 32 is that the extension line of the fifth scan line 31 passes through the via H, so the fifth scan line 31 needs to be routed around the via H. Specifically, the fifth scan line 31 includes at least two fourth extension portions 311 and a fourth surrounding portion 312 connecting adjacent fourth extension portions 311; the fourth surrounding portion 312 surrounds a portion of the contour of the via H; the extension direction of the sixth scan line 32 is the same as the extension direction of the fourth extension portion 311. The extension direction of the fourth extension portion 311 is the first direction X.

[0121] Optionally, the fourth extension portion 311 and the fourth surrounding portion 312 are connected as an integral structure, i.e., are formed in the same routing and by the same mask process. The fourth surrounding portion 312 surrounds the via H along the contour edge of the via H, and the extension lines of the fourth extension portions 311 in the same fifth scan line 31 are collinear.

[0122] Exemplarily, the number of the via hole H is 1, and the fifth scan line 31 includes two fourth extending portions 311 and a fourth surrounding portion 312 connecting the two.

[0123] Exemplarily, the number of vias H is 2, and the fifth scan line 31 includes three fourth extension portions 311 and two fourth surrounding portions 312. One fourth surrounding portion 312 connects two adjacent fourth extension portions 311, and different fourth surrounding portions 312 connect different adjacent fourth extension portions 311.

[0124] Exemplarily, the number of vias H is 3, and the fifth scan line 31 includes four fourth extension portions 311 and three fourth surrounding portions 312. One fourth surrounding portion 312 connects two adjacent fourth extension portions 311, and different fourth surrounding portions 312 connect different adjacent fourth extension portions 311.

[0125] In some embodiments, the fifth scan line 31 and the sixth scan line 32 may be arranged in a single-layer layout or a double-layer layout. Optionally, the fifth scan line 31 and the sixth scan line 32 may be arranged in a single-layer layout.

[0126] In some embodiments, Figure 10 A schematic diagram of the wiring layout of the fourth scan signal line provided in an embodiment of the present disclosure is shown in FIG. Figure 10 As shown, an output terminal 104a of the fourth gate drive circuit 104 can be electrically connected to a fourth scan signal line 4, or electrically connected to multiple fourth scan signal lines 4 at the same time. The multiple fourth scan signal lines 4 include a seventh scan line 41 and an eighth scan line 42; wherein the seventh scan line 41 and the eighth scan line 42 are both used to transmit the fourth scan signal EM to the fifth transistor T5 and the sixth transistor T6 connected thereto. The difference between the seventh scan line 41 and the eighth scan line 42 is that the extension line of the seventh scan line 41 (the fifth extension portion 411) passes through the via H, so the seventh scan line 41 needs to be routed around the via H. For example, Figure 10 As shown, one output terminal 104a of the fourth gate driving circuit 104 is electrically connected to two adjacent seventh scanning lines 41 at the same time. Figure 10 As shown, one output terminal 104a of the fourth gate driving circuit 104 is electrically connected to two adjacent eighth scan lines 42. For another example, one output terminal of the fourth gate driving circuit 104 is electrically connected to one seventh scan line 41 and one eighth scan line 42.

[0127] The seventh scan line 41 includes at least two fifth extensions 411 and a fifth surrounding portion 412 connecting adjacent fifth extensions 411; the fifth surrounding portion 412 surrounds a portion of the outline of the via H. Optionally, the plurality of seventh scan lines 41 are divided into a plurality of third scan signal line groups 30a; each third scan signal line group 30a includes at least two adjacent seventh scan lines 41; the plurality of sub-pixels Px are divided into a plurality of rows; different seventh scan lines 41 are electrically connected to sub-pixels Px in different rows; for any third scan signal line group 30a, the fifth surrounding portion 412 of each seventh scan line 41 is shared, the first ends of the fifth extensions 411 of each seventh scan line 41 are electrically connected to each other, and the second ends of the fifth extensions 411 of each seventh scan line 41 are electrically connected to each other. An output terminal 104a of the fourth gate driver circuit 104 is electrically connected to one end of each seventh scan line 41 in the third scan signal line group 30a (i.e., the first end of the fifth extension portion 411 of the seventh scan line 41), thereby simultaneously providing a fourth scan signal to each of the seventh scan lines 41 in the third scan signal line group 30a. This achieves the effect of one fourth gate driver circuit 104 driving multiple sub-pixels (e.g., one fourth gate driver circuit 104 simultaneously drives two rows of sub-pixels Px). Optionally, an output terminal 104a of the fourth gate driver circuit 104 is electrically connected to one end of each of the seventh scan lines 41 in the third scan signal line group 30a via a third connection line 43.

[0128] Exemplarily, the third scan signal line group 30a includes two adjacent seventh scan lines 41. For any third scan signal line group 30a, the first end of the fifth extension portion 411 of one seventh scan line 41 is electrically connected to the first end of the fifth extension portion 411 of another seventh scan line 41 via a fifth adapter line 44; and the second end of the fifth extension portion 411 of one seventh scan line 41 is electrically connected to the second end of the fifth extension portion 411 of another seventh scan line 41 via a sixth adapter line 45. The ends of the fifth surrounding portion 412 are connected to the fifth adapter line 44 and the sixth adapter line 45, respectively.

[0129] Optionally, the seventh scan line 41 adopts a single-layer wiring layout.

[0130] Optionally, the third connecting line 43 , the fifth adapter line 44 and the sixth adapter line 45 are all single-layer wiring.

[0131] In the winding design of the seventh scan line 41 in this embodiment, multiple fifth extension portions 411 are combined into one fifth surrounding portion 412 for winding, so that a narrow frame of the via H can be achieved.

[0132] In some embodiments, as Figure 10 As shown, the plurality of fourth scan signal lines 4 also include an eighth scan line 42; the plurality of eighth scan lines 42 are divided into a plurality of fourth scan signal line groups 40a; each fourth scan signal line group 40a includes at least two adjacent eighth scan lines 42; different eighth scan lines 42 are electrically connected to different rows of sub-pixels Px; and for any fourth scan signal line group 40a, the first ends of the eighth scan lines 42 are electrically connected to each other, and the second ends of the eighth scan lines 42 are electrically connected to each other. An output terminal of the fourth gate driver circuit 104 is electrically connected to the first ends of the eighth scan lines 42 in a fourth scan signal line group 40a, for simultaneously providing the fourth scan signal EM to each eighth scan line 42 in the fourth scan signal line group 40a, thereby achieving the effect of one fourth gate driver circuit 104 driving multiple rows (for example, one fourth gate driver circuit 104 simultaneously drives two rows of sub-pixels Px). Optionally, an output terminal 104 a of the fourth gate driving circuit 104 is electrically connected to one end of each eighth scan line 42 in a fourth scan signal line group 40 a through a fourth connection line 46 .

[0133] For example, Figure 10 As shown, each fourth scan signal line group 40a includes two eighth scan lines 42. For any fourth scan signal line group 40a, the first end of one eighth scan line 42 is electrically connected to the first end of another first eighth scan line 42 via a seventh adapter line 47; and the second end of one eighth scan line 42 is electrically connected to the second end of another eighth scan line 42 via an eighth adapter line 48.

[0134] Optionally, the eighth scan line 42 adopts a single-layer wiring layout.

[0135] Optionally, the third connecting line 43 , the seventh adapter line 47 and the eighth adapter line 48 may all adopt a single-layer routing layout.

[0136] This embodiment adopts a design scheme in which the fourth gate driving circuit 104 drives two (two eighth scanning lines 42 ), which can achieve a narrow frame.

[0137] In some embodiments, Figure 11 A schematic diagram of the routing layout of the fifth scan signal line provided in an embodiment of the present disclosure is shown in FIG. Figure 11 As shown, an output terminal 105a of the fifth gate driver circuit 105 can be electrically connected to one fifth scan signal line 5, or to multiple fifth scan signal lines 5 simultaneously. The multiple fifth scan signal lines 5 include a ninth scan line 51 and a tenth scan line 52; both the ninth scan line 51 and the tenth scan line 52 are used to transmit the fifth scan signal Reset_H to the seventh transistor T7 and the eighth transistor T8 connected thereto. The difference between the ninth scan line 51 and the tenth scan line 52 is that the extension of the ninth scan line 51 (the sixth extension 511) passes through the via H, so the ninth scan line 51 needs to be routed around the via H. For example, an output terminal 105a of a fifth gate driver circuit 105 is electrically connected to two adjacent ninth scan lines 51. For another example, an output terminal 105a of the fifth gate driver circuit 105 is electrically connected to two adjacent tenth scan lines 52. For another example, an output terminal 105a of the fifth gate driver circuit 105 is electrically connected to one ninth scan line 51 and one tenth scan line 52 simultaneously.

[0138] The ninth scan line 51 includes at least two sixth extensions 511 and a sixth surrounding portion 512 connecting adjacent sixth extensions 511; the sixth surrounding portion 512 surrounds a portion of the outline of the via H. Optionally, the plurality of ninth scan lines 51 are divided into a plurality of fifth scan signal line groups 50a; each fifth scan signal line group 50a includes at least two adjacent ninth scan lines 51; the plurality of sub-pixels Px are divided into a plurality of rows; different ninth scan lines 51 are electrically connected to sub-pixels Px in different rows; for any fifth scan signal line group 50a, the sixth surrounding portion 512 of each ninth scan line 51 is shared, the first ends of the sixth extensions 511 of each ninth scan line 51 are electrically connected to each other, and the second ends of the sixth extensions 511 of each ninth scan line 51 are electrically connected to each other. An output terminal 105a of the fifth gate driver circuit 105 is electrically connected to one end of each ninth scan line 51 in the fifth scan signal line group 50a (i.e., the first end of the sixth extension portion 511 of the ninth scan line 51), thereby simultaneously providing the fifth scan signal EM to each ninth scan line 51 in the fifth scan signal line group 50a. This achieves the effect of one fifth gate driver circuit 105 driving multiple sub-pixels (e.g., one fifth gate driver circuit 105 simultaneously drives two rows of sub-pixels Px). Optionally, an output terminal of the fifth gate driver circuit 105 is electrically connected to one end of each ninth scan line 51 in the fifth scan signal line group 50a via a fifth connection line 53.

[0139] Exemplarily, the fifth scan signal line group 50a includes two adjacent ninth scan lines 51. For any fifth scan signal line group 50a, the first end of the sixth extension portion 511 of one ninth scan line 51 is electrically connected to the first end of the sixth extension portion 511 of another ninth scan line 51 via a ninth adapter line 54; and the second end of the sixth extension portion 511 of one ninth scan line 51 is electrically connected to the second end of the sixth extension portion 511 of another ninth scan line 51 via a tenth adapter line 55. The ends of the sixth surrounding portion 512 are connected to the ninth adapter line 54 and the tenth adapter line 55, respectively.

[0140] Optionally, the ninth scan line 51 adopts a single-layer routing layout.

[0141] Optionally, the fifth connecting line 53 , the ninth connecting line 54 and the tenth connecting line 55 may all adopt a single-layer routing layout.

[0142] In the winding design of the ninth scanning line 51 in this embodiment, multiple sixth extension portions 511 are combined into one sixth surrounding portion 512 for winding, so as to achieve a narrow frame of the via H.

[0143] Optionally, the ninth scan line 51 adopts a single-layer routing layout.

[0144] In some embodiments, as Figure 11 As shown, the plurality of fifth scan signal lines 5 also include a tenth scan line 52; the plurality of tenth scan lines 52 are divided into a plurality of sixth scan signal line groups 60a; each sixth scan signal line group 60a includes at least two adjacent tenth scan lines 52; different tenth scan lines 52 are electrically connected to different rows of sub-pixels Px; and for any sixth scan signal line group 60a, the first ends of the tenth scan lines 52 are electrically connected to each other, and the second ends of the tenth scan lines 52 are electrically connected to each other. An output terminal 105a of the fifth gate driver circuit 105 is electrically connected to the first ends of the tenth scan lines 52 in the sixth scan signal line group 60a, for simultaneously providing the fifth scan signal EM to the tenth scan lines 52 in the sixth scan signal line group 60a, thereby achieving the effect of one fifth gate driver circuit 105 driving multiple rows (for example, one fifth gate driver circuit 105 simultaneously drives two rows of sub-pixels Px). Optionally, an output terminal 105 a of the fifth gate driving circuit 105 is electrically connected to one end of each tenth scan line 52 in a group of sixth scan signal lines 60 a through a sixth connection line 56 .

[0145] For example, Figure 11 As shown, each sixth scan signal line group 60a includes two tenth scan lines 52. For any sixth scan signal line group 60a, the first end of one tenth scan line 52 is electrically connected to the first end of another first tenth scan line 52 via an eleventh adapter line 57; and the second end of one tenth scan line 52 is electrically connected to the second end of another tenth scan line 52 via a twelfth adapter line 58.

[0146] Optionally, the tenth scan line 52 adopts a single-layer routing layout.

[0147] Optionally, the sixth connecting line 56 , the eleventh connecting line 57 and the twelfth connecting line 58 may all adopt a single-layer routing layout.

[0148] This embodiment adopts a design scheme in which the fifth gate driving circuit 105 drives two (two tenth scanning lines 52 ), which can achieve a narrow frame.

[0149] In some embodiments, Figure 12 for Figure 7 The cross-sectional view along the B-B' direction is shown in the figure below. Figure 12As shown, the display panel includes a first conductive layer 02, a second conductive layer 03, a third conductive layer 04, a fourth conductive layer 05 and a fifth conductive layer 06 arranged in sequence along a direction away from the base substrate 01; the first sub-scanning line 111 is located in the third conductive layer 04; the second sub-scanning line 112 is located in the fourth conductive layer 05; the second scanning signal line 2 is located in the first conductive layer 02; the third scanning signal line 3 is located in the second conductive layer 03; the fourth scanning signal line 4 and the fifth scanning signal line 5 are both located in the fifth conductive layer 06.

[0150] The first conductive layer 02 also includes a light-shielding structure (not shown). The orthographic projection of this light-shielding structure on the substrate 01 covers the orthographic projection of the active layers of each transistor on the substrate 01, preventing light from reaching the channel region of the active layer, thereby reducing the impact of light on the characteristics of the channel region. The second scanning signal line 2 is provided on the same layer as the light-shielding structure, and both can be fabricated using the same mask process, reducing process costs and improving fabrication efficiency.

[0151] The second conductive layer 03 , the third conductive layer 04 and the fourth conductive layer 05 are all gate electrode layers, which are used for arranging various scanning signal lines.

[0152] The fifth conductive layer 06 also includes the source and drain electrodes of the transistors, i.e., the fifth conductive layer 06 is a source and drain electrode layer. The fourth and fifth scan signal lines 4 and 5 and the source and drain electrodes (i.e., the first and second electrodes) of some transistors can be formed using the same mask process, reducing process costs and improving production efficiency.

[0153] like Figure 12 As shown, the display panel further includes a plurality of data lines 7, each data line 7 electrically connected to a column of sub-pixels Px. Specifically, the data line 7 is electrically connected to the first electrode of the fourth transistor T4 in the pixel driving circuit 200. Two adjacent data lines 7 are located in different conductive layers. The display panel further includes a sixth conductive layer 07 disposed on a side of the fifth conductive layer 06 facing away from the fourth conductive layer 05, and a seventh conductive layer 08 disposed on a side of the sixth conductive layer 07 facing away from the fifth conductive layer 06. The data lines 7 in odd columns (or even columns) are located in the sixth conductive layer 07, and the data lines 7 in even columns (or odd columns) are all located in the seventh conductive layer 08.

[0154] In a second aspect, embodiments of the present disclosure further provide a display device comprising the display panel of any of the aforementioned embodiments. The display device may be, for example, a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, vehicle-mounted device, or any other product with a display function. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0155] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises a hole area, a display area surrounding the hole area, and a non-display area surrounding the display area; the display panel comprises a base substrate, a via hole provided on the base substrate and located in the hole area, a first gate driving circuit located in the non-display area, a plurality of sub-pixels located in the display area, and a plurality of first scanning signal lines extending from the display area to the non-display area; the first gate driving circuit is electrically connected to the sub-pixels through the first scanning signal lines; The plurality of first scan signal lines include a first scan line; the first scan line includes a first sub-scan line and a second sub-scan line that are stacked; the first sub-scan line is connected in parallel with the second sub-scan line; The first sub-scan line includes at least two first extension sections and a first surrounding section connecting adjacent first extension sections; the first surrounding section surrounds a portion of the contour of the via hole; the second sub-scan line includes at least two second extension sections and a second surrounding section connecting adjacent second extension sections; the second surrounding section surrounds a portion of the contour of the via hole.

2. The display panel according to claim 1, wherein: The orthographic projections of the first surrounding portion and the second surrounding portion on the base substrate at least partially overlap.

3. The display panel according to claim 1, wherein: The first extension portion and the second extension portion overlap in orthographic projection on the base substrate.

4. The display panel according to claim 1, wherein: The plurality of first scan signal lines further include a second scan line; an extending direction of the second scan line, an extending direction of the first extending portion, and an extending direction of the second extending portion are all the same.

5. The display panel according to claim 4, wherein: The second scan line includes a third sub-scan line and a fourth sub-scan line that are stacked; the third sub-scan line is connected in parallel with the fourth sub-scan line.

6. The display panel according to claim 1, wherein: The plurality of sub-pixels are divided into a plurality of rows; the plurality of first scanning signal lines are divided into a plurality of first scanning signal line groups; each first scanning signal line group includes at least two adjacent first scanning signal lines; different first scanning signal lines are electrically connected to the sub-pixels in different rows; For any first scanning signal line group, first ends of the first scanning signal lines are electrically connected to each other, and second ends of the first scanning signal lines are electrically connected to each other; An output end of the first gate driving circuit is electrically connected to a first end of each of the first scanning signal lines in a group of the first scanning signal lines.

7. The display panel according to any one of claims 1 to 6, wherein: The display panel further includes a plurality of second scan signal lines, third scan signal lines, fourth scan signal lines, and fifth scan signal lines extending from the display area to the non-display area; the sub-pixels include light-emitting devices and pixel driving circuits for driving the light-emitting devices; The pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a storage capacitor; The control electrode of the first transistor is electrically connected to the second scanning signal line, the first electrode is electrically connected to the first reference signal line, and the second electrode is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the first scanning signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node; The control electrode of the third transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the third scan signal line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the fourth scan signal line, the first electrode is electrically connected to the first power signal line, and the second electrode is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the fourth scan signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the first electrode of the light emitting device; The control electrode of the seventh transistor is electrically connected to the fifth scan signal line, the first electrode is electrically connected to the second reference signal line, and the second electrode is electrically connected to the first electrode of the light emitting device; The control electrode of the eighth transistor is electrically connected to the fifth scan signal line, the first electrode is electrically connected to the third reference signal line, and the second electrode is electrically connected to the second node; The first plate of the storage capacitor is electrically connected to the first power signal line, and the second plate is electrically connected to the first node.

8. The display panel according to claim 7, wherein: The display panel further includes a second gate driving circuit; the second gate driving circuit is electrically connected to the second scanning signal line; The plurality of second scanning signal lines include a third scanning line and a fourth scanning line; the third scanning line includes at least two third extension portions and a third surrounding portion connecting adjacent third extension portions; the third surrounding portion surrounds a portion of the contour of the via hole; the extension direction of the fourth scanning line is the same as the extension direction of the third extension portion.

9. The display panel according to claim 8, wherein: The plurality of sub-pixels are divided into a plurality of rows; the plurality of second scanning signal lines are divided into a plurality of second scanning signal line groups; each second scanning signal line group includes at least two adjacent second scanning signal lines; different second scanning signal lines are electrically connected to the sub-pixels in different rows; For any second scanning signal line group, first ends of the second scanning signal lines are electrically connected to each other, and second ends of the second scanning signal lines are electrically connected to each other; An output end of the second gate driving circuit is electrically connected to a first end of each second scanning signal line in a group of second scanning signal lines.

10. The display panel according to claim 7, wherein: The non-display area includes a first sub-frame area and a second sub-frame area arranged opposite to each other along a first direction; the display panel further includes two third gate driving circuits respectively located in the first sub-frame area and the second sub-frame area; the two third gate driving circuits arranged opposite to each other along the first direction are electrically connected via one third scanning signal line; the plurality of sub-pixels are divided into a plurality of rows; one third scanning signal line is electrically connected to the sub-pixels in one row; The plurality of third scan signal lines include a fifth scan line and a sixth scan line; the fifth scan line includes at least two fourth extension portions and a fourth surrounding portion connecting adjacent fourth extension portions; the fourth surrounding portion surrounds a portion of the contour of the via hole; the extension direction of the sixth scan line is the same as the extension direction of the fourth extension portion.

11. The display panel according to claim 7, wherein: The non-display area includes a first sub-frame area and a second sub-frame area arranged opposite to each other along a first direction; the display panel further includes a fourth gate driving circuit located in the second sub-frame area; the fourth gate driving circuit is electrically connected to the fourth scan signal line; The plurality of fourth scan signal lines include a seventh scan line; the seventh scan line includes at least two fifth extensions and a fifth surrounding portion connecting adjacent fifth extensions; the fifth surrounding portion surrounds a portion of the contour of the via hole; The plurality of seventh scan lines are divided into a plurality of third scan signal line groups; each of the third scan signal line groups includes at least two adjacent seventh scan lines; the plurality of sub-pixels are divided into a plurality of rows; different seventh scan lines are electrically connected to sub-pixels in different rows; for any third scan signal line group, the fifth surrounding portions of the seventh scan lines are shared, the first ends of the fifth extension portions of the seventh scan lines are electrically connected to each other, and the second ends of the fifth extension portions of the seventh scan lines are electrically connected to each other; An output end of the fourth gate driving circuit is electrically connected to one end of each of the seventh scanning lines in a group of the third scanning signal lines.

12. The display panel according to claim 11, wherein: The plurality of fourth scan signal lines further include an eighth scan line; the plurality of eighth scan lines are divided into a plurality of fourth scan signal line groups; each of the fourth scan signal line groups includes at least two adjacent eighth scan lines; different eighth scan lines are electrically connected to different rows of sub-pixels; For any of the fourth scan signal line groups, first ends of the eighth scan lines are electrically connected to each other, and second ends of the eighth scan lines are electrically connected to each other; An output end of the fourth gate driving circuit is electrically connected to the first end of each of the eighth scan lines in a group of the fourth scan signal lines.

13. The display panel according to claim 7, wherein: The non-display area includes a first sub-frame area and a second sub-frame area arranged opposite to each other along a first direction; the display panel further includes a fifth gate driving circuit located in the second sub-frame area; the fifth gate driving circuit is electrically connected to the fifth scan signal line; The plurality of fifth scan signal lines include a ninth scan line; the ninth scan line includes at least two sixth extensions and a sixth surrounding portion connecting adjacent sixth extensions; the sixth surrounding portion surrounds a portion of the contour of the via hole; The plurality of ninth scan lines are divided into a plurality of fifth scan signal line groups; each of the fifth scan signal line groups includes at least two adjacent ninth scan lines; the plurality of sub-pixels are divided into a plurality of rows; different ninth scan lines are electrically connected to sub-pixels in different rows; for any fifth scan signal line group, the sixth surrounding portions of the ninth scan lines are shared, the first ends of the sixth extension portions of the ninth scan lines are electrically connected to each other, and the second ends of the sixth extension portions of the ninth scan lines are electrically connected to each other; An output end of the fifth gate driving circuit is electrically connected to one end of each of the ninth scanning lines in a group of the fifth scanning signal lines.

14. The display panel according to claim 13, wherein: The plurality of fifth scan signal lines further include a tenth scan line; the plurality of tenth scan lines are divided into a plurality of sixth scan signal line groups; each of the sixth scan signal line groups includes at least two adjacent tenth scan lines; different tenth scan lines are electrically connected to different rows of sub-pixels; For any of the sixth scan signal line groups, first ends of the tenth scan lines are electrically connected to each other, and second ends of the tenth scan lines are electrically connected to each other; An output end of the fifth gate driving circuit is electrically connected to the first end of each of the tenth scan lines in a group of the sixth scan signal lines.

15. The display panel according to claim 7, wherein: The display panel comprises a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer which are sequentially arranged in a direction away from the base substrate; The first sub-scan line is located in the third conductive layer; the second sub-scan line is located in the fourth conductive layer; the second scan signal line is located in the first conductive layer; the third scan signal line is located in the second conductive layer; the fourth scan signal line and the fifth scan signal line are both located in the fifth conductive layer.

16. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 15.

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