Power protection circuit

Abstract

The present application proposes a power supply protection circuit, which is applied to the field of power supply output protection technology. The power supply protection circuit includes a filter circuit, a load switch, a voltage monitoring circuit, a load switch control circuit, a voltage difference monitoring circuit and an abnormal response circuit; the filter circuit filters the input power supply to stabilize the output voltage, reduce output noise and conducted interference, monitors the input voltage through the voltage monitoring circuit, and quickly detects abnormalities when a short circuit or negative voltage surge occurs through the voltage difference monitoring circuit and transmits them to the abnormal response circuit; the load switch control circuit controls the opening and closing of the load switch according to the outputs of the voltage monitoring circuit and the abnormal response circuit. Thus, through the coordinated cooperation and rapid signal transmission of each circuit module, fast-response power supply short circuit and negative voltage surge protection is achieved at a relatively low cost, and self-recovery can be quickly completed after the negative voltage surge or short circuit disappears.

Description

Technical Field

[0001] The present application relates to the technical field of power supply output protection, and in particular to a power supply protection circuit. Background Art

[0002] In the power supply system, short circuits and negative voltage surges will affect circuit operation, and in severe cases will directly cause damage to circuit components.

[0003] Currently, there are two main types of power supply protection solutions. The first is an EFUSE (electronic fuse) or LOADSWITCH chip that integrates a MOS tube (Metal Oxide Semiconductor Field Effect Transistor), which shuts down the circuit through current detection and logic control. However, these solutions rely on high-cost integrated circuits and are difficult to meet low-cost design requirements. The second is a resettable fuse based on a PPTC (Polymeric Positive Temperature Coefficient) that limits overcurrent by utilizing the property that the material's resistance increases with temperature. However, its response speed is limited by thermal inertia, resulting in a long response time.

[0004] In summary, how to achieve fast-response power supply short circuit and negative voltage surge protection at a lower cost has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The present application proposes a power protection circuit, which aims to achieve fast response power short circuit and negative voltage surge protection at a relatively low cost.

[0006] To achieve the above objectives, the present application proposes a power supply protection circuit, which includes a filter circuit, a load switch, a voltage monitoring circuit, a load switch control circuit, a voltage difference monitoring circuit, and an abnormal response circuit;

[0007] The first end of the filter circuit is connected to the first power output end, and the second end of the filter circuit is connected to the first end of the load switch control circuit and the second power output end respectively;

[0008] The source of the load switch is connected to the second power supply output terminal, the drain of the load switch is connected to the third power supply output terminal, and the gate of the load switch is connected to the second terminal of the load switch control circuit;

[0009] A first terminal of the voltage monitoring circuit is connected to the second power supply output terminal, and a second terminal of the voltage monitoring circuit is connected to a third terminal of the load switch control circuit;

[0010] A first end of the voltage difference monitoring circuit is connected to the first power supply output end, a second end of the voltage difference monitoring circuit is connected to the second power supply output end, and a third end of the voltage difference monitoring circuit is connected to the first end of the abnormality response circuit;

[0011] The second end of the abnormal response circuit is connected to the second power supply output end, and the third end of the abnormal response circuit is connected to the second end of the load switch control circuit.

[0012] In one embodiment, the filter circuit includes a first liquid electrolytic capacitor, an inductor, and a second liquid electrolytic capacitor;

[0013] The first end of the first liquid electrolytic capacitor and the first end of the inductor serve together as the first end of the filter circuit, and the first end of the second liquid electrolytic capacitor and the second end of the inductor serve together as the second end of the filter circuit;

[0014] The second end of the first liquid electrolytic capacitor and the second end of the second liquid electrolytic capacitor are grounded.

[0015] In one embodiment, the load switch control circuit includes a first resistor, a first capacitor, a first field effect transistor, and a fourth resistor;

[0016] The first end of the first resistor and the first end of the first capacitor jointly serve as the first end of the load switch control circuit; the second end of the first resistor, the second end of the first capacitor, and the first end of the fourth resistor jointly serve as the second end of the load switch control circuit; and the gate of the first field effect transistor serves as the third end of the load switch control circuit;

[0017] The drain of the first field effect transistor is connected to the second end of the fourth resistor, and the source of the first field effect transistor is grounded.

[0018] In one embodiment, the voltage monitoring circuit includes a voltage sampling circuit and a voltage monitoring reset chip;

[0019] A first pin of the voltage monitoring reset chip is grounded, and a second pin of the voltage monitoring reset chip serves as a second end of the voltage monitoring circuit;

[0020] The first end of the voltage sampling circuit serves as the first end of the voltage monitoring circuit, and the second end of the voltage sampling circuit is connected to the third pin of the voltage monitoring reset chip.

[0021] In one embodiment, the voltage sampling circuit includes a second resistor, a third resistor and a second capacitor;

[0022] The first end of the second resistor serves as the first end of the voltage sampling circuit, the second end of the second resistor, the first end of the third resistor, and the first end of the second capacitor collectively serve as the second end of the voltage sampling circuit, and the second end of the third resistor and the second end of the second capacitor are commonly grounded.

[0023] In one embodiment, the power protection circuit further includes a second field effect transistor, the gate of the second field effect transistor is connected to the third end of the voltage difference monitoring circuit, the drain of the second field effect transistor is connected to the second end of the voltage sampling circuit, and the source of the second field effect transistor is grounded.

[0024] In one embodiment, the voltage difference monitoring circuit includes a fifth resistor, a first transistor, a sixth resistor, and a seventh resistor, wherein the emitter of the first transistor serves as the first end of the voltage difference monitoring circuit, and the first end of the fifth resistor serves as the second end of the voltage difference monitoring circuit;

[0025] The base of the first transistor is connected to the second end of the fifth resistor, and the collector of the first transistor is connected to the first end of the sixth resistor;

[0026] The second end of the sixth resistor is connected to the first end of the seventh resistor, the second end of the seventh resistor is grounded, and the second end of the sixth resistor and the first end of the seventh resistor together serve as the third end of the voltage difference monitoring circuit.

[0027] In one embodiment, the abnormal response circuit includes a third field effect transistor, an eighth resistor, and a second transistor, the gate of the third field effect transistor serves as the first end of the abnormal response circuit, the emitter of the second transistor serves as the second end of the abnormal response circuit, and the collector of the second transistor serves as the third end of the abnormal response circuit;

[0028] A first end of the eighth resistor is connected to the drain of the third field effect transistor, a second end of the eighth resistor is connected to the base of the second transistor, and a source of the third field effect transistor is grounded.

[0029] In one embodiment, the second terminal of the voltage sampling circuit and the third terminal of the voltage monitoring and reset chip are connected to ground through a ninth resistor.

[0030] In one embodiment, the load switch is a PMOS tube (positive Metal-Oxide-Semiconductor Field-Effect Transistor), and the first field-effect transistor, the second field-effect transistor, and the third field-effect transistor are NMOS tubes (N-Metal-Oxide-Semiconductor Field-Effect Transistor).

[0031] The power protection circuit proposed in the present application includes a filter circuit, a load switch, a voltage monitoring circuit, a load switch control circuit, a voltage difference monitoring circuit and an abnormal response circuit; the first end of the filter circuit is connected to the first power output end, and the second end of the filter circuit is connected to the first end and the second power output end of the load switch control circuit respectively; the source of the load switch is connected to the second power output end, the drain of the load switch is connected to the third power output end, and the gate of the load switch is connected to the second end of the load switch control circuit; the first end of the voltage monitoring circuit is connected to the second power output end, and the second end of the voltage monitoring circuit is connected to the third end of the load switch control circuit; the first end of the voltage difference monitoring circuit is connected to the first power output end, the second end of the voltage difference monitoring circuit is connected to the second power output end, and the third end of the voltage difference monitoring circuit is connected to the first end of the abnormal response circuit; the second end of the abnormal response circuit is connected to the second power output end, and the third end of the abnormal response circuit is connected to the second end of the load switch control circuit.

[0032] The power protection circuit proposed in the present application filters the input power supply through a filtering circuit to stabilize the output voltage, reduce output noise and conducted interference, monitors the input voltage through a voltage monitoring circuit, and quickly detects the abnormality when a short circuit or negative voltage surge occurs through a voltage difference monitoring circuit and transmits it to the abnormal response circuit. The load switch control circuit controls the opening and closing of the load switch according to the output of the voltage monitoring circuit and the abnormal response circuit. Thus, through the coordinated cooperation and rapid signal transmission of each circuit module, fast-response power short circuit and negative voltage surge protection is achieved at a relatively low cost. Moreover, after the negative voltage surge or short circuit disappears, the second power supply output end can quickly return to normal voltage, and the voltage monitoring circuit will drive the load switch to turn on, thereby enabling rapid self-recovery. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0034] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0035] Figure 1 This is a circuit connection diagram of an embodiment of the power protection circuit of the present application;

[0036] Figure 2 This is another circuit diagram of an embodiment of the power protection circuit of the present application.

[0037] Figures 1 to 2 Description of Figure Numbers:

[0038]

[0039] The purpose, features and advantages of this application will be further explained with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0040] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0041] In the power supply system, short circuits and negative voltage surges will affect circuit operation, and in severe cases will directly cause damage to circuit components.

[0042] Currently, there are two main types of power supply protection solutions. The first is an EFUSE or LOADSWITCH chip with integrated MOS tubes, which shuts down the circuit through current detection and logic control. However, such solutions rely on high-cost integrated circuits and are difficult to meet low-cost design requirements. The second is a PPTC-based resettable fuse, which uses the characteristic that the material resistance increases with temperature to limit overcurrent. However, its response speed is limited by thermal inertia, resulting in a long response time.

[0043] In summary, how to achieve fast-response power supply short circuit and negative voltage surge protection at a lower cost has become a technical problem that urgently needs to be solved in this field.

[0044] The embodiment of the present application provides a solution, and proposes a power protection circuit, such as Figure 1As shown, the power protection circuit includes a filter circuit 10, a load switch Q1, a voltage monitoring circuit 20, a load switch control circuit 30, a voltage difference monitoring circuit 40 and an abnormal response circuit 50; the first end of the filter circuit 10 is connected to the first power output terminal VCCOUT, and the second end of the filter circuit 10 is connected to the first end and the second power output terminal VCCOUT_FLT of the load switch control circuit 30 respectively; the source S of the load switch Q1 is connected to the second power output terminal VCCOUT_FLT, the drain D of the load switch Q1 is connected to the third power output terminal VCCOUT_C, and the gate G of the load switch Q1 is connected to the second end of the load switch control circuit 30; A first end of the voltage monitoring circuit 20 is connected to the second power supply output terminal VCCOUT_FLT, and a second end of the voltage monitoring circuit 20 is connected to a third end of the load switch control circuit 30; a first end of the voltage difference monitoring circuit 40 is connected to the first power supply output terminal VCCOUT, a second end of the voltage difference monitoring circuit 40 is connected to the second power supply output terminal VCCOUT_FLT, and a third end of the voltage difference monitoring circuit 40 is connected to a first end of the abnormal response circuit 50; a second end of the abnormal response circuit 50 is connected to the second power supply output terminal VCCOUT_FLT, and a third end of the abnormal response circuit 50 is connected to a second end of the load switch control circuit 30.

[0045] In summary, the power protection circuit proposed in the embodiment of the present application filters the input power supply through the filter circuit 10 to stabilize the output voltage, reduce output noise and conducted interference, monitors the input voltage through the voltage monitoring circuit 20, and quickly detects the abnormality when a short circuit or negative voltage surge occurs through the voltage difference monitoring circuit 40 and transmits it to the abnormal response circuit 50. The load switch control circuit 30 controls the opening and closing of the load switch Q1 according to the output of the voltage monitoring circuit 20 and the abnormal response circuit 50. Thus, through the coordinated cooperation and rapid signal transmission of each circuit module, fast-response power supply short circuit and negative voltage surge protection is achieved at a relatively low cost. Moreover, after the negative voltage surge or short circuit disappears, the second power supply output end can quickly return to normal voltage, and the voltage monitoring circuit will drive the load switch to turn on, thereby enabling rapid self-recovery.

[0046] The following will clearly and completely describe the technical solutions in the embodiments of this application in conjunction with the accompanying drawings. If there are descriptions of "first" or "second" in the embodiments of this application, the descriptions of "first" or "second" are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly specifying the number of the indicated technical features. Therefore, the features specified as "first" or "second" may explicitly or implicitly include at least one of such features.

[0047] This embodiment provides a power protection circuit, aiming to achieve fast-response power short circuit and negative voltage surge protection at a relatively low cost.

[0048] Please refer to Figure 1 , Figure 1 This is a circuit diagram of the first embodiment of the power protection circuit of the present application.

[0049] In this embodiment, the power protection circuit includes a filter circuit 10, a load switch Q1, a voltage monitoring circuit 20, a load switch control circuit 30, a voltage difference monitoring circuit 40 and an abnormal response circuit 50;

[0050] The first end of the filter circuit 10 is connected to the first power output terminal VCCOUT, and the second end of the filter circuit 10 is connected to the first end of the load switch control circuit 30 and the second power output terminal VCCOUT_FLT respectively;

[0051] In this embodiment, the filter circuit 10 may be a π-type filter circuit for stabilizing the output voltage and reducing output noise and conducted interference.

[0052] The source S of the load switch Q1 is connected to the second power output terminal VCCOUT_FLT, the drain D of the load switch Q1 is connected to the third power output terminal VCCOUT_C, and the gate G of the load switch Q1 is connected to the second terminal of the load switch control circuit 30;

[0053] In this embodiment, the load switch Q1 acts as a switch for power output, and determines whether to provide power to the load according to a signal from the load switch control circuit 30 .

[0054] In a feasible implementation, the load switch Q1 can be Figure 2 Specifically, pins 1, 2, and 3 of the load switch Q1 together form the source S of the load switch Q1, pin 4 of the load switch Q1 forms the gate G of the load switch Q1, and pins 5, 6, 7, and 8 of the load switch Q1 together form the drain D of the load switch Q1.

[0055] A first terminal of the voltage monitoring circuit 20 is connected to the second power supply output terminal VCCOUT_FLT, and a second terminal of the voltage monitoring circuit 20 is connected to a third terminal of the load switch control circuit 30;

[0056] In this embodiment, the voltage monitoring circuit 20 is configured to detect the power voltage of the second power output terminal VCCOUT_FLT and transmit the detected voltage information to the load switch control circuit 30 .

[0057] A first terminal of the voltage difference monitoring circuit 40 is connected to the first power output terminal VCCOUT, a second terminal of the voltage difference monitoring circuit 40 is connected to the second power output terminal VCCOUT_FLT, and a third terminal of the voltage difference monitoring circuit 40 is connected to the first terminal of the abnormal response circuit 50;

[0058] In this embodiment, the voltage difference monitoring circuit 40 detects the voltage difference between the first power output terminal VCCOUT and the second power output terminal VCCOUT_FLT, and transmits the detected voltage difference information to the abnormal response circuit 50. When the circuit is operating normally, the voltage difference monitoring circuit 40 outputs a low level by default, and outputs a high level when an instantaneous voltage difference between the first power output terminal VCCOUT and the second power output terminal VCCOUT_FLT is caused by a short circuit or a negative voltage surge.

[0059] A second terminal of the abnormal response circuit 50 is connected to the second power output terminal VCCOUT_FLT, and a third terminal of the abnormal response circuit 50 is connected to the second terminal of the load switch control circuit 30 .

[0060] In this embodiment, when the voltage difference monitoring circuit 40 detects an abnormality (such as a short circuit or a negative voltage surge), the abnormal response circuit 50 can quickly reduce the gate-source GS voltage difference of the load switch Q1 through the load switch control circuit 30, causing the load switch Q1 to be instantly turned off, thereby cutting off the power output.

[0061] In a possible embodiment, Figure 2 As shown, the filter circuit 10 includes a first liquid electrolytic capacitor EC1, an inductor L1 and a second liquid electrolytic capacitor EC2;

[0062] The first end of the first liquid electrolytic capacitor EC1 and the first end of the inductor L1 serve together as the first end of the filter circuit 10, and the first end of the second liquid electrolytic capacitor EC2 and the second end of the inductor L1 serve together as the second end of the filter circuit 10;

[0063] A second end of the first liquid electrolytic capacitor EC1 and a second end of the second liquid electrolytic capacitor EC2 are grounded.

[0064] In this embodiment, the first end of the first liquid electrolytic capacitor EC1 and the first end of the inductor L1 are connected to the first power output terminal VCCOUT, and the first end of the second liquid electrolytic capacitor EC2 and the second end of the inductor L1 are connected to the first end of the load switch control circuit 30 and the second power output terminal VCCOUT_FLT.

[0065] Filter circuit 10 consists of two liquid electrolytic capacitors (EC1 and EC2) and an inductor (L1). It uses the filtering characteristics of the capacitors and the energy storage characteristics of the inductor to filter the input power supply to reduce output noise and conduction interference, ensure the stability and purity of the power supply output, provide a stable power supply for subsequent circuits, and avoid false triggering or other problems caused by power supply noise or ripple.

[0066] In addition, it is worth mentioning that the equivalent series resistance (ESR) of liquid electrolytic capacitors is generally regarded as a disadvantage in the prior art because it causes additional energy loss, but this characteristic is not effectively utilized to build a protection mechanism. In this embodiment, the ESR of the liquid electrolytic capacitor is used as a means of checking the output current to achieve short-circuit protection and negative voltage surge protection.

[0067] In a possible embodiment, Figure 2 As shown, the load switch control circuit 30 includes a first resistor R1, a first capacitor C1, a first field effect transistor Q2 and a fourth resistor R4;

[0068] The first end of the first resistor R1 and the first end of the first capacitor C1 together serve as the first end of the load switch control circuit 30; the second end of the first resistor R1, the second end of the first capacitor C1, and the first end of the fourth resistor R4 together serve as the second end of the load switch control circuit 30; and the gate G of the first field effect transistor Q2 serves as the third end of the load switch control circuit 30;

[0069] A drain D of the first field effect transistor Q2 is connected to the second end of the fourth resistor R4 , and a source S of the first field effect transistor Q2 is grounded.

[0070] In this embodiment, the first end of the first resistor R1 and the first end of the first capacitor C1 are connected to the second end of the filter circuit 10, the second end of the first resistor R1, the second end of the first capacitor C1, and the first end of the fourth resistor R4 are connected to the gate G of the load switch Q1, and the gate G of the first field effect transistor Q2 is connected to the second end of the voltage monitoring circuit 20. Figure 2 The PG_VCCOUT labeled in the figure represents a power good indicator signal used to monitor or indicate whether the power supply output is stable.

[0071] When the voltage monitoring circuit 20 outputs a high level, the first field-effect transistor Q2 turns on. At this point, the voltage output from the second power output terminal VCCOUT_FLT, after being divided by the first resistor R1 and the fourth resistor R4, creates a voltage difference between the gate-source electrode GS of the load switch Q1. This turns on the load switch Q1, and power is output to the third power output terminal VCCOUT_C. When the voltage monitoring circuit 20 outputs a low level, the first field-effect transistor Q2 turns off, and there is no voltage difference between the gate-source electrode GS of the load switch Q1. The load switch Q1 turns off, and the power output is cut off.

[0072] It is worth mentioning that the first capacitor C1 acts as a slow-start capacitor, which can prevent the impact of instantaneous large current on the power supply and load, thereby preventing the power supply voltage from being instantly pulled down or erroneously triggering the overcurrent protection.

[0073] In a possible embodiment, Figure 2 As shown, the voltage monitoring circuit 20 includes a voltage sampling circuit and a voltage monitoring reset chip U1;

[0074] The first pin of the voltage monitoring reset chip U1 is grounded, and the second pin of the voltage monitoring reset chip U1 serves as the second end of the voltage monitoring circuit 20;

[0075] The first end of the voltage sampling circuit serves as the first end of the voltage monitoring circuit 20 , and the second end of the voltage sampling circuit is connected to the third pin of the voltage monitoring reset chip U1 .

[0076] In this embodiment, the first pin GND of the voltage monitoring reset chip U1 is grounded. Figure 2 The monitor chip is marked as Monitor IC. The second pin RST# of the voltage monitoring reset chip U1 is connected to the third end of the load switch control circuit 30. The first end of the voltage sampling circuit is connected to the second power supply output end VCCOUT_FLT. The second end of the voltage sampling circuit is connected to the third pin VDD of the voltage monitoring reset chip U1.

[0077] The voltage monitoring circuit 20 samples and monitors the voltage of the second power supply output terminal VCCOUT_FLT. Specifically, the voltage sampling circuit samples the voltage of the second power supply output terminal VCCOUT_FLT, and the voltage monitoring reset chip U1 determines whether the power supply voltage is normal based on the sampled voltage signal. When the sampled voltage is higher than the set threshold, the second pin RST# of the voltage monitoring reset chip U1 outputs a high level; when the sampled voltage is lower than the set threshold, the second pin RST# of the voltage monitoring reset chip U1 outputs a low level. The output signal of the second pin RST# is transmitted to the load switch control circuit 30 for controlling the on and off of the load switch Q1 to ensure the stability of the power supply output.

[0078] For example, when the threshold is set to 90% of the rated voltage, the voltage monitoring reset chip U1 monitors the input voltage. When the input voltage is higher than 90% of the rated voltage, after a period of delay, the RST# of the voltage monitoring reset chip U1 will be pulled high, otherwise the output will be pulled low.

[0079] In a possible embodiment, Figure 2 As shown, the voltage sampling circuit includes a second resistor R2, a third resistor R3 and a second capacitor C2;

[0080] The first end of the second resistor R2 serves as the first end of the voltage sampling circuit, the second end of the second resistor R2, the first end of the third resistor R3, and the first end of the second capacitor C2 collectively serve as the second end of the voltage sampling circuit, and the second end of the third resistor R3 and the second end of the second capacitor C2 are commonly grounded.

[0081] In this embodiment, the first end of the second resistor R2 is connected to the second power output terminal VCCOUT_FLT, and the second end of the second resistor R2, the first end of the third resistor R3 and the first end of the second capacitor C2 are connected to the third pin of the voltage monitoring reset chip U1.

[0082] The voltage sampling circuit divides and samples the voltage at the second power supply output terminal VCCOUT_FLT. Through the voltage dividing effect of the second resistor R2 and the third resistor R3, the higher power supply voltage is reduced to a voltage range suitable for processing by the voltage monitoring reset chip U1. The second capacitor C2 is used to filter out high-frequency noise in the sampled voltage to ensure the stability of the sampled signal.

[0083] In a possible embodiment, Figure 2 As shown, the power protection circuit further includes a second field effect transistor Q6, the gate G of the second field effect transistor Q6 is connected to the third end of the voltage difference monitoring circuit 40, the drain D of the second field effect transistor Q6 is connected to the second end of the voltage sampling circuit, and the source S of the second field effect transistor Q6 is grounded.

[0084] In this embodiment, under normal operating conditions, the second field-effect transistor Q6 is in a closed state, and the sampled voltage of the voltage sampling circuit is normally transmitted to the third pin VDD of the voltage monitoring reset chip U1. When the voltage difference monitoring circuit 40 detects a short circuit or a negative voltage surge, it outputs a high-level signal to the gate G of the second field-effect transistor Q6, turning on the second field-effect transistor Q6. After the second field-effect transistor Q6 is turned on, the path between its drain D and source S quickly discharges the sampled voltage of the voltage sampling circuit to ground, thereby rapidly reducing the voltage at the input end of the voltage monitoring reset chip U1. Figure 2The VIN_M labeled in the middle represents the middle voltage input (Middle Voltage Input) of the drain D of the second FET Q6, which provides the operating voltage for the voltage monitoring reset chip U1. Then, the second pin RST# of the voltage monitoring reset chip U1 is quickly pulled low, causing the first FET Q2 in the load switch control circuit 30 to turn off. After the first FET Q2 turns off, there is no voltage difference between the gate-source GS of the load switch Q1, and the load switch Q1 turns off, thereby cutting off the power output. This effectively prevents damage to the power supply and load caused by short circuits or negative voltage surges, while ensuring the response speed and reliability of the power protection circuit.

[0085] In a possible embodiment, Figure 2 As shown, the voltage difference monitoring circuit 40 includes a fifth resistor R5, a first transistor Q3, a sixth resistor R6 and a seventh resistor R7, the emitter E of the first transistor Q3 serves as the first end of the voltage difference monitoring circuit 40, and the first end of the fifth resistor R5 serves as the second end of the voltage difference monitoring circuit 40;

[0086] The base B of the first transistor Q3 is connected to the second end of the fifth resistor R5, and the collector C of the first transistor Q3 is connected to the first end of the sixth resistor R6;

[0087] The second end of the sixth resistor R6 is connected to the first end of the seventh resistor R7 , the second end of the seventh resistor R7 is grounded, and the second end of the sixth resistor R6 and the first end of the seventh resistor R7 together serve as the third end of the voltage difference monitoring circuit 40 .

[0088] In this embodiment, the emitter E of the first transistor Q3 is connected to the first power output terminal VCCOUT, the first end of the fifth resistor R5 is connected to the second power output terminal VCCOUT_FLT, and the second end of the sixth resistor R6 and the first end of the seventh resistor R7 are connected to the first end of the abnormal response circuit 50.

[0089] Under normal operating conditions, the voltage difference across the inductor L1 is very small, and the voltage at the base B of the first transistor Q3 is insufficient to turn it on. Therefore, the first transistor Q3 is in the off state, and the node between the sixth resistor R6 and the seventh resistor R7 outputs a low level. When a short circuit or a negative voltage surge occurs, a transient voltage difference is generated across the inductor L1. This voltage difference is transmitted to the base B of the first transistor Q3 through the fifth resistor R5, causing the voltage at the base B of the first transistor Q3 to increase. When the voltage at the base B reaches the turn-on threshold of the first transistor Q3, the first transistor Q3 turns on, and current from its collector C flows through the sixth resistor R6 to the seventh resistor R7, generating a high-level signal at the node between the sixth resistor R6 and the seventh resistor R7. The signal output by the third terminal of the voltage difference monitoring circuit 40 (i.e., the node between the sixth resistor R6 and the seventh resistor R7) is used to trigger the abnormal response circuit 50, thereby achieving the effect of outputting a high-level signal when a short circuit or a negative voltage surge is detected, notifying the abnormal response circuit 50 to take protective measures.

[0090] In a possible embodiment, Figure 2 As shown, the abnormal response circuit 50 includes a third field effect transistor Q4, an eighth resistor R8 and a second transistor Q5, the gate G of the third field effect transistor Q4 serves as the first end of the abnormal response circuit 50, the emitter E of the second transistor Q5 serves as the second end of the abnormal response circuit 50, and the collector C of the second transistor Q5 serves as the third end of the abnormal response circuit 50;

[0091] A first end of the eighth resistor R8 is connected to the drain D of the third field effect transistor Q4 , a second end of the eighth resistor R8 is connected to the base B of the second transistor Q5 , and a source S of the third field effect transistor Q4 is grounded.

[0092] In this embodiment, the gate G of the third field effect transistor Q4 is connected to the third terminal of the voltage difference monitoring circuit 40, the emitter E of the second transistor Q5 is connected to the second power input terminal, and the collector C of the second transistor Q5 is connected to the second terminal of the load switch control circuit 30. Figure 2 VG marked in the figure represents the gate voltage that controls the on and off of the load switch Q1.

[0093] Under normal operating conditions, the output of the voltage difference monitoring circuit 40 is low, the gate G of the third field-effect transistor Q4 is low, and the third field-effect transistor Q4 is off. No current flows through the eighth resistor R8, and the voltage at the base B of the second transistor Q5 is insufficient to turn it on, so the second transistor Q5 is also off. When the voltage difference monitoring circuit 40 detects a short circuit or a negative voltage surge, it outputs a high-level signal to the gate G of the third field-effect transistor Q4, turning it on. After the third field-effect transistor Q4 turns on, current flows through the eighth resistor R8 to the base B of the second transistor Q5, turning it on. After the second transistor Q5 turns on, the path between its collector C and emitter E connects the gate G and source S of the load switch Q1, rapidly reducing the voltage difference between the gate and source GS of the load switch Q1, causing the load switch Q1 to quickly turn off, cutting off the power output and achieving a rapid protection function.

[0094] In a possible embodiment, Figure 2 As shown, the second end of the voltage sampling circuit and the third end of the voltage monitoring reset chip U1 are connected to the ground through a ninth resistor R9.

[0095] In this embodiment, the function of the ninth resistor R9 is to provide a stable ground reference level for the input terminal of the voltage monitoring reset chip U1, and at the same time prevent the input terminal from being suspended, so as to prevent the G pole of the first field effect transistor Q2 from being suspended uncontrollably and causing abnormal operation when the voltage monitoring reset chip U1 is not powered.

[0096] In a feasible embodiment, the load switch Q1 is a PMOS transistor, and the first field effect transistor Q2, the second field effect transistor Q6, and the third field effect transistor Q4 are NMOS transistors.

[0097] In this embodiment, the load switch Q1 is a PMOS transistor, used to control the on / off of the power output. The first field-effect transistor Q2, the second field-effect transistor Q6, and the third field-effect transistor Q4 are all NMOS transistors. The first field-effect transistor Q2 controls the gate G voltage of the load switch Q1 based on the output signal of the voltage monitoring reset chip U1, thereby achieving on / off control of the load switch Q1. The second field-effect transistor Q6 is triggered in abnormal conditions (such as a short circuit or a negative voltage surge) to quickly discharge the voltage at the input terminal of the voltage monitoring reset chip U1, ensuring that the voltage monitoring reset chip U1 can quickly respond and cut off the power output. The third field-effect transistor Q4 receives the output signal of the voltage difference monitoring circuit 40 and controls the conduction state of the second transistor Q5, thereby achieving rapid shutdown of the load switch Q1.

[0098] In summary, in this embodiment, the input power is filtered by the filter circuit 10 to stabilize the output voltage, reduce output noise and conducted interference, the input voltage is monitored by the voltage monitoring circuit 20, and the abnormality is quickly detected by the voltage difference monitoring circuit 40 when a short circuit or negative voltage surge occurs and transmitted to the abnormality response circuit 50. The load switch control circuit 30 controls the opening and closing of the load switch Q1 based on the outputs of the voltage monitoring circuit 20 and the abnormality response circuit 50. Thus, through the coordinated cooperation and rapid signal transmission of various circuit modules, fast-response power supply short circuit and negative voltage surge protection is achieved at a relatively low cost. Moreover, after the negative voltage surge or short circuit disappears, the second power supply output terminal VCCOUT_FLT can quickly return to normal voltage, and the voltage monitoring circuit 20 will output a high level to drive the load switch Q1 to turn on, thereby enabling rapid self-recovery.

[0099] The above are merely optional embodiments of the present application and do not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application specification and drawings under the application concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A power protection circuit, characterized in that: The power protection circuit includes a filter circuit, a load switch, a voltage monitoring circuit, a load switch control circuit, a voltage difference monitoring circuit and an abnormal response circuit; The first end of the filter circuit is connected to the first power output end, and the second end of the filter circuit is connected to the first end of the load switch control circuit and the second power output end respectively; The source of the load switch is connected to the second power supply output terminal, the drain of the load switch is connected to the third power supply output terminal, and the gate of the load switch is connected to the second terminal of the load switch control circuit; A first terminal of the voltage monitoring circuit is connected to the second power supply output terminal, and a second terminal of the voltage monitoring circuit is connected to a third terminal of the load switch control circuit; A first end of the voltage difference monitoring circuit is connected to the first power supply output end, a second end of the voltage difference monitoring circuit is connected to the second power supply output end, and a third end of the voltage difference monitoring circuit is connected to the first end of the abnormality response circuit; The second end of the abnormal response circuit is connected to the second power supply output end, and the third end of the abnormal response circuit is connected to the second end of the load switch control circuit; The voltage difference monitoring circuit includes a fifth resistor, a first transistor, a sixth resistor and a seventh resistor, the emitter of the first transistor serves as the first end of the voltage difference monitoring circuit, and the first end of the fifth resistor serves as the second end of the voltage difference monitoring circuit; The base of the first transistor is connected to the second end of the fifth resistor, and the collector of the first transistor is connected to the first end of the sixth resistor; The second end of the sixth resistor is connected to the first end of the seventh resistor, the second end of the seventh resistor is grounded, and the second end of the sixth resistor and the first end of the seventh resistor together serve as the third end of the voltage difference monitoring circuit; The abnormal response circuit includes a third field effect transistor, an eighth resistor and a second transistor, the gate of the third field effect transistor serves as the first end of the abnormal response circuit, the emitter of the second transistor serves as the second end of the abnormal response circuit, and the collector of the second transistor serves as the third end of the abnormal response circuit; A first end of the eighth resistor is connected to the drain of the third field effect transistor, a second end of the eighth resistor is connected to the base of the second transistor, and a source of the third field effect transistor is grounded.

2. The power protection circuit according to claim 1, wherein: The filter circuit includes a first liquid electrolytic capacitor, an inductor and a second liquid electrolytic capacitor; The first end of the first liquid electrolytic capacitor and the first end of the inductor serve together as the first end of the filter circuit, and the first end of the second liquid electrolytic capacitor and the second end of the inductor serve together as the second end of the filter circuit; The second end of the first liquid electrolytic capacitor and the second end of the second liquid electrolytic capacitor are grounded.

3. The power protection circuit according to claim 1, wherein: The load switch control circuit includes a first resistor, a first capacitor, a first field effect transistor and a fourth resistor; The first end of the first resistor and the first end of the first capacitor jointly serve as the first end of the load switch control circuit; the second end of the first resistor, the second end of the first capacitor, and the first end of the fourth resistor jointly serve as the second end of the load switch control circuit; and the gate of the first field effect transistor serves as the third end of the load switch control circuit; The drain of the first field effect transistor is connected to the second end of the fourth resistor, and the source of the first field effect transistor is grounded.

4. The power protection circuit according to claim 1, wherein: The voltage monitoring circuit includes a voltage sampling circuit and a voltage monitoring reset chip; The first pin of the voltage monitoring reset chip is grounded, and the second pin of the voltage monitoring reset chip serves as the second end of the voltage monitoring circuit; The first end of the voltage sampling circuit serves as the first end of the voltage monitoring circuit, and the second end of the voltage sampling circuit is connected to the third pin of the voltage monitoring reset chip.

5. The power protection circuit according to claim 4, wherein: The voltage sampling circuit includes a second resistor, a third resistor and a second capacitor; The first end of the second resistor serves as the first end of the voltage sampling circuit, the second end of the second resistor, the first end of the third resistor, and the first end of the second capacitor collectively serve as the second end of the voltage sampling circuit, and the second end of the third resistor and the second end of the second capacitor are commonly grounded.

6. The power protection circuit according to claim 4, wherein: The power protection circuit also includes a second field effect transistor, the gate of the second field effect transistor is connected to the third end of the voltage difference monitoring circuit, the drain of the second field effect transistor is connected to the second end of the voltage sampling circuit, and the source of the second field effect transistor is grounded.

7. The power protection circuit according to claim 4, wherein: The second end of the voltage sampling circuit and the third end of the voltage monitoring reset chip are connected to the ground through a ninth resistor.

8. The power protection circuit according to any one of claims 1 to 7, wherein: The load switch is a PMOS tube, and the first field effect tube, the second field effect tube, and the third field effect tube are NMOS tubes.

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