High-speed, low-latency, real-time signal convolution modulation method and device based on FPGA

Abstract

The present invention relates to a high-speed, low-latency, real-time signal convolution modulation method and device based on an FPGA (FGPA), belonging to the field of digital signal processing technology. The method comprises: obtaining a noise convolution kernel signal in an FPGA memory based on a random addressing code generated by a radio frequency signal; circularly shifting the noise convolution kernel signal in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and copying the radio frequency signal to obtain a radio frequency signal to be convolved; and parallel reading the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved in a pipeline manner to perform multiplication calculations, and accumulating the multiplication results to obtain a convolution modulation result. The high-speed, low-latency, real-time signal convolution modulation method based on an FPGA provided by the present invention improves the interference effect of the signal, utilizes circular convolution instead of linear convolution to save a large amount of computing time, solves the problem of long computing time, and completes real-time convolution calculations with low latency.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing technology, and in particular to a high-speed, low-latency, real-time signal convolution modulation method and device based on FPGA. Background Art

[0002] Low-latency, real-time convolution modulation of RF signals can be widely used in digital signal processing, including wireless communications, industrial automation control, radar, and electronic countermeasures systems. The RF signal band typically ranges from 3 kHz to 300 GHz, which can be divided into multiple sub-bands depending on the frequency. For example, in radar electronic countermeasures, the microwave band (3 GHz to 300 GHz) is widely used. Convolution modulation of RF radar signals can achieve effective radar jamming in electronic countermeasures. Implementing convolution modulation jamming of RF signals at high sampling rates in hardware requires real-time modulation of the high-speed RF signal through digital signal processing. After receiving the RF signal, the convolution modulation device stores it in a digital RF memory. Next, the signal modulation processing module quickly reads the stored RF signal and the noise convolution kernel signal into the convolution modulation module, modulating the signals through convolution. Finally, the convolution modulated signal undergoes power control to produce the desired RF radar convolution modulation jamming signal. To achieve this goal, the main technologies used include signal sampling and signal convolution in digital signal processing. However, convolution modulation of RF signals at high sampling rates still has certain defects and difficulties in actual application environments.

[0003] The first type is the problem that the noise signal distribution type in the convolution kernel of the noise signal involved in the convolution modulation is single, making the corresponding interference effect it produces easy to identify. Using a single convolution kernel for convolution modulation with all RF signals will make the final convolution modulation interference output easy to identify. If the noise signal convolution kernel used can be identified through signal analysis means, the effect of the modulation interference will be greatly reduced.

[0004] The second type is due to insufficient computing power of hardware devices. The convolution modulation processing of RF signals requires a lot of time and registers, making it difficult to meet the real-time requirements under high sampling rates. For convolution calculation, from the perspective of its mathematical principle, its calculation process is a process of circular shift, multiplication and addition. The linear convolution formula of discrete digital signals is as follows: The formula represents a process of shifting, multiplying, and accumulating, in which each step of the operation processing requires a CLK clock and also occupies the corresponding register resources. Summary of the Invention

[0005] In view of this, it is necessary to provide a high-speed, low-latency, real-time signal convolution modulation method and device based on FGPA to achieve the purpose of improving the interference effect and reducing the convolution modulation time.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a high-speed, low-latency, real-time signal convolution modulation method based on FPGA, comprising:

[0007] Obtaining a noise convolution kernel signal in an FPGA memory based on a random addressing code generated by a radio frequency signal; the FPGA memory is used to store convolution noise signals of various distribution types;

[0008] The noise convolution kernel signal is cyclically shifted in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and the radio frequency signal is copied to obtain a radio frequency signal to be convolved;

[0009] In a pipeline manner, the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved are read in parallel for multiplication calculation, and the multiplication calculation results are accumulated to obtain the convolution modulation result.

[0010] In one possible implementation, the cyclic shifting of the noise convolution kernel signal in a pipeline manner to obtain the noise convolution kernel signal to be convolved, and copying the RF signal to obtain the RF signal to be convolved, includes:

[0011] Inverting the highest bits of the signal points of the radio frequency signal and the noise convolution kernel signal respectively to obtain a signed target radio frequency signal and a target noise convolution kernel signal;

[0012] Circularly shifting and splicing the target noise convolution kernel signal in a parallel processing manner to obtain the noise convolution kernel signal to be convolved;

[0013] The target radio frequency signal is copied and then spliced ​​to obtain the radio frequency signal to be convolved.

[0014] In one possible implementation, the pipeline method is used to parallel read the noise convolution kernel signal to be convolved and the signal points in the RF signal to be convolved for multiplication, and accumulate the multiplication results to obtain the convolution modulation result, including:

[0015] Reading the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved in parallel based on a preset corresponding relationship to obtain an associated radio frequency signal and a convolution kernel signal;

[0016] Performing multiplication calculation on the associated radio frequency signal and the signal point in the convolution kernel signal to obtain a multiplication calculation result;

[0017] The multiplication calculation results are accumulated and concatenated to obtain a convolution modulation result.

[0018] In one possible implementation, after reading the noise convolution kernel signal to be convolved and the signal points in the RF signal to be convolved in parallel and performing multiplication calculations in a pipeline manner, and accumulating the multiplication results to obtain the convolution modulation result, the method further includes:

[0019] Based on the bit width requirement of the output signal, the bit width of the convolution modulation result is adjusted.

[0020] In a possible implementation, adjusting the bit width of the convolution modulation result based on the bit width requirement of the output signal includes:

[0021] Converting the convolution modulation result from a fixed-point number of a first bit width to a floating-point number of a second bit width;

[0022] Convert the floating-point number of the second bit width into a fixed-point number that meets the requirements.

[0023] In a possible implementation, the random addressing code generated based on the radio frequency signal, before acquiring the noise convolution kernel signal in the FPGA memory, further includes:

[0024] The random addressing code is determined based on a value of a target signal point in the radio frequency signal.

[0025] In a second aspect, the present invention further provides a high-speed, low-latency, real-time signal convolution modulation device based on FPGA, comprising:

[0026] An acquisition unit is configured to acquire a noise convolution kernel signal in an FPGA memory based on a random addressing code generated by a radio frequency signal; the FPGA memory is configured to store convolution noise signals of various distribution types;

[0027] a preprocessing unit, configured to perform a cyclic shift on the noise convolution kernel signal in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and to copy the radio frequency signal to obtain a radio frequency signal to be convolved;

[0028] The convolution modulation unit is used to read the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved in parallel in a pipeline manner to perform multiplication calculations, and accumulate the multiplication calculation results to obtain a convolution modulation result.

[0029] In a third aspect, the present invention further provides an electronic device comprising a memory and a processor, wherein:

[0030] The memory is used to store programs;

[0031] The processor is coupled to the memory and is used to execute the program stored in the memory to implement the high-speed, low-latency, real-time signal convolution modulation method based on FGPA described in any of the above implementation methods.

[0032] In a fourth aspect, the present invention also provides a computer-readable storage medium for storing computer-readable programs or instructions, which, when executed by a processor, can implement the steps of the FGPA-based high-speed, low-latency, real-time signal convolution modulation method described in any of the above-mentioned implementation methods.

[0033] The beneficial effects of the present invention are as follows: the high-speed, low-latency, real-time signal convolution modulation method and device based on FGPA provided by the present invention stores convolution noise signals of various distribution types in the FPGA memory. When a group of radio frequency signals needs to be convolved, the noise convolution kernel signal is randomly obtained in the FPGA memory according to the random addressing code, thereby increasing the richness and randomness of the noise signal, solving the problem that the noise signal type is single and easy to identify, thereby improving the interference effect of the signal, performing a circular shift on the noise convolution kernel signal to obtain the noise convolution kernel signal to be convolved, and copying the radio frequency signal to obtain the radio frequency signal to be convolved, using circular convolution instead of linear convolution to save a lot of calculation time, and performing multiplication calculation by parallel reading the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved, and accumulating the convolution modulation result with the multiplication calculation results, thereby solving the problem of long calculation time and completing real-time convolution calculation with low latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A flowchart of an embodiment of a high-speed, low-latency, real-time signal convolution modulation method based on FGPA provided by the present invention;

[0036] Figure 2 A schematic diagram of the generation and storage of multiple types of noise signals provided by the present invention;

[0037] Figure 3 The convolution modulation data preprocessing pipeline diagram provided by the present invention;

[0038] Figure 4 The dual parallel, circular convolution pipeline diagram provided by the present invention;

[0039] Figure 5The data width adjustment pipeline diagram provided by the present invention;

[0040] Figure 6 The present invention provides a low-latency, multi-random, real-time convolution implementation framework;

[0041] Figure 7 The present invention provides a low-latency, multi-random real-time convolution pipeline graph;

[0042] Figure 8 A schematic structural diagram of an embodiment of a high-speed, low-latency, real-time signal convolution modulation device based on FGPA provided by the present invention;

[0043] Figure 9 This is a schematic structural diagram of an embodiment of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0045] In the description of the embodiments of the present invention, unless otherwise specified, "plurality" means two or more. "And / or" describes the association relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0046] The terms "first," "second," and so on, used in the embodiments of the present invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, technical features designated as "first" or "second" may explicitly or implicitly include at least one such feature.

[0047] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute a separate or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] The present invention provides a high-speed, low-latency, real-time signal convolution modulation method and device based on FPGA, which are described below.

[0049] Figure 1A flow chart of an embodiment of the high-speed, low-latency, real-time signal convolution modulation method based on FGPA provided by the present invention is shown as follows: Figure 1 As shown in FIG, the high-speed, low-latency, real-time signal convolution modulation method based on FGPA includes:

[0050] S101. Obtain a noise convolution kernel signal in an FPGA memory based on a random addressing code generated by a radio frequency signal; the FPGA memory is used to store convolution noise signals of various distribution types.

[0051] Simulation software can be used to generate noise signals of various distribution types, such as Gaussian noise, white noise, random noise, etc. The generated noise signals are converted into binary digital signals and stored in the FPGA memory in the form of noise convolution kernels (Noise_Kernels).

[0052] When a group of RF signals needs to be convolved, a random addressing code can be generated based on the RF signal, so that the noise convolution kernel signal can be randomly obtained in the FPGA memory according to the random addressing code. The noise convolution kernel signal can be randomly accessed, so that the convolution kernel involved in the convolution has randomness, making it more difficult to analyze the noise signal when detecting and identifying the interference signal.

[0053] S102: Performing a cyclic shift on the noise convolution kernel signal in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and copying the radio frequency signal to obtain a radio frequency signal to be convolved.

[0054] The obtained noise convolution kernel signal and radio frequency signal are preprocessed respectively. For example, the sign bits of the noise convolution kernel signal and the radio frequency signal can be converted to convert the obtained unsigned noise convolution kernel signal and radio frequency signal into signed signals.

[0055] The noise convolution kernel signal is pipelined and the circular convolution shift processing required in the circular convolution is performed, and then the convolution kernel signal is spliced ​​to obtain the noise convolution kernel signal to be convolved. At the same time, the RF signal is copied and spliced ​​to obtain the RF signal to be convolved.

[0056] S103 . Read the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved in parallel in a pipeline manner, perform multiplication calculations, and accumulate the multiplication calculation results to obtain a convolution modulation result.

[0057] The signal points in the noise convolution kernel signal to be convolved and the RF signal to be convolved are read in parallel in a pipeline manner, and multiplication calculations are performed on each group of signal points read at the same time. Then, the multiplication results are accumulated, that is, addition calculations are performed to obtain the convolution modulation result.

[0058] The embodiment of the present invention provides a high-speed, low-latency, real-time signal convolution modulation method based on FPGA. By storing convolution noise signals of various distribution types in an FPGA memory, when a group of radio frequency signals needs to be convolved, a noise convolution kernel signal is randomly obtained in the FPGA memory according to a random addressing code, thereby increasing the richness and randomness of the noise signal, solving the problem that the noise signal type is single and easy to identify, thereby improving the interference effect of the signal. The noise convolution kernel signal is circularly shifted to obtain a noise convolution kernel signal to be convolved, and the radio frequency signal is copied to obtain a radio frequency signal to be convolved. Circular convolution is used instead of linear convolution to save a lot of computing time. By reading the signal points in the noise convolution kernel signal to be convolved and the radio frequency signal to be convolved in parallel and performing multiplication calculations, the multiplication calculation results are accumulated to obtain the convolution modulation result, thereby solving the problem of long computing time and completing real-time convolution calculation with low latency.

[0059] In some embodiments of the present invention, the random addressing code generated based on the radio frequency signal, before obtaining the noise convolution kernel signal in the FPGA memory, further includes:

[0060] Generate noise signals of various distribution types through simulation software;

[0061] The noise signal is converted into a binary digital signal and stored in the FPGA memory in the form of a noise convolution kernel.

[0062] The main purpose of generating and storing multiple types of noise signals is to achieve the diversification of noise signal types and the storage and subsequent use of noise signals. In the noise signal generation preprocessing stage, the embodiment of the present invention first uses mathematical tools to generate noise signals of multiple distribution types, including Gaussian noise signals, white noise signals, random noise signals, etc., and further adjusts different parameters for different types of noise signals to obtain multiple noise convolution kernel signals of different types and distributions.

[0063] The generated noise signal is then converted into a binary digital signal in the form of a noise convolution kernel (Noise_Kernels) and stored in the FPGA memory, which can be read from it for subsequent use. Figure 2 The schematic diagram of the generation and storage of multiple types of noise signals provided by the present invention is as follows: Figure 2 Shown is the specific implementation process of the program.

[0064] In some embodiments of the present invention, the random addressing code generated based on the radio frequency signal, before obtaining the noise convolution kernel signal in the FPGA memory, further includes:

[0065] The random addressing code is determined based on a value of a target signal point in the radio frequency signal.

[0066] The generation of noise convolution kernel signal is a preprocessing process, and the reading of noise convolution kernel signal is the first step in the convolution adjustment pipeline scheme. Its specific implementation scheme is: when a group of RF signals need to be convolved, the number of points of the RF signal is , the bit width of each signal point is N (bit), that is, the total length of the RF signal is .

[0067] A set of random addressing codes Random_Code with a bit width of M is obtained through the radio frequency signal, where each bit of the addressing code is the i-th bit of the radio frequency signal. The value on N bits, that is, Random_Code(i) = N i (where i=1:M).

[0068] In this way, the noise convolution kernel signal can be randomly selected, making the convolution kernel involved in the convolution random, making it more difficult to analyze the noise signal when detecting and identifying the interference signal.

[0069] In some embodiments of the present invention, the step of cyclically shifting the noise convolution kernel signal in a pipeline manner to obtain the noise convolution kernel signal to be convolved, and copying the radio frequency signal to obtain the radio frequency signal to be convolved includes:

[0070] Inverting the highest bits of the signal points of the radio frequency signal and the noise convolution kernel signal respectively to obtain a signed target radio frequency signal and a target noise convolution kernel signal;

[0071] Circularly shifting and splicing the target noise convolution kernel signal in a parallel processing manner to obtain the noise convolution kernel signal to be convolved;

[0072] The target radio frequency signal is copied and then spliced ​​to obtain the radio frequency signal to be convolved.

[0073] The convolution modulation data preprocessing part mainly preprocesses the high-speed RF signal and noise convolution kernel to be convolved, and prepares data for subsequent parallel processing solutions.

[0074] The noise convolution kernel is obtained by using the random reading method provided in the above embodiment. The random reading method can further improve the randomness of the noise signal to be convolved and enhance the interference effect.

[0075] After obtaining the RF signal Signal and convolution kernel Noise_Kernels required for convolution, the subsequent processing flow begins. The following is the data Signal (N ) and noise convolution kernel Noise_Kernels(N )’s pipelined preprocessing process is introduced in detail.

[0076] Figure 3 The convolution modulation data preprocessing pipeline diagram provided by the present invention is as follows: Figure 3 As shown, each group of RF signals to be processed Signal(N ) is N, and the number of signal points is The convolution kernel Noise_Kernels(N ) is also N in width and the number of points is .

[0077] The specific preprocessing pipeline includes the following three steps:

[0078] (1) The first step of the pipeline: At the first CLK clock, the RF signal and the convolution kernel signal are converted from unsigned signal points to signed signal points. That is, the highest bit of the signal points of the RF signal and the noise convolution kernel signal are inverted to obtain the signed target RF signal and target noise convolution kernel signal.

[0079] (2) The second step of the pipeline: At the second CLK clock, you need to use The registers are shifted and stored in parallel, and the convolution kernel Noise_Kernels is completed in one CLK clock. Second circular shift, that is, to obtain The convolution kernel signal after cycles.

[0080] (3) The third step of the pipeline: At the third CLK clock, the previously obtained The noise convolution kernel signal after the cycle is spliced ​​together to obtain the noise convolution kernel signal to be convolved, and a The register stores the concatenated convolution kernel signal, and the obtained data can be used for subsequent parallel processing. Similarly, the RF signal Signal also needs to be copied. After that, they are spliced ​​and stored to obtain the RF signal to be convolved.

[0081] At this point, the data preprocessing pipeline for convolution modulation is complete. Only three CLK clocks are required to complete dual-parallel low-latency cyclic convolution modulation data preprocessing, ensuring real-time processing of high-speed RF signals.

[0082] In some embodiments of the present invention, the pipeline method is used to parallel read the noise convolution kernel signal to be convolved and the signal points in the RF signal to be convolved for multiplication calculation, and accumulate the multiplication results to obtain the convolution modulation result, including:

[0083] Reading the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved in parallel based on a preset corresponding relationship to obtain an associated radio frequency signal and a convolution kernel signal;

[0084] Performing multiplication calculation on the associated radio frequency signal and the signal point in the convolution kernel signal to obtain a multiplication calculation result;

[0085] The multiplication calculation results are accumulated and concatenated to obtain a convolution modulation result.

[0086] In the convolution modulation data preprocessing stage, 3 CLK clocks are consumed to complete the data preparation for the subsequent dual parallel, low-latency cyclic convolution. The convolution modulation data preprocessing stage has been completed in the previous step, and two groups of The concatenated signals to be convolved are the copied and concatenated RF signal Signal and the convolution kernel signal Noise_Kernels after the loop.

[0087] The following convolution calculation will use a loop parallel approach to simultaneously perform the two groups of The signal is processed and the RF signal and convolution kernel are combined one by one according to the convolution calculation method for subsequent calculation and processing.

[0088] The dual-parallel, low-latency loop convolution calculation is also achieved in a pipeline manner. Figure 4 This is the dual-parallel, circular convolution pipeline diagram provided by the present invention.

[0089] like Figure 4 As shown, this stage mainly needs to complete the multiplication and addition calculations in the convolution operation. The signals are mapped one-to-one according to the mathematical model of circular convolution, and then the corresponding mathematical calculations are completed. The pipeline steps are divided into the following three steps:

[0090] (1) The first step of the pipeline: the two groups obtained in the convolution modulation data preprocessing stage The signal to be convolved is processed in parallel in a loop as follows Figure 4 The corresponding relationship shown (i.e. the preset corresponding relationship) is The N-bit point width is read to obtain the associated RF signal and convolution kernel signal, which are then loaded into the multiplication and addition module of the convolution calculation.

[0091] That is, the required circular convolution is performed simultaneously within one CLK clock. The data to be convolved are loaded into A subsequent convolution multiplication and addition processing module is needed here. The register computing resources of the multiplication and addition processing module.

[0092] (2) The second step of the pipeline: After the signal involved in the convolution is loaded, it is completed again in parallel processing using the time of one CLK clock. The group width is N, and the number of points is Multiplication of points.

[0093] Take the processing of a set of multiplication and addition calculation modules as an example. In the module, there is a set of corresponding RF signals Signal and convolution kernel signals Noise_Kernels. Each signal has The signal points with a bit width of N are multiplied again in a cyclic parallel manner. At the same time, the RF signal and the points corresponding to the convolution kernel are multiplied to obtain mult1.1 to mult Total The result of a multiplication calculation.

[0094] (3) The third step of the pipeline: After completing the parallel multiplication calculation, at the next CLK clock, The multiplication calculation of each group of signals corresponding to the group is obtained The multiplication calculation results mult are added together through an accumulator Adder to obtain the multiplication and addition result Adder Result (3N) of this group of signals. The accumulated results with a bit width of 3N are concatenated to obtain the final convolution calculation result Conv_Result (3N ).

[0095] At this point, the entire calculation process of circular convolution is completed.

[0096] In summary, combining convolution modulation data preprocessing with parallel loop convolution calculations requires only six clock cycles. This solution meets low latency requirements and solves the problem of excessive convolution modulation time. Furthermore, the registers' data storage function enables real-time processing of RF signals at high sampling rates.

[0097] In some embodiments of the present invention, after reading the noise convolution kernel signal to be convolved and the signal points in the RF signal to be convolved in parallel by a pipeline method for multiplication calculation, and accumulating the multiplication results to obtain the convolution modulation result, the method further includes:

[0098] Based on the bit width requirement of the output signal, the bit width of the convolution modulation result is adjusted.

[0099] For some specific industrial application scenarios, after convolution modulation is completed, the bit width of the final modulated data needs to be adjusted accordingly to meet the bit width requirements of the output signal.

[0100] In some embodiments of the present invention, the bit width adjustment of the convolution modulation result based on the bit width requirement of the output signal includes:

[0101] Converting the convolution modulation result from a fixed-point number of a first bit width to a floating-point number of a second bit width;

[0102] Convert the floating-point number of the second bit width into a fixed-point number that meets the requirements.

[0103] Direct interception will result in loss of data accuracy. Therefore, when adjusting the bit width, the data accuracy needs to be guaranteed as much as possible. The present invention adopts the following method to adjust the bit width while maintaining data accuracy.

[0104] Figure 5 The data width adjustment pipeline diagram provided by the present invention is as follows: Figure 5 As shown, the specific pipeline steps are as follows:

[0105] The first step is to use the fixed-point to floating-point IP core. After 4 CLK clocks, the convolution modulation output is converted from a fixed-point number with a bit width of 3N (the first bit width) to a floating-point number with a bit width of M (the second bit width).

[0106] The second step is to use the IP core that converts floating-point numbers into fixed-point numbers. After 5CLK clocks, the floating-point number with a bit width of M is converted into a fixed-point number that meets the output bit width requirements, and the final convolution modulation output result that meets the bit width requirements is obtained: Conv_Result(L ).

[0107] At this point, low-latency convolution modulation for high-speed RF signals is completed.

[0108] That is, to address the problem that the first type of noise signal distribution type is easily identifiable, the present invention proposes a method for storing multiple types of digital noise signals based on FPGA. The main principle is to utilize the memory in the FPGA to store digital signals in advance. First, mathematical tools are used to generate noise signals of different distribution types. Then, the previously acquired noise signals are stored in the memory of the FPGA development board in the form of digital signals. When the noise signal is needed later, a random code addressing method is used to randomly read the stored noise signal. In this way, the problem that the noise signal type is single and easy to identify can be effectively solved.

[0109] In response to the problem that the signal convolution modulation processing time of the second type at high sampling rate is long and difficult to meet real-time requirements, the present invention proposes a dual-parallel convolution calculation method based on circular convolution. The principle is to use parallel processing to complete the calculation process of circular shift and multiplication and addition in circular convolution.

[0110] Here we conduct a comparative analysis, taking a set of convolution signal points as Take the signal as an example to analyze the time consumption in the linear convolution process in detail:

[0111] The number of cyclic shifts is: Second-rate.

[0112] The number of multiplication calculations after each shift is: 1+2+…+ + +…+2+1 = .

[0113] The number of addition calculations after each shift is: 0+1+2+…+ + +…+2+1+0 = + .

[0114] Similarly, two sets of points are used as As an example, let’s analyze the time required for each step of circular convolution under the original solution:

[0115] Number of cyclic shifts: .

[0116] The number of multiplication calculations after each shift is: .

[0117] The number of addition calculations after each shift is: .

[0118] From the above analysis, we can see that the time and register resources required by circular convolution are far less than those of linear convolution. In addition, based on circular convolution, the idea of ​​dual parallel processing can further reduce the time.

[0119] The principle is to convert the convolution required The loop is completed, which requires a lot of register resources, and then through a loop calculation method, the previously completed The multiplication and addition calculation of group signals can save The multiplication and addition calculation time is shortened. At the same time, the parallel calculation method is also used in the multiplication and addition calculation module. In each group of signals Point multiplication calculation, then you can save Calculation time.

[0120] This algorithm framework mainly consists of three modules: noise signal generation and reading preprocessing, convolution data preprocessing, and dual parallel low-latency cyclic convolution implementation.

[0121] Figure 6 The low-latency multi-random real-time convolution implementation framework provided by the present invention is as follows: Figure 6 As shown, the first step is the noise signal generation and reading preprocessing stage, in which the required various types of noise signals are generated through simulation software, and then stored in the memory in the form of digital signals for subsequent modulation needs.

[0122] When performing convolution calculation, take a group of high-speed radio frequency signals as an example. This group of signals has When the convolution module receives the RF signal, it first generates a set of random addressing codes based on this set of signals, and obtains the Gaussian convolution kernel through this code.

[0123] Next is the data preprocessing stage before the convolution modulation calculation, in which the RF signal and noise convolution kernel to be convolved are preprocessed accordingly. Finally, a dual-parallel, low-latency cyclic convolution calculation is performed. The result of the convolution calculation is finally adjusted according to the bit width requirements of the output signal to obtain the final convolution modulation output.

[0124] The present invention still uses pipeline to process the low-latency and multi-random convolution scheme of high-speed radio frequency signals in real time. Figure 7 The present invention provides a low-latency, multi-random real-time convolution pipeline graph, such as Figure 7 As shown, the specific pipeline steps are as follows:

[0125] (1) The first step of the pipeline: complete the reading of the noise convolution kernel data to be convolved.

[0126] (2) The second step of the pipeline: complete the sign bit conversion of the data to be convolved, and convert the unsigned RF signal and the noise convolution kernel signal read previously into signed signals.

[0127] (3) The third step of the pipeline: preprocess the two sets of signals to be convolved, complete the circular convolution shift required by the noise convolution kernel in the circular convolution, and then splice them to form the data required for subsequent parallel convolution calculations.

[0128] (4) The fourth step of the pipeline: adopt a dual parallel processing method. On the basis of parallel processing of multiple groups of data, the multiplication and addition calculations of each single group of signals are processed in parallel at the same time.

[0129] (5) The fifth step of the pipeline: while retaining the data accuracy, complete the adjustment of the data bit width.

[0130] The high-speed, low-latency, real-time signal convolution modulation method and device based on FPGA provided by the present invention have the following advantages:

[0131] A dual-parallel approach is used to achieve fast convolution calculation of RF signals at high sampling rates. First, to address the problem that the noise signal type is single and easy to identify, a multi-type noise signal mixing solution is adopted. Different types of noise signals are mixed and stored in the form of digital signals. When performing convolution calculations, a random read method is used to obtain the final calculated noise signal, which increases the richness and randomness of the noise signal and makes the final signal interference effect better. At the same time, to address the problems of long convolution calculation time of RF signals at high sampling rates and non-real-time data processing, a dual-parallel processing method is proposed. Circular convolution is used instead of linear convolution to save a lot of computing time, solve the problem of long computing time, and complete real-time convolution calculations with low latency.

[0132] From a performance perspective, the processing scheme of the present invention takes the convolution data preprocessing stage into consideration, and the total number of clocks required is six CLK clocks, which is much shorter than the time of linear convolution: + + .

[0133] From a cost perspective, in terms of time cost, this solution uses parallel computing, which consumes less time than the traditional linear one-to-one computing method.

[0134] In terms of register resource consumption, this solution adopts a circular convolution solution. The register consumption is as follows: The number of bits consumed by the circular shift register is: , multiplier consumption number: ,Adder consumption: , compared to the number of registers for linear convolution: + + The computational cost is significantly reduced. However, this solution requires certain parallel computing capabilities and requires corresponding chips that can process large amounts of data simultaneously.

[0135] From the perspective of security and reliability, this solution fully adopts the mathematical principle of circular convolution, and transforms it into a specific implementation algorithm based on the mathematical model of circular convolution. Its calculation results can be verified through simulation results, and the results are completely consistent with the actual calculation results.

[0136] That is, in order to achieve the purpose of fast calculation of convolution modulation of RF signals at high sampling rates, the present invention combines digital signal processing technology and adopts the method of cyclic fast convolution to design a real-time convolution implementation scheme with multiple noise types and low latency.

[0137] This solution consists of three main parts: noise signal generation and storage preprocessing module, convolution modulation data preprocessing module, and dual parallel low-latency convolution implementation module. The specific implementation process of the entire solution is as follows:

[0138] (1) The first step is to generate and store noise signals. Using mathematical tools, we generate noise signals of various distribution types. These signals are then stored in memory as digital signals. When the noise signal is subsequently needed for convolution calculations, the corresponding noise signal is randomly read from the memory using a set of random addressing codes.

[0139] (2) The next step is the convolution modulation data preprocessing stage. The number of points in a group of signals is the number of cycles required for the circular convolution. Here, a large number of registers are required to complete all the cycles of the noise signal simultaneously within one CLK clock. point as an example, using registers, and then use a The register concatenates all the noise signals after the loop. At the same time, the RF signal also needs to be copied to the same length. At this point, the data preprocessing result before convolution modulation can be obtained.

[0140] (3) Finally, the low-latency convolution calculation implementation process under the dual parallel mode requires the use of parallel processing to splice the previous Each group of registers The RF signal and the corresponding noise signal are loaded into the multiplication and addition calculation module, and a total of Group, at the same time in each group of RF signal and noise signal multiplication and addition calculation module, each corresponding point in each group of signals is calculated in parallel, and The multiplication results are added together to obtain the multiplication and addition results of the RF signal and the noise signal. The result is the final output of the convolution modulation. This solution can complete the circular convolution calculation within six CLK clocks, thus meeting the low latency requirement of convolution modulation of RF signals at high sampling rates.

[0141] In summary, to address the current problem of noise signals being of a single type and easily identifiable in signal interference modulation in industrial environments, this present invention proposes a solution that uses mixed storage and random access of multiple noise signals. This makes noise signals more difficult to identify and enhances the signal interference effect.

[0142] Aiming at the problem of long calculation time and poor real-time performance of convolution modulation of radio frequency signals at high sampling rates in FPGA, the present invention proposes a dual-parallel, low-latency convolution modulation calculation scheme. Circular convolution is used instead of linear convolution, which greatly reduces the utilization of register resources. Before performing the convolution calculation, all the cyclic results of the noise signal in the circular convolution are completed within the same clock, and then a parallel method is used to simultaneously complete the multiplication and addition calculations of all the circularly shifted signals. When performing the multiplication and addition calculations of each group of circularly shifted signals, a parallel method is also used. Multiplication calculations are performed on all points in each group of signals at the same time, and the calculation results are then added at the same time to obtain the calculation results of this group of signals. The calculations of other groups of signals will also be completed at the same time. Finally, a low-latency and real-time convolution modulation interference signal can be obtained.

[0143] In order to better implement the high-speed, low-latency, real-time signal convolution modulation method based on FGPA in the embodiment of the present invention, based on the high-speed, low-latency, real-time signal convolution modulation method based on FGPA, correspondingly, Figure 8 As shown, an embodiment of the present invention further provides a high-speed, low-latency, real-time signal convolution modulation device based on FGPA. The high-speed, low-latency, real-time signal convolution modulation device 800 based on FGPA includes:

[0144] An acquisition unit 801 is configured to acquire a noise convolution kernel signal from an FPGA memory based on a random addressing code generated by a radio frequency signal; the FPGA memory is configured to store convolution noise signals of various distribution types;

[0145] The preprocessing unit 802 is configured to perform a cyclic shift on the noise convolution kernel signal in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and to copy the RF signal to obtain a RF signal to be convolved;

[0146] The convolution modulation unit 803 is used to read the noise convolution kernel signal to be convolved and the signal points in the RF signal to be convolved in parallel in a pipeline manner to perform multiplication calculations, and accumulate the multiplication calculation results to obtain a convolution modulation result.

[0147] The FGPA-based high-speed, low-latency, real-time signal convolution modulation device 800 provided in the above embodiment can implement the technical solution described in the above embodiment of the FGPA-based high-speed, low-latency, real-time signal convolution modulation method. The specific implementation principles of the above modules or units can refer to the corresponding contents in the above embodiment of the FGPA-based high-speed, low-latency, real-time signal convolution modulation method, which will not be repeated here.

[0148] like Figure 9As shown, the present invention also provides an electronic device 900. The electronic device 900 includes a processor 901, a memory 902 and a display 903. Figure 9 Only some of the components of the electronic device 900 are shown, but it should be understood that implementation of all of the shown components is not required, and more or fewer components may be implemented instead.

[0149] In some embodiments, the processor 901 can be a central processing unit (CPU), a microprocessor, or other data processing chip, used to run the program code or process data stored in the memory 902, such as the high-speed, low-latency real-time signal convolution modulation method based on FGPA in the present invention.

[0150] In some embodiments, the processor 901 may be a single server or a server group. The server group may be centralized or distributed. In some embodiments, the processor 901 may be local or remote. In some embodiments, the processor 901 may be implemented on a cloud platform. In some embodiments, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, multiple clouds, or any combination thereof.

[0151] In some embodiments, the memory 902 may be an internal storage unit of the electronic device 900, such as a hard disk or memory of the electronic device 900. In other embodiments, the memory 902 may also be an external storage device of the electronic device 900, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 900.

[0152] Furthermore, the memory 902 may include both an internal storage unit of the electronic device 900 and an external storage device. The memory 902 is used to store application software installed in the electronic device 900 and various data.

[0153] In some embodiments, the display 903 can be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an organic light-emitting diode (OLED) touchscreen. The display 903 is used to display information on the electronic device 900 and to display a visual user interface. Components 901-903 of the electronic device 900 communicate with each other via a system bus.

[0154] In one embodiment, when the processor 901 executes the high-speed, low-latency, real-time signal convolution modulation program based on the FGPA in the memory 902, the following steps may be implemented:

[0155] Obtaining a noise convolution kernel signal in an FPGA memory based on a random addressing code generated by a radio frequency signal; the FPGA memory is used to store convolution noise signals of various distribution types;

[0156] The noise convolution kernel signal is cyclically shifted in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and the radio frequency signal is copied to obtain a radio frequency signal to be convolved;

[0157] In a pipeline manner, the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved are read in parallel for multiplication calculation, and the multiplication calculation results are accumulated to obtain the convolution modulation result.

[0158] It should be understood that when the processor 901 executes the FGPA-based high-speed, low-latency real-time signal convolution modulation program in the memory 902, in addition to the above functions, it can also implement other functions. For details, please refer to the description of the corresponding method embodiment above.

[0159] Furthermore, the embodiment of the present invention does not specifically limit the type of the electronic device 900 mentioned. The electronic device 900 may be a portable electronic device such as a mobile phone, a tablet computer, a personal digital assistant (PDA), a wearable device, a laptop computer, or the like. Exemplary embodiments of portable electronic devices include, but are not limited to, portable electronic devices equipped with IOS, Android, Microsoft, or other operating systems. The above-mentioned portable electronic devices may also be other portable electronic devices, such as a laptop computer with a touch-sensitive surface (e.g., a touch panel). It should also be understood that in some other embodiments of the present invention, the electronic device 900 may not be a portable electronic device, but a desktop computer with a touch-sensitive surface (e.g., a touch panel).

[0160] Accordingly, an embodiment of the present invention also provides a computer-readable storage medium, which is used to store computer-readable programs or instructions. When the program or instructions are executed by a processor, it can implement the steps or functions of the high-speed, low-latency, real-time signal convolution modulation method based on FGPA provided in the above-mentioned method embodiments.

[0161] Those skilled in the art will appreciate that all or part of the process flow of the above-described method embodiment can be implemented by instructing related hardware (such as a processor, controller, etc.) through a computer program, and the computer program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a magnetic disk, an optical disk, a read-only memory, or a random access memory.

[0162] The above is a detailed introduction to the high-speed, low-latency, real-time signal convolution modulation method and device based on FGPA provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A high-speed, low-latency, real-time signal convolution modulation method based on FPGA, characterized in that: include: Based on the random addressing code generated by the RF signal, the noise convolution kernel signal is obtained in the FPGA memory; The FPGA memory is used to store convolution noise signals of multiple distribution types; The noise convolution kernel signal is cyclically shifted in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and the radio frequency signal is copied to obtain a radio frequency signal to be convolved; Reading the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved in parallel in a pipeline manner to perform multiplication calculations, and accumulating the multiplication calculation results to obtain a convolution modulation result; The step of cyclically shifting the noise convolution kernel signal in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and copying the radio frequency signal to obtain a radio frequency signal to be convolved, includes: Inverting the highest bits of the signal points of the radio frequency signal and the noise convolution kernel signal respectively to obtain a signed target radio frequency signal and a target noise convolution kernel signal; Circularly shifting and splicing the target noise convolution kernel signal in a parallel processing manner to obtain the noise convolution kernel signal to be convolved; The target radio frequency signal is copied and then spliced ​​to obtain the radio frequency signal to be convolved.

2. The high-speed, low-latency, real-time signal convolution modulation method based on FPGA according to claim 1, characterized in that: The pipeline method is used to read the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved in parallel for multiplication calculation, and accumulate the multiplication calculation results to obtain the convolution modulation result, including: Reading the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved in parallel based on a preset corresponding relationship to obtain an associated radio frequency signal and a convolution kernel signal; Performing multiplication calculation on the associated radio frequency signal and the signal point in the convolution kernel signal to obtain a multiplication calculation result; The multiplication calculation results are accumulated and concatenated to obtain a convolution modulation result.

3. The high-speed, low-latency, real-time signal convolution modulation method based on FPGA according to claim 1, characterized in that: After the pipeline method is used to read the noise convolution kernel signal to be convolved and the signal points in the radio frequency signal to be convolved in parallel for multiplication calculation, and accumulating the multiplication calculation results to obtain the convolution modulation result, the method further includes: Based on the bit width requirement of the output signal, the bit width of the convolution modulation result is adjusted.

4. The high-speed, low-latency, real-time signal convolution modulation method based on FPGA according to claim 3, characterized in that: The step of adjusting the bit width of the convolution modulation result based on the bit width requirement of the output signal includes: Converting the convolution modulation result from a fixed-point number of a first bit width to a floating-point number of a second bit width; Convert the floating-point number of the second bit width into a fixed-point number that meets the requirements.

5. The high-speed, low-latency, real-time signal convolution modulation method based on FPGA according to claim 1, characterized in that: The random addressing code generated based on the radio frequency signal, before obtaining the noise convolution kernel signal in the FPGA memory, further includes: The random addressing code is determined based on a value of a target signal point in the radio frequency signal.

6. The high-speed, low-latency, real-time signal convolution modulation method based on FPGA according to claim 1, characterized in that: The random addressing code generated based on the radio frequency signal, before obtaining the noise convolution kernel signal in the FPGA memory, further includes: Generate noise signals of various distribution types through simulation software; The noise signal is converted into a binary digital signal and stored in the FPGA memory in the form of a noise convolution kernel.

7. A high-speed, low-latency, real-time signal convolution modulation device based on FPGA, characterized in that: include: an acquisition unit, configured to acquire a noise convolution kernel signal in an FPGA memory based on a random addressing code generated by the radio frequency signal; The FPGA memory is used to store convolution noise signals of multiple distribution types; a preprocessing unit, configured to perform a cyclic shift on the noise convolution kernel signal in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and to copy the radio frequency signal to obtain a radio frequency signal to be convolved; A convolution modulation unit is configured to read the noise convolution kernel signal to be convolved and the signal points in the RF signal to be convolved in parallel in a pipeline manner, perform multiplication calculations, and accumulate the multiplication results to obtain a convolution modulation result; The step of cyclically shifting the noise convolution kernel signal in a pipeline manner to obtain a noise convolution kernel signal to be convolved, and copying the radio frequency signal to obtain a radio frequency signal to be convolved, includes: Inverting the highest bits of the signal points of the radio frequency signal and the noise convolution kernel signal respectively to obtain a signed target radio frequency signal and a target noise convolution kernel signal; Circularly shifting and splicing the target noise convolution kernel signal in a parallel processing manner to obtain the noise convolution kernel signal to be convolved; The target radio frequency signal is copied and then spliced ​​to obtain the radio frequency signal to be convolved.

8. An electronic device, characterized in that: comprising a memory and a processor, wherein, The memory is used to store programs; The processor is coupled to the memory and is used to execute the program stored in the memory to implement the steps in the high-speed, low-latency, real-time signal convolution modulation method based on FGPA as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that Used to store computer-readable programs or instructions, which, when executed by a processor, can implement the steps of the FGPA-based high-speed, low-latency, real-time signal convolution modulation method as described in any one of claims 1 to 6.

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