SM4 hardware acceleration and anti-side channel protection method and system for domestic FPGA

Abstract

The present invention relates to the field of FPGA architecture technology, specifically a method and system for SM4 hardware acceleration and side-channel protection for a domestically produced FPGA. The method comprises: utilizing an acceleration block to perform a data type identification operation on batches of plaintext and ciphertext data to obtain a data type; dynamically configuring resources for the batches of plaintext and ciphertext data based on a pre-established parallelization strategy and the data type to obtain resource configuration information; and configuring a configured SM4 algorithm based on the resource configuration information, key-mode parameters, and dynamic control instructions; encrypting the batches of plaintext and ciphertext data according to the configured SM4 algorithm to obtain encrypted data to be protected; and utilizing the protection block to perform a protection operation based on physical layer leakage suppression, logical layer obfuscation association, and system layer dynamic response on the key-mode parameters, dynamic control instructions, the batches of plaintext and ciphertext data, and the encryption process, thereby converting the encrypted data to be protected into protected encrypted data. The present invention can improve encryption processing performance and security.

Description

Technical Field

[0001] The present invention relates to the field of FPGA architecture technology, and in particular to a method and system for SM4 hardware acceleration and anti-side channel protection of a domestically produced FPGA. Background Art

[0002] As my country's standard commercial cryptographic algorithm, SM4's hardware acceleration and side-channel protection are core requirements for improving the security and efficiency of cryptographic systems in FPGAs. Hardware acceleration implements algorithm logic through dedicated circuits, increasing computational speed by dozens of times compared to software execution. This meets the high throughput requirements of real-time-sensitive scenarios such as the Internet of Things and financial payments, while also reducing overall system power consumption. Side-channel protection targets side-channel attacks such as power analysis and electromagnetic radiation, employing mechanisms such as masking and randomized execution paths to prevent key information from leaking through physical side channels.

[0003] However, in specific usage scenarios, the SM4 and anti-side-channel protection configurations are usually used by default. Adjusting the FPGA speed-up configuration relies on subjective configuration by technicians, and has a high usage threshold. This results in performance waste and poor dynamic protection capabilities of SM4 and anti-side-channel protection during use. Summary of the Invention

[0004] The present invention provides a method for SM4 hardware acceleration and anti-side channel protection of a domestic FPGA, the main purpose of which is to improve encryption processing performance and security.

[0005] To achieve the above objectives, the present invention provides a method for SM4 hardware acceleration and anti-side channel protection for a domestic FPGA, comprising:

[0006] Using a pre-built PCIe bus, connecting a pre-built adaptive acceleration and protection FPGA to a pre-built target computer, wherein the adaptive acceleration and protection FPGA includes an acceleration block and a protection block, and the target computer includes a CPU and a DDR;

[0007] Obtaining key-mode parameters and dynamic control instructions generated by the CPU, and obtaining plaintext-ciphertext batch data in the DDR, wherein the key-mode parameters include a master key, encryption mode parameters, and a function switching signal; the dynamic control instructions include instructions for starting / pausing data transmission and adjusting pipeline depth; and the plaintext-ciphertext batch data includes plaintext / ciphertext data blocks and intermediate state cache information;

[0008] Using the acceleration block, performing a data type identification operation on the plaintext-ciphertext batch data to obtain a data type, and dynamically configuring resources for the plaintext-ciphertext batch data according to a pre-built parallelization strategy and the data type to obtain resource configuration information, and configuring a configured SM4 algorithm according to the resource configuration information, a key-mode parameter, and a dynamic control instruction;

[0009] Encrypting the plaintext-ciphertext batch data according to the configured SM4 algorithm to obtain encrypted data to be protected;

[0010] By utilizing the protection block, the key-mode parameters, dynamic control instructions, plaintext-ciphertext batch data and the encryption processing process are subjected to protection operations based on physical layer leakage suppression, logical layer confusion association and system layer dynamic response, thereby converting the encrypted data to be protected into protected encrypted data.

[0011] Optionally, obtaining the key-mode parameters and dynamic control instructions generated in the CPU, and obtaining the plaintext-ciphertext batch data in the DDR, includes:

[0012] Using a pre-built AXI-Lite bus, the key-mode parameters and dynamic control instructions generated in the CPU are sent to a pre-built control register in the acceleration block;

[0013] The pre-built AXI-Stream bus is used to send the plaintext and ciphertext batch data pre-loaded by the CPU in the DDR to the pre-built input cache module in the acceleration block.

[0014] Optionally, performing a data type identification operation on the plaintext-ciphertext batch data to obtain the data type includes:

[0015] Performing data block metadata analysis on the plaintext-ciphertext batch data to obtain data block size distribution and transmission interval characteristics;

[0016] Using a pre-built sliding time window, a throughput and delay correlation analysis is performed on the plaintext-ciphertext batch data to obtain the data processing volume and average response delay;

[0017] Performing feature-weighted calculation on the data block size distribution, transmission interval characteristics, data processing volume, and average response delay according to a preset weight coefficient sequence to obtain a data type score;

[0018] Obtain a size relationship between the data type score and a pre-constructed classification threshold, and obtain the data type based on the size relationship, wherein the data type includes a large data block type and a small data block type.

[0019] Optionally, dynamically configuring resources for the plaintext-ciphertext batch data according to the pre-built parallelization strategy and the data type to obtain resource configuration information includes:

[0020] Determining whether the data type is a large data block type or a small data block type according to a pre-built parallelization strategy;

[0021] When the data type is a large data block type, determining that the resource configuration information is first type configuration information;

[0022] When the data type is a small data block type, determining that the resource configuration information is second type configuration information;

[0023] The first type of configuration information includes: utilizing the CPU to obtain task-related data, utilizing the PCIe bus to preload the task-related data into the DDR for storage, and utilizing a pre-built FPGA multi-core parallel architecture and a 32-stage pipeline design to process the plaintext-ciphertext batch data;

[0024] Among them, the second type of configuration information includes using a pre-built bit slicing service to reorganize the plaintext and ciphertext batch data into a bit width supported by a preset SIMD instruction, obtain a data grouping result, and process multiple groups in the data grouping result in the same batch.

[0025] Optionally, configuring the configured SM4 algorithm according to the resource configuration information, the key-mode parameter, and the dynamic control instruction includes:

[0026] Performing an acceleration architecture selection operation on a pre-built SM4 algorithm based on the resource configuration information;

[0027] Parsing the key-mode parameters to obtain a master key, encryption mode parameters, and a function switching signal, performing a key expansion operation based on a superimposed random mask on the master key according to a pre-built SM4 key expansion instruction to obtain a round key, and storing the round key in a pre-built secure storage area;

[0028] Configure the encryption process in the SM4 algorithm according to the encryption mode parameters, and configure the working logic in the SM4 algorithm according to the function switching signal;

[0029] According to the dynamic control instruction, a combination mode of the number of pipeline stages and the number of parallel cores in the SM4 algorithm is configured to obtain a configured SM4 algorithm.

[0030] Optionally, the utilizing of the protection block to perform protection operations based on physical layer leakage suppression, logical layer obfuscation association, and system layer dynamic response on the key-mode parameters, dynamic control instructions, plaintext-ciphertext batch data, and the encryption processing process includes:

[0031] Using the protection block, the encryption process is subjected to a signal weakening operation based on power consumption and electromagnetic radiation characteristics, and a correlation perturbation operation based on timing and clock jitter, thereby completing the physical layer leakage suppression process;

[0032] Performing an intermediate value randomization operation on the encryption process to complete the logic layer obfuscation association process;

[0033] A system-level dynamic response process based on abnormal event detection and response is performed on the AXI-Lite bus and the AXI-Stream bus.

[0034] Optionally, the utilizing the protection block to perform a signal attenuation operation based on power consumption and electromagnetic radiation characteristics, and a correlation perturbation operation based on timing and clock jitter on the encryption process, includes:

[0035] Using the pre-built adjustable load circuit in the protection block, a power consumption difference balancing operation is performed on the encryption process during the operation phase;

[0036] Using a pre-built metal shielding layer to cover the preset high leakage risk area in the configured SM4 algorithm;

[0037] A timing perturbation operation is performed on data transmission in the AXI-Lite bus and the AXI-Stream bus using pre-constructed true random numbers.

[0038] Optionally, performing an intermediate value randomization operation on the encryption process to complete a logic layer obfuscation association process includes:

[0039] Performing threshold segmentation on intermediate values preset during the encryption process, wherein the intermediate values include S-box outputs and round function intermediate values;

[0040] The pre-built dual-track redundant calculation module in the protection block is used to perform real-time comparison and output consistency on the encryption process, completing the logic layer obfuscation association process.

[0041] Optionally, the system-layer dynamic response process based on abnormal event detection and response for the AXI-Lite bus and the AXI-Stream bus includes:

[0042] Using the pre-built CNN attack recognition model in the protection block, the AXI-Lite bus and the AXI-Stream bus are subjected to attack pattern recognition and monitoring based on timing characteristics to obtain the target attack pattern;

[0043] According to the preset dynamic switching strategy, the target attack mode type is protected to complete the system layer dynamic response process.

[0044] To achieve the above objectives, the present invention further provides a domestically produced FPGA SM4 hardware acceleration and anti-side channel protection system, comprising:

[0045] a data acquisition module, configured to connect a pre-built adaptive acceleration and protection FPGA to a pre-built target computer using a pre-built PCIe bus, wherein the adaptive acceleration and protection FPGA includes an acceleration block and a protection block, and the target computer includes a CPU and a DDR, and to acquire key-mode parameters and dynamic control instructions generated in the CPU, and to acquire plaintext-ciphertext batch data in the DDR, wherein the key-mode parameters include a master key, an encryption mode parameter, and a function switching signal, the dynamic control instructions include instructions for starting / pausing data transmission and adjusting pipeline depth, and the plaintext-ciphertext batch data includes plaintext / ciphertext data blocks and intermediate state cache information;

[0046] an SM4 algorithm acceleration configuration module, configured to utilize the acceleration block to perform a data type identification operation on the plaintext-ciphertext batch data to obtain a data type, and to perform dynamic resource configuration on the plaintext-ciphertext batch data based on a pre-built parallelization strategy and the data type to obtain resource configuration information, and to configure a configured SM4 algorithm based on the resource configuration information, key-mode parameters, and dynamic control instructions;

[0047] An anti-side channel protection module is used to encrypt the plaintext and ciphertext bulk data according to the configured SM4 algorithm to obtain the encrypted data to be protected, and use the protection block to perform protection operations based on physical layer leakage suppression, logical layer obfuscation association and system layer dynamic response on the key-mode parameters, dynamic control instructions, plaintext and ciphertext bulk data and the encryption processing process, thereby converting the encrypted data to be protected into protected encrypted data.

[0048] In order to solve the above problem, the present invention further provides an electronic device, comprising:

[0049] a memory storing at least one instruction;

[0050] The processor executes the instructions stored in the memory to implement the SM4 hardware acceleration and anti-side channel protection method of the domestic FPGA described above.

[0051] In order to solve the above problems, the present invention also provides a computer-readable storage medium, which stores at least one instruction. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned SM4 hardware acceleration and anti-side channel protection method of the domestic FPGA.

[0052] The present invention aims to solve the problems described in the background technology. The SM4 algorithm in the FPGA of the present invention obtains data from both the CPU and the DDR. Among them, the plaintext and ciphertext batch data sent by the DDR is the main data to be processed. Through the collaboration between the DDR memory and the FPGA, massive data can be processed quickly, thereby improving data processing efficiency. The key-mode parameters and dynamic control instructions sent by the CPU have a small amount of data, but play a controlling role on the SM4 algorithm in the FPGA. In this solution, the CPU will adjust the pipeline depth in the FPGA in advance according to the task requirements, and the present invention also configures parallelization in the acceleration block in the FPGA. The strategy uses pipeline depth adjustment and parallelization strategies to optimize single-core timing efficiency, while parallelization expands multi-core processing capabilities. These two complementary goals improve the processing efficiency of the acceleration block. Furthermore, due to changes in the SM4 algorithm encryption processing within the acceleration block, as well as changes in the data acquisition paths from the CPU and DDR, the anti-side channel protection scheme must also change. The present invention adaptively implements anti-side channel protection for changes in the protection block from three aspects: physical layer leakage suppression, logical layer obfuscation association, and system layer dynamic response. This ensures overall system security while maintaining SM4 hardware acceleration. Therefore, the present invention can improve encryption processing performance and security. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A flowchart of a method for SM4 hardware acceleration and anti-side channel protection for a domestic FPGA provided in one embodiment of the present invention;

[0054] Figure 2 A functional module diagram of the SM4 hardware acceleration and anti-side channel protection system for a domestic FPGA provided in one embodiment of the present invention;

[0055] Figure 3 A schematic structural diagram of an electronic device for implementing the SM4 hardware acceleration and anti-side channel protection method of the domestic FPGA provided in one embodiment of the present invention.

[0056] Description of reference numerals:

[0057] 1. Electronic device; 10. Processor; 11. Memory; 12. Bus.

[0058] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0059] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0060] The present embodiment provides a method for SM4 hardware acceleration and side-channel protection for a domestically produced FPGA. The method can be performed by at least one of a server, a terminal, or other electronic device capable of executing the method provided by the present embodiment. In other words, the method can be executed by software or hardware installed on a terminal or server device, where the software can be a blockchain platform. The server can include, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0061] Reference Figure 1 FIG. 1 is a flow chart of a method for hardware acceleration and side-channel protection of SM4 in a domestic FPGA according to an embodiment of the present invention. In this embodiment, the method for hardware acceleration and side-channel protection of SM4 in a domestic FPGA includes:

[0062] S1. Use a pre-built PCIe bus to connect a pre-built adaptive acceleration and protection FPGA to a pre-built target computer, wherein the adaptive acceleration and protection FPGA includes an acceleration block and a protection block, and the target computer includes a CPU and a DDR.

[0063] The PCIe bus is a high-speed serial computer expansion bus standard used to connect a computer motherboard with external devices (such as graphics cards, solid-state drives, network cards, FPGAs, etc.).

[0064] Among them, FPGA refers to field programmable gate array, which is a programmable logic device that can reconfigure its internal structure to achieve different functions. It can be understood as editable hardware, and the hardware functions change with editing.

[0065] The adaptive acceleration protection FPGA refers to an FPGA that adaptively configures the SM4 algorithm processing according to the target computer's task requirements. This design aims to improve the speed and security of SM4 algorithm execution. The portion responsible for accessing and processing SM4 encrypted data is called the acceleration block. The portion of the acceleration block's encryption process that provides side-channel protection for the data source and data processing is called the protection block.

[0066] Specifically, in an embodiment of the present invention, the acceleration block in the adaptive acceleration protection FPGA is designed to improve the execution efficiency of the SM4 symmetric encryption algorithm through dedicated hardware architecture or instruction set optimization, thereby meeting the requirements of high-throughput, low-latency encryption. The anti-side-channel protection refers to a defense technology against side-channel attacks. It aims to prevent attackers from stealing sensitive data (such as keys and passwords) through indirect means by suppressing or obfuscating physical or logical leakage information (such as power consumption, electromagnetic radiation, and timing differences) generated by the encryption device during operation. This disclosure will subsequently refer to the adaptive acceleration protection FPGA as simply FPGA.

[0067] Specifically, in the embodiment of the present invention, the target computer refers to a computer that needs to process a large amount of video data or financial data, and includes at least a CPU and a DDR. The CPU refers to a central processing unit, and the DDR refers to a memory module.

[0068] In an embodiment of the present invention, the adaptive acceleration protection FPGA is connected to the target computer via a pre-built PCIe bus, thereby accelerating the process of encryption processing of massive data that the target computer cannot perform.

[0069] Specifically, the FPGA is connected to the host computer via the PCIe bus, supporting DMA transfers and enabling low-latency data exchange between the CPU and FPGA, with a maximum bandwidth of 64Gbps (PCIe Gen4 x16). The AXI interconnect protocol then utilizes the AXI4 bus to schedule data between FPGA modules, supporting multi-channel concurrent transmission and ensuring efficient task distribution and result return.

[0070] S2. Obtain key-mode parameters and dynamic control instructions generated in the CPU, and obtain plaintext-ciphertext batch data in the DDR, wherein the key-mode parameters include a master key, encryption mode parameters, and a function switching signal; the dynamic control instructions include instructions for starting / pausing data transmission and adjusting pipeline depth; and the plaintext-ciphertext batch data includes plaintext / ciphertext data blocks and intermediate state cache information.

[0071] The key-mode parameters include a master key, encryption mode parameters, and a function switching signal. The master key (MK) is used to generate round keys (rk0-rk31) and is the core input of the SM4 algorithm. Encryption mode parameters (such as the initialization vector (IV) for CBC and the counter value for CTR) control the context of the encryption process. The function switching signal (encryption / decryption, fixed key mode / changing key mode) determines the operating logic of the algorithm core.

[0072] The dynamic control instructions are instructions for controlling the progress and mode of data processing. The start / pause data transmission instructions manage the start and pause of FPGA data processing. The pipeline depth adjustment instructions manage the relationship between the pipeline and the number of parallel cores when the FPGA processes data.

[0073] The plaintext-ciphertext batch data refers to the data that needs to be processed during CPU tasks. Part of this data is encrypted during storage in the DDR, resulting in a mixture of plaintext and ciphertext data blocks. Furthermore, the intermediate state cache information refers to the intermediate results of the pipeline encryption process (such as the rk value after round key expansion). The DDR is used to preserve context during multi-core task switching.

[0074] In detail, in an embodiment of the present invention, obtaining the key-mode parameters and dynamic control instructions generated in the CPU, and obtaining the plaintext-ciphertext batch data in the DDR, includes:

[0075] Using a pre-built AXI-Lite bus, the key-mode parameters and dynamic control instructions generated in the CPU are sent to a pre-built control register in the acceleration block;

[0076] The pre-built AXI-Stream bus is used to send the plaintext and ciphertext batch data pre-loaded by the CPU in the DDR to the pre-built input cache module in the acceleration block.

[0077] The AXI-Lite bus is a streamlined, memory-mapped bus designed for low-throughput data transmission between a host (e.g., a CPU) and a slave (e.g., a peripheral register, or control register in this case). Control registers are key components for configuring hardware logic behavior and can be programmed to dynamically adjust the functions or parameters of various modules in the FPGA.

[0078] The AXI-Stream bus is a transmission line that requires no address management, supports burst transmissions of unlimited length, and transmits data in a continuous stream. The input buffer module, a component of the FPGA's input / output block (IOB), is responsible for receiving external signals and performing level conversion, noise filtering, and timing synchronization to ensure stable signal transmission to the FPGA's internal logic units.

[0079] Specifically, in this embodiment of the present invention, the AXI-Lite bus does not support burst transactions and can only read and write data at a single address (e.g., 32 or 64 bits) at a time. However, the channel structure includes independent read address, read data, write address, write data, and write response channels. Each channel implements a handshake mechanism via VALID and READY signals, making it suitable for effectively controlling the FPGA. The AXI-Lite bus transmits key-mode parameters and dynamic control instructions generated by the CPU to pre-built control registers in the acceleration block, thereby controlling the FPGA using the control registers.

[0080] Specifically, in this embodiment of the present invention, the AXI-Stream bus supports a high-speed channel design, containing only data-related signals (such as TDATA, TLAST, and TREADY), eliminating address lines and reducing protocol overhead. The AXI-Stream bus sends batches of plaintext and ciphertext data to a pre-built input buffer module within the acceleration block, which then uses the input buffer module to input the data into the acceleration block.

[0081] In this embodiment of the present invention, the AXI-Lite bus focuses on low-speed, precise register-level control, suitable for simple peripheral interaction, while the AXI-Stream bus is designed for high-speed, continuous data stream transmission, suitable for scenarios with high real-time requirements. The two are interconnected through the AXI Interconnect to achieve an efficient architecture that separates control and data.

[0082] Furthermore, it should be noted that the core operations of the SM4 algorithm (such as S-box transformations and round function iterations) can be implemented using the general-purpose computing power of the CPU, particularly with the SIMD instruction set (such as AVX and SSE) to optimize parallel processing. For example, using the CPU's vectorized instructions can achieve multi-group parallel encryption, but due to the CPU's serial execution architecture, it can easily become a performance bottleneck when processing massive amounts of data. SIMD (Single Instruction, Multiple Data) is a parallel computing technology that allows the processor to perform the same operation on multiple data elements simultaneously using a single instruction. Its core goal is to improve the computational efficiency of data-intensive tasks, especially in scenarios where large amounts of similar data need to be processed in batches.

[0083] Specifically, in an embodiment of the present invention, the CPU can use a pipeline optimization algorithm to generate instructions for adjusting the pipeline depth in dynamic control instructions based on task requirements. The pipeline shortens the critical path delay by splitting long paths into multiple short paths (by inserting registers), thereby increasing the clock frequency (i.e., increasing F). For example, a three-stage pipeline design with an original path delay of t can shorten the clock cycle to approximately t / 3, increasing the system speed by three times the original rate. This mechanism improves throughput by optimizing the timing efficiency of individual tasks (trading area for speed).

[0084] S3. Using the acceleration block, perform a data type identification operation on the plaintext-ciphertext batch data to obtain a data type, and dynamically configure resources for the plaintext-ciphertext batch data based on a pre-built parallelization strategy and the data type to obtain resource configuration information, and configure the configured SM4 algorithm based on the resource configuration information, key-mode parameters, and dynamic control instructions.

[0085] The data type identification operation refers to analyzing whether the data processed by the acceleration block is a large data stream scenario such as video encryption or a small data stream scenario similar to IoT instructions. The data types refer to the preset data types corresponding to the two data stream scenarios, including large data block types and small data block types.

[0086] The essence of this parallelization strategy is to leverage the independence of the FPGA's programmable logic cells to increase the number of operations per cycle (N) by processing multiple tasks simultaneously (e.g., multi-core, multi-channel designs), directly increasing throughput. For example, designing four parallel SM4 cores, each independently processing packet data, can theoretically increase throughput by four times.

[0087] Dynamic resource configuration refers to the configuration information for data sources, data retrieval, and processing methods. This resource configuration information refers to two types of dynamic resource configuration results: one that directly retrieves data from DDR and processes it in parallel, and the other that uses single-core processing, grouping data and processing multiple groups at once.

[0088] The process of configuring and obtaining a configured SM4 algorithm refers to optimizing the dedicated hardware architecture or instruction set in the SM4 algorithm to improve the execution efficiency of the SM4 symmetric encryption algorithm, thereby meeting the encryption requirements of high throughput and low latency. The configured SM4 algorithm represents an FPGA structure information with a configured architecture and instructions that can be used to implement the SM4 algorithm.

[0089] In detail, in an embodiment of the present invention, performing a data type identification operation on the plaintext-ciphertext batch data to obtain the data type includes:

[0090] Performing data block metadata analysis on the plaintext-ciphertext batch data to obtain data block size distribution and transmission interval characteristics;

[0091] Using a pre-built sliding time window, a throughput and delay correlation analysis is performed on the plaintext-ciphertext batch data to obtain the data processing volume and average response delay;

[0092] Performing feature-weighted calculation on the data block size distribution, transmission interval characteristics, data processing volume, and average response delay according to a preset weight coefficient sequence to obtain a data type score;

[0093] Obtain a size relationship between the data type score and a pre-constructed classification threshold, and obtain the data type based on the size relationship, wherein the data type includes a large data block type and a small data block type.

[0094] Data block metadata analysis refers to the process of analyzing the size, speed, and frequency of data in plaintext and ciphertext batches. Data block size distribution refers to the average amount of data transmitted in a single transaction. Large data streams typically exhibit continuous and uniform block sizes (e.g., 1MB-10MB / block), while small data blocks typically exhibit a discrete distribution (e.g., KB-level). Transmission interval characteristics refer to the high-frequency, continuous transmission characteristics of large data streams (e.g., microsecond-level intervals), while small data blocks exhibit low-frequency, bursty transmission characteristics (e.g., second-level intervals).

[0095] The sliding time window is a dynamic statistical or control mechanism that divides time into multiple consecutive or overlapping sub-windows, enabling flexible analysis of data or resource management within different time periods. Its core goal is to dynamically adjust the statistical range based on the passage of time, thereby more accurately reflecting system status or processing streaming data.

[0096] The throughput-latency correlation analysis refers to the process of calculating the data processing volume (TPS) and average response latency per unit time using a sliding time window. The data processing volume and average response latency refer to the fact that in large data flow scenarios, TPS and latency are linearly negatively correlated (latency increases sharply when resources are saturated), while in small data block scenarios, TPS fluctuates greatly and latency is relatively stable (low resource utilization).

[0097] The weight coefficient sequence refers to the influence score of each indicator on the data type size judgment, such as data block size distribution 0.3, transmission interval characteristics 0.3, data processing volume 0.2 and average response delay 0.2.

[0098] The feature weighted calculation refers to the process of weighting the probability scores of each feature for determining the data type. The data type score refers to the weighted result of the feature weighted calculation.

[0099] The classification threshold is configured as 50%.

[0100] Specifically, in this embodiment of the present invention, four metrics that can distinguish data flow types are obtained through two methods: data block metadata analysis and throughput and latency correlation analysis. These metrics are then weighted using a pre-built weight coefficient sequence. Finally, a weighted feature calculation is performed to obtain a data type score. If the data type score is less than 50%, the data type is determined to be a small data block type. If the data type score is greater than 50%, the data type is determined to be a large data block type.

[0101] In detail, in an embodiment of the present invention, the dynamic resource configuration of the plaintext-ciphertext batch data according to the pre-built parallelization strategy and the data type to obtain the resource configuration information includes:

[0102] Determining whether the data type is a large data block type or a small data block type according to a pre-built parallelization strategy;

[0103] When the data type is a large data block type, determining that the resource configuration information is first type configuration information;

[0104] When the data type is a small data block type, determining that the resource configuration information is second type configuration information;

[0105] The first type of configuration information includes: utilizing the CPU to obtain task-related data, utilizing the PCIe bus to preload the task-related data into the DDR for storage, and utilizing a pre-built FPGA multi-core parallel architecture and a 32-stage pipeline design to process the plaintext-ciphertext batch data;

[0106] Among them, the second type of configuration information includes using a pre-built bit slicing service to reorganize the plaintext and ciphertext batch data into a bit width supported by a preset SIMD instruction, obtain a data grouping result, and process multiple groups in the data grouping result in the same batch.

[0107] Among them, the first type of configuration information and the second type of configuration information and the methods of expressing the two types of resource configuration information described in the above-mentioned process of expressing "dynamic resource configuration" are not described in detail here.

[0108] The task-related data refers to massive amounts of data to be processed, such as traffic video data, financial trend data, etc.

[0109] The FPGA multi-core parallel architecture and 32-stage pipeline design are initialized FPGA operation modes. The processing of the plaintext-ciphertext batch data refers to encrypting the plaintext-ciphertext batch data with the SM4 algorithm.

[0110] Among them, the bit slicing service is an optimization implementation technology for cryptographic algorithms. Its core goal is to improve encryption efficiency through data reorganization and parallel processing, while enhancing the ability to resist side-channel attacks.

[0111] The bit width supported by SIMD instructions refers to the ability of SIMD to pack multiple data elements (such as pixel values, floating-point numbers, integers, etc.) into wide registers (such as 128-bit, 256-bit, or even 512-bit), allowing batch operations to be performed using a single instruction. The data grouping result refers to the groups of data after grouping. Batch processing refers to the simultaneous SM4 encryption of multiple groups of grouped data.

[0112] Specifically, in an embodiment of the present invention, resource configuration information is configured according to the data type. When the data type is a large data block type, the resource configuration information is determined to be first type configuration information. When the data type is a small data block type, the resource configuration information is determined to be second type configuration information.

[0113] In detail, in an embodiment of the present invention, configuring the configured SM4 algorithm according to the resource configuration information, key-mode parameters and dynamic control instructions includes:

[0114] Performing an acceleration architecture selection operation on a pre-built SM4 algorithm based on the resource configuration information;

[0115] Parsing the key-mode parameters to obtain a master key, encryption mode parameters, and a function switching signal, performing a key expansion operation based on a superimposed random mask on the master key according to a pre-built SM4 key expansion instruction to obtain a round key, and storing the round key in a pre-built secure storage area;

[0116] Configure the encryption process in the SM4 algorithm according to the encryption mode parameters, and configure the working logic in the SM4 algorithm according to the function switching signal;

[0117] According to the dynamic control instruction, a combination mode of the number of pipeline stages and the number of parallel cores in the SM4 algorithm is configured to obtain a configured SM4 algorithm.

[0118] The SM4 algorithm is a commercial cryptographic algorithm issued by the China National Cryptography Administration, which is a block cipher and is commonly used for data encryption.

[0119] Among them, the acceleration architecture selection operation refers to configuring the data retrieval and processing method in the SM4 algorithm as the first type of configuration information or the second type of configuration information in the resource configuration information.

[0120] The parsing refers to the process of regularizing and standardizing the key-mode parameter content. The SM4 key expansion instruction refers to the standardized process instruction in the SM4 algorithm.

[0121] The key expansion operation based on superimposed random masks refers to the addition of a true random number (TRNG) to each key expansion process. The key expansion process involves generating round keys from an initial key using the SM4 key expansion instruction and storing them in a secure storage area. Key operands contain multiple round keys, supporting dynamic switching (e.g., changing keys for each batch of data). Superimposing the random mask generated by the TRNG during the key expansion process can disrupt the correlation of side-channel attacks.

[0122] The round key refers to the key expansion result of the master key in a certain round. The secure storage area refers to a storage area such as TEE or encrypted BRAM.

[0123] The encryption mode parameters may support ECB, CBC, CTR, etc. For example, the CBC mode requires configuring an initialization vector and writing it into a register via AXI-Lite.

[0124] The configuration of the encryption process in the SM4 algorithm refers to selecting a type of control encryption mode parameters, such as ECB, CBC, CTR, etc.

[0125] The configuring of the working logic in the SM4 algorithm refers to configuring the start and pause functions.

[0126] Configuring the combination of pipeline stages and parallel core count in the SM4 algorithm involves monitoring the data queue depth and dynamically adjusting the pipeline stages or core count. For example, when the queue depth is greater than 8KB, 4-core parallelism is enabled, and otherwise, single-core high-frequency mode is switched.

[0127] Specifically, in an embodiment of the present invention, the above content is a configuration scheme, and an electronic design automation (EDA) tool can be executed to program the FPGA structure according to the structure of the SM4 algorithm, and then according to resource configuration information, key-mode parameters, master key, encryption mode parameters, function switching signals and dynamic control instructions to obtain a configured SM4 algorithm.

[0128] S4. Encrypt the plaintext-ciphertext batch data according to the configured SM4 algorithm to obtain encrypted data to be protected.

[0129] In this embodiment of the present invention, the configured SM4 algorithm still uses the calculation process of the national standard SM4 algorithm, but it has been accelerated in terms of data retrieval efficiency. Therefore, the process of encrypting batches of plaintext and ciphertext data is not described in detail here. The encrypted data to be protected refers to the encryption result of the configured SM4 algorithm on the batches of plaintext and ciphertext data.

[0130] S5. Utilize the protection block to perform protection operations based on physical layer leakage suppression, logical layer obfuscation association, and system layer dynamic response on the key-mode parameters, dynamic control instructions, plaintext-ciphertext batch data, and the encryption processing process, and convert the encrypted data to be protected into protected encrypted data.

[0131] The protection operation refers to a specific implementation method for improving the security of the encryption result.

[0132] The physical layer leakage suppression method refers to the method of protecting hardware through physical methods. The logical layer obfuscation association method refers to the protection method of randomizing intermediate values in the calculation process to ensure that a single point of leakage cannot restore the key information. The system layer dynamic response method refers to the use of AI to extract time series features during system processing and data transmission to determine whether there is an attacker interfering with the data encryption process.

[0133] The protected encrypted data refers to the encrypted data to be protected that has passed the security authentication of each protection process.

[0134] In detail, in an embodiment of the present invention, the protection block is used to perform protection operations based on physical layer leakage suppression, logical layer obfuscation association, and system layer dynamic response on the key-mode parameters, dynamic control instructions, plaintext-ciphertext batch data, and the encryption process, including:

[0135] Using the protection block, the encryption process is subjected to a signal weakening operation based on power consumption and electromagnetic radiation characteristics, and a correlation perturbation operation based on timing and clock jitter, thereby completing the physical layer leakage suppression process;

[0136] Performing an intermediate value randomization operation on the encryption process to complete the logic layer obfuscation association process;

[0137] A system-level dynamic response process based on abnormal event detection and response is performed on the AXI-Lite bus and the AXI-Stream bus.

[0138] Among them, the signal attenuation operation based on power consumption and electromagnetic radiation characteristics means that during the data transmission process, information may be exposed due to the power consumption and electromagnetic radiation generated by each unit and route. Therefore, weakening this information, such as balancing the power consumption in each process, or covering the electromagnetic radiation through a layer, can effectively reduce information leakage.

[0139] The perturbation operation based on the correlation between timing and clock jitter means that an attacker can perform a timing attack through the correlation between timing and clock jitter. By perturbing the correlation between timing and clock jitter, the attacker's correlation analysis of read and write timing can be disrupted.

[0140] Among them, the intermediate value randomization operation refers to an operation used to ensure that a single point of leakage cannot restore the key information, such as inserting a dual-track redundant computing module in the encryption pipeline, comparing output consistency in real time, and detecting and blocking fault injection attacks.

[0141] The system-level dynamic response process based on abnormal event detection and response refers to the process of detecting abnormal events during data transmission and processing using AI models, and autonomously handling them based on the detection results. For example, when a low risk is detected, redundant checking is disabled to improve performance; when an attack is detected, a 3rd-order threshold mask is enabled.

[0142] In detail, in an embodiment of the present invention, the use of the protection block to perform a signal attenuation operation based on power consumption and electromagnetic radiation characteristics, and a correlation perturbation operation based on timing and clock jitter on the encryption process includes:

[0143] Using the pre-built adjustable load circuit in the protection block, a power consumption difference balancing operation is performed on the encryption process during the operation phase;

[0144] Using a pre-built metal shielding layer to cover the preset high leakage risk area in the configured SM4 algorithm;

[0145] A timing perturbation operation is performed on data transmission in the AXI-Lite bus and the AXI-Stream bus using pre-constructed true random numbers.

[0146] The adjustable load circuit is an electronic system that can dynamically adjust equivalent resistance or load parameters, and is mainly used to simulate different load conditions and test the performance of power supplies, batteries or other power supply devices.

[0147] The power consumption difference balancing operation in the operation phase refers to embedding an adjustable load circuit in the FPGA logic unit to balance the power consumption differences in different operation phases of the SM4 algorithm (such as S-box replacement and round key XOR), thereby weakening the effectiveness of differential power analysis (DPA).

[0148] The metal shielding layer is made of a material that can shield or suppress electromagnetic waves. The cover is used to shield electromagnetic waves.

[0149] The true random number refers to a randomly generated number or character. The timing perturbation operation refers to introducing a timing perturbation based on a true random number (TRNG) in the AXI bus transmission path to disrupt the attacker's correlation analysis of the read and write timings.

[0150] Specifically, in an embodiment of the present invention, a pre-constructed adjustable load circuit in the protection block is used to balance the power consumption differences in the operation phase of the encryption processing, which is beneficial to weakening the effectiveness of differential power consumption analysis; a pre-constructed metal shielding layer is used to cover the preset high leakage risk area in the configured SM4 algorithm to suppress the electromagnetic radiation signal during the encryption processing; a pre-constructed true random number is used to perform a timing perturbation operation on the data transmission in the AXI-Lite bus and the AXI-Stream bus to disrupt the attacker's correlation analysis of the read and write timing, thereby completing the physical layer leakage suppression process.

[0151] In detail, in an embodiment of the present invention, the intermediate value randomization operation is performed on the encryption process to complete the logic layer obfuscation association process, including:

[0152] Performing threshold segmentation on intermediate values preset during the encryption process, wherein the intermediate values include S-box outputs and round function intermediate values;

[0153] The pre-built dual-track redundant calculation module in the protection block is used to perform real-time comparison and output consistency on the encryption process, completing the logic layer obfuscation association process.

[0154] The intermediate value refers to the S-box output and the intermediate value of the round function.

[0155] Threshold partitioning is a cryptographic technique that breaks sensitive information (such as keys or data) into multiple independent parts (called "shares" or "shadows") and distributes them to different participants. Only when a predetermined number of shares (known as a "threshold") are combined can the original secret be recovered.

[0156] Among them, the dual-track redundant computing module is a hardware redundancy technology that improves system reliability through parallel computing and real-time verification. Its core principle is to synchronously execute the same task through two independent computing units and compare the output results to detect or correct errors.

[0157] Real-time output consistency comparison refers to the system's real-time monitoring and comparison of output results from different data sources or processing flows in dynamic data scenarios, ensuring consistency in content, status, or logical relationships. Its core goal is to quickly identify and locate inconsistent nodes during continuous data updates, thereby ensuring business accuracy and reliability.

[0158] Specifically, in an embodiment of the present invention, multiplication mask and threshold can be used to implement: threshold segmentation of S-box output and intermediate values of round functions (such as third-order threshold mask) to ensure that single-point leakage cannot restore key information. Redundant check logic can be used to implement: inserting a dual-track redundant calculation module into the encryption pipeline, comparing output consistency in real time, detecting and blocking fault injection attacks, thereby completing the intermediate value randomization operation and realizing the logic layer obfuscation association process.

[0159] In detail, in an embodiment of the present invention, the system-level dynamic response process based on abnormal event detection and response for the AXI-Lite bus and the AXI-Stream bus includes:

[0160] Using the pre-built CNN attack recognition model in the protection block, the AXI-Lite bus and the AXI-Stream bus are subjected to attack pattern recognition and monitoring based on timing characteristics to obtain the target attack pattern;

[0161] According to the preset dynamic switching strategy, the target attack mode type is protected to complete the system layer dynamic response process.

[0162] The CNN attack recognition model refers to a lightweight, easily trained CNN neural network that detects attacks and identifies attack patterns based on the timing characteristics of anomalies in data transmission and processing. Attack pattern recognition monitoring refers to the execution of the CNN attack recognition model. The target attack pattern refers to the recognition result of the CNN attack recognition model, which can include no attack, DoS attack, or fault injection attack.

[0163] The dynamic switching strategy refers to adjusting the protection strength according to the threat level. The protection refers to the execution process of the dynamic switching strategy, for example, when the risk is low, redundancy check is disabled to improve performance, and when an attack is detected, the third-order threshold mask is enabled.

[0164] Specifically, in the embodiment of the present invention, a CNN attack recognition model is used to detect attacks on the data transmission and processing timing information in the AXI-Lite bus and the AXI-Stream bus. Once an attacker is detected, protection is automatically performed according to a dynamic switching strategy, thereby completing the dynamic response process at the system layer.

[0165] Specifically, in an embodiment of the present invention, a full-stack protection system is constructed with physical layer leakage suppression, logical layer confusion association, and system layer dynamic response. If the encrypted data to be protected passes the authentication of the above protection process, the encrypted data to be protected will be converted into protected encrypted data.

[0166] The present invention aims to solve the problems described in the background technology. The SM4 algorithm in the FPGA of the present invention obtains data from both the CPU and the DDR. Among them, the plaintext and ciphertext batch data sent by the DDR is the main data to be processed. Through the collaboration between the DDR memory and the FPGA, massive data can be processed quickly, thereby improving data processing efficiency. The key-mode parameters and dynamic control instructions sent by the CPU have a small amount of data, but play a controlling role on the SM4 algorithm in the FPGA. In this solution, the CPU will adjust the pipeline depth in the FPGA in advance according to the task requirements, and the present invention also configures parallelization in the acceleration block in the FPGA. The strategy uses pipeline depth adjustment and parallelization strategies to optimize single-core timing efficiency, while parallelization expands multi-core processing capabilities. These two complementary goals improve the processing efficiency of the acceleration block. Furthermore, due to changes in the SM4 algorithm encryption processing within the acceleration block, as well as changes in the data acquisition paths from the CPU and DDR, the anti-side channel protection scheme must also change. The present invention adaptively implements anti-side channel protection for changes in the protection block from three aspects: physical layer leakage suppression, logical layer obfuscation association, and system layer dynamic response. This ensures overall system security while maintaining SM4 hardware acceleration. Therefore, the present invention can improve encryption processing performance and security.

[0167] like Figure 2 , which is a functional module diagram of the SM4 hardware acceleration and anti-side channel protection system of the domestic FPGA provided by one embodiment of the present invention.

[0168] The SM4 hardware acceleration and anti-side-channel protection system 100 for a domestically produced FPGA can be installed in an electronic device. Depending on the functionality implemented, the SM4 hardware acceleration and anti-side-channel protection system 100 can include a data acquisition module 101, an SM4 algorithm acceleration configuration module 102, and an anti-side-channel protection module 103. A module, also referred to as a unit, refers to a series of computer program segments that can be executed by an electronic device processor and perform a fixed function, and is stored in the electronic device's memory.

[0169] The data acquisition module 101 is configured to connect a pre-built adaptive acceleration and protection FPGA to a pre-built target computer using a pre-built PCIe bus, wherein the adaptive acceleration and protection FPGA includes an acceleration block and a protection block, and the target computer includes a CPU and a DDR, and to obtain key-mode parameters and dynamic control instructions generated in the CPU, and to obtain plaintext and ciphertext batch data in the DDR, wherein the key-mode parameters include a master key, an encryption mode parameter, and a function switching signal, the dynamic control instructions include instructions for starting / pausing data transmission and adjusting pipeline depth, and the plaintext and ciphertext batch data includes plaintext / ciphertext data blocks and intermediate state cache information;

[0170] The SM4 algorithm acceleration configuration module 102 is configured to use the acceleration block to perform a data type identification operation on the plaintext-ciphertext batch data to obtain a data type, and to perform dynamic resource configuration on the plaintext-ciphertext batch data according to a pre-built parallelization strategy and the data type to obtain resource configuration information, and to configure the configured SM4 algorithm according to the resource configuration information, key-mode parameters, and dynamic control instructions;

[0171] The anti-side channel protection module 103 is used to encrypt the plaintext and ciphertext batch data according to the configured SM4 algorithm to obtain the encrypted data to be protected, and use the protection block to perform protection operations based on physical layer leakage suppression, logical layer obfuscation association and system layer dynamic response on the key-mode parameters, dynamic control instructions, plaintext and ciphertext batch data and the encryption processing process, thereby converting the encrypted data to be protected into protected encrypted data.

[0172] In detail, the modules in the SM4 hardware acceleration and anti-side channel protection system 100 of the domestic FPGA in the embodiment of the present invention are used in the same manner as above. Figure 1 The SM4 hardware acceleration of the domestic FPGA described in the article uses the same technical means as the anti-side channel protection method and can produce the same technical effects, so I will not go into details here.

[0173] like Figure 3 , which is a schematic structural diagram of an electronic device for implementing a method for SM4 hardware acceleration and anti-side channel protection of a domestic FPGA provided by an embodiment of the present invention.

[0174] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and run on the processor 10, such as the SM4 hardware acceleration and anti-side channel protection method program of the domestic FPGA.

[0175] The memory 11 includes at least one type of readable storage medium, including flash memory, a removable hard drive, a multimedia card, a card-type memory (e.g., SD or DX memory), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as a removable hard drive of the electronic device 1. In other embodiments, the memory 11 may also be an external storage device of the electronic device 1, such as a plug-in removable hard drive, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. Furthermore, the memory 11 includes both internal storage units of the electronic device 1 and external storage devices. The memory 11 can be used not only to store application software installed in the electronic device 1 and various types of data, such as the code for the SM4 hardware acceleration and anti-side-channel protection method program for a domestic FPGA, but also to temporarily store data that has been output or is about to be output.

[0176] In some embodiments, the processor 10 may be comprised of an integrated circuit, such as a single packaged integrated circuit or multiple packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and a combination of various control chips. The processor 10 is the control core (control unit) of the electronic device, connecting the various components of the entire electronic device using various interfaces and circuits. It executes programs or modules stored in the memory 11 (such as the SM4 hardware acceleration and anti-side channel protection method program for a domestic FPGA) and accesses data stored in the memory 11 to perform various functions and process data.

[0177] The bus 12 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus 12 may be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to enable communication between the memory 11 and at least one processor 10, etc.

[0178] Figure 3 Only the electronic device with components is shown, and it can be understood by those skilled in the art that Figure 3The structure shown does not constitute a limitation on the electronic device 1 , and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0179] For example, although not shown, the electronic device 1 may further include a power supply (e.g., a battery) to power various components. Preferably, the power supply may be logically connected to the at least one processor 10 via a power management device, thereby enabling functions such as charge management, discharge management, and power consumption management via the power management device. The power supply may further include any components such as one or more DC or AC power supplies, a recharging device, a power failure detection circuit, a power converter or inverter, and a power status indicator. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which are not further described here.

[0180] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0181] Optionally, the electronic device 1 may further include a user interface, which may be a display or an input unit (such as a keyboard). Optionally, the user interface may also be a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display may also be appropriately referred to as a display screen or a display unit, and is used to display information processed by the electronic device 1 and to display a visual user interface.

[0182] The SM4 hardware acceleration and anti-side channel protection method program of the domestic FPGA stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can achieve:

[0183] Using a pre-built PCIe bus, connecting a pre-built adaptive acceleration and protection FPGA to a pre-built target computer, wherein the adaptive acceleration and protection FPGA includes an acceleration block and a protection block, and the target computer includes a CPU and a DDR;

[0184] Obtaining key-mode parameters and dynamic control instructions generated by the CPU, and obtaining plaintext-ciphertext batch data in the DDR, wherein the key-mode parameters include a master key, encryption mode parameters, and a function switching signal; the dynamic control instructions include instructions for starting / pausing data transmission and adjusting pipeline depth; and the plaintext-ciphertext batch data includes plaintext / ciphertext data blocks and intermediate state cache information;

[0185] Using the acceleration block, performing a data type identification operation on the plaintext-ciphertext batch data to obtain a data type, and dynamically configuring resources for the plaintext-ciphertext batch data according to a pre-built parallelization strategy and the data type to obtain resource configuration information, and configuring a configured SM4 algorithm according to the resource configuration information, a key-mode parameter, and a dynamic control instruction;

[0186] Encrypting the plaintext-ciphertext batch data according to the configured SM4 algorithm to obtain encrypted data to be protected;

[0187] By utilizing the protection block, the key-mode parameters, dynamic control instructions, plaintext-ciphertext batch data and the encryption processing process are subjected to protection operations based on physical layer leakage suppression, logical layer confusion association and system layer dynamic response, thereby converting the encrypted data to be protected into protected encrypted data.

[0188] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 3 The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0189] Furthermore, if the modules / units integrated into the electronic device 1 are implemented as software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium. The computer-readable storage medium may be volatile or non-volatile. For example, the computer-readable medium may include any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0190] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program. When the computer program is executed by a processor of an electronic device, the computer program can implement:

[0191] Using a pre-built PCIe bus, connecting a pre-built adaptive acceleration and protection FPGA to a pre-built target computer, wherein the adaptive acceleration and protection FPGA includes an acceleration block and a protection block, and the target computer includes a CPU and a DDR;

[0192] Obtaining key-mode parameters and dynamic control instructions generated by the CPU, and obtaining plaintext-ciphertext batch data in the DDR, wherein the key-mode parameters include a master key, encryption mode parameters, and a function switching signal; the dynamic control instructions include instructions for starting / pausing data transmission and adjusting pipeline depth; and the plaintext-ciphertext batch data includes plaintext / ciphertext data blocks and intermediate state cache information;

[0193] Using the acceleration block, performing a data type identification operation on the plaintext-ciphertext batch data to obtain a data type, and dynamically configuring resources for the plaintext-ciphertext batch data according to a pre-built parallelization strategy and the data type to obtain resource configuration information, and configuring a configured SM4 algorithm according to the resource configuration information, a key-mode parameter, and a dynamic control instruction;

[0194] Encrypting the plaintext-ciphertext batch data according to the configured SM4 algorithm to obtain encrypted data to be protected;

[0195] By utilizing the protection block, the key-mode parameters, dynamic control instructions, plaintext-ciphertext batch data and the encryption processing process are subjected to protection operations based on physical layer leakage suppression, logical layer confusion association and system layer dynamic response, thereby converting the encrypted data to be protected into protected encrypted data.

[0196] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only exemplary, and actual implementations may have other division methods.

[0197] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of the modules may be selected to achieve the purpose of the solution of this embodiment according to actual needs.

[0198] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or hardware plus software functional modules.

[0199] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0200] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for SM4 hardware acceleration and anti-side channel protection of domestic FPGA, characterized in that: The method comprises: Using a pre-built PCIe bus, connecting a pre-built adaptive acceleration and protection FPGA to a pre-built target computer, wherein the adaptive acceleration and protection FPGA includes an acceleration block and a protection block, and the target computer includes a CPU and a DDR; Obtaining key-mode parameters and dynamic control instructions generated by the CPU, and obtaining plaintext-ciphertext batch data in the DDR, wherein the key-mode parameters include a master key, encryption mode parameters, and a function switching signal; the dynamic control instructions include instructions for starting / pausing data transmission and adjusting pipeline depth; and the plaintext-ciphertext batch data includes plaintext / ciphertext data blocks and intermediate state cache information; Using the acceleration block, performing a data type identification operation on the plaintext-ciphertext batch data to obtain a data type, and dynamically configuring resources for the plaintext-ciphertext batch data according to a pre-built parallelization strategy and the data type to obtain resource configuration information, and configuring a configured SM4 algorithm according to the resource configuration information, a key-mode parameter, and a dynamic control instruction; Encrypting the plaintext-ciphertext batch data according to the configured SM4 algorithm to obtain encrypted data to be protected; By utilizing the protection block, the key-mode parameters, dynamic control instructions, plaintext-ciphertext batch data and the encryption processing process are subjected to protection operations based on physical layer leakage suppression, logical layer confusion association and system layer dynamic response, thereby converting the encrypted data to be protected into protected encrypted data.

2. The SM4 hardware acceleration and anti-side channel protection method for domestic FPGAs according to claim 1 is characterized in that: The obtaining of the key-mode parameters and dynamic control instructions generated in the CPU, and obtaining the plaintext-ciphertext batch data in the DDR, includes: Using a pre-built AXI-Lite bus, the key-mode parameters and dynamic control instructions generated in the CPU are sent to a pre-built control register in the acceleration block; The pre-built AXI-Stream bus is used to send the plaintext and ciphertext batch data pre-loaded by the CPU in the DDR to the pre-built input cache module in the acceleration block.

3. The SM4 hardware acceleration and anti-side channel protection method for domestic FPGAs according to claim 2, characterized in that: The performing a data type identification operation on the plaintext-ciphertext batch data to obtain the data type includes: Performing data block metadata analysis on the plaintext-ciphertext batch data to obtain data block size distribution and transmission interval characteristics; Using a pre-built sliding time window, a throughput and delay correlation analysis is performed on the plaintext-ciphertext batch data to obtain the data processing volume and average response delay; Performing feature-weighted calculation on the data block size distribution, transmission interval characteristics, data processing volume, and average response delay according to a preset weight coefficient sequence to obtain a data type score; Obtain a size relationship between the data type score and a pre-constructed classification threshold, and obtain the data type based on the size relationship, wherein the data type includes a large data block type and a small data block type.

4. The SM4 hardware acceleration and anti-side channel protection method for domestic FPGAs as described in claim 3 is characterized in that: The method of dynamically configuring resources for the plaintext-ciphertext batch data according to the pre-built parallelization strategy and the data type to obtain resource configuration information includes: Determining whether the data type is a large data block type or a small data block type according to a pre-built parallelization strategy; When the data type is a large data block type, determining that the resource configuration information is first type configuration information; When the data type is a small data block type, determining that the resource configuration information is second type configuration information; The first type of configuration information includes: utilizing the CPU to obtain task-related data, utilizing the PCIe bus to preload the task-related data into the DDR for storage, and utilizing a pre-built FPGA multi-core parallel architecture and a 32-stage pipeline design to process the plaintext-ciphertext batch data; Among them, the second type of configuration information includes using a pre-built bit slicing service to reorganize the plaintext and ciphertext batch data into a bit width supported by a preset SIMD instruction, obtain a data grouping result, and process multiple groups in the data grouping result in the same batch.

5. The SM4 hardware acceleration and anti-side channel protection method for domestic FPGAs as described in claim 4 is characterized in that: The configuring of the configured SM4 algorithm according to the resource configuration information, the key-mode parameter and the dynamic control instruction includes: Performing an acceleration architecture selection operation on a pre-built SM4 algorithm based on the resource configuration information; Parsing the key-mode parameters to obtain a master key, encryption mode parameters, and a function switching signal, performing a key expansion operation based on a superimposed random mask on the master key according to a pre-built SM4 key expansion instruction to obtain a round key, and storing the round key in a pre-built secure storage area; Configure the encryption process in the SM4 algorithm according to the encryption mode parameters, and configure the working logic in the SM4 algorithm according to the function switching signal; According to the dynamic control instruction, a combination mode of the number of pipeline stages and the number of parallel cores in the SM4 algorithm is configured to obtain a configured SM4 algorithm.

6. The SM4 hardware acceleration and anti-side channel protection method for domestic FPGAs according to claim 5, characterized in that: The protection block is used to perform protection operations based on physical layer leakage suppression, logical layer obfuscation association, and system layer dynamic response on the key-mode parameters, dynamic control instructions, plaintext-ciphertext batch data, and the encryption process, including: Using the protection block, the encryption process is subjected to a signal weakening operation based on power consumption and electromagnetic radiation characteristics, and a correlation perturbation operation based on timing and clock jitter, thereby completing the physical layer leakage suppression process; Performing an intermediate value randomization operation on the encryption process to complete the logic layer obfuscation association process; A system-level dynamic response process based on abnormal event detection and response is performed on the AXI-Lite bus and the AXI-Stream bus.

7. The SM4 hardware acceleration and anti-side channel protection method for domestic FPGAs according to claim 6, characterized in that: The method of using the protection block to perform a signal weakening operation based on power consumption and electromagnetic radiation characteristics, and a correlation perturbation operation based on timing and clock jitter on the encryption process includes: Using the pre-built adjustable load circuit in the protection block, a power consumption difference balancing operation is performed on the encryption process during the operation phase; Using a pre-built metal shielding layer to cover the preset high leakage risk area in the configured SM4 algorithm; A timing perturbation operation is performed on data transmission in the AXI-Lite bus and the AXI-Stream bus using pre-constructed true random numbers.

8. The SM4 hardware acceleration and anti-side channel protection method for domestic FPGA according to claim 7, characterized in that: The process of performing intermediate value randomization operation on the encryption process to complete the logic layer obfuscation association process includes: Performing threshold segmentation on intermediate values preset during the encryption process, wherein the intermediate values include S-box outputs and round function intermediate values; The pre-built dual-track redundant calculation module in the protection block is used to perform real-time comparison and output consistency on the encryption process, completing the logic layer obfuscation association process.

9. The SM4 hardware acceleration and anti-side channel protection method for domestic FPGAs according to claim 8, characterized in that: The system-level dynamic response process based on abnormal event detection and response for the AXI-Lite bus and the AXI-Stream bus includes: Using the pre-built CNN attack recognition model in the protection block, the AXI-Lite bus and the AXI-Stream bus are subjected to attack pattern recognition and monitoring based on timing characteristics to obtain the target attack pattern; According to the preset dynamic switching strategy, the target attack mode type is protected to complete the system layer dynamic response process.

10. A domestic FPGA SM4 hardware acceleration and anti-side channel protection system, characterized in that: The system comprises: a data acquisition module, configured to connect a pre-built adaptive acceleration and protection FPGA to a pre-built target computer using a pre-built PCIe bus, wherein the adaptive acceleration and protection FPGA includes an acceleration block and a protection block, and the target computer includes a CPU and a DDR, and to acquire key-mode parameters and dynamic control instructions generated in the CPU, and to acquire plaintext-ciphertext batch data in the DDR, wherein the key-mode parameters include a master key, an encryption mode parameter, and a function switching signal, the dynamic control instructions include instructions for starting / pausing data transmission and adjusting pipeline depth, and the plaintext-ciphertext batch data includes plaintext / ciphertext data blocks and intermediate state cache information; an SM4 algorithm acceleration configuration module, configured to utilize the acceleration block to perform a data type identification operation on the plaintext-ciphertext batch data to obtain a data type, and to perform dynamic resource configuration on the plaintext-ciphertext batch data based on a pre-built parallelization strategy and the data type to obtain resource configuration information, and to configure a configured SM4 algorithm based on the resource configuration information, key-mode parameters, and dynamic control instructions; An anti-side channel protection module is used to encrypt the plaintext and ciphertext bulk data according to the configured SM4 algorithm to obtain the encrypted data to be protected, and use the protection block to perform protection operations based on physical layer leakage suppression, logical layer obfuscation association and system layer dynamic response on the key-mode parameters, dynamic control instructions, plaintext and ciphertext bulk data and the encryption processing process, thereby converting the encrypted data to be protected into protected encrypted data.

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