Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The forming method comprises the following steps: forming a stacked film layer on a substrate; forming a mask layer on the stacked film layer, wherein the mask layer comprises a mask opening; forming a spacer layer on the side wall of the mask opening; etching the stacked film layer and the substrate by taking the mask layer and the spacing layer as masks so as to form a first groove in the stacked film layer, and forming a first groove in the substrate; performing an etching process to reduce the thickness of the first semiconductor layer and respectively form a second trench and a second groove in the stacked film layer and the substrate, and forming a protection layer in the second groove; wherein in the first direction, the width of the second groove is larger than that of the first groove, and the width of the second groove is larger than that of the first groove. According to the forming method, the protection material layer can be prevented from remaining, and the stability of the performance of the formed device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] Memory is widely used in mobile devices such as mobile phones and tablet computers due to its advantages of small volume, high integration level, and fast transmission speed. The memory includes a plurality of chip units integrated on a wafer. However, during the manufacturing process, affected by the manufacturing process, the number of chip units integrated on a single wafer is small, and the storage density is low.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), which usually includes a plurality of transistors stacked on a substrate, meets the above requirements. To form a stacked multilayer horizontal memory cell, an initial stacked film layer needs to be formed on the substrate, and then processes such as etching and ion implantation are performed on the stacked film layer. During this process, a thinning process needs to be performed on some of the stacked film layers. Due to the increase in the number of stacked layers and the limitation of the thinning process, the lengths of the thinned film layers are inconsistent, resulting in inconsistent device performance, thereby affecting the overall performance of the finally formed semiconductor device.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The present disclosure provides a semiconductor structure and a method for forming the same, which can improve the storage density without increasing the number of layers of the first semiconductor layer, and at the same time reduce the lateral loss of the semiconductor layer in the thinning process, and improve the stability of the performance of the formed device.

[0006] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, including:

[0007] Forming a stacked film layer on a substrate, the stacked film layer including a plurality of first semiconductor layers and second semiconductor layers alternately distributed in a second direction, the plurality of first semiconductor layers extending in a first direction, the second direction intersecting the first direction;

[0008] Forming a mask layer on the stacked film layer, the mask layer including a mask opening;

[0009] Forming a spacer layer on the sidewall of the mask opening;

[0010] Using the mask layer and the spacer layer as a mask, etch the stacked film layer and the substrate to form a first trench in the stacked film layer and a first groove in the substrate. The first trench penetrates through each of the first semiconductor layers along the second direction, and the first trench communicates with the first groove;

[0011] Perform an etching process to thin the thickness of the first semiconductor layer and form a second trench and a second groove in the stacked film layer and the substrate respectively. The second trench communicates with the second groove;

[0012] Form a protective layer in the second groove;

[0013] Wherein, along the first direction, the width of the second trench is greater than the width of the first trench and the width of the second groove is greater than the width of the first groove.

[0014] In an exemplary embodiment of the present disclosure, the etching process includes:

[0015] Perform a lateral etching on the second semiconductor layer through the first trench to remove the second semiconductor layer and form a gap between the adjacent first semiconductor layers along the second direction;

[0016] Perform an isotropic wet etching process on the first semiconductor layer through the gap and the first trench to thin the thickness of the first semiconductor layer.

[0017] In an exemplary embodiment of the present disclosure, the step of forming the spacer layer on the sidewall of the mask opening includes:

[0018] Form a spacer material layer on the top of the mask layer, the top of the stacked film layer, and the sidewall of the mask opening, and remove the spacer material layer located on the top of the mask layer and the top of the stacked film layer. The spacer material layer located on the sidewall of the mask opening forms the spacer layer.

[0019] In an exemplary embodiment of the present disclosure, the spacer material layer is formed by an atomic layer deposition process.

[0020] In an exemplary embodiment of the present disclosure, the material of the spacer layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon oxynitride.

[0021] In an exemplary embodiment of the present disclosure, before forming the protective layer in the second groove, it further includes:

[0022] Remove the spacer layer.

[0023] In an exemplary embodiment of the present disclosure, the material of the protective layer is one or more of polysilicon, low-k dielectric material, and silicon nitride.

[0024] In an exemplary embodiment of the present disclosure, the material of the mask layer is different from the material of the spacer layer.

[0025] In an exemplary embodiment of the present disclosure, the material of the first semiconductor layer is single-crystalline silicon, and the material of the second semiconductor layer is silicon germanium.

[0026] According to another aspect of the present disclosure, there is provided a semiconductor structure formed by the method for forming a semiconductor structure described in any one of the above.

[0027] The semiconductor structure and the method for forming the same of the present disclosure form a plurality of first semiconductor layers distributed along the second direction on a substrate, so that more first semiconductor layers can be integrated per unit area, providing a basis for manufacturing more chip units. By etching the first semiconductor layer to reduce its thickness, a larger process space can be reserved for preparing word lines between two adjacent first semiconductor layers distributed along the second direction subsequently, which helps to reduce the process difficulty of manufacturing word lines subsequently. At the same time, before etching the stacked film layer through the mask layer, a spacer layer is formed on the sidewall of the mask opening to reduce the size of the mask opening, so that after etching to form the first trench, the size of the first semiconductor layer in the first direction is greater than the preset size, thereby offsetting the loss of the first semiconductor layer in the first direction caused by isotropic etching in the subsequent thinning process and improving the performance stability of the formed semiconductor device. In addition, the process steps of forming a protective layer on the sidewall of the first semiconductor layer by using an additional process and removing the protective layer after the thinning process can be avoided, improving the efficiency of the manufacturing process and helping to reduce the manufacturing cost.

[0028] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0030] Figure 1 It is a schematic diagram of a method for forming a semiconductor structure in the existing process.

[0031] Figure 2It is a flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0032] Figure 3 It is a schematic diagram of forming a stacked film layer in an embodiment of the present disclosure.

[0033] Figure 4 It is a schematic diagram of forming a mask layer in an embodiment of the present disclosure.

[0034] Figure 5 It is a schematic diagram of forming a spacer material layer in an embodiment of the present disclosure.

[0035] Figure 6 It is a schematic diagram of forming a spacer layer in an embodiment of the present disclosure.

[0036] Figure 7 It is a schematic diagram of forming a first trench in an embodiment of the present disclosure.

[0037] Figure 8 It is a schematic diagram of forming a gap in an embodiment of the present disclosure.

[0038] Figure 9 It is a schematic diagram after an etching process in an embodiment of the present disclosure.

[0039] Figure 10 It is a schematic diagram of forming a protective material layer in an embodiment of the present disclosure.

[0040] Figure 11 It is a schematic diagram of forming a protective layer in an embodiment of the present disclosure.

[0041] In the figure: 1. Substrate; 2. Stacked film layer; 21. First semiconductor layer; 22. Protective layer; 23. Second semiconductor layer; 24. Mask layer; 241. Mask opening; 25. Spacer material layer; 26. Spacer layer; 201. First trench; 2011. Second trench; 202. First groove; 2021. Second groove; 204. Gap; 27. Dielectric layer; 28. Protective material layer; 29. Protective layer; x. First direction; y. Second direction. Detailed implementation manners

[0042] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0043] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0044] The terms "a", "an", "the", "said" and "at least one" are used to denote the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to denote an open-ended inclusion meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second" are used only as labels and are not a limitation on the quantity of their objects.

[0045] In the manufacturing process of 3D dynamic random access memory (DRAM), in order to improve the storage density, multiple semiconductor groups are usually formed on a substrate with lateral spacing. Each semiconductor group includes multiple first semiconductor layers distributed longitudinally. At the same time, in order to facilitate the preparation of word lines between two adjacent first semiconductor layers distributed longitudinally, the first semiconductor layer needs to be thinned. However, during the process of thinning the first semiconductor layer, the lateral loss of the first semiconductor layer is relatively large, resulting in a relatively large spacing between adjacent semiconductor groups distributed laterally. As a result, the number of chip units formed based on it in the lateral direction is small and the storage density is low. On the other hand, due to the size limitation of the opening of the mask layer for etching, it is impossible to form a sufficiently precise fine size, which limits the etching of the stacked film layer and makes it impossible to obtain the required etching size, so that the electrical performance of the formed storage device cannot be guaranteed.

[0046] As Figure 1 (a)-1(f) are schematic diagrams of the process method for etching the stacked film layer and thinning the first semiconductor layer in the prior art. As Figure 1 (a) shows that a stacked film layer is formed on a substrate 1. The stacked film layer usually includes a first semiconductor layer 11 and a second semiconductor layer 13 that are alternately distributed along the second direction y. The first semiconductor layer 11 and the second semiconductor layer 13 can be epitaxially grown with the substrate 1 as the growth layer by using an epitaxial process. As Figure 1As shown in (b), a mask layer 14 is formed on the stacked film layer. The material of the mask layer 14 can be conventional materials in the art, such as silicon oxide, silicon nitride, etc. A mask opening is formed in the mask layer 14, and the mask opening exposes the upper surface of the stacked film layer. As Figure 1 As shown in (c), using the mask layer 14 as a mask, the stacked film layer is etched through the mask opening to form a trench 101. The trench 101 penetrates the stacked film layer and extends into the interior of the substrate 1. The second semiconductor layer 13 is laterally etched through the trench 101 to remove the second semiconductor 13 in the stacked film layer, thereby forming a gap 104 between the first semiconductor layers 11. As Figure 1 As shown in (d), an isotropic wet etching process is performed on the first semiconductor layer 11 through the trench 101 and the gap 104 to reduce the thickness of the first semiconductor layer 11. At the same time, due to the isotropic etching characteristics of the wet etching, while reducing the thickness of the first semiconductor layer 11, the length of the first semiconductor layer 11 in the first direction x is also shortened, such that the width d1 (preset width) of the mask opening in the first direction is smaller than the width d2 between the adjacent first semiconductor layers 11 in the first direction after thinning. As Figure 1 (e)-1(f), subsequently, a dielectric layer 105 is filled between the first semiconductor layers 11 and a protective material layer 18 is filled in the trench 101. When the protective material layer 18 is etched back through the mask opening of the mask layer to form a protective layer 19 for protecting the substrate, due to the size reduction of the first semiconductor layer 11 in the first direction x, part of the protective material layer 181 remains on the sidewall of the trench 101 and covers the sidewall of the first semiconductor layer 11 at the same time. And subsequent processes need to expose the sidewall of the first semiconductor layer 11 to facilitate the formation of a bit line structure or a capacitor structure. Due to the residue of the protective material layer, it is easy to cause the electrical connection failure between the first semiconductor 11 and the bit line structure or the capacitor structure, thereby affecting the function of the formed memory device.

[0047] Based on this, the embodiments of the present disclosure provide a method for forming a semiconductor structure, as Figure 2 shown. The forming method includes step S110 and step S120, wherein:

[0048] Step S110: Form a stacked film layer on a substrate. The stacked film layer includes a plurality of first semiconductor layers and second semiconductor layers that are alternately distributed along a second direction. The plurality of first semiconductor layers extend along a first direction, and the second direction intersects the first direction. Form a mask layer on the stacked film layer. The mask layer includes a mask opening. Form a spacer layer on the sidewall of the mask opening. Use the mask layer and the spacer layer as a mask to etch the stacked film layer and the substrate to form a first trench in the stacked film layer and a first groove in the substrate. The first trench penetrates through each of the first semiconductor layers along the second direction, and the first trench communicates with the first groove.

[0049] Step S120: Perform an etching process to reduce the thickness of the first semiconductor layer and form a second trench and a second groove in the stacked film layer and the substrate respectively. The second trench communicates with the second groove. Form a protective layer in the second groove. Wherein, along the first direction, the width of the second trench is greater than the width of the first trench and the width of the second groove is greater than the width of the first groove.

[0050] The method for forming a semiconductor structure of the present disclosure forms a plurality of first semiconductor layers distributed along a second direction on a substrate, enabling more first semiconductor layers to be integrated per unit area, providing a basis for manufacturing more chip units. By etching the first semiconductor layer to reduce its thickness, a larger process space can be reserved for fabricating word lines between two adjacent first semiconductor layers distributed along the second direction, which helps reduce the process difficulty of subsequent word line fabrication. Moreover, during the process of etching and thinning the first semiconductor layer, since protective layers are respectively formed on the end faces of the first semiconductor layers exposed in the trenches, and the etching rate of the protective layer is less than that of the first semiconductor layer, during the process of etching and thinning the first semiconductor layer, the protective layer can be used to protect the ends of the first semiconductor layer close to the trenches, reducing the damage to the first semiconductor layer in the first direction during the etching process, making the spacing between the first semiconductor layers on both sides of the trench relatively small, enabling more first semiconductor layers to be arranged along the first direction on the substrate, which helps fabricate a larger number of chip units on the substrate. That is, the storage density can be increased without increasing the number of layers of the first semiconductor layer. At the same time, before etching the stacked film layer through a mask layer, a spacer layer is formed on the sidewall of the mask opening to reduce the size of the mask opening, so that after etching to form the first trench, the size of the first semiconductor layer in the first direction is greater than a preset size, thereby offsetting the loss of the first semiconductor layer in the first direction caused by isotropic etching in the subsequent thinning process and improving the stability of the performance of the formed semiconductor device. In addition, the process steps of forming a protective layer on the sidewall of the first semiconductor layer using an additional process and removing the protective layer after the thinning process can be avoided, reducing further damage to the first semiconductor layer and improving the stability of the performance of the formed device. On the other hand, by forming a spacer layer with a precisely controlled thickness on the sidewall of the mask opening to adjust the size of the mask opening, the same set of mask plates can be applied to different process requirements, effectively reducing the number of mask plates used, improving the efficiency of the fabrication process, and helping to reduce the fabrication cost.

[0051] The following will detail each step and its specific details of the method for forming a semiconductor structure of the present disclosure:

[0052] As Figure 2As shown, in step S110, a stacked film layer is formed on a substrate. The stacked film layer includes a plurality of first semiconductor layers and second semiconductor layers alternately distributed along a second direction. The plurality of first semiconductor layers extend along a first direction, and the second direction intersects the first direction. A mask layer is formed on the stacked film layer. The mask layer includes a mask opening. A spacer layer is formed on a sidewall of the mask opening. Using the mask layer and the spacer layer as a mask, the stacked film layer and the substrate are etched to form a first trench in the stacked film layer and a first groove in the substrate. The first trench penetrates through each of the first semiconductor layers along the second direction, and the first trench communicates with the first groove.

[0053] As Figure 3 shown, the substrate 1 may have a flat structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be a semiconductor material. For example, its material may be silicon, but is not limited to silicon or other semiconductor materials. Other materials include single-crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon carbide, silicon germanide, Germanium on Insulator (GOI), or Silicon on Insulator (SOI), etc. In some embodiments, a suitable substrate material may be selected according to the material of the stacked film layer formed on the substrate and the process conditions. In the embodiments of the present disclosure, in order to form a silicon-germanium-silicon stacked film layer on the substrate using an epitaxial process, the substrate material is selected as a single-crystalline silicon material. In some embodiments, the single-crystalline silicon material may be subjected to N-type or P-type doping treatment and annealing treatment to form an N-type or P-type substrate. The N-type element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In). In some embodiments, only the upper surface of the substrate may be doped to form an N-type doped layer or a P-type doped layer on the substrate surface, or the entire substrate may be doped to form an N-type substrate or a P-type substrate. In the embodiments of the present disclosure, before epitaxially forming a stacked film layer on the substrate 1, the surface of the substrate may be pretreated to remove surface impurities or a natural oxide layer.

[0054] In an exemplary embodiment of the present disclosure, a stacked film layer 2 is formed on the substrate 1. The stacked film layer 2 includes a plurality of first semiconductor layers 21 and second semiconductor layers 23 alternately distributed along a second direction y. As Figure 2As shown, each first semiconductor layer 21 and each second semiconductor layer 23 can extend along the first direction x, and the first direction x can be any direction parallel to the substrate 1. Each first semiconductor layer 21 and each second semiconductor layer 23 can be stacked and distributed along the second direction y. For example, each first semiconductor layer 21 and each second semiconductor layer 23 can be alternately distributed in sequence along the second direction y on the substrate 1. In one embodiment, in the stacked film layer 2, the film layer farthest from the substrate 1 is the first semiconductor layer 21.

[0055] In some embodiments of the present disclosure, the material of the first semiconductor layer 21 can be silicon, and the material of the second semiconductor layer 23 can be silicon germanium. The thickness of the first semiconductor layer 21 can be greater than the thickness of the second semiconductor layer 23. For example, the thickness ratio of the first semiconductor layer 21 to the second semiconductor layer 23 can be 5:1 to 2:1. For example, the thickness of the first semiconductor layer 21 can be 50 nm, and the thickness of the second semiconductor layer 23 can be 10 nm; or, the thickness of the first semiconductor layer 21 can be 45 nm, and the thickness of the second semiconductor layer 23 can be 15 nm; or, the thickness of the first semiconductor layer 21 can be 40 nm, and the thickness of the second semiconductor layer 23 can be 20 nm.

[0056] For example, the number of the first semiconductor layers 21 can be 2 to 20. For example, the number can be 2, 6, 10, 14, 18, or 20. Of course, the number of the first semiconductor layers 21 can also be other numbers, which will not be listed one by one here.

[0057] In some embodiments of the present disclosure, the second direction y can intersect the first direction x. For example, the second direction y and the first direction x can be perpendicular to each other. It should be noted that perpendicularity can be absolute perpendicularity or approximately perpendicular. There will inevitably be deviations during the manufacturing process. In the present disclosure, due to process limitations, there may be angular deviations, resulting in a certain deviation in the included angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within the preset range, it can be considered that the first direction x is perpendicular to the second direction y. For example, the preset range can be 10°, that is: when the included angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°, it can be considered that the first direction x and the second direction y are perpendicular.

[0058] A plurality of first semiconductor layers 21 and a plurality of second semiconductor layers 23 which are alternately distributed in sequence along the second direction y can be formed on the substrate 1 by means of atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, etc. Of course, the first semiconductor layers 21 and the second semiconductor layers 23 can also be formed by other means. In the embodiments of the present disclosure, in order to reduce the interval mismatch between the first semiconductor layer 21 and the second semiconductor layer 23, by means of epitaxial growth, with the substrate 1 as the epitaxial growth layer, the second semiconductor layer 23 is first epitaxially formed, and then the first semiconductor layer 21 is formed on the second semiconductor layer 23 by means of epitaxial growth. Since the material of the first semiconductor layer is single crystal silicon and the material of the second semiconductor layer is germanium silicon, the crystal lattices between the two are similar, thereby reducing the interval mismatch between the first semiconductor layer and the second semiconductor layer and improving the electrical performance of the formed semiconductor device.

[0059] Such as Figure 4 , a mask layer 24 is formed on the stacked film layer 2, wherein the mask layer 24 includes a mask opening 241. The material of the mask layer 24 can be silicon oxide, silicon nitride, polysilicon, etc., which has a high etching selectivity with respect to the first semiconductor layer 21 or the second semiconductor layer 23 in the stacked film layer, so as to protect the top of the stacked film layer when etching the first trench in the stacked film layer. The method of forming the mask layer 24 includes forming a mask material layer on the top of the stacked film layer 2, etching the mask material layer through a photoresist mask, removing part of the mask material layer, and exposing the top of the stacked film layer 2. The remaining mask material layer forms the mask layer and the mask opening 241 in the mask layer 24. Among them, along the first direction x, the mask opening has a preset size d0. In the embodiments of the present disclosure, the preset size refers to the size expected to be obtained in the existing process, that is, the design size.

[0060] Such as Figure 5As shown, a spacer material layer 25 is formed on the top of the mask layer 24, the top of the stacked film layer 2, and the sidewalls of the mask opening 241. The material of the spacer layer 25 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon oxynitride. Among them, in order to use the spacer layer as a mask to etch the stacked film layer, the material of the spacer material layer needs to have a high etching selectivity ratio with respect to the first semiconductor layer 21 or the second semiconductor layer 23 in the stacked film layer. In addition, in order to remove the spacer layer and retain the mask layer 24 in the later stage, the material of the spacer material layer needs to be different from the material of the mask layer and have a high etching selectivity ratio. In some embodiments, the material of the mask layer 24 is silicon oxide, and the material of the spacer layer 25 is silicon nitride. The embodiments of the present disclosure do not make specific limitations in this regard, and any material combination that can achieve the required etching selectivity ratio is acceptable. The spacer material layer 25 can be formed by processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). In some embodiments, in order to precisely control the thickness of the spacer layer 26 formed on the sidewalls of the mask opening 241, the atomic layer deposition process (ALD) can be used to form the spacer material layer 25. The ALD process has good step coverage and can precisely control the deposition thickness, which is beneficial to controlling the constriction size of the formed mask opening. As Figure 6 shown, the spacer material layer 25 on the top of the mask layer 24 and the top of the stacked film layer 2 is removed, and the spacer material layer on the sidewalls of the mask opening 241 forms a spacer layer 26. In some embodiments, a dry etching process can be used to remove part of the spacer material layer, and the remaining spacer material layer forms the spacer layer 26.

[0061] As Figure 7As shown, using the mask layer 24 and the spacer layer 26 as masks, the stacked film layer 2 and the substrate 1 are etched to form a first trench 201 in the stacked film layer and a first groove 202 in the substrate 1. The first trench 201 penetrates through each first semiconductor layer 21 and the second semiconductor layer 23 along the second direction y, and the first trench 201 communicates with the first groove 202. The first semiconductor layers 21 and the second semiconductor layers 23 on the substrate 1 can be etched by dry etching, wet etching, or a combination of both to form the first trench 201. That is, the sidewalls of the first trench 201 can be composed of the first semiconductor layers 21 and the second semiconductor layers 23. In some embodiments of the present disclosure, the first trench 201 extends along the second direction y and penetrates into the interior of the substrate 1, thereby forming a first groove 202 extending from the upper surface to the lower surface inside the substrate 1, and the first groove 202 communicates with the first trench 201. By making the first trench 201 extend along the second direction y and penetrate into the interior of the substrate 1, the first semiconductor layer 21 and the second semiconductor layer 22 can be completely etched, preventing the occurrence of insufficient etching. In some embodiments, the first trench 201 and the first groove 202 can be completed in the same etching process or in different etching processes. For example, the etching process of the stacked film layer 2 is first performed to form the first trench 201, and then the substrate is etched through the first trench 201 to form the first groove 202. The embodiments of the present disclosure do not make specific limitations on this.

[0062] In some embodiments of the present disclosure, the number of the first trenches 201 and the first grooves 202 can be multiple. The multiple first trenches 201 can be spaced apart along the first direction x, and thus the structure formed by the first semiconductor layers 21 and the second semiconductor layers 23 together can be divided into multiple spaced-apart semiconductor groups through the multiple first trenches 201.

[0063] In some embodiments of the present disclosure, along the first direction x, the first trench 201 and the first groove 202 have the same width d3, where d3 < d0.

[0064] As Figure 8 shown, the end of the second semiconductor layer 23 close to the trench 201 can be laterally etched, and thus a gap 204 is formed between two adjacent first semiconductor layers 21 distributed along the second direction y. That is, in the second direction y, the width of the gap 204 is equal to the thickness of the second semiconductor layer 23. For example, when the thickness of the second semiconductor layer 23 is 10 nm, in the second direction y, the width of the gap 204 is 10 nm.

[0065] As Figure 9As shown, an etching process is performed to thin the thickness of the first semiconductor layer 21 and form a second trench and a second groove in the stacked film layer and the substrate respectively. The second trench and the second groove communicate with each other. Wherein, along the first direction x, the width of the second trench is greater than the width of the first trench and the width of the second groove is greater than the width of the first groove. In some embodiments, the first semiconductor layer 21 can be etched by a wet etching process, thereby reducing the thickness of the first semiconductor layer 21, and further leaving a larger process space for fabricating word lines between two adjacent first semiconductor layers 21 distributed along the second direction y, which helps to reduce the process difficulty of fabricating word lines subsequently. Through an isotropic wet etching process, the exposed surfaces of the first semiconductor layer 202 and the substrate 1 are etched along the gap 204 and the first trench 201 to thin the thickness of the first semiconductor layer 202 along the second direction y, and a part of the length of the first semiconductor layer and a part of the substrate are etched away along the first direction x, so as to form a second trench 2011 and a second groove 2021 in the stacked film layer and the substrate respectively. As Figure 9 shown, after the etching process, the formed second trench 2011 and second groove 2021 communicate with each other. In some embodiments, along the first direction x, the second trench 2011 and the second groove 2021 have the same width d4, where d4 > d3. Optionally, in some embodiments, d4 <= d0.

[0066] As Figure 9 and Figure 10 , a protective layer 29 is formed in the second groove 2021. Wherein, the material of the protective layer is one or more of polysilicon, low-k dielectric material, and silicon nitride. In some embodiments, the upper surface of the protective layer 29 is flush with the upper surface of the substrate 1, or higher than the upper surface of the substrate 1 and lower than the lower surface of the first semiconductor layer 21 closest to the substrate 1. Thus, the second groove 2021 on the surface of the substrate 1 can be completely filled with the protective layer 29, preventing process damage to the substrate in subsequent processes, and effectively isolating the substrate 1 from the memory device structure formed on the substrate 1. In some embodiments, the step of forming the protective layer 29 includes: as Figure 9 and Figure 10 shown, after etching and thinning the first semiconductor layer 21, a dielectric material layer (not shown) is filled between the thinned first semiconductor layers 21. The dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon oxynitride. The spacer layer 26 located on the sidewall of the mask opening 241 is removed. Using the mask layer 24 as a mask, a part of the dielectric material layer is removed, and the second trench 2011 and the second groove 2021 communicating with the second trench 2011 are exposed. The dielectric material layer located between the thinned first semiconductor layers 21 forms a dielectric layer 27. Further, as Figure 10As shown, a protective material layer 28 is filled in the second trench 2011 and the second groove 2021 communicating with the second trench 2011. The protective material layer 28 can be formed by processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. As Figure 11 As shown, the protective material layer 28 is etched back through the mask layer 24, and the remaining part of the protective material layer forms the protective layer 29. In some embodiments, since d4 <= d0, when the protective material layer in the second trench 2011 and the second groove 2021 communicating with the second trench 2011 is etched back with the mask layer 24 as the mask, the protective material layer on the sidewall of the thinned first semiconductor layer 21 can be completely removed, effectively preventing the residual protective material layer on the sidewall of the second trench 2011, that is, the sidewall of the thinned first semiconductor layer 21 can be completely exposed, so as to facilitate the formation of a bit line structure or a capacitor structure on the sidewall of the thinned first semiconductor layer 21 subsequently, improving the electrical performance of the finally formed device.

[0067] The method for forming a semiconductor structure of the present disclosure involves forming multiple first semiconductor layers distributed along a second direction on a substrate, enabling more first semiconductor layers to be integrated per unit area, providing a basis for manufacturing more chip units. By etching the first semiconductor layer to reduce its thickness, a larger process space can be reserved for fabricating word lines between two adjacent first semiconductor layers distributed along the second direction, which helps reduce the process difficulty of fabricating word lines subsequently. Moreover, during the process of etching and thinning the first semiconductor layer, since protective layers are respectively formed on the end faces of the first semiconductor layers exposed in the trenches, and the etching rate of the protective layer is less than that of the first semiconductor layer, the end portions of the first semiconductor layer close to the trenches can be protected by the protective layers during the process of etching and thinning the first semiconductor layer. The damage to the first semiconductor layer in a first direction during the etching process can be reduced, making the spacing between the first semiconductor layers on both sides of the trench relatively small, enabling more first semiconductor layers to be arranged along the first direction on the substrate, which helps fabricate a larger number of chip units on the substrate. That is, the storage density can be increased without increasing the number of layers of the first semiconductor layer. Meanwhile, before etching the stacked film layer through a mask layer, a spacer layer is formed on the sidewall of the mask opening to reduce the size of the mask opening, such that after etching to form a first trench, the size of the first semiconductor layer in the first direction is greater than a preset size, thereby offsetting the loss of the first semiconductor layer in the first direction caused by isotropic etching in subsequent thinning processes and improving the performance stability of the formed semiconductor device. In addition, the process steps of forming a protective layer on the sidewall of the first semiconductor layer using an additional process and removing the protective layer after the thinning process can be avoided, reducing further damage to the first semiconductor layer and improving the performance stability of the formed device. On the other hand, by forming a spacer layer with a precisely controlled thickness on the sidewall of the mask opening to adjust the size of the mask opening, the same set of mask plates can be applicable to different process requirements, effectively reducing the number of mask plates used, improving the efficiency of the fabrication process, and helping to reduce the fabrication cost.

[0068] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the drawings, this does not require or imply that these steps must be executed in that specific order, or that all the shown steps must be executed to achieve the desired result. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution, etc.

[0069] The embodiments of the present disclosure further provide a semiconductor structure, which can be formed by the method for forming a semiconductor structure in any of the above embodiments.

[0070] The specific details and manufacturing processes of each part in the above semiconductor structure have been described in detail in the corresponding method for forming the semiconductor structure. Therefore, they will not be elaborated here.

[0071] For example, the semiconductor structure can be a Dynamic Random Access Memory (DRAM), a static random access memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed one by one here.

[0072] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Form a stacked film layer on a substrate, the stacked film layer including a plurality of first semiconductor layers and second semiconductor layers alternately distributed in a second direction, the plurality of first semiconductor layers extending in a first direction, the second direction intersecting the first direction; Form a mask layer on the stacked film layer, the mask layer including a mask opening; Form a spacer layer on the sidewall of the mask opening; Using the mask layer and the spacer layer as a mask to etch the stacked film layer and the substrate to form a first trench in the stacked film layer and a first groove in the substrate, the first trench penetrating through each of the first semiconductor layers in the second direction, the first trench communicating with the first groove; Perform an etching process to thin the thickness of the first semiconductor layer and form a second trench and a second groove in the stacked film layer and the substrate respectively, the second trench communicating with the second groove; Form a protective layer in the second groove; Wherein, along the first direction, the width of the second trench is greater than the width of the first trench and the width of the second groove is greater than the width of the first groove.

2. The forming method according to claim 1, wherein The etching process includes: Perform lateral etching on the second semiconductor layer through the first trench to remove the second semiconductor layer and form a gap between the adjacent first semiconductor layers along the second direction; Perform an isotropic wet etching process on the first semiconductor layer through the gap and the first trench to thin the thickness of the first semiconductor layer.

3. The forming method according to claim 2, wherein The step of forming a spacer layer on the sidewall of the mask opening includes: Form a spacer material layer on the top of the mask layer, the top of the stacked film layer and the sidewall of the mask opening, remove the spacer material layer located on the top of the mask layer and the top of the stacked film layer, and the spacer material layer located on the sidewall of the mask opening forms the spacer layer.

4. The forming method according to claim 3, wherein The spacer material layer is formed by an atomic layer deposition process.

5. The forming method according to any one of claims 1-4, characterized in that, The material of the spacer layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride.

6. The forming method according to any one of claims 1-4, characterized in that, Before forming the protective layer in the second groove, it further includes: Remove the spacer layer.

7. The forming method according to any one of claims 1-4, characterized in that, The material of the protective layer is one or more of polysilicon, low-K dielectric material, silicon nitride.

8. The forming method according to any one of claims 1-4, characterized in that, The material of the mask layer is different from the material of the spacer layer.

9. The forming method according to any one of claims 2-4, characterized in that, The material of the first semiconductor layer is single crystal silicon, and the material of the second semiconductor layer is silicon germanium.

10. A semiconductor structure, characterized in that, The semiconductor structure is formed by the formation method of the semiconductor structure according to any one of claims 1-9.

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