Memory component and method of manufacturing the same

Abstract

The invention provides a memory component and a manufacturing method thereof. The memory component comprises a substrate, a plurality of word lines, a selection gate and a dummy word line. The plurality of word lines is over the substrate. And the selection gate is arranged on one side of the word line. The dummy word line is between the plurality of word lines and the select gate. A first gap between the plurality of word lines has a first gap width, a second gap between the dummy word line and an outermost word line of the plurality of word lines has a second gap width, and a third gap between the dummy word line and the select gate has a third gap width, the ratio of the width of the third gap to the width of the first gap ranges from 0.95 to 1.05.

Description

Technical Field

[0001] The present invention relates to a semiconductor component and a manufacturing method thereof, and more particularly to a memory component and a manufacturing method thereof. Background Art

[0002] With the progress of technology, various electronic products are developing towards the trend of being thinner, lighter, shorter and smaller. The critical dimensions of memory components are also gradually reduced, making the lithography process increasingly difficult. In the existing lithography process, methods for reducing critical dimensions include using optical components with a larger numerical aperture (NA), a shorter exposure wavelength (such as EUV), or an interface medium other than air (such as water immersion).

[0003] The resolution of the existing lithography process is close to the theoretical limit, and manufacturers have begun to turn to the Self-Aligning Double Patterning (SADP) method to overcome the optical limit and thus improve the integration density of memory components. However, currently, due to the different pattern densities at the center and the edge of the array region, the etching process will face the Loading Effect, resulting in inconsistent profiles of memory cells at the center and the edge of the array region, thus causing electrical problems. Summary of the Invention

[0004] The present invention provides a memory component, including: a substrate, a plurality of word lines, a selection gate, and dummy word lines. The plurality of word lines are located above the substrate. The selection gate is on one side of the word lines. The dummy word lines are between the plurality of word lines and the selection gate. A first gap between the plurality of word lines has a first gap width, a second gap between the dummy word lines and the outermost word line of the plurality of word lines has a second gap width, a third gap between the dummy word lines and the selection gate has a third gap width, and the ratio of the third gap width to the first gap width is between 0.95 and 1.05.

[0005] The present invention provides a manufacturing method of a memory component, including the following steps. Providing a substrate. Forming a target layer on the substrate. Forming a sacrificial layer on the target layer. Forming a core layer on the sacrificial layer. Forming a plurality of spacers on a plurality of sidewalls of the core layer. Removing the core layer. Using the plurality of spacers as a mask to pattern the sacrificial layer to form a patterned sacrificial layer. Forming a hard mask layer between the patterned sacrificial layers. Removing the patterned sacrificial layer. Using the hard mask layer as a mask to pattern the target layer to form a plurality of word lines, dummy word lines, and a selection gate, wherein the dummy word lines are between the plurality of word lines and the selection gate.

[0006] Based on the above, the embodiments of the present invention can avoid the load effect during the etching process of the target layer, and the distance between the select gate and the word line can be accurately controlled to mitigate or suppress the gate induced drain leakage (GIDL) effect caused by the gate string, the select gate leakage current, and the electron injection into the floating gate corresponding to the word line adjacent to the select gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional schematic diagram of a memory component according to an embodiment of the present invention;

[0008] Figure 2A A top view of a memory component according to an embodiment of the present invention;

[0009] Figure 2B yes Figure 2A A magnified view of a local area;

[0010] Figures 3A to 3I is a top view of a method for manufacturing a memory component according to an embodiment of the present invention;

[0011] Figures 4A to 4F as well as Figure 4G They are Figures 3A to 3F as well as Figure 3I A cross-sectional view along line IV-IV. DETAILED DESCRIPTION

[0012] Please refer to Figure 1 The memory component 100A of the embodiment of the present invention is formed on a substrate 10A. The memory component 100A is, for example, a NAND flash memory. The memory component 100 may include a plurality of word lines WL1, WL2, ..., WL n-1 , WL n , a plurality of dummy word lines DWL1, DWL1' and a plurality of select gates SG1, SG1'. The select gate SG1 is adjacent to the contact COA1. The select gate SG1' is adjacent to the contact COA1'. The contact COA1 is, for example, connected to the source, and the contact COA1' is, for example, connected to the drain. The dummy word line DWL1 is disposed between the select gate SG1 and the word line WL1. The dummy word line DWL1' is disposed between the select gate SG1' and the word line WL n between.

[0013] Word lines WL1 to WL nHave substantially the same width W1. The dummy word lines DWL1 and DWL1' have widths W2 and W2' respectively. The select gates SG1 and SG1' have widths W3 and W3' respectively. In some embodiments, the widths W3 and W3' are substantially equal. The widths W2 and W2' are substantially equal. The widths W3 and W3' are greater than the widths W2 and W2', and the widths W2 and W2' are greater than the width W1. The ratio W2 / W1 of the width W2 to the width W1 is, for example, between 1.1 and 2.5. The ratio W2' / W1 of the width W2' to the width W1 is, for example, between 1.1 and 2.5.

[0014] The word lines WL1 to WL n Have a first gap width W 11 Between them. There is a second gap width W 21 Between the dummy word line DWL1 and the word line WL1. n Have a second gap width W 21 ' Between the dummy word line DWL1' and the word line WL 32 '. There is a third gap width W n Between the select gate SG1 and the dummy word line DWL1. 32 '.

[0015] In this embodiment, the third gap widths W 32 , W 32 ', the second gap widths W 21 , W 21 ' and the first gap width W 11 Are equal or substantially equal, or within the process error range, such as ±5%. That is to say, the ratio W 32 (or W 32 ') of the third gap width W 21 (or W 21 ') to the second gap width W 32 / W 21 (or W 32 ' / W 21 ) is between 0.95 and 1.05. The ratio W 32 (or W 32 ) of the third gap width W 11 ' to the first gap width W 32 / W 11 (or W 32 ' / W 11 ) is between 0.95 and 1.05. The ratio W 21 (or W 21 ) of the second gap width W 11 ' to the first gap width W 21 / W 11 (or W21 ’ / W 11 ) is between 0.95 and 1.05. In some embodiments, the third gap width W 32 (or W 32 ’) is equal to the first gap width W 11 . The second gap width W 21 (or W 21 ’) is equal to the first gap width W 11 . In other embodiments, the third gap width W 32 (or W 32 ’) and the second gap width W 21 (or W 21 ’) are equal to the first gap width W 11 . Since the third gap width W 32 (or W 32 ’), the second gap width W 21 (or W 21 ’) are equal to or approximately equal to the first gap width W 11 , during the etching process of forming the first gap, the second gap and the third gap, the load effect can be reduced and the uniformity of the etching process can be improved.

[0016] In an embodiment of the present invention, by adjusting the widths W2 and W2’ of the dummy word lines DWL1 and DWL1’, a sufficient distance d1 can be provided between the select gate SG1 and the word line WL1, and a sufficient distance d1’ can be provided between the select gate SG1’ and the word line WL n . Therefore, during the programming operation of the memory component 100A, the gate-induced drain leakage (GIDL) effect, the select gate leakage current, and the injection of electrons into the floating gate corresponding to the word line adjacent to the select gate can be slowed down or suppressed.

[0017] An embodiment of the present invention provides a method for manufacturing a memory component 100. Referring to Figure 3A and Figure 4A , a substrate 10 is provided. The substrate 10 may include an array region R1, a transition region R2, and a wiring region R3. In this embodiment, the array region R1 may be a memory array region having one or more memory cells, and the wiring region R3 may be a wiring region having one or more word line contacts. The transition region R2 is between the array region R1 and the wiring region R3. In one embodiment, the substrate 10 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor-on-insulator (SOI) substrate. In this embodiment, the substrate 10 is a silicon substrate.

[0018] Next, a target layer 12 is formed on the substrate 10. The target layer 12 may be a stacked layer 112 stacked in the direction D3. Specifically, the stacked layer 112 may sequentially include a tunneling dielectric layer 102, a patterned floating gate layer 104, an inter-gate dielectric layer 106, a control gate layer 108, and a capping layer 110 from bottom to top. The material of the tunneling dielectric layer 102 may be, for example, silicon oxide. The patterned floating gate layer 104 may include a conductor material, such as doped polysilicon, undoped polysilicon, or a combination thereof. The inter-gate dielectric layer 106 may be, for example, a composite layer composed of nitride / oxide / nitride / oxide / nitride (NONON), but the present invention is not limited thereto, and this composite layer may also be a single layer or multiple layers. The material of the control gate layer 108 may include a conductor material, such as doped polysilicon, undoped polysilicon, or a combination thereof. In some other embodiments, the material of the control gate layer 108 may further include a metal, such as W, TiN, or a combination thereof. The material of the capping layer 110 may include a dielectric material, such as silicon nitride, silicon oxynitride, or a combination thereof.

[0019] A sacrificial layer 14 is formed on the target layer 12. The sacrificial layer 14 may include a conductor material, such as doped polysilicon, undoped polysilicon, or a combination thereof. A core layer 16 is formed on the sacrificial layer 14. The core layer 16 may include a carbide layer. In another embodiment, the core layer 16 may include a carbide layer and an anti-reflection layer. The material of the carbide layer may be, for example, spin-on-carbon (SoC). The anti-reflection layer may be located above the carbide layer, and its material may be, for example, silicon oxynitride. The core layer 16 is formed, for example, by first forming a carbide material and an anti-reflection material, and then forming a photoresist pattern on the anti-reflection material via a photolithography process. In some embodiments, after forming the photoresist pattern, a trimming process is further performed to reduce the width of the formed photoresist pattern. Thereafter, an etching process is performed to transfer the pattern of the photoresist pattern downward to the anti-reflection material and the carbide material. After that, the photoresist pattern is removed, leaving the carbide layer and the anti-reflection layer.

[0020] Referring to Figure 3B and Figure 4B , a spacer material 18 is formed on the surface and sidewalls of the core layer 16 and on the sacrificial layer 14. The spacer material 18 includes an oxide, such as silicon oxide. The spacer material 18 is, for example, a conformal layer having a substantially the same thickness t.

[0021] Referring to Figure 3C and Figure 4C, an anisotropic etching process is performed on the spacer material 18, such as a reactive ion etching process, to remove a portion of the spacer material 18 until the top surface of the core layer 18 is exposed, so as to form spacers 18a on the sidewalls of the core layer 18. Thereafter, a selective etching process is performed to remove the core layer 16, exposing the sacrificial layer 14.

[0022] Refer to Figure 3D And Figure 4D , using the spacers 18a as a mask, an anisotropic etching process is performed, such as a reactive ion etching process, to remove the sacrificial layer 14 not covered by the spacers 18a, so as to form a patterned sacrificial layer 14a. There are gaps 20 between the patterned sacrificial layers 14a.

[0023] Refer to Figure 3E And Figure 4E , a hard mask layer 22 is formed in the gaps 20. The method for forming the hard mask layer 22 is as described below. A hard mask material is formed on the spacers 18a and within the gaps 20. Examples of the hard mask material include oxides, such as silicon oxide. The hard mask material can be formed via a flowable chemical vapor deposition method (FCVD). Thereafter, a planarization process, such as chemical mechanical polishing, is performed to remove the hard mask material on the spacers 18a and the spacers 18a, exposing the patterned sacrificial layer 14a, and forming a hard mask layer 22 in the gaps 20.

[0024] Refer to Figure 3F And Figure 4F , a selective etching process is performed to remove the patterned sacrificial layer 14a, exposing the top cover layer 110. In the Figure 3F top view, in the array region R1 and the transition region R2, the top cover layer 110 not covered by the hard mask layer 22 surrounds the hard mask layer 22, that is, the top cover layer 110 not covered by the hard mask layer 22 surrounds both sides S1 and S2 and the ends E of the hard mask layer 22.

[0025] Refer to Figure 3G , a mask layer 24 is formed above the substrate 10. The mask layer 24 is, for example, a patterned photoresist layer. The mask layer 24 partially covers the array region R1, the transition region R2, and the winding region R3. The mask layer 24 has an opening OP, exposing the winding region R3, the hard mask layer 22 in the transition region R2, and the top cover layer 110 not covered by the hard mask layer 22. The opening OP includes a first portion OP1 and a second portion OP2. The first portion OP1 extends in the direction D2, extending from the winding region R3 to the transition region R2. The second portion OP2 extends in the direction D1. The second portion OP2 is located at the end E of the hard mask layer 22 close to the array region R1 (shown in Figure 3F ).

[0026] Refer to Figure 3H, a selective etching process is performed to remove the hard mask layer 22 exposed by the opening OP, so as to expose the top cover layer 110.

[0027] Refer to Figure 3I and Figure 4G , the mask layer 24 is removed, and then a shearing process is performed. The shearing process uses the hard mask layer 22 as a mask to perform an anisotropic etching process to pattern the target layer 12. In this embodiment, the top cover layer 110, the control gate layer 108, the inter-gate dielectric layer 106, and the patterned floating gate layer 104 of the stacked layer 112 are patterned to form a patterned stacked layer SKT.

[0028] Refer to Figure 3I , the patterned stacked layer SKT includes a plurality of patterned stacked layers SK, SK’, SKS, SK0, and SK0’ located in the array region R1. The patterned stacked layers SK, SK’, SKS, SK0, and SK0’ extend in the direction D2 respectively and are arranged in the direction D1. Figure 3I It shows that the patterned stacked layer SK includes patterned stacked layers SK1 to SK8, and the patterned stacked layer SK’ includes patterned stacked layers SK1’ to SK8’.

[0029] There are gaps G11, G11’, G21, G21’, G32, G32’, G44’ between the multiple patterned stacked layers SK, SK’, SKS, SK0, and SK0’ of the patterned stacked layer SKT. The gaps G11, G11’, G21, G21’, G32, G32’, G44’ in the embodiment of the present invention correspond to the positions of the spacers 18a. Therefore, the present invention belongs to an implementation method of reverse tone SADP (Reverse tone SADP implement). Since the gaps G11, G11’, G21, G21’, G32, G32’, G44’ are formed after the removal of the patterned sacrificial layer 14a (shown in Figure 4E and Figure 4F ), and the pattern of the patterned sacrificial layer 14a is transferred from the spacers 18a (shown in Figure 4C and Figure 4E ). Therefore, the size of the gaps G11, G11’, G21, G21’, G32, G32’, G44’ can be determined by the thickness t of the spacers 18a. The spacers 18a can be controlled to have the same or substantially the same thickness t through deposition and etching processes. Therefore, when performing the etching process to remove the patterned sacrificial layer 14a and the target layer 12, since the widths t of the patterned sacrificial layer 14a are substantially the same or close, the loading effect can be reduced or avoided.

[0030] Refer to Figure 3I, the patterned stacked layer SKT may further include a plurality of dummy pillars SP located in the transition region R2. The plurality of dummy pillars SP include, for example, SPS, SP1, SP3, SP5, and SP7, corresponding to the patterned stacked layers SKS, SK1, SK3, SK5, and SK7 respectively. Viewed from the top view, a part of each of the patterned stacked layers SKS, SK1, SK3, SK5, and SK7 is strip-shaped. The plurality of dummy pillars SP1, SP3, SP5, and SP7 are island-shaped respectively. The dummy pillar SPS is connected to the stacked layer SKS.

[0031] Referring to Figure 3I , the patterned stacked layer SKT may further include a dummy comb SC located in the transition region R2. The dummy comb SC includes a main body portion MP and a plurality of extending portions EP. The main body portion MP extends in the direction D1. The plurality of extending portions EP are provided on the same side of the main body portion MP and are connected to the main body portion MP. The plurality of extending portions EP include, for example, extending portions EP0, EP2, EP4, EP6, and EP8, extending in the direction D2, arranged in the direction D1, and corresponding to the patterned stacked layers SK0, SK2, SK4, SK6, and SK8 respectively. In the direction D1, the plurality of extending portions EP and the plurality of dummy pillars SP are alternately arranged. The length L1 of the plurality of extending portions EP in the direction D2 is greater than the length L2 of the plurality of dummy pillars SP in the direction D2. Furthermore, the dummy comb SC is connected to the patterned stacked layer SK0'.

[0032] Referring to Figure 3I , Figure 2A and Figure 2B , Figure 2A shows Figure 3I a top view of the control gate layer 108 of the patterned stacked layer SKT shown. Figure 2B shows Figure 2A a partial enlarged view of the region 50 shown. The control gate layers 108 of the patterned stacked layers SKS, SK0, SK0', SK, and SK' provided in the array region R1 serve as the selection gate SG, the dummy word line DWL, DWL', and the word line WL, WL' respectively. The control gate layer 108 provided in the wiring region R3 serves as a plurality of landing pads LP' for the contact (pickup) of the word line WL'. In an embodiment of the present invention, the selection gate SG and the plurality of landing pads LP' can be formed in the same etching process as the dummy word lines DWL, DWL' and the word lines WL, WL' without additional photolithography and etching processes for patterning.

[0033] Referring to Figure 2B, a dummy comb SC and a plurality of dummy pillars SP are disposed in the transition region R2. The extension portion EP of the dummy comb SC and the control gate layer 108 of the plurality of dummy pillars SP are adjacent to the ends E1 of the plurality of word lines WL, the ends E2 of the dummy word lines DWL, and the ends E3 of the select gate SG. The control gate layer 108 of the plurality of dummy pillars SP can be square, rectangular, circular or oval. The widths w1, w3 of the control gate layer 108 of the plurality of dummy pillars SP in the direction D1 are substantially the same as the widths W1, W3 of the corresponding word lines WL1, select gate SG, respectively.

[0034] The widths w1”, w2 of the control gate layer 108 of the extension portion EP of the dummy comb SC in the direction D1 are substantially the same as the widths W1, W2 of the corresponding word lines WL2, dummy word line DWL, respectively. The dummy pillars SP are disposed between adjacent extension portions EP. The first gap width W11, the second gap width W21, and the third gap width W32 corresponding to the adjacent patterned stacked layers SK between the adjacent dummy pillars SP and the extension portions EP are substantially the same.

[0035] Reference Figure 4G , the patterned stacked layers SKS, SK0, SK1, SK2, SK3, SK0’, SK1’, SK2’, SK3’ sequentially include a tunneling dielectric layer 102, a patterned floating gate layer 104, an inter-gate dielectric layer 106, a control gate layer 108, and a top cap layer 110 from bottom to top. The control gate layer 108 of the patterned stacked layer SKS can be used as the select gate SG. The control gate layer 108 of the patterned stacked layers SK1, SK2, SK3 and SK1’, SK2’, SK3’ can be used as the word lines WL1, WL2, WL3 and WL1’, WL2’, WL3’. The control gate layer 108 of the patterned stacked layer SK0 located between the patterned stacked layer SKS and the patterned stacked layer SK1 can be used as the dummy word line DWL, and the control gate layer 108 of the patterned stacked layer SK0’ located between the patterned stacked layer SKS and the patterned stacked layer SK1’ can be used as the dummy word line DWL’.

[0036] The width W3 of the select gate SG is greater than the width W2 of the dummy word line DWL and the width W2’ of the dummy word line DWL’, and greater than the widths W1 of the word lines WL1~WL3 and the widths W1’ of the word lines WL1’~WL3’. The widths W2, W2’ of the dummy word lines DWL, DWL’ can be greater than the widths W1, W1’ of the word lines WL1~WL3, WL1’~WL3’, respectively. In some embodiments, the ratio W2 / W1 of the width W2 to the width W1 is between 1.1 and 2.5, and the ratio W2’ / W1’ of the width W2’ to the width W1’ is between 1.1 and 2.5.

[0037] A first gap G11 / G11' between multiple word lines WL / WL' has a first gap width W11 / W11'. A second gap G21 / G21' between dummy word lines DWL / DWL' and outermost word lines WL1 / WL1' of the multiple word lines WL / WL' has a second gap width W21 / W21'. A third gap G32 / G32' between a select gate SG and dummy word lines DWL / DWL' has a third gap width W32 / W32'.

[0038] Referring to Figure 3I and Figure 2A , a landing pad LP', each dummy post SP, and a dummy comb SC are similar in composition and patterning to the patterned stacked layer SK, and sequentially include a tunneling dielectric layer 102, a patterned floating gate layer 104, an inter-gate dielectric layer 106, a control gate layer 108, and a top cover layer 110 from bottom to top. The width W4' of the landing pad LP' is greater than the width W3 of the select gate SG. A fourth gap G44' between landing pads LP' has a fourth gap width W44'.

[0039] Referring to Figure 3I and Figure 4G , in an embodiment of the present invention, the fourth gap width W44', the third gap widths W32, W32', the second gap widths W21, W21' and the first gap widths W11, W11' are substantially equal, or within the process error range, such as ±5%. That is to say, the ratio W44' / W11' of the fourth gap width W44' to the first gap width W11 (or W11') is between 0.95 and 1.05. The ratio W32 / W11 (or W32' / W11') of the third gap width W32 (or W32') to the first gap width W11 (or W11') is between 0.95 and 1.05. The ratio W21 / W11 (or W21' / W11') of the second gap width W21 (or W21') to the first gap width W11 (or W11') is between 0.95 and 1.05. In some embodiments, the fourth gap width W44' is equal to the first gap width W11'. In some embodiments, the widths W1, W1' of word lines WL1 - WL3, WL1' - WL3' are substantially equal to the fourth gap width W44', the third gap widths W32, W32', the second gap widths W21, W21' and the first gap widths W11, W11', or within the process error range, such as ±5%.

[0040] Referring to Figure 4A and Figure 4G, in the embodiments of the present invention, the distance d3 / d3' between the core layer 16 corresponding to the select gate SG and the word line WL1 / WL' can be controlled to form dummy word lines DWL / DWL' with a larger width W2 / W2', so that there is a sufficient distance d1 / d1' between the select gate SG and the word line WL1 / WL1'. Therefore, during the programming operation of the memory component, the gate-induced drain leakage (GIDL) effect, select gate leakage current, and electron injection into the floating gate corresponding to the word line adjacent to the select gate caused by the gate stack can be slowed down or inhibited.

[0041] In the embodiments of the present invention, the size of the gap between the patterned stacked layers SKT is related to the thickness t (dimension) of the spacer 18a, as shown in Figures 4B to 4D . In terms of technology, compared with the control of the size of the core layer 16, the thickness t of the spacer 18a can be more precisely controlled by changing the conditions of the etching process. Therefore, the size of the gap between adjacent patterned stacked layers SKT can be precisely controlled by adjusting the thickness t of the spacer 18a. In other words, the distance d1 between the select gate SG and the word line WL1, or the distance d1' between the select gate SG and the word line WL1' can be precisely controlled.

[0042] Although the above embodiments take the flash memory as an example to illustrate a series of patterning steps, the present invention is not limited thereto. In other embodiments, this patterning step can also be used to form a dynamic random access memory (DRAM) or a similar target layer / membrane.

[0043] In the embodiments of the present invention, the loading effect can be reduced or avoided during the etching process of the target layer, and the distance between the select gate and the word line can be precisely controlled. Therefore, during the programming operation of the memory component, the gate-induced drain leakage effect, select gate leakage current, and electron injection into the floating gate corresponding to the word line adjacent to the select gate caused by the gate stack can be slowed down or inhibited.

[0044] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory component, characterized in that, Comprising: A substrate; A plurality of word lines located above the substrate; A select gate on one side of the word lines; And Dummy word lines between the plurality of word lines and the select gate, wherein a first gap between the plurality of word lines has a first gap width, a second gap between the dummy word line and the outermost word line of the plurality of word lines has a second gap width, and a third gap between the dummy word line and the select gate has a third gap width, and a ratio of the third gap width to the first gap width is between 0.95 and 1.

05.

2. The memory component according to claim 1, wherein a width of the dummy word line is greater than a width of the word line.

3. The memory component according to claim 2, wherein a ratio of the width of the dummy word line to the width of the word line is between 1.1 and 2.

5.

4. The memory component according to claim 1, wherein a ratio of the second gap width to the first gap width is between 0.95 and 1.

05.

5. The memory component according to claim 1, further comprising: Dummy combs and a plurality of dummy pillars adjacent to a plurality of ends of the plurality of word lines, the dummy word lines, and the select gate.

6. The memory component according to claim 1, wherein the dummy comb comprises: A main body portion; And A plurality of extending portions located between the main body portion and the plurality of word lines and connected to the main body portion.

7. The memory component according to claim 6, wherein the plurality of dummy pillars are located between the main body portion and the plurality of word lines and are alternately arranged with the plurality of extending portions.

8. The memory component according to claim 6, wherein the plurality of dummy pillars and the plurality of extending portions are arranged corresponding to the plurality of word lines, the dummy word lines, and the select gate.

9. A manufacturing method of a memory component, characterized in that, Comprising: Providing a substrate; Forming a target layer on the substrate; Forming a sacrificial layer on the target layer; Forming a core layer on the sacrificial layer; Forming a plurality of spacers on a plurality of sidewalls of the core layer; Removing the core layer; Using the plurality of spacers as a mask to pattern the sacrificial layer to form a patterned sacrificial layer; Forming a hard mask layer between the patterned sacrificial layers; Removing the patterned sacrificial layer; And Using the hard mask layer as a mask to pattern the target layer to form a plurality of word lines, dummy word lines, and a select gate, wherein the dummy word lines are between the plurality of word lines and the select gate.

10. The manufacturing method of the memory component according to claim 9, wherein a width of the dummy word line is greater than a width of the word line.

11. The manufacturing method of the memory component according to claim 9, wherein a first gap between the plurality of word lines has a first gap width, a second gap between the dummy word line and the outermost word line of the plurality of word lines has a second gap width, and a ratio of the second gap width to the first gap width is between 0.95 and 1.

05.

12. The manufacturing method of the memory component according to claim 11, wherein a third gap between the dummy word line and the selection gate has a third gap width, and a ratio of the third gap width to the first gap width is between 0.95 and 1.

05.

13. The manufacturing method of the memory component according to claim 9, further comprising: Locally removing the hard mask layer to expose a part of the target layer.

14. The manufacturing method of the memory component according to claim 13, wherein patterning the target layer using the hard mask layer as a mask further comprises: Forming a dummy comb and a plurality of dummy pillars adjacent to a plurality of ends of the plurality of word lines, the dummy word line, and the selection gate, wherein the dummy comb comprises: A main body portion; and A plurality of extending portions located between the main body portion and the plurality of word lines and connected to the main body portion, wherein the plurality of dummy pillars are located between the main body portion and the plurality of word lines and are alternately arranged with the plurality of extending portions, and the plurality of dummy pillars and the plurality of extending portions are arranged corresponding to the plurality of word lines, the dummy word line, and the selection gate.

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