Shaped surface brightness led with adjustable brightness gradient

Abstract

The present specification discloses light emitting device electrical contacts that improve performance and specificity for an operator of a light emitting device. The small number of electrical contacts includes two or three contacts that can be driven independently of one another to achieve a desired brightness distribution. With the devices and methods described in the present specification, forward voltage Vf and internal quantum efficiency (IQE) can be readily known, thereby allowing ease of use in combination with adaptation.

Description

[0001] Cross - reference to related applications This application claims the benefit of the priority of U.S. Provisional Application No. 63 / 433,297, filed on December 16, 2022, which is hereby incorporated by reference in its entirety into this application. Background of the Invention

[0002] Semiconductor light - emitting diodes and laser diodes (collectively referred to herein as "LEDs") are among the most efficient light sources currently available. The emission spectrum of an LED typically exhibits a single narrow peak at a wavelength determined by the structure of the device and the composition of the semiconductor materials that make it up. By appropriately selecting the device structure and material system, an LED can be designed to operate at ultraviolet, visible, or infrared wavelengths.

[0003] An LED can be combined with one or more wavelength - converting materials (generally referred to herein as "phosphors") that absorb the light emitted by the LED and, in response, emit light at a longer wavelength. For such phosphor - converted LEDs ("pcLEDs"), the fraction of the light emitted by the LED that is absorbed by the phosphor depends on the amount of phosphor material in the optical path of the light emitted by the LED, e.g., on the concentration of the phosphor material in a phosphor layer disposed on or around the LED and the thickness of that layer. A phosphor - converted LED can be designed such that all of the light emitted by the LED is absorbed by one or more phosphors, in which case the emission from the pcLED comes entirely from the phosphors. In such a case, for example, the phosphors can be selected to emit light in a narrow spectral region that is not directly and efficiently generated by the LED. Alternatively, a pcLED can be designed such that only a portion of the light emitted by the LED is absorbed by the phosphor, in which case the emission from the pcLED is a mixture of the light emitted by the LED and the light emitted by the phosphor. By appropriately selecting the LED, the phosphor, and the phosphor composition, such a pcLED can be designed to emit, for example, white light having a desired color temperature and desired color - rendering properties.

[0004] Inorganic LEDs and pcLEDs have been widely used in the manufacture of different types of displays, matrices, and light engines, including: motor vehicle adaptive headlights, augmented reality (AR) displays, virtual reality (VR) displays, mixed reality (MR) displays (AR, VR, and MR systems are referred to herein as visualization systems), smart glasses, and displays for mobile phones, smart watches, monitors, and televisions, as well as flash lighting for cameras in mobile phones. Depending on the size of the matrix or display and its pixel - per - inch requirements, each LED or pcLED in these architectures can have an area ranging from several square millimeters down to several square micrometers (e.g., micro - LEDs).

[0005] Such LEDs and pcLEDs can be arranged in arrays for use, for example, in motor vehicles and for general lighting, including indoor and outdoor. Specifically, some of these LEDs and pcLEDs can be shaped to have a specific brightness distribution with a brightness gradient and / or a region with peak brightness. In particular, these multi-die packages with these LEDs and pcLEDs can be used for high beam and low beam applications in motor vehicle headlights. Analysis of some motor vehicle system optics shows that shaped surface brightness with a peak at the center or a gradient from one side to the other has the best system optics efficiency, which is indicated by the system optics figure of merit (FOM).

[0006] The ideal brightness shape will depend on many parameters, such as the system optics, the application area, and the operating conditions. For edge-shifted luminance (ESL) dies and center-peak luminance (CPL) dies, there may be different degrees of brightness distribution. Figure 11 Dies with different brightness distributions are depicted. The first row shows the ESL dies, and the second row shows the CPL dies with different gradients between the peak brightness and the opposite side, as well as the corresponding internal quantum efficiency (IQE) and forward voltage Vf. Note that the IQE and Vf losses will strongly depend on the operating current level.

[0007] Many motor vehicle kit manufacturers are using custom-designed system optics with specific board layouts and shapes, primary and secondary optics, and the number of LEDs. Ultimately, all headlights are different, and there is no ideal surface brightness distribution that will fit all systems. The trade-off between the brightness gradient, IQE drop, and Vf increase will also strongly depend on the application and operating conditions. Therefore, it is beneficial to allow the end user to dynamically adapt the surface brightness distribution to fit specific system optics requirements, operating conditions, and application conditions.

[0008] A shaped brightness distribution die is defined as a die in which the brightness averaged over a region equal to at least 10% of the entire emission area deviates by 20% or more from the average brightness averaged over the entire emission area. When this deviation involves more brightness, this region can be called the peak brightness region.

[0009] Typically, dynamic driving of the brightness shape is obtained by feeding or adding more current to different segments or regions of the die. The typical way to produce different brightness distributions with the same die involves a large number of contact paths - for example, more than three - which results in too abrupt changes. These existing methods have a strong impact on the IQE drop and Vf increase. The drop in IQE is mainly caused by current crowding and lower IQE at higher currents.

[0010] Another disadvantage of the dynamic variation of the light-emitting area (LEA) with undefined or a large number of electrical contacts is that it leaves too many driving possibilities for the end user without clear guidance on how to achieve the desired brightness distribution and how to minimize the impact on IQE and Vf. Additionally, with so many electrical contacts, a larger pitch will be required between the electrical contacts. As a result, the interconnect area will be very small and, consequently, the thermal resistance (Rth) will be very high. What is needed is a method and device that provide simplified and clear driving possibilities adaptable to different brightness distributions. Summary of the Invention

[0011] This specification discloses a method and device for driving current into a die, where a small number (e.g., three or four) of electrical contacts are disengaged from the die, which can provide increased efficiency when adjusting the shaped brightness of the die. The die can have two or three n-side electrical contacts that can be driven independently of each other to provide good adaptability to different desired brightness distributions. This method provides increased clarity for the die operator on what type of distribution can be obtained and at what performance cost.

[0012] The present invention can be used in any motor vehicle headlamp where a single-die package or a multi-die package is required. It is preferably used in a multi-die package where the surface brightness distribution of each die is intentionally non-uniform and where large solder pads must completely cover the area where peak current is generated to reduce the thermal resistance.

[0013] When referring to the following more detailed description of the present invention in conjunction with the accompanying drawings, which are briefly described first, other embodiments, features, and advantages of the present invention will become clearer to those skilled in the art. Brief Description of the Drawings

[0014] Figure 1 A schematic cross-sectional view of an exemplary pcLED is shown.

[0015] Figure 2A and Figure 2B Schematic cross-sectional and top views of a pcLED array are shown, respectively. Figure 2C A schematic top view of an LED wafer is shown, from which an LED array such as Figure 2A and Figure 2B the LED arrays shown in can be formed.

[0016] Figure 3A A schematic top view of an electronic board on which an LED or a pcLED array can be mounted is shown, and Figure 3B similarly, a pcLED array mounted on the Figure 3A electronic board is shown.

[0017] Figure 4A A schematic cross-sectional view of a pcLED array arranged relative to a waveguide and a projection lens is shown. Figure 4B A layout similar to that without the waveguide is shown Figure 4A is shown.

[0018] Figure 5 An example camera flash system is schematically shown.

[0019] Figure 6a A top view of a bonding structure on the n-side is shown, where the bonding structure can contact a semiconductor diode structure. Figure 6b A dielectric layer between two n-sides of the bonding structure and one p-side of the bonding structure is shown. Figure 6c An electrical contact detached from a die connected to the bonding structure is shown.

[0020] Figure 7 A cross-section of a die is shown, which includes an epitaxial layer, a bonding structure, and two types of n-contacts and one type of p-contact.

[0021] Figure 8a A top view of a bonding structure on the n-side is shown, where the bonding structure can contact a semiconductor diode structure. Figure 8b A dielectric layer between two n-sides of the bonding structure and one p-side of the bonding structure is shown. Figure 8c An electrical contact detached from a die connected to the bonding structure is shown.

[0022] Figure 9 a shows a cross-section of a package, where one of the two n-contacts is wire-bonded under the semiconductor diode structure instead of soldered.

[0023] Figure 10 A top view of a bonding structure having three rather than two bonding structures on the n-side is shown.

[0024] Figure 11 Dies having different brightness distributions are depicted.

[0025] Figure 12 It shows how the kurtosis of an edge-offset brightness die can be adjusted by adjusting the current of two n-contacts.

[0026] Figure 13 A graph used as a basis for constructing a look-up table is shown, which allows for simplifying the adjustment of the brightness distribution in embodiments of the present invention. Detailed Description

[0027] The following detailed description should be read with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout the different figures. The drawings, which are not necessarily to scale, depict alternative embodiments and are not intended to limit the scope of the invention. The detailed description illustrates, by way of example, not by way of limitation, the principles of the invention.

[0028] Figure 1 An example of a single pcLED 100 is shown, which includes a light-emitting semiconductor diode (LED) structure 102 disposed on a substrate 104, and a phosphor layer 106 (which may also be referred to herein as a wavelength conversion structure) disposed on the LED. The light-emitting semiconductor diode structure 102 generally includes an active region disposed between an n-type layer and a p-type layer. Applying an appropriate forward bias across the diode structure causes light to be emitted from the active region. The wavelength of the emitted light is determined by the composition and structure of the active region.

[0029] For example, the LED can be a Group III nitride LED that emits ultraviolet, blue, green, or red light. LEDs formed from any other suitable material system and emitting any other suitable wavelength of light can also be used. Other suitable material systems can include, for example, Group III phosphide materials, Group III arsenide materials, and II-IV materials.

[0030] Any suitable phosphor material can be used, depending on the desired optical output and color specifications from the pcLED. The phosphor layer can, for example, include phosphor particles dispersed in a binder material or bonded to each other with a binder material, or can be or include a sintered ceramic phosphor plate.

[0031] Figure 2A - Figure 2B A cross-sectional view and a top view of an array 200 of pcLEDs 100 including a phosphor layer 106 disposed on a substrate 202 are shown, respectively. Such an array can include any suitable number of pcLEDs arranged in any suitable manner. In the illustrated example, the array is depicted as being formed monolithically on a shared substrate, but alternatively, an array of LEDs or pcLEDs can be formed from individually mechanically separated LEDs or pcLEDs. The substrate 202 can optionally include CMOS circuitry for driving the LEDs and can be formed from any suitable material.

[0032] Although Figure 2A - Figure 2BA three-by-three array of nine pcLEDs is shown, but such arrays can include, for example, dozens, hundreds, or thousands of LEDs or pcLEDs. The width (e.g., side length) of each LED or pcLED in the array plane can be, for example, less than or equal to 1 millimeter (mm), less than or equal to 500 micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, or less than or equal to 10 micrometers. The LEDs in such an array can be spaced apart from each other by streets or lanes, which have a width in the array plane of, for example, hundreds of micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, less than or equal to 10 micrometers, or less than or equal to 5 micrometers. Although the example shown depicts rectangular LEDs or pcLEDs arranged in a symmetric matrix, the LEDs or pcLEDs and the array can have any suitable shape or arrangement and do not all need to have the same shape or size. For example, the LEDs or pcLEDs located in the central portion of the array may be larger than the LEDs or pcLEDs located in the peripheral portion of the array. Alternatively, the LEDs or pcLEDs located in the central portion of the array can be smaller than the LEDs or pcLEDs located in the peripheral portion of the array.

[0033] Figure 2C A schematic top view of a portion of an LED wafer 210 is shown from which an LED array such as Figure 2A and Figure 2B the LED arrays shown in Figure 2C can be formed. An enlarged 3×3 portion of the wafer is also shown. In the example wafer, each LED or pcLED 111 having a side length (e.g., width) of W1 is arranged in a square matrix, with the center-to-center distance between adjacent LEDs or pcLEDs being D1 and separated by a lane 113 having a width of W2. W1 can be, for example, less than or equal to 1 millimeter (mm), less than or equal to 500 micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, or less than or equal to 10 micrometers. W2 can be, for example, hundreds of micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, less than or equal to 10 micrometers, or less than or equal to 5 micrometers. D1 = W1 + W2.

[0034] For example, an array can be formed by cutting the wafer 210 into individual LEDs or pcLEDs and arranging the die on a substrate. Alternatively, the array can be formed from the entire wafer 210 or by dividing the wafer 210 into smaller LED or pcLED arrays.

[0035] LEDs or pcLEDs having dimensions (e.g., side length) in the array plane less than or equal to about 50 micrometers are generally referred to as microLEDs, and an array of such microLEDs can be referred to as a microLED array.

[0036] In a pcLED array, all pcLEDs can be configured to emit light of substantially the same spectrum. Alternatively, the pcLED array can be a multicolor array, where different pcLEDs in the array can be configured to emit light of different spectra (colors) by employing different phosphor compositions. Similarly, in an array of direct-emitting LEDs (i.e., without wavelength conversion by a phosphor), all LEDs in the array can be configured to emit light of substantially the same spectrum, or the array can be a multicolor array that includes LEDs configured to emit light of different colors.

[0037] Individual LEDs or pcLEDs in the array can be individually operable (addressable) and / or can be operable as part of a group or subset of LEDs or pcLEDs in the array (e.g., adjacent).

[0038] An array of LEDs or pcLEDs, or portions of such an array, can be formed as a segmented monolithic structure, where individual LEDs or pcLEDs are electrically isolated or partially electrically isolated from each other by trenches and / or insulating materials, but the electrically isolated or partially electrically isolated segments remain physically connected to each other through other portions of the semiconductor structure. For example, in such a monolithic structure, an active region and a first semiconductor layer of a first conductivity type (n or p) on one side of the active region can be segmented, and a second unsegmented semiconductor layer of the opposite conductivity type (p or n) is located on the side of the active region opposite the first semiconductor layer. The second semiconductor layer can then physically and electrically connect the segmented structures to each other on one side of the active region, where the segmented structures are otherwise electrically isolated from each other and can thus be operated individually as separate LEDs.

[0039] Thus, an LED or pcLED array can be or include a monolithic multicolor matrix of individually operable LED or pcLED light emitters. The LEDs or pcLEDs in the monolithic array can be, for example, microLEDs as described above.

[0040] A single individually operable LED or pcLED or a group of adjacent such LEDs or pcLEDs can correspond to a single pixel (picture element) in a display. For example, a group of three individually operable adjacent LEDs or pcLEDs including a red emitter, a blue emitter, and a green emitter can correspond to a single color-tunable pixel in a display.

[0041] As Figure 3A - Figure 3BAs shown, an LED or pcLED array 200 can be mounted, for example, on an electronic board 300 that includes a power and control module 302, a sensor module 304, and an attachment area 306. The power and control module 302 can receive power and control signals from an external source as well as signals from the sensor module 304, and the power and control module 302 controls the operation of the LED / pcLED based on these signals. The sensor module 304 can receive signals from any suitable sensor (such as from a temperature or light sensor). Alternatively, the array 200 can be mounted on a separate board (not shown) from the power and control module and the sensor module.

[0042] Each LED or pcLED can optionally be combined or arranged in combination with a phosphor layer positioned adjacent to the LED or pcLED or a lens or other optical element disposed on the phosphor layer of the LED or pcLED. Such optical elements not shown in the figures can be referred to as "primary optical elements". Additionally, as Figure 4A - Figure 4B shown, the array 200 (e.g., mounted on the electronic board 300) can be arranged in combination with secondary optical elements such as waveguides, lenses, or both for use in an intended application. In Figure 4A this case, the light emitted by the pcLED 100 is collected by the waveguide 402 and directed to the projection lens 404. For example, the projection lens 404 can be a Fresnel lens. Such an arrangement can be suitable for use, for example, in vehicle headlights. In Figure 4B this case, the light emitted by the pcLED 100 is directly collected by the projection lens 404 without using an intervening waveguide. This arrangement can be particularly suitable when the LEDs or pcLEDs can be spaced close enough to each other and can also be used in vehicle headlights as well as in camera flash applications. For example, a micro-LED display application can use an optical arrangement similar to the Figure 4A - Figure 4B optical arrangement depicted.

[0043] In another example arrangement, a central block of LEDs or pcLEDs in the array can be associated with a single common (shared) optical device, and the edge LEDs or pcLEDs in the array located at the periphery of the central block are each associated with a corresponding individual optical device.

[0044] Generally, depending on the desired application, any suitable optical element arrangement can be used in combination with the LED and pcLED arrays described herein.

[0045] The LED and pcLED arrays as described herein can be used in applications that require or benefit from fine-grained intensity, spatial, and temporal control of light distribution. Such applications can include, but are not limited to, precise special patterning of the emitted light from individual LEDs or pcLEDs or from groups (e.g., blocks) of LEDs or pcLEDs. Depending on the application, the emitted light can be spectrally distinct, time-adaptive, and / or environment-responsive. Such arrays can provide pre-programmed light distributions in various intensity, spatial, or temporal patterns. The emitted light can be at least partially based on received sensor data and can be used for optical wireless communication. The associated electronics and optics can be distinct at the level of individual LEDs / pcLEDs, groups, or devices.

[0046] An array of individually operable LEDs or pcLEDs can be used in combination with lenses, lens systems, or other optical devices or optical systems (e.g., as described above) to provide illumination suitable for a particular purpose. For example, in operation, such an adaptive lighting system can provide illumination that changes color and / or intensity across an illuminated scene or object and / or aims in a desired direction. Beam focusing or steering of the light emitted by the LED or pcLED array can be electronically performed by activating the LEDs or pcLEDs in groups of different sizes or sequentially activating the LEDs or pcLEDs to allow dynamic adjustment of the beam shape and / or direction without moving the optics or changing the focus of the lenses in the lighting device. The controller can be configured to receive data indicating the position and color characteristics of objects or people in the scene and control the LEDs or pcLEDs in the array based on this information to provide illumination suitable for the scene. Such data can be provided by, for example, image sensors, optical (e.g., laser scanning) sensors, or non-optical (e.g., millimeter wave radar) sensors. Such adaptive lighting is becoming increasingly important for motor vehicles (e.g., adaptive headlights), mobile device cameras (e.g., adaptive flash), and AR, VR, and MR applications (such as the applications described below).

[0047] Figure 5 An example camera flash system 500 including an LED or pcLED array and an optical (e.g., lens) system 502 is schematically shown. The example camera flash system 500 can be or include an adaptive lighting system as described above, in which the LEDs or pcLEDs in the array can be individually operable or group-operable. In the operation of the camera flash system, the illumination from some or all of the LEDs or pcLEDs in the array and the optical system 502 can be adjusted (deactivated, operated at full intensity, or operated at intermediate intensity). As described above, the array can be a monolithic array or include one or more monolithic arrays. As described above, the array can be a microLED array.

[0048] The flash system 500 also includes an LED driver 506 controlled by a controller 504, such as a microprocessor. The controller 504 may also be coupled to a camera 507 and a sensor 508, and operate according to instructions and profiles stored in a memory 510. The camera 507 and the LED or pcLED array and lens system 502 may be controlled by the controller 504 to, for example, match the illumination provided by the system 502 (i.e., the field of view of the illumination system) to the field of view of the camera 507, or otherwise adapt the illumination provided by the system 502 to the scene observed by the camera as described above. The sensor 508 may include, for example, a position sensor (e.g., a gyroscope and / or an accelerometer) and / or other sensors that may be used to determine the position and orientation of the system 500.

[0049] As described above, shaped brightness dies are particularly useful for many applications. A large number of contact paths into the die can be utilized to achieve shaped brightness. However, if there are too many contact paths, this may lead to current crowding and a decrease in efficiency.

[0050] To reduce the risk of sharp current crowding and associated uncontrollable Vf increase when changing the surface brightness distribution of a shaped brightness die, embodiments of the present invention include a specific die design with an adjustable brightness gradient. These methods and devices may include balancing (e.g., with different magnitudes) independently driven currents between two paths on the n-side. One path is a central n-contact connecting all etched regions within the die area, and the other path is an n-external contact located along the outer mesa etched region. By balancing the current between the central n-contact and the n-contact edge, it is possible to smoothly change the brightness distribution and minimize the negative impact on IQE and Vf, without the need to add an excessive number of n-vias (i.e., bonding structures passing through the p-type layer and insulated by the first dielectric layer), increase the size of the n-vias, or segment the die into many individually controllable small parts to obtain a specific brightness gradient. This allows the user of the die to adjust the surface brightness distribution to obtain an optimal system performance FOM, while having a low impact on IQE reduction and Vf increase. Additionally, this reduces the risk of lower process yield due to non-periodic die patterning.

[0051] In a semiconductor die, the conductivity of the p-type layer or pGaN is typically lower than that of the n-type layer or nGaN. As a result, current can be uniformly injected into the pGaN layer to minimize Vf increase.

[0052] However, on the n-side, current will be injected via two different paths connected in parallel: the central n-contact and the n outer-edge contact. The contact region of the epitaxial layer having a bonding structure electrically connected to the n outer-edge contact may include all or a portion of the outer mesa etch region surrounding the die. The bonding structure may have a width w (shown in Figure 6a or Figure 8a ) of several microns (such as from 1 - 50 microns, for example 1 - 10 microns) over the mesa etch region surrounding the active region of the die. The width may be measured perpendicular to the direction of the corresponding edge of the epitaxial layer adjacent to a particular portion of the bonding structure. Around the perimeter of the epitaxial layer, the mesa may have the same width or a greater width.

[0053] In an embodiment of the present invention, Figure 6a - Figure 6c a top-view layout of the n-contact and p-contact and current injection paths, and the bonding structure to be attached to the epitaxial layer are shown such that the die can produce a CPL luminance distribution. The n portion of the bonding structure may be made of two different parts: one part contacts only the central n via (i.e., the central bonding structure), and one part contacts only the n edge / outer region. The p-contact, which makes a total of three electrical contacts, is detached from the die and attached to the drive circuit. Many other variations are possible. For example, the isolated n outer contact may also be connected to some of the n vias.

[0054] Figure 6a Only the layout of the n-bonding structure 664 and the central n via (n central bonding structure 666) is shown. The n outer bonding structure 664 may be drawn as a square or rectangle completely surrounding the n central bonding structure 666, and the n central bonding structures 666 are spaced apart from each other in an A×B array, where A and B may be from 1 to 10, for example 3, as shown in FIG. 6A. The central n via may have any shape (circular, rectangular slot, etc.). This figure only depicts a portion of the bonding structure in direct contact with the n-type layer 670. That is, the central n vias of the n central bonding structures 666 are spaced apart from each other at least at the points of contact with the epitaxial layer. However, they may all be connected together such that they are all electrically conductive with each other at a certain distance from the epitaxial layer.

[0055] Figure 6b A first dielectric 660 is shown, which has openings for the n central bonding structure 666 and the p-bonding structure 668. The first dielectric 660 spaces apart the n-bonding structure and the p-bonding structure and isolates the n-bonding structure and the p-bonding structure from being directly electrically connected to each other.

[0056] Figure 6cShows n external contacts 624, n center contacts 626, and p contacts 628 that are disposed below the n - junction structure and p - junction structures 664, 666, and 668 and are connected to the n - junction structure and p - junction structures 664, 666, and 668 respectively.

[0057] Figure 7 Shows a cross - section of die 602 having electrical connections / pads attached to the epitaxial layer and / or stack that are similar or identical to those of FIG. 6, particularly the connections of n external contacts 624, n center contacts 626, and p contacts 628. Each of the n external contacts 624 and n center contacts 626 can be driven by a current independent of each other. The epitaxial layer 610 includes an n - type layer 670 (e.g., nGaN), quantum wells 675, and a p - type layer 673 (e.g., pGaN). The n external contact 624 can be in a shape that surrounds the n center contact 626 and the p contact 628. The n external contact 624 is electrically connected to the n - type layer 670 through an n external junction structure 664, and the n external junction structure 664 is physically spaced from the p - type layer 673 by a first dielectric 665. The first dielectric 665 can be or include SiO2, SiN x or TiO x 、AlO x 、NbO x any one of; any material that is substantially non - conductive and compatible with PECVD or ALD processes. The n center contact 626 is electrically connected to the n - type layer through an n center junction structure 666. The p contact 628 is electrically connected to the p - type layer through a p junction structure 668. The p junction structure 668 makes direct physical contact with both: the p contact 628; and a p - type layer or mirror layer 680 that is in electrical contact and / or direct physical contact with the p - type layer 673. The mirror layer 680 can include: a silver layer; and / or a dielectric mirror having a conductive via passing through the dielectric mirror such that the conductive via contacts the p - type layer 673, thereby electrically connecting the p contact 628 to the p - type layer 673. The n external junction structure 664, n center junction structure 666, and p junction structure 668 are spaced from adjacent junction structures by a first dielectric 660. For example, in FIG. 6, the left - most p junction structure 668 is spaced from the n center junction structure 666 on the left, with only the first dielectric 660 in between (which prevents a direct electrical connection between the two); the lower p contact 628 makes direct physical contact and direct electrical connection with the p junction structure 668 while being spaced from the n center junction structure 666 such that the two are neither in direct physical contact nor in direct electrical connection. The n external junction structure 664 and n center junction structure 666 are similarly spaced by the first dielectric such that they are neither in direct physical contact nor in direct electrical connection. In addition, the n external junction structure 664 and n center junction structure 666 are spaced from the p - type layer 673, quantum wells 675, and mirror layer 680 by the first dielectric 660.

[0058] The n-external contact 624 and the corresponding n-external bonding structure 664 can be disposed below a mesa 630 etched around the perimeter or a portion of the perimeter of the n-type layer 670. The n-external bonding structure 664 can be in direct contact with the mesa 630. The top surface of the n-external contact 624 can partially overlap or fully overlap the mesa 630 (e.g., when viewed along the third direction Z, their areas can partially intersect or fully intersect). Thus, the n-type layer 670 has a mesa 630 that has a height in a third direction Z (perpendicular to the first direction X and the second direction Y) that is less than an adjacent region in the n-type layer 670 that has a greater height. The outer edge of the n-external bonding structure 664 can be flush with the edge of the mesa 630 and / or flush with the outermost edge of the n-type layer 670. However, this is not required, and the n-external bonding structure 664 can extend beyond the edge of the epitaxial layer 610 or be surrounded by the edge of the epitaxial layer 610.

[0059] The n-external bonding structure 664, the n-center bonding structure 666, and the p-bonding structure 668 can be made of Cu, Al, or Ag and / or any combination. Generally, any conductive material can be used. The sheet resistance of this layer is typically low to reduce current spreading losses.

[0060] The n-external contact 624, the n-center contact 626, and the p-contact 628 can be spaced apart from each other by a silicone resin or an air gap and / or a second dielectric 662. The second dielectric 662 can be the same or a different material from the first dielectric 660. In an embodiment of the present invention, the second dielectric 662 can be omitted.

[0061] Figure 7 One n-external contact 624, one n-center contact 626, and one p-contact 628 are depicted. As a result, only three electrical terminals come out of the die 600 and are connected to the drive circuit. However, this is not required, and there can be more terminals, such as a second n-external contact that is electrically isolated from the first external contact, to make a total of four electrical terminals. In summary, two different n-current injection paths are connected to two different bonding structures, which are connected to two different solder pads / contacts. In summary, a die according to an embodiment of the present invention can have only three different terminals: a common p-contact, one connected to a center n via, and one connected to an n-external n via bonding structure.

[0062] Disposed on the die 610 can be a substrate 658 (e.g., a sapphire wafer or an undoped semiconductor material) bonded to a phosphor layer 655 through an adhesive layer 650. The die having an adjustable light-emitting region can be a VTF (Vertical Thin Film or Embedded Contact Vertical Film), a CSP (Sapphire Still Epitaxial), or a TFFC (Thin Film Flip Chip).

[0063] According to an embodiment of the present invention, Figure 8a - FIG. 8e shows a top view layout of n and p contacts and current injection paths, as well as a bonding structure that will be attached to the epitaxial layer so that the die can produce an ESL luminance distribution (i.e., where the luminance gradient varies from one side of the die to the opposite side). In this example, the n external contact 664 is only arranged as a U-shaped ring, rather than along the entire mesa etch region, such that it only overlaps with a portion of the mesa 630. That is, the n external contact 624 only partially surrounds the non-mesa portion of the epitaxial layer and the n center bonding structure 666. The n external contact 664 can have other shapes, such as: extending only along one edge of the die without extending around the other edges, extending only along one corner of the die without extending entirely along the entire edge, extending only along a portion of one edge without intersecting the corner, and other similar configurations.

[0064] Figure 8a Only the layout of the n bonding structure 664 and the center n vias (n center bonding structure 666) is shown. The n center bonding structure 666 shows a 3×4 array of center n vias.

[0065] Figure 8b The first dielectric 660 is shown, which has openings for the n center bonding structure 666 and the p bonding structure 668. This first dielectric 660 spaces apart the n and p bonding structures and isolates the n and p bonding structures from being directly electrically connected to each other.

[0066] Figure 8c The n external contact 624, the n center contact 626, and the p contact 628 are shown, which are disposed below the n and p bonding structures 664, 666, and 668 and are respectively connected to the n and p bonding structures 664, 666, and 668. The n external contact 624 and the p contact 628 can be disposed on opposite sides of the die, and the n center contact 626 is in between. All the contacts can have the same or similar dimensions, although this is not necessary.

[0067] Using only three large pads, the die with an adjustable luminance gradient can be connected to a tile through standard flip-chip solder bumps.

[0068] Figure 9An embodiment of the present invention is depicted, where the die substrate 658 (which can be an undoped semiconductor) can be etched, and the n external contact 624 can be disposed on top of the epitaxial layer 610 via wire bonding 649, to the separate pad regions 644 of the tile 640. That is, the n external contact 624 is located on the opposite side of the epitaxial layer 610 as the n center contact 626 and the p contact 628. As a result, only two electrical pads are present at the bottom of the epitaxial layer 610, which maximizes the interconnect area and reduces the reliability risk. These two electrical pads can include the n center contact 626, the p contact 628, and the solder 646, and the solder 646 connects this contact to the tile top metallization layer 648 arranged to be in direct contact with the tile 640. The tile 640 can be CMOS.

[0069] The die with an adjustable brightness gradient can be a VTF (Vertical Thin Film or Embedded Contact Vertical Thin Film), a chip-scale package (CSP; sapphire is still epitaxial), or a TFFC (Thin Film Flip Chip).

[0070] For such a die, the kurtosis (i.e., the deviation of the average brightness of the peak brightness region from the average brightness of the entire emission region) can be increased by reducing the portion of the current injected via the n external contact 624. For example, if a flat brightness distribution can be obtained for a ratio of 1 / 1 between the n center current and the n external current, this ratio can be set to 0.6 / 0.4 to obtain a peak brightness distribution. Additionally, if the die is operated at a current where the increase in Vf and the decrease in IQE are not significant, the operator will be free to further increase the ratio between the n center contact current and the n external (top-side) contact current, such as 0.8 / 0.2, thereby further increasing the kurtosis. In Figure 12 an example of current driving for obtaining different "degrees" of edge-offset brightness distribution is shown.

[0071] An adjustable brightness gradient die can be fabricated to switch between an ESL and a CPL brightness distribution. In this case, there may be a total of four electrical terminals coming out of the die instead of three. Here, there are three electrical contacts on the n side, which can be independently driven from each other (e.g., by currents of different magnitudes). In other words, these three n-side electrical contacts can be electrically connected to portions of a bonding structure that are electrically isolated from each other by a first dielectric. Figure 10This depicts such a layout: a region 664 with an n external bonding structure, a region 666 with an n center bonding structure, and a region 665 with a second n external bonding structure. All of these bonding structures can be segmented such that they do not physically contact each other directly at any point. The n external bonding structures can together form the entire perimeter of the die or epitaxial layer. For example, one extends the length of one edge and the other is in a U-shaped loop. In this case, at least one additional pad may be required, which will clamp the pad area under the epitaxial layer. Thus, the contact with the tile / base may have to be done via GGI (gold-to-gold interconnect) or solder microbumps. For example, compared to the rest of the bonding structures in the die, when most of the current in the die passes through the n center bonding structure 666, there is a CPL distribution with a very many peaks at the center; when the n center bonding structure 666 has most of the current and some of the current passes through both the n external bonding structure 665 and the second n external bonding structure 665, then there is a CPL distribution with a medium kurtosis; when most of the current passes through the n external bonding structure 664 and some of the current is in the n center bonding structure 666, there may be an ESL distribution with a kurtosis along the edge of the n external bonding structure 664 (e.g., extending along the Y direction).

[0072] In an embodiment of the present invention, a look-up table can be provided between the luminance distribution (kurtosis or gradient), Vf increase, and IQE loss, such that for example, a customer who orders dies and places them together on a package can learn how to adjust the luminance according to their needs. Then, these tables can be put into an IC unit (such as a controller on or outside the tile 640) to dynamically adapt the luminance distribution to external conditions or different driving conditions. This principle is shown in Figure 13 shown below.

[0073] The die according to the embodiment of the present invention described above can be constructed by a standard process. An important step is to obtain at least three electrically isolated bonding structures: two connected to the n-type layer and one connected to a second doped semiconductor layer. This can be achieved by using a shadow mask during deposition or by etching the bonding structures after deposition.

[0074] Preferably, first and second dielectric layers will be provided before and after the deposition of the bonding structures to ensure that the bonding structures connect to the first doped semiconductor (i.e., the maximum of the n vias) without the risk of short circuits. However, it may also be possible to use only one dielectric layer.

[0075] To electrically connect a die to a wafer, a substrate, or a board, standard flip chip solder bumps suitable for bonding areas greater than 150 um may simply be used. For smaller bonding areas, flip chip fine pitch solder bumps or flip chip micro bumps may be used. If the electrical contact area is less than 50 um, Cu pillar bumps may be used.

[0076] Although the above description depicts two or three n-side terminals emerging from the die connected in parallel with one p-contact emerging from the die, any description of the n-side and p-side of the terminals emerging from the die (and the corresponding bonding structures / semiconductor layers etc. connected to these terminals) may be reversed. For example, there may be two or three p-side terminals, with only one n-side terminal emerging from the die.

[0077] The present invention can be used in motor vehicle headlights where a gradient or peak surface brightness is required. It can also be used in any application where the surface brightness pattern must vary dynamically as a function of time, as a function of external conditions, or as a function of operating conditions.

[0078] This disclosure is illustrative and not restrictive. Given this disclosure, further modifications will be apparent to those skilled in the art and are intended to fall within the scope of the appended claims.

Claims

1. A light emitting diode, comprising: A semiconductor diode structure including an n-type layer and a p-type layer; A bonding structure disposed below the semiconductor diode structure, the bonding structure including: At least one n-center bonding structure, An n-external bonding structure spaced apart from the at least one n-center bonding structure, and A p-bonding structure spaced apart from the at least one n-center bonding structure and the n-external bonding structure; and An n-center contact electrically connected to the at least one n-center bonding structure; An n-external contact electrically connected to the n-external bonding structure; and A p-contact electrically connected to the p-bonding structure.

2. The light emitting diode according to claim 1, wherein the at least one n-center bonding structure and the n-external bonding structure are in direct contact with the n-type layer.

3. The light emitting diode according to claim 1, wherein the n-center contact and the n-external contact are configured to be independently driven by currents of different amplitudes.

4. The light emitting diode according to claim 1, wherein the at least one n-center bonding structure includes an n-through hole array contacting the semiconductor diode structure, wherein each region is spaced apart from each other region of the n-through holes at a direct contact point with the n-type layer.

5. The light emitting diode according to claim 4, wherein the array is an A×B array, where A ranges from 1 to 10 and B ranges from 1 to 10.

6. The light emitting diode according to claim 4, wherein the longest dimension of the shape formed by the n-through hole array is shorter than the longest dimension of the n-external bonding structure.

7. The light emitting diode according to claim 4, wherein the n-through hole array is completely surrounded by the n-external bonding structure.

8. The light emitting diode according to claim 1, wherein the n-external bonding structure is disposed on a mesa etched on the n-type layer.

9. The light emitting diode according to claim 8, wherein the n-external bonding structure forms a rectangle.

10. The light emitting diode according to claim 8, wherein the width of the n-external bonding structure is 1 - 50 microns as it at least partially extends around the mesa.

11. The light emitting diode according to claim 8, wherein the mesa includes four corners, and the n-external bonding structure surrounds at most only two of the four corners.

12. The light emitting diode according to claim 1, wherein the at least one n-center bonding structure and the n-external bonding structure are spaced apart from each other by a first dielectric.

13. The light emitting diode according to claim 1, wherein the n-center contact, the n-external contact, and the p-contact are spaced apart from each other by a second dielectric.

14. The light emitting diode according to claim 1, further comprising a second n-external bonding structure spaced apart from the n-external bonding structure, and a second n-external contact spaced apart from the n-external contact.

15. The light emitting diode according to claim 1, wherein the n-center contact, the n-external contact, and the p-contact include solder.

Images