Apparatus for manufacturing display apparatus

Abstract

A display device, a device for manufacturing the same, and a method of manufacturing the same are provided. The display device includes a substrate including a first display area including a first pixel area, a second pixel area, and a first transmissive area, a second display area adjacent to the first display area, and a third display area adjacent to the second display area, the second display area comprises a third pixel area, a fourth pixel area, a second transmission area and a third transmission area, and the third display area is adjacent to the second display area.

Description

[0001] This application is a divisional application of Application No. 202010672816.4, titled "Display Device, Equipment for Manufacturing the Same, and Method for Manufacturing the Same", filed with the State Intellectual Property Office of China on July 14, 2020. Technical Field

[0002] Aspects of some example embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0003] Display devices can be used for various purposes. Additionally, since the thickness and weight of display devices have decreased as technology has advanced, the range of use of display devices has increased.

[0004] Depending on the use of the display device, different methods can be used to design the shape of the display device, and different functions can be embedded in or linked to the display device.

[0005] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0006] One or more example embodiments include a display device that includes a sensor area in which sensors or other suitable components can be arranged in a display area. Some example embodiments may also include an equipment for manufacturing a display device and a method of manufacturing a display device. However, the above technical features are only examples, and the scope of the disclosure is not limited thereto.

[0007] Additional aspects will be partially set forth in the following description, and will be more apparent in part through the description, or may be learned by practice of the presented example embodiments of the disclosure.

[0008] According to some example embodiments, a display device includes: a substrate including a first display region, a second display region, and a third display region, the first display region including a first pixel region, a second pixel region, and a first transmissive region, the second display region being disposed adjacent to the first display region and including a third pixel region, a fourth pixel region, a second transmissive region, and a third transmissive region, the third display region being disposed adjacent to the second display region; a first pixel disposed in the first pixel region, each of the first pixels including a first pixel electrode, a first pair of electrodes, and a first intermediate layer between the first pixel electrode and the first pair of electrodes; a second pixel disposed in the second pixel region, each of the second pixels including a second pixel electrode, a second pair of electrodes, and a second intermediate layer between the second pixel electrode and the second pair of electrodes; a third pixel disposed in the third pixel region, each of the third pixels including a third pixel electrode, a third pair of electrodes, and a third intermediate layer between the third pixel electrode and the third pair of electrodes; and a fourth pixel disposed in the fourth pixel region, each of the fourth pixels including a fourth pixel electrode, a fourth pair of electrodes, and a fourth intermediate layer between the fourth pixel electrode and the fourth pair of electrodes, wherein the third pair of electrodes is connected to the first pair of electrodes or the second pair of electrodes, the third pair of electrodes and the fourth pair of electrodes are connected to each other, and the third pair of electrodes and the fourth pair of electrodes have different planar areas from each other.

[0009] According to some example embodiments, the first pixel region, the second pixel region, and the first transmissive region may be alternately arranged as a grid.

[0010] According to some example embodiments, the first transmissive region may be defined as a region defined by the first pixel region and the second pixel region connected to each other.

[0011] According to some example embodiments, the first pair of electrodes and the second pair of electrodes may be partially in surface contact with each other.

[0012] According to some example embodiments, the second pair of electrodes may be disposed on the first pair of electrodes in the surface contact region.

[0013] According to some example embodiments, the first transmissive region and the third transmissive region may have different shapes from each other.

[0014] According to some example embodiments, the light transmittance of the first display region may be different from the light transmittance of at least one of the second display region and the third display region.

[0015] According to some example embodiments, the first display region may provide an image having a lower resolution than the image provided by at least one of the second display region and the third display region.

[0016] According to some example embodiments, the main pixels may be arranged in the third display region, and each of the main pixels may include a main pixel electrode, a main counter electrode, and a main intermediate layer between the main pixel electrode and the main counter electrode, and the main counter electrode may be arranged on the entire surface of the third display region.

[0017] According to some example embodiments, the main counter electrode may be connected to the fourth counter electrode in the second display region.

[0018] According to some example embodiments, a plurality of main counter electrodes having a stripe shape may be provided, and the plurality of main counter electrodes may be spaced apart from each other.

[0019] According to some example embodiments, a display device includes: a substrate including a first display region, a second display region, and a third display region, the first display region including a first pixel region, a second pixel region, and a first transmissive region, the second display region being arranged adjacent to the first display region, the second display region including a third pixel region, a fourth pixel region, a second transmissive region, and a third transmissive region, the third display region being arranged adjacent to the second display region; a first pixel arranged in the first pixel region, each of the first pixels including a first pixel electrode, a first counter electrode, and a first intermediate layer between the first pixel electrode and the first counter electrode; a second pixel arranged in the second pixel region, each of the second pixels including a second pixel electrode, a second counter electrode, and a second intermediate layer between the second pixel electrode and the second counter electrode; a third pixel arranged in the third pixel region, each of the third pixels including a third pixel electrode, a third counter electrode, and a third intermediate layer between the third pixel electrode and the third counter electrode; a fourth pixel arranged in the fourth pixel region, each of the fourth pixels including a fourth pixel electrode, a fourth counter electrode, and a fourth intermediate layer between the fourth pixel electrode and the fourth counter electrode; and a component arranged on the surface of the substrate to correspond to the first display region, the component including an electronic element that emits or receives light, wherein the third counter electrode is connected to the first counter electrode or the second counter electrode, the third counter electrode and the fourth counter electrode are connected to each other, and the third counter electrode and the fourth counter electrode have different planar areas.

[0020] According to some example embodiments, the component may emit or receive light passing through the first transmissive region, and the light transmittance of the second display region and the light transmittance of the third display region may be less than the light transmittance of the first display region.

[0021] According to some example embodiments, an apparatus for manufacturing a display device includes: a chamber, a part of which is selectively opened / closed; a first support member disposed in the chamber, the first support member supporting a substrate; a mask assembly disposed in the chamber, the mask assembly facing the substrate; a second support member disposed in the chamber, the second support member supporting the mask assembly; and a deposition source disposed in the chamber, the deposition source supplying a deposition material onto the substrate, wherein the mask assembly includes a first mask assembly and a second mask assembly that are replaceable with each other, the second mask assembly includes: a mask frame; and a mask sheet mounted on the mask frame, and the mask sheet includes a first opening, a second opening disposed in a portion different from the first opening in the mask sheet, and a third opening disposed in a portion different from the first and second openings in the mask sheet, wherein the second opening is connected to the third opening, the first opening is separated from the second and third openings, the first opening and the second opening have different shapes from each other, and an area of the first opening is smaller than an area of the second opening.

[0022] According to some example embodiments, the deposition source may be in a corner of the chamber.

[0023] According to some example embodiments, the first opening may have a square shape and the second opening may have a rectangular shape.

[0024] According to some example embodiments, at least one of the first support member and the second support member may adjust a position of the substrate relative to the first mask assembly.

[0025] According to some example embodiments, a plurality of third openings may be provided to be spaced apart from each other, and each of the plurality of third openings may be provided in a line shape.

[0026] According to some example embodiments, a method of manufacturing a display device includes: disposing a substrate and a first mask assembly in a chamber; forming a first pair of electrodes in a first display region of the substrate by using a deposition material that has been supplied from the deposition source and has passed through the first mask assembly; changing a position of at least one of the substrate and the first mask assembly; forming a second pair of electrodes in the first display region by using the deposition material that has been supplied from the deposition source and has passed through the first mask assembly, the first pair of electrodes and the second pair of electrodes being at least partially stacked on each other, and forming a third pair of electrodes and a fourth pair of electrodes in a second display region and a main pair of electrodes in a third display region of the substrate after replacing the first mask assembly with the second mask assembly and supplying the deposition material from the deposition source onto the substrate, wherein the third pair of electrodes connects one of the first pair of electrodes and the second pair of electrodes to the fourth pair of electrodes, and the third pair of electrodes and the fourth pair of electrodes have different planar areas from each other.

[0027] According to some example embodiments, a first transmissive region may be provided between a first pair of electrodes and a second pair of electrodes.

[0028] According to some example embodiments, the first pair of electrodes and the second pair of electrodes may be partially in surface contact with each other.

[0029] According to some example embodiments, a second transmissive region may be provided between one of the first pair of electrodes and the second pair of electrodes, a third pair of electrodes, and a fourth pair of electrodes, and a third transmissive region may be provided between one of the first pair of electrodes and the second pair of electrodes, the third pair of electrodes, the fourth pair of electrodes, and a main pair of electrodes.

[0030] According to some example embodiments, the second transmissive region and the third transmissive region may have different shapes from each other.

[0031] According to some example embodiments, the first display region may provide an image having a resolution lower than that of an image provided by at least one of the second display region and the third display region.

[0032] According to some example embodiments, the light transmittance of the first display region may be different from that of at least one of the second display region and the third display region.

[0033] According to some example embodiments, the light transmittance of the second display region may be less than that of the first display region and greater than that of the third display region.

[0034] Other aspects, features, and characteristics of the disclosure will become better understood through the accompanying drawings, claims, and detailed description.

[0035] Systems, methods, computer-readable storage media, and / or combinations thereof may be used to implement such general and specific aspects of some example embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other aspects, features, and characteristics of certain example embodiments of the disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0037] Figure 1 is a perspective view of a display device according to some example embodiments;

[0038] Figure 2 is a cross-sectional view of a display device according to some example embodiments;

[0039] Figure 3 is a plan view of a display panel according to some example embodiments;

[0040] Figure 4 is a plan view showing Figure 3 an enlarged view of a first display region of

[0041] Figure 5 and Figure 6 is an equivalent circuit diagram of a pixel in a display panel according to some example embodiments;

[0042] Figure 7 is a diagram of a pixel circuit in a pixel according to some example embodiments;

[0043] Figure 8 is a cross-sectional view taken along line I-I' and line II-II' of Figure 7 ;

[0044] Figure 9 and Figure 10 is a plan view showing a part of a first display area according to some example embodiments;

[0045] Figure 11 and Figure 12 is a cross-sectional view taken along line B-B' of Figure 9 for showing some manufacturing processes of a display panel according to some example embodiments;

[0046] Figure 13 is a cross-sectional view taken along line B-B' of Figure 9 ;

[0047] Figure 14 is a plan view of the arrangement of counter electrodes in a display panel according to some example embodiments;

[0048] Figure 15 is a cross-sectional view taken along line C-C' of Figure 14 ;

[0049] Figure 16 is a cross-sectional view taken along line D-D' of Figure 14 ;

[0050] Figure 17 is a cross-sectional view of a device for manufacturing a display device according to some example embodiments;

[0051] Figure 18 is according to some example embodiments of Figure 17 a perspective view of a first mask assembly;

[0052] Figure 19 is a plan view showing a part of a first mask sheet of Figure 17 according to some example embodiments;

[0053] Figure 20 is a plan view showing a part of a second mask sheet of Figure 17 according to some example embodiments;

[0054] Figure 21 is a plan view of an arrangement of counter electrodes in a display panel according to some example embodiments;

[0055] Figure 22 is a plan view showing a part of a second mask sheet according to some example embodiments; Figure 17 of;

[0056] Figure 23 is a plan view of an arrangement of counter electrodes in a display panel according to some example embodiments; and

[0057] Figure 24 is a plan view showing a part of a second mask sheet according to some example embodiments; Figure 17 of. DETAILED DESCRIPTION

[0058] Since the present disclosure allows for various changes and many embodiments, aspects of some example embodiments will be shown in the drawings and described in more detail in the written description. Refer to the drawings showing one or more example embodiments in order to obtain a sufficient understanding, their advantages, and some characteristics of some example embodiments. However, the example embodiments may have different forms and should not be construed as limited to the description set forth herein.

[0059] Example embodiments will be described in more detail below with reference to the drawings. Regardless of the figure numbers, the same or corresponding components are given the same reference numerals, and redundant descriptions are omitted.

[0060] Although terms such as "first", "second", etc. may be used to describe various components, such components are not limited to the above terms. The above terms are only used to distinguish one component from another.

[0061] Expressions used in the singular include plural expressions unless they have a distinctly different meaning in the context.

[0062] In this specification, it will be understood that the terms "comprising", "having", and "including" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or may be added.

[0063] It will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, the layer, region, or component may be formed directly or indirectly on the other layer, region, or component. That is, for example, there may be an intermediate layer, intermediate region, or intermediate component.

[0064] For ease of explanation, the dimensions of components in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0065] The X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0066] When a certain embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order.

[0067] Figure 1 is a perspective view of a display device 1 according to some example embodiments.

[0068] Referring to Figure 1 , the display device 1 includes a display area DA that implements (or displays) an image and a non-display area NDA that does not implement (or does not display) an image. The display area DA includes a first display area DA1, a second display area DA2, and a third display area DA3. The display device 1 may provide a main image based on light emitted from a plurality of main pixels PXm arranged in the third display area DA3.

[0069] As will be described in more detail below with reference to Figure 2 , at least one of the first display area DA1 and the second display area DA2 may be an area in which components such as sensors using infrared rays, visible light, or sound are arranged. Hereinafter, for ease of description, a case where components are arranged in the first display area DA1 will be described, but the embodiments are not limited thereto.

[0070] Therefore, according to some example embodiments, the display device 1 may include a display area DA having a plurality of sub-display areas (e.g., DA1, DA2, and DA3, although the embodiments are not limited to three sub-display areas, and various embodiments may include any suitable number of sub-display areas according to the design of the display device 1). One or more of the sub-display areas may be an area in which a plurality of main pixels PXm for displaying an image are arranged. In addition, one or more of the sub-display areas may be an area in which an image can be displayed by pixels, but may also be an area in which one or more components (such as sensors or transmitters) may be located to receive or sense an input signal (e.g., light, sound, etc.) and / or to emit or transmit an output signal (e.g., light, sound, etc.).

[0071] The first display area DA1 may include a first transmissive area TA1 through which light and / or sound can be output or emitted from the component to the outside, or light and / or sound traveling from an external source can be transmitted through the first transmissive area TA1 to the component. According to some example embodiments, when light is transmitted through the first display area DA1, the light transmittance may be about 10% or greater, for example, 20% or greater, 25% or greater, 50% or greater, 85% or greater, or 90% or greater.

[0072] The light transmittance of the first display area DA1 may be different from at least one of the light transmittances of the second display area DA2 and the third display area DA3. For example, the light transmittance of the first display area DA1 may be greater than the light transmittance of the second display area DA2 or the third display area DA3. According to some example embodiments, the light transmittance of the first display area DA1 may be greater than the light transmittances of the second display area DA2 and the third display area DA3. In this case, the light transmittance of the second display area DA2 may be greater than the light transmittance of the third display area DA3. For example, the light transmittance of the second display area DA2 may be equal to the arithmetic mean of the sum of the light transmittance of the first display area DA1 and the light transmittance of the third display area DA3.

[0073] According to some example embodiments, a plurality of auxiliary pixels PXa may be arranged in the first display area DA1, and an image (e.g., a set or predetermined image) may be provided by using the light emitted from the plurality of auxiliary pixels PXa. The image provided from the first display area DA1 is an auxiliary image having a lower resolution than the image provided from at least one of the second display area DA2 and the third display area DA3. That is, since the first display area DA1 includes the first transmissive area TA1 through which light and / or sound can be transmitted, the number of auxiliary pixels PXa arranged per unit area may be less than the number of connection pixels PXc arranged per unit area in the second display area DA2 or the number of main pixels PXm arranged per unit area in the third display area DA3. According to some example embodiments, the number of auxiliary pixels PXa arranged per unit area in the first display area DA1 may be less than the number of connection pixels PXc arranged per unit area in the second display area DA2 and the number of main pixels PXm arranged per unit area in the third display area DA3. In this case, the number of connection pixels PXc arranged per unit area in the second display area DA2 may be less than the number of main pixels PXm arranged per unit area in the third display area DA3.

[0074] Hereinafter, according to some example embodiments, although the display device 1 is described as an organic light-emitting display device, the disclosure is not limited thereto. According to some example embodiments, the display device 1 may be an inorganic light-emitting display, a quantum dot light-emitting display, or the like.

[0075] Referring to Figure 1 , the first display area DA1 is at one side of the rectangular second display area DA2, but is not limited thereto. The first display area DA1 may have a circular shape, an elliptical shape, or a polygonal shape such as a triangle, a pentagon, etc., and the position and number of the first display area DA1 may be variously modified.

[0076] Figure 2 is a cross-sectional view of the display device 1 according to some example embodiments. Figure 2 may correspond to a cross-section taken along the Figure 1 line A-A'.

[0077] Referring to Figure 2 , the display device 1 may include a display panel 10 and components 20, wherein the display panel 10 includes display elements, and the components 20 are below the display panel 10 corresponding to the first display area DA1.

[0078] The display panel 10 may include a substrate 100, a display element layer 200 on the substrate 100, and a thin film encapsulation layer 300 as an encapsulation member for sealing the display element layer 200. In addition, the display panel 10 may further include a lower protective film 175 disposed below the substrate 100.

[0079] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer containing a polymer resin and an inorganic layer.

[0080] The display element layer 200 may include a circuit layer including a thin film transistor TFT, an organic light-emitting diode OLED as a display element, and an insulating layer IL between the thin film transistor TFT and the organic light-emitting diode OLED.

[0081] In the third display region DA3, main pixels PXm each including a thin-film transistor TFT and an organic light-emitting diode OLED connected to the thin-film transistor TFT are arranged. In the second display region DA2, connection pixels PXc each including a thin-film transistor TFT and an organic light-emitting diode OLED connected to the thin-film transistor TFT are arranged. In the first display region DA1, auxiliary pixels PXa each including a thin-film transistor TFT and an organic light-emitting diode OLED connected to the thin-film transistor TFT are arranged, and lines electrically connected to the main pixels PXm, the connection pixels PXc, and the auxiliary pixels PXa may be arranged.

[0082] In addition, a first transmissive region TA1 in which no pixels are arranged may be in the first display region DA1. The first transmissive region TA1 may be understood as a region through which light / signals emitted from the component 20 or light / signals incident on the component 20 pass through. Similar to the first display region DA1, a second transmissive region TA2 and a third transmissive region TA3 may be in the second display region DA2.

[0083] The component 20 may be in the first display region DA1 and the second display region DA2. For example, the component 20 may be in the first display region DA1. The component 20 may be an electronic component using light or sound. For example, the component 20 may include a sensor that receives light (e.g., an infrared sensor), a sensor that outputs and senses light or sound to measure distance or sense a fingerprint, etc., a small-sized lamp that emits light, or a speaker that outputs sound. The electronic component using light may use various bands of light such as visible light, IR, ultraviolet (UV) light, etc. A plurality of components 20 may be in the first display region DA1. For example, a light-emitting device and a light-receiving device may be provided as the component 20 in one first display region DA1. Alternatively, one component 20 may include a light-emitting portion and a light-receiving portion.

[0084] The thin-film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, referring to Figure 2 , the thin-film encapsulation layer 300 may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0085] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymeric material. The polymeric material may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or a combination thereof.

[0086] The lower protective film 175 is attached to the lower portion of the substrate 100 to protect and support the substrate 100. The lower protective film 175 may include an opening 175OP corresponding to the first display area DA1. Since the lower protective film 175 includes the opening 175OP, the light transmittance of the first display area DA1 can be improved. The lower protective film 175 may include polyethylene terephthalate (PET) or polyimide (PI).

[0087] The area of the first display area DA1 may be larger than the area of the region where the component 20 is disposed. In Figure 2 it is shown that the first display area DA1 has an area equal to the area of the opening 175OP, but the area of the opening 175OP in the lower protective film 175 may not be equal to the area of the first display area DA1. For example, the area of the opening 175OP may be smaller than the area of the first display area DA1.

[0088] According to some example embodiments, components such as an input sensing member for sensing a touch input, an antireflection member including a polarizer and a retarder or a color filter and a black matrix, a transparent window, etc. may be further disposed on the display panel 10.

[0089] In addition, according to some example embodiments, the thin film encapsulation layer 300 is used as an encapsulation member for sealing the display element layer 200, but one or more embodiments are not limited thereto. For example, an encapsulation substrate bonded to the substrate 100 via a sealant or a frit may be used as a member for encapsulating the display element layer 200.

[0090] Figure 3 is a plan view of the display panel 10 according to some example embodiments. Figure 4 is a plan view showing Figure 3 an enlarged view of the first display area DA1 of

[0091] Referring to Figure 3 and Figure 4, various components of the display panel 10 are on the substrate 100. The substrate 100 includes a display area DA and a non-display area NDA surrounding the display area DA. The display area DA includes a second display area DA2, a third display area DA3 where a main image is displayed, and a first display area DA1 that includes a first transmissive area TA1 and displays an auxiliary image.

[0092] A plurality of main pixels PXm are in the third display area DA3. A plurality of connection pixels PXc are in the second display area DA2. Each of the main pixels PXm and each of the connection pixels PXc may include a display element such as an organic light-emitting diode OLED. Each of the main pixels PXm and each of the connection pixels PXc may emit light (e.g., red light, green light, blue light, or white light) via the organic light-emitting diode OLED. In the specification, as described above, each of the main pixels PXm and each of the connection pixels PXc may be understood as a pixel that emits red light, green light, blue light, or white light. The second display area DA2 and the third display area DA3 are covered by the encapsulation member described above with reference to Figure 2 to be protected from external air or moisture.

[0093] The first display area DA1 may be at one side of the second display area DA2, and a plurality of auxiliary pixels PXa are in the first display area DA1. Each of the auxiliary pixels PXa may include a display element such as an organic light-emitting diode OLED. Each of the auxiliary pixels PXa may emit light (e.g., red light, green light, blue light, or white light) via the organic light-emitting diode OLED. In the specification, as described above, the auxiliary pixels PXa may be understood as pixels that emit red light, green light, blue light, or white light. In addition, the first display area DA1 may include the first transmissive area TA1.

[0094] Since the first display area DA1 includes the first transmissive area TA1, the resolution of the first display area DA1 may be less than the resolution of at least one of the second display area DA2 and the third display area DA3. For example, the resolution of the first display area DA1 may be half of the resolution of at least one of the second display area DA2 and the third display area DA3. In some embodiments, the resolution of at least one of the second display area DA2 and the third display area DA3 may be 400 ppi or greater, and the resolution of the first display area DA1 may be approximately 200 ppi or greater.

[0095] The following will refer to Figure 4 describe the first display area DA1 in more detail.

[0096] The first display area DA1 may include an auxiliary pixel area PA1 and a first transmissive area TA1. The auxiliary pixel area PA1 includes at least one auxiliary pixel PXa. The auxiliary pixel area PA1 and the first transmissive area TA1 are alternately arranged in a first direction DR1 and a second direction DR2, for example, arranged as a grille. In an exemplary embodiment, when it is described that an area includes an element / component, it means that the element / component is located in the area. Similarly, when it is described that an area does not include an element / component, it means that the element / component is not arranged in the area.

[0097] The auxiliary pixel area PA1 may include an auxiliary pixel Pr that emits red light, an auxiliary pixel Pg that emits green light, and an auxiliary pixel Pb that emits blue light. Figure 4 A pentile-type auxiliary pixel PXa is shown, but the auxiliary pixel PXa may have various shapes (e.g., a strip shape, etc.). Additionally, in Figure 4 there are eight auxiliary pixels PXa in the auxiliary pixel area PA1, but the number of auxiliary pixels PXa may vary according to the resolution of the first display area DA1.

[0098] According to some example embodiments, one main pixel PXm, one connection pixel PXc, and one auxiliary pixel PXa may include the same pixel circuit as each other. However, one or more embodiments are not limited thereto. The pixel circuits in the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa may be different from each other.

[0099] The first transmissive area TA1 may not include the auxiliary pixel PXa. Not including the auxiliary pixel PXa may mean that the auxiliary pixel PXa does not include display elements such as an organic light-emitting diode OLED. That is, it can be understood that the first transmissive area TA1 does not include the pixel electrode, the intermediate layer, and the counter electrode of the organic light-emitting diode OLED, as well as the pixel circuit electrically connected to the organic light-emitting diode OLED. Some of the signal lines PL, DL, SL, and EL connected to supply signals to the auxiliary pixels PXa in the auxiliary pixel area PA1 may pass through the first transmissive area TA1. However, even in this case, in order to improve the light transmittance of the first transmissive area TA1, the signal lines PL, DL, SL, and EL may be arched around the center of the first transmissive area TA1.

[0100] According to some example embodiments, a conductive layer may be on the substrate 100 corresponding to the auxiliary pixel area PA1 of the first display area DA1. The conductive layer may be under the auxiliary pixel PXa, for example, between the thin-film transistor of the auxiliary pixel PXa and the substrate 100. The conductive layer may prevent or reduce external light emitted from the component 20 from incident on the pixel circuit of the auxiliary pixel PXa (PC, see for example Figure 5) and the case of affecting the auxiliary pixel PXa. A constant voltage or signal is applied to the conductive layer to prevent damage to the pixel circuit PC due to electrostatic discharge. There may be a plurality of conductive layers in the first display area DA1, and if necessary, the conductive layers may receive different voltages from each other.

[0101] The second transmissive area TA2 and the third transmissive area TA3 may be similar to the first transmissive area TA1. That is, the second transmissive area TA2 and the third transmissive area TA3 may not include the connecting pixel PXc. Here, the description of not including the connecting pixel PXc is similar to the above description of not including the auxiliary pixel PXa, and therefore, its detailed description is omitted here.

[0102] Return reference Figure 3 , each of the main pixel PXm, the connecting pixel PXc, and the auxiliary pixel PXa may be electrically connected to a peripheral circuit in the non-display area NDA. In the non-display area NDA, a first scan driving circuit 110, a second scan driving circuit 120, a terminal 140, a data driving circuit 150, a first power supply line 160, and a second power supply line 170 may be arranged.

[0103] The first scan driving circuit 110 may provide a scan signal to each of the main pixel PXm, the connecting pixel PXc, and the auxiliary pixel PXa via a scan line SL. The first scan driving circuit 110 may provide an emission control signal to each of the main pixel PXm, the connecting pixel PXc, and the auxiliary pixel PXa via an emission control line EL. The second scan driving circuit 120 may be arranged in parallel with the first scan driving circuit 110, and a display area DA is arranged between the second scan driving circuit 120 and the first scan driving circuit 110. Some of the main pixel PXm, the connecting pixel PXc, and the auxiliary pixel PXa arranged in the display area DA may be electrically connected to the first scan driving circuit 110, and other pixels may be connected to the second scan driving circuit 120. According to some exemplary embodiments, the second scan driving circuit 120 may be omitted.

[0104] The terminal 140 may be arranged at one side of the substrate 100. The terminal 140 may be exposed without being covered by an insulating layer and may be electrically connected to a printed circuit board PCB. A terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB may transmit signals or power from a controller to the display panel 10. Control signals generated by the controller may be respectively transmitted to the first scan driving circuit 110 and the second scan driving circuit 120 via the printed circuit board PCB. The controller may provide a first power voltage ELVDD and a second power voltage (or common voltage) ELVSS to the first power supply line 160 and the second power supply line 170 via a first connection line 161 and a second connection line 171 respectively (seeFigure 5 and Figure 6 )。The first power voltage ELVDD is supplied to each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa via a driving voltage line PL connected to the first power supply line 160. The second power voltage ELVSS may be supplied to the counter electrode of each pixel PXm or PXa connected to the second power supply line 170.

[0105] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be supplied to each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa via a connection line 151 connected to the terminal 140 and the data line DL connected to the connection line 151. Although Figure 3 the data driving circuit 150 is shown to be arranged on the printed circuit board PCB, according to some example embodiments, the data driving circuit 150 may be arranged on the substrate 100. For example, the data driving circuit 150 may be between the terminal 140 and the first power supply line 160.

[0106] The first power supply line 160 may include a first sub-line 162 and a second sub-line 163. The first sub-line 162 and the second sub-line 163 extend parallel to each other in the X direction, and the display area DA is disposed between the first sub-line 162 and the second sub-line 163. The second power supply line 170 has an annular shape with an open side to partially surround the display area DA.

[0107] Figure 5 and Figure 6 is an equivalent circuit diagram of the pixels in the display panel 10 according to some example embodiments.

[0108] Referring to Figure 5 and Figure 6 , each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa includes a pixel circuit PC connected to the scan line SL and the data line DL and an organic light emitting diode OLED connected to the pixel circuit PC.

[0109] The pixel circuit PC includes a driving thin film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 is connected to the scan line SL and the data line DL and transmits the data signal Dm input through the data line DL to the driving TFT T1 according to the scan signal Sn input through the scan line SL.

[0110] The storage capacitor Cst is connected to the switching TFT T2 and the driving voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from the switching TFT T2 and the first power voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0111] The driving TFT T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED can emit light with a brightness (e.g., a set or predetermined brightness) according to the driving current.

[0112] Figure 5 An example is shown in which the pixel circuit PC includes two TFTs and one storage capacitor, but one or more embodiments are not limited thereto. As Figure 6 shown, the pixel circuit PC may include seven TFTs and one storage capacitor. In Figure 6 it, the pixel circuit PC includes one storage capacitor Cst, but the pixel circuit PC may include two or more storage capacitors.

[0113] Referring to Figure 6 , each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa includes a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a storage capacitor Cst and a plurality of TFTs. The TFTs and the storage capacitor Cst may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0114] In Figure 6 it, each of the main pixel PXm, the connection pixel PXc, and the auxiliary pixel PXa is connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL, but one or more embodiments are not limited thereto. According to some example embodiments, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL may be shared by adjacent pixels.

[0115] The signal lines include a scan line SL for transmitting a scan signal Sn, a previous scan line SL-1 for transmitting the previous scan signal Sn-1 to the first initialization TFT T4 and the second initialization TFT T7, an emission control line EL for transmitting an emission control signal En to the operation control TFT T5 and the emission control TFT T6, and a data line DL that intersects the scan line SL and transmits a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to the driving TFT T1, and the initialization voltage line VL transmits an initialization voltage Vint for initializing the driving TFT T1 and the pixel electrode.

[0116] The driving gate electrode G1 of the driving TFT T1 is connected to the lower electrode CE1 of the storage capacitor Cst. The driving source electrode S1 of the driving TFT T1 is connected to the driving voltage line PL via the operation control TFT T5. The driving drain electrode D1 of the driving TFT T1 is electrically connected to the pixel electrode of the organic light-emitting diode OLED via the emission control TFT T6. The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2 to supply the driving current I to the organic light-emitting diode OLED. OLED .

[0117] The switching gate electrode G2 of the switching TFT T2 is connected to the scanning line SL. The switching source electrode S2 of the switching TFT T2 is connected to the data line DL. The switching drain electrode D2 of the switching TFT T2 is connected to the driving source electrode S1 of the driving TFT T1 and is simultaneously connected to the driving voltage line PL via the operation control TFT T5. The switching TFT T2 is turned on according to the scanning signal Sn received through the scanning line SL and performs a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving TFT T1.

[0118] The compensating gate electrode G3 of the compensating TFT T3 is connected to the scanning line SL. The compensating source electrode S3 of the compensating TFT T3 is connected to the driving drain electrode D1 of the driving TFT T1 and is simultaneously connected to the pixel electrode of the organic light-emitting diode OLED via the emission control TFT T6. The compensating drain electrode D3 of the compensating TFT T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensating TFT T3 is turned on according to the scanning signal Sn received through the scanning line SL to electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving TFT T1 to each other and to diode-connect the driving TFT T1.

[0119] The first initialization gate electrode G4 of the first initialization TFT T4 is connected to the previous scanning line SL-1. The first initialization source electrode S4 of the first initialization TFT T4 is connected to the second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line VL. The first initialization drain electrode D4 of the first initialization TFT T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the compensating drain electrode D3 of the compensating TFT T3, and the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 is turned on according to the previous scanning signal Sn-1 transmitted through the previous scanning line SL-1 to transmit the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1 and to perform an initialization operation for initializing the voltage at the driving gate electrode G1 of the driving TFT T1.

[0120] The operation control gate electrode G5 of the operation control TFT T5 is connected to the emission control line EL. The operation control source electrode S5 of the operation control TFT T5 is connected to the driving voltage line PL. And the operation control drain electrode D5 of the operation control TFT T5 is connected to the driving source electrode S1 of the driving TFT T1 and the switching drain electrode D2 of the switching TFT T2.

[0121] The emission control gate electrode G6 of the emission control TFT T6 is connected to the emission control line EL. The emission control source electrode S6 of the emission control TFT T6 is connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3. And the emission control drain electrode D6 of the emission control TFT T6 is electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the organic light emitting diode OLED.

[0122] The operation control TFT T5 and the emission control TFT T6 are simultaneously turned on according to the emission control signal En transmitted through the emission control line EL to transmit the driving voltage ELVDD to the organic light emitting diode OLED and allow the driving current I OLED to flow in the organic light emitting diode OLED.

[0123] The second initialization gate electrode G7 of the second initialization TFT T7 is connected to the previous scan line SL-1. The second initialization source electrode S7 of the second initialization TFT T7 is connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode of the organic light emitting diode OLED. And the second initialization drain electrode D7 of the second initialization TFT T7 is connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line VL. The second initialization TFT T7 is turned on according to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to initialize the pixel electrode of the organic light emitting diode OLED.

[0124] Figure 6 The situation where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1 is shown, but one or more embodiments are not limited thereto. According to some example embodiments, the first initialization TFT T4 may be connected to the previous scan line SL-1 to operate according to the previous scan signal Sn-1, and the second initialization TFT T7 may be connected to a separate signal line (e.g., the subsequent scan line) to operate according to the signal transmitted to the signal line.

[0125] The upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light-emitting diode OLED is connected to the common voltage ELVSS. Accordingly, the organic light-emitting diode OLED receives a driving current I from the driving TFT T1 OLED and emits light to display an image.

[0126] In Figure 6 , the compensation TFT T3 and the first initialization TFT T4 have dual gate electrodes, but the compensation TFT T3 and the first initialization TFT T4 may each have one gate electrode.

[0127] Figure 7 is a diagram of a pixel circuit in a pixel according to some example embodiments. Figure 8 is a cross-sectional view taken along Figure 7 lines I-I' and II-II'.

[0128] Referring to Figure 7 and Figure 8 , the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 are arranged along the semiconductor layer 1130.

[0129] The semiconductor layer 1130 is disposed on a substrate 100 on which a buffer layer including an inorganic insulating material is disposed. According to some example embodiments, the semiconductor layer 1130 may include low-temperature polycrystalline silicon (LTPS). Since the polycrystalline silicon material has a high electron mobility (100 cm 2 / Vs or greater), the polycrystalline silicon material can be used as the semiconductor layer of the TFTs in the display device 1 due to its low power consumption and excellent reliability. However, one or more embodiments are not limited thereto, that is, according to some example embodiments, the semiconductor layer 1130 may include amorphous silicon (a-Si) and / or an oxide semiconductor. Alternatively, the semiconductor layer of some of the plurality of TFTs may include LTPS, and the semiconductor layer of some other TFTs may include a-Si and / or an oxide semiconductor.

[0130] Some regions in the semiconductor layer 1130 correspond to the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7. In other words, the semiconductor layers 1130 of the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 are connected to each other and bent in various shapes.

[0131] The semiconductor layer 1130 includes a channel region and source and drain regions on opposite sides of the channel region. The source and drain regions can be understood as the source and drain electrodes of the corresponding TFTs, respectively. Hereinafter, for convenience of description, the source and drain regions will be referred to as the source and drain electrodes.

[0132] The driving TFT T1 includes a driving gate electrode G1 stacked on the driving channel region and a driving source electrode S1 and a driving drain electrode D1 on opposite sides of the driving channel region. The driving channel region stacked with the driving gate electrode G1 has a curved shape (e.g., Ω shape) to establish a long channel length in a narrow space. When the driving channel region has a long length, the driving range of the gate voltage increases. Therefore, the gray level of the light emitted from the organic light-emitting diode OLED can be finely controlled, and the quality of the displayed image can be improved.

[0133] The switching TFT T2 includes a switching gate electrode G2 stacked on the switching channel region and a switching source electrode S2 and a switching drain electrode D2 on opposite sides of the switching channel region. The switching drain electrode D2 can be connected to the driving source electrode S1.

[0134] The compensating TFT T3 is a dual TFT, which includes a compensating gate electrode G3 stacked on two compensating channel regions respectively and a compensating source electrode S3 and a compensating drain electrode D3 on opposite sides of the two compensating channel regions. The compensating TFT T3 can be connected to the driving gate electrode G1 of the driving TFT T1 via a node connection line 1174 to be described later.

[0135] The first initialization TFT T4 is a dual TFT, which includes a first initialization gate electrode G4 stacked on two first initialization channel regions respectively and a first initialization source electrode S4 and a first initialization drain electrode D4 on opposite sides of the two first initialization channel regions.

[0136] The operation control TFT T5 may include an operation control gate electrode G5 stacked on the operation control channel region and an operation control source electrode S5 and an operation control drain electrode D5 on opposite sides of the operation control gate electrode G5. The operation control drain electrode D5 can be connected to the driving source electrode S1.

[0137] The emission control TFT T6 may include an emission control gate electrode G6 stacked on the emission control channel region and an emission control source electrode S6 and an emission control drain electrode D6 on opposite sides of the emission control gate electrode G6. The emission control source electrode S6 can be connected to the driving drain electrode D1.

[0138] The second initialization TFT T7 may include a second initialization gate electrode G7 stacked with a second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 at opposite sides of the second initialization gate electrode G7.

[0139] The above TFTs may be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL.

[0140] The scan line SL, the previous scan line SL-1, the emission control line EL, and the driving gate electrode G1 may be arranged on the semiconductor layer 1130, and (some) insulating layers are provided between the semiconductor layer 1130 and the scan line SL, the previous scan line SL-1, the emission control line EL, and the driving gate electrode G1.

[0141] The scan line SL may extend in a first direction DR1. Some regions in the scan line SL may correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, the regions of the scan line SL stacked with the channel regions of the switching TFT T2 and the compensation TFT T3 may be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0142] The previous scan line SL-1 extends along the first direction DR1, and some regions of the previous scan line SL-1 may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7. For example, the regions of the previous scan line SL-1 stacked with the channel regions of the first initialization TFT T4 and the second initialization TFT T7 may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0143] The emission control line EL extends along the first direction DR1. Some regions in the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6. For example, the regions of the emission control line EL stacked with the channel regions of the operation control TFT T5 and the emission control TFT T6 may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0144] The driving gate electrode G1 is a floating electrode that can be connected to the compensation TFT T3 via the node connection line 1174.

[0145] The electrode voltage line HL may be arranged on the scan line SL, the previous scan line SL-1, the emission control line EL, and the driving gate electrode G1, and (some) insulating layers are provided between the electrode voltage line HL and the scan line SL, the previous scan line SL-1, the emission control line EL, and the driving gate electrode G1.

[0146] The electrode voltage line HL can extend in the first direction DR1 to intersect with the data line DL and the driving voltage line PL. A part of the electrode voltage line HL covers at least a part of the driving gate electrode G1, and can construct a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 can become the lower electrode CE1 of the storage capacitor Cst, and a part of the electrode voltage line HL can become the upper electrode CE2 of the storage capacitor Cst.

[0147] The upper electrode CE2 of the storage capacitor Cst is electrically connected to the driving voltage line PL. In this regard, the electrode voltage line HL can be connected to the driving voltage line PL on the electrode voltage line HL via the contact hole CNT. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the driving voltage line PL. For example, the electrode voltage line HL can have a constant voltage of +5V. The electrode voltage line HL can be understood as a driving voltage line in the lateral direction.

[0148] The driving voltage line PL extends along the second direction DR2, and the electrode voltage line HL electrically connected to the driving voltage line PL extends along the first direction DR1 intersecting with the second direction DR2. Therefore, multiple driving voltage lines PL and electrode voltage lines HL in the display area DA can generate a grid structure.

[0149] The data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174 can be arranged on the electrode voltage line HL, and (some) insulating layers are provided between the electrode voltage line HL and the data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174.

[0150] The data line DL extends in the second direction DR2, and can be connected to the switching source electrode S2 of the switching TFT T2 via the contact hole 1154. A part of the data line DL can be understood as the switching source electrode S2.

[0151] The driving voltage line PL extends in the second direction DR2, and as described above, is connected to the electrode voltage line HL via the contact hole CNT. In addition, the driving voltage line PL can be connected to the operation control TFT T5 via the contact hole 1155. The driving voltage line PL can be connected to the operation control source electrode S5 via the contact hole 1155.

[0152] One end of the initialization connection line 1173 is connected to the first initialization TFT T4 and the second initialization TFT T7 via the contact hole 1152, and the other end of the initialization connection line 1173 can be connected to the initialization voltage line VL described later via the contact hole 1151.

[0153] One end of the node connection line 1174 can be connected to the compensation drain electrode D3 via the contact hole 1156, and the other end of the node connection line 1174 can be connected to the driving gate electrode G1 via the contact hole 1157.

[0154] The initialization voltage line VL can be arranged on the data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174, and (some) insulating layers are provided between the initialization voltage line VL and the data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174.

[0155] The initialization voltage line VL extends in the first direction DR1. The initialization voltage line VL can be connected to the first initialization TFT T4 and the second initialization TFT T7 via the initialization connection line 1173. The initialization voltage line VL can have a constant voltage (for example, -2V, etc.).

[0156] The initialization voltage line VL is arranged at the same layer as the pixel electrode 210 of the organic light-emitting diode OLED (see Figure 8 ) and can include the same material as the material of the pixel electrode 210. The pixel electrode 210 can be connected to the emission control TFT T6. The pixel electrode 210 is connected to the connection metal 1175 via the contact hole 1163, and the connection metal 1175 can be connected to the emission control drain electrode D6 via the contact hole 1153.

[0157] In Figure 7 , the initialization voltage line VL is arranged at the same layer as the layer of the pixel electrode 210, but according to some exemplary embodiments, the initialization voltage line VL can be arranged at the same layer as the electrode voltage line HL.

[0158] Hereinafter, the stacking structure of the components included in the display panel 10 according to some exemplary embodiments will be described with reference to Figure 8 The substrate 100 can include glass or a polymer resin. The polymer resin can include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc. The substrate 100 including the polymer resin can be flexible, rollable, or bendable. The substrate 100 can have a multilayer structure including a layer containing a polymer resin and an inorganic layer.

[0159] The substrate 100 can include glass or a polymer resin. The polymer resin can include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc. The substrate 100 including the polymer resin can be flexible, rollable, or bendable. The substrate 100 can have a multilayer structure including a layer containing a polymer resin and an inorganic layer.

[0160] The buffer layer 111 is positioned on the substrate 100 to reduce or block the infiltration of impurities, moisture, or external air from the lower part of the substrate 100 and to provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide material or a nitride material, an organic material, or an inorganic-organic composite material, and may have a single-layer structure or a multi-layer structure including an inorganic material and an organic material. A barrier layer for preventing or reducing the infiltration of external air may be further provided between the substrate 100 and the buffer layer 111.

[0161] The gate electrodes G1 and G6 are respectively disposed on the semiconductor layers A1 and A6, and the first gate insulating layer 112 is disposed between the gate electrodes G1 and G6 and the semiconductor layers A1 and A6. The gate electrodes G1 and G6 may both include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer structure or a multi-layer structure. As an example, the gate electrodes G1 and G6 may both have a single layer including Mo. The scan line SL (see Figure 7 ), the previous scan line SL-1, and the emission control line EL may be provided at the same layer as the layer of the gate electrodes G1 and G6. That is, the gate electrodes G1 and G6, the scan line SL (see Figure 7 ), the previous scan line SL-1, and the emission control line EL may be disposed on the first gate insulating layer 112.

[0162] The first gate insulating layer 112 may include insulating materials such as silicon dioxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc peroxide (ZnO2).

[0163] The second gate insulating layer 113 may be provided to cover the gate electrodes G1 and G6. The second gate insulating layer 113 may include insulating materials such as silicon dioxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc peroxide (ZnO2).

[0164] The lower electrode CE1 of the storage capacitor Cst may be integrally provided with the driving gate electrode G1 of the driving TFT T1. For example, the driving gate electrode G1 of the driving TFT T1 may be used as the lower electrode CE1 of the storage capacitor Cst.

[0165] The upper electrode CE2 of the storage capacitor Cst and the lower electrode CE1 are stacked, and the second gate insulating layer 113 is between the upper electrode CE2 and the lower electrode CE1 of the storage capacitor Cst. In this case, the second gate insulating layer 113 can be used as the dielectric layer of the storage capacitor Cst. The upper electrode CE2 can include a conductive material containing Mo, Al, Cu, Ti, etc., and can have a single-layer structure or a multi-layer structure. As an example, the upper electrode CE2 can have a single-layer structure including Mo or a multi-layer structure including Mo / Al / Mo.

[0166] In the drawings, the storage capacitor Cst is shown as being stacked with the driving TFT T1, but one or more disclosed embodiments are not limited thereto. Various modifications can be made to the storage capacitor Cst. For example, the storage capacitor Cst can be arranged not to be stacked with the driving TFT T1.

[0167] The upper electrode CE2 can be used as the electrode voltage line HL. For example, a part of the electrode voltage line HL can be used as the upper electrode CE2 of the storage capacitor Cst.

[0168] The interlayer insulating layer 115 can be provided to cover the upper electrode CE2. The interlayer insulating layer 115 can include insulating materials such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc peroxide (ZnO2). In Figure 8 this case, the interlayer insulating layer 115 has a single-layer structure, but according to some exemplary embodiments, the interlayer insulating layer 115 can have a multi-layer structure.

[0169] The data line DL, the driving voltage line PL, and the connection metal 1175 can be arranged on the interlayer insulating layer 115. The data line DL, the driving voltage line PL, and the connection metal 1175 can include a conductive material containing Mo, Al, Cu, Ti, etc., and can have a single-layer structure or a multi-layer structure including the above materials. For example, each of the data line DL, the driving voltage line PL, and the connection metal 1175 can have a multi-layer structure including Ti / Al / Ti.

[0170] The upper electrode CE2 of the storage capacitor Cst can be connected to the driving voltage line PL via a contact hole CNT defined in the interlayer insulating layer 115. This means that the electrode voltage line HL is connected to the driving voltage line PL via the contact hole CNT. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the driving voltage line PL.

[0171] The connection metal 1175 is connected to the semiconductor layer A6 of the emission control TFT T6 via a contact hole 1153 that penetrates the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The emission control TFT T6 can be electrically connected to the pixel electrode 210 of the organic light-emitting diode OLED via the connection metal 1175.

[0172] The planarization layer 117 is positioned on the data line DL, the driving voltage line PL, and the connection metal 1175, and the organic light-emitting diode OLED can be positioned on the planarization layer 117.

[0173] The planarization layer 117 can have a flat upper surface to flatten the pixel electrode 210. The planarization layer 117 can include a single-layer structure or a multi-layer structure containing an organic material. The planarization layer 117 can include general-purpose polymers (benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, parylene polymers, vinyl alcohol polymers, and blends thereof. The planarization layer 117 can include an inorganic material. The planarization layer 117 can include insulating materials such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc peroxide (ZnO2). When the planarization layer 117 includes an inorganic material, chemical mechanical polishing can be performed if necessary. Alternatively, the planarization layer 117 can include both an organic material and an inorganic material.

[0174] The pixel electrode 210 can be a (semi)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode 210 can include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer. The reflective layer includes silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and mixtures thereof. The transparent or semi-transparent electrode layer can include at least one electrode material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide, and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 can include a stacked structure including ITO / Ag / ITO.

[0175] The pixel defining layer 119 may be positioned on the planarization layer 117. The pixel defining layer 119 includes an opening 119OP that exposes the central portion of the pixel electrode 210 to define the light emitting region of the pixel. Additionally, the pixel defining layer 119 increases the distance between the edge of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210 to prevent arcing at the edge of the pixel electrode 210. The pixel defining layer 119 may include an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be obtained by spin coating or the like.

[0176] The intermediate layer 220 of the organic light emitting diode OLED may include an organic light emitting layer. The organic light emitting layer may include an organic material containing a fluorescent material or a phosphorescent material that emits red light, green light, blue light, or white light. The organic light emitting layer may include a low molecular weight organic material or a polymer organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be selectively disposed under and on the organic light emitting layer. The intermediate layer 220 may correspond to each of the plurality of pixel electrodes 210 respectively. However, one or more embodiments are not limited thereto. The intermediate layer 220 may be variously modified, that is, the intermediate layer 220 may be arranged to extend over the plurality of pixel electrodes 210, that is, the intermediate layer 220 may be shared over the plurality of pixel electrodes 210.

[0177] The counter electrode 230 may be a transmissive electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or semi-transparent electrode, and may be provided as a metal thin film including Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and mixtures thereof having a small work function. Additionally, a transparent conductive oxide (TCO) such as ITO, IZO, ZnO, or In2O3 may be further provided on the metal thin film.

[0178] When the pixel electrode 210 is a reflective electrode and the counter electrode 230 is a transmissive electrode, the light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and the display device 1 is a top emission type. When the pixel electrode 210 is a transparent or semi-transparent electrode and the counter electrode 230 is a reflective electrode, the light emitted from the intermediate layer 220 is emitted toward the substrate 100, and the display device 1 may be a bottom emission type. However, one or more embodiments are not limited thereto. The display device 1 according to some example embodiments may be a dual emission type in which light is emitted to the top surface and the bottom surface.

[0179] According to some example embodiments, the counter electrode 230 is included in the auxiliary pixel PXa positioned in the first display area DA1. However, since the first display area DA1 includes the auxiliary pixel area PA1 in which the auxiliary pixel PXa is positioned and the first transmissive area TA1, the counter electrode 230 may not be partially included in some areas corresponding to the first transmissive area TA1. In a top-emission type display device, light may be emitted toward the counter electrode 230, but due to the counter electrode 230, the light transmittance may be reduced to some extent. Therefore, since the area corresponding to the first transmissive area TA1 does not include the counter electrode 230, the light transmittance of the first transmissive area TA1 can be increased.

[0180] To this end, the counter electrode 230 in the first display area DA1 may be patterned to correspond to each auxiliary pixel area PA1. The counter electrode 230 in the first display area DA1 may be formed by a laser lift-off process or by a fine metal mask (FMM) patterning process by partially removing the area corresponding to the first transmissive area TA1. Hereinafter, it will be assumed that the counter electrode 230 is formed in the first display area DA1 by the FMM patterning process.

[0181] The counter electrode 230 may also be included in the connection pixel PXc in the second display area DA2. However, since the second display area DA2 includes the connection pixel area in which the connection pixel PXc is positioned, the second transmissive area TA2, and the third transmissive area TA3, the counter electrode 230 may not be included in some areas corresponding to the second transmissive area TA2 and the third transmissive area TA3. In a top-emission type display device, light may be emitted toward the counter electrode 230, but due to the counter electrode 230, the light transmittance may be reduced to some extent. Therefore, the counter electrode 230 is not provided in the area corresponding to the second transmissive area TA2 and the third transmissive area TA3, and thus the light transmittance of the second transmissive area TA2 and the third transmissive area TA3 can be increased.

[0182] To this end, the counter electrode 230 in the second display area DA2 may be patterned to correspond to each connection pixel area. The counter electrode 230 in the second display area DA2 may be formed by a laser lift-off process or by an FMM patterning process by partially removing some areas corresponding to the second transmissive area TA2 and the third transmissive area TA3. Hereinafter, it will be assumed that the counter electrode 230 is formed in the second display area DA2 by the FMM patterning process.

[0183] The counter electrode 230 is provided to cover the entire surface of the third display area DA3, and some edges may be positioned in the non-display area NDA. The counter electrode 230 may be integrally provided relative to the main pixels PXm (i.e., a plurality of organic light-emitting diodes OLEDs) in the third display area DA3 to correspond to the plurality of pixel electrodes 210.

[0184] Figure 9 and Figure 10 is a plan view showing a part of the first display area DA1 according to some example embodiments.

[0185] Referring Figure 9 and Figure 10 , as described above, the first display area DA1 includes the auxiliary pixel area PA1 and the first transmissive area TA1, and the auxiliary pixels PXa are arranged in the auxiliary pixel area PA1. The auxiliary pixel area PA1 includes a first pixel area PA1-1 and a second pixel area PA1-2 as shown in Figure 9 , and the auxiliary pixels PXa include a first pixel PXa1 and a second pixel PXa2 as shown in Figure 9 . A plurality of first pixels PXa1 are in the first pixel area PA1-1, and a plurality of second pixels PXa2 are in the second pixel area PA1-2.

[0186] According to some example embodiments, a first counter electrode 230a is in the first pixel area PA1-1, and a second counter electrode 230b is in the second pixel area PA1-2. The first counter electrode 230a may correspond to the first pixel area PA1-1, and the second counter electrode 230b may correspond to the second pixel area PA1-2. Additionally, the first counter electrode 230a and the second counter electrode 230b may be in partial contact with each other. Here, the first counter electrode 230a and the second counter electrode 230b may have the same shape as each other.

[0187] Referring Figure 10 , a plurality of first pixels PXa1 are arranged in the first pixel area PA1-1. Each of the plurality of first pixels PXa1 includes a scan line SL for receiving a scan signal and a data line DL for receiving a data signal. The scan line SL extends in a first direction DR1, and the data line DL may extend in a second direction DR2 that intersects (e.g., crosses) the first direction DR1. Here, other signal lines PL, EL, SL-1, VL (see Figure 7 ) may also be provided in the first pixel area PA1-1.

[0188] The data line DL and the scan line SL can be partially positioned in the first transmissive region TA1. In this case, the scan line SL can have, for example, an arched portion that arches around the edge of the first transmissive region TA1 to increase the light transmittance of the first transmissive region TA1. The arched portion can also be applied to other signal lines PL, EL, SL-1, and VL (see Figure 7 ).

[0189] The plurality of first pixels PXa1 in the first pixel region PA1-1 can include a first pair of electrodes 230a that are integrally provided with respect to one first pixel region PA1-1.

[0190] The plurality of second pixels PXa2 in the second pixel region PA1-2 can include a second pair of electrodes 230b that are integrally provided with respect to one second pixel region PA1-2.

[0191] The first pixel region PA1-1 and the second pixel region PA1-2 can be arranged in different rows from each other. In this case, the first pixel region PA1-1 and the second pixel region PA1-2 can surround the first transmissive region TA1. That is, the first pixel region PA1-1 and the second pixel region PA1-2 can be arranged in a zigzag pattern. For example, as shown in Figure 9 and Figure 10 , the first pixel region PA1-1 and the second pixel region PA1-2 can be alternately arranged in a third direction DR3 and / or a fourth direction DR4 that intersect the first direction DR1 and the second direction DR2.

[0192] The first pair of electrodes 230a and the second pair of electrodes 230b can correspond to the first pixel region PA1-1 and the second pixel region PA1-2, respectively, and can be in partial contact with each other. There is a first contact region CTA1 where the first pair of electrodes 230a and the second pair of electrodes 230b are in contact with each other between the first pixel region PA1-1 and the second pixel region PA1-2 adjacent to the first pixel region PA1-1, and the first pair of electrodes 230a and the second pair of electrodes 230b can be electrically connected to each other via the first contact region CTA1.

[0193] In this case, since the first pair of electrodes 230a and the second pair of electrodes 230b are connected to each other via the first contact region CTA1, an increase in the resistance of the first pair of electrodes 230a and the second pair of electrodes 230b in the first display region DA1 can be prevented.

[0194] Figure 11 and Figure 12 are cross-sectional views taken along line B-B' of Figure 9 for showing some manufacturing processes of the display panel 10 according to some example embodiments.Figure 13 is a cross-sectional view taken along line B-B' of Figure 9 .

[0195] Referring to Figures 11 to 13 , an insulating layer IL in which a pixel circuit PC is positioned is formed on a substrate 100, and a first pixel electrode 210a and a second pixel electrode 210b electrically connected to the pixel circuit PC are formed. The first pixel electrode 210a is in a first pixel region PA1-1, and the second pixel electrode 210b is in a second pixel region PA1-2.

[0196] A pixel defining layer 119 having openings exposing a central portion of the first pixel electrode 210a and a central portion of the second pixel electrode 210b is disposed on the first pixel electrode 210a and the second pixel electrode 210b. A first intermediate layer 220a is disposed on an exposed portion of the first pixel electrode 210a, and a second intermediate layer 220b is disposed on an exposed portion of the second pixel electrode 210b, where the exposed portions are exposed through the openings of the pixel defining layer 119. It is understood that the first intermediate layer 220a and the second intermediate layer 220b include the same material as the intermediate layer 220 described above with reference to Figure 8 .

[0197] Thereafter, a first pair of electrodes 230a and a second pair of electrodes 230b can be disposed on the first intermediate layer 220a and the second intermediate layer 220b. According to some example embodiments, the first pair of electrodes 230a and the second pair of electrodes 230b can be obtained by different processes. Here, the first pair of electrodes 230a and the second pair of electrodes 230b can be formed using a first mask sheet 422A of a first mask assembly to be described later. That is, after the first pair of electrodes 230a is formed, at least one of the first mask assembly and the substrate 100 is moved to a position different from the initial position, and then the second pair of electrodes 230b can be formed on the substrate 100. According to some example embodiments, after the second pair of electrodes 230b is formed, at least one of the first mask assembly and the substrate 100 is moved to a position different from the initial position, and then the first pair of electrodes 230a can be formed on the substrate 100. Hereinafter, for convenience of description, a case where the second pair of electrodes 230b is formed by moving the position of the substrate 100 after the first pair of electrodes 230a is formed will be described in detail below.

[0198] Specifically, as shown in Figure 11 , the first pair of electrodes 230a is formed on the first intermediate layer 220a. The first pair of electrodes 230a can be formed when deposition material passing through a first opening 422A-1 of the first mask sheet 422A is deposited on the substrate 100. Thereafter, as shown in Figure 12 , the substrate 100 is moved to Figure 11on the left side of [the above] to form a second pair of electrodes 230b on the second intermediate layer 220b. The second pair of electrodes 230b can be fabricated through the first opening 422A-1 of the first mask sheet 422A.

[0199] Referring to Figure 13 , the first pair of electrodes 230a and the second pair of electrodes 230b obtained as above can be in surface contact with each other in the first contact area CTA1. The surface contact between the first pair of electrodes 230a and the second pair of electrodes 230b can be understood as the second pair of electrodes 230b being stacked on the first pair of electrodes 230a to contact each other, and there is no intermediate layer between the second pair of electrodes 230b and the first pair of electrodes 230a.

[0200] In the first contact area CTA1, the second pair of electrodes 230b are disposed on the first pair of electrodes 230a. This indicates that the second pair of electrodes 230b are obtained in the post-processing of forming the first pair of electrodes 230a. According to some example embodiments, when the first pair of electrodes 230a are formed after the second pair of electrodes 230b are formed, the first pair of electrodes 230a can be disposed on the second pair of electrodes 230b in the first contact area CTA1. Since the first pair of electrodes 230a and the second pair of electrodes 230b are in surface contact with each other in the first contact area CTA1, the first contact area CTA1 can have a thickness less than twice the thickness of the area where only the first pair of electrodes 230a or the second pair of electrodes 230b are disposed. Additionally, the first contact area CTA1 may not be disposed in the light-emitting areas of the first pixel PXa1 and the second pixel PXa2. Here, the light-emitting areas are formed in the first opening OP1 and the second opening OP2 of the pixel defining layer 119, and the first opening OP1 and the second opening OP2 expose the central portions of the first pixel electrode 210a and the second pixel electrode 210b, respectively. That is to say, the first contact area CTA1 can be set not to overlap with the first opening OP1 and the second opening OP2 formed in the pixel defining layer 119.

[0201] As the area of the first contact area CTA1 increases, the resistance of the first pair of electrodes 230a and the second pair of electrodes 230b can be further reduced. However, as described above, when the area of the first contact area CTA1 increases to be greater than a certain degree, the first contact area CTA1 overlaps with the light-emitting areas of the first pixel PXa1 and the second pixel PXa2, which reduces the light-emitting performance of the first pixel PXa1 and the second pixel PXa2.

[0202] Therefore, the area of the first contact area CTA1 can be set so as not to block the first opening OP1 and the second opening OP2.

[0203] Referring to Figure 2 , Figure 11 and Figure 13, compared with the first pixel region PA1-1, the first transmissive region TA1 may not include display elements such as organic light-emitting diodes (OLEDs) and pixel circuits (PCs) electrically connected to the display elements. In addition, the first transmissive region TA1 may be defined as a region where some layers on the substrate 100 are removed.

[0204] Figure 14 is a plan view of the arrangement of the counter electrodes in the display panel 10 according to some exemplary embodiments. Figure 15 is along Figure 14 a cross-sectional view taken along line C-C'. Figure 16 is along Figure 14 a cross-sectional view taken along line D-D'.

[0205] Referring to Figures 14 to 16 , the first display region DA1 may include the first pixel region PA1-1, the second pixel region PA1-2, and the first transmissive region TA1 as described above. Here, the first counter electrode 230a may be in the first pixel region PA1-1, and the second counter electrode 230b may be in the second pixel region PA1-2.

[0206] The second display region DA2 may include a third pixel region PA2-1, a fourth pixel region PA2-2, a second transmissive region TA2, and a third transmissive region TA3. The connected pixel region PA2 may include the third pixel region PA2-1 and the fourth pixel region PA2-2. Here, the third counter electrode 230c may be in the third pixel region PA2-1, and the fourth counter electrode 230d may be in the fourth pixel region PA2-2.

[0207] In the above case, the third counter electrode 230c and the fourth counter electrode 230d may have different shapes from each other. For example, the third counter electrode 230c may have the same shape as the first counter electrode 230a or the second counter electrode 230b, and the fourth counter electrode 230d may have a shape different from that of the third counter electrode 230c. Specifically, the third counter electrode 230c may have a square shape, and the fourth counter electrode 230d may have a rectangular shape. Additionally, the fourth counter electrode 230d may be equal to or larger than at least two third counter electrodes 230c connected to each other.

[0208] The third display region DA3 may include a main pixel region PA3, and the main counter electrode 230e may be in the main pixel region PA3.

[0209] In the above case, the third counter electrode 230c and the fourth counter electrode 230d may be formed simultaneously with the formation of the main counter electrode 230e.

[0210] A plurality of third pairs of electrodes 230c and a plurality of fourth pairs of electrodes 230d can be provided. The plurality of third pairs of electrodes 230c can be spaced apart from each other. Additionally, the plurality of fourth pairs of electrodes 230d can be spaced apart from each other. In this case, the plurality of third pairs of electrodes 230c and the plurality of fourth pairs of electrodes 230d can be arranged in rows in the Figure 14 X direction of. Additionally, each of the third pairs of electrodes 230c and each of the fourth pairs of electrodes 230d can be arranged to be connected to each other in the Figure 14 Y direction of.

[0211] The third pair of electrodes 230c can be connected to the first pair of electrodes 230a or the second pair of electrodes 230b. Here, the third pair of electrodes 230c can include a second contact area CTA2 that overlaps with the first pair of electrodes 230a or the second pair of electrodes 230b. In this case, in the second contact area CTA2, the third pair of electrodes 230c can be in surface contact with the first pair of electrodes 230a or the second pair of electrodes 230b. Additionally, in the second contact area CTA2, the third pair of electrodes 230c can be arranged on the first pair of electrodes 230a or the second pair of electrodes 230b, or can be arranged below the first pair of electrodes 230a or the second pair of electrodes 230b. Hereinafter, for ease of description, the case where the third pair of electrodes 230c is arranged on the second pair of electrodes 230b in the second contact area CTA2 will be described in detail below.

[0212] In the above case, the thickness of the second contact area CTA2 can be greater than the thickness of the second pair of electrodes 230b or the thickness of the third pair of electrodes 230c. For example, the thickness of the second contact area CTA2 can be approximately twice the thickness of the second pair of electrodes 230b or approximately twice the thickness of the third pair of electrodes 230c.

[0213] In the above case, the third pair of electrodes 230c and the fourth pair of electrodes 230d that are connected to each other can have a third contact area CTA3, and the third pair of electrodes 230c and the fourth pair of electrodes 230d overlap each other in the third contact area CTA3. In this case, the thickness of the third contact area CTA3 can be the same as or similar to the thickness of the third pair of electrodes 230c or the thickness of the fourth pair of electrodes 230d. That is, because the third pair of electrodes 230c and the fourth pair of electrodes 230d are formed simultaneously in the third contact area CTA3, one of the third pair of electrodes 230c and the fourth pair of electrodes 230d can directly contact the upper surface of the other of the third pair of electrodes 230c and the fourth pair of electrodes 230d. In this case, the third pair of electrodes 230c and the fourth pair of electrodes 230d can be in surface contact with each other. Hereinafter, for ease of description, the case where the fourth pair of electrodes 230d is on the third pair of electrodes 230c as shown in Figure 16 will be described in detail below.

[0214] The fourth pair of electrodes 230d may be connected to the main pair of electrodes 230e. Here, the fourth pair of electrodes 230d may be partially spaced apart from the main pair of electrodes 230e and may be in direct contact with the main pair of electrodes 230e in part. Here, the fourth pair of electrodes 230d has a T shape to be connected to the main pair of electrodes 230e. That is, a part of the fourth pair of electrodes 230d may protrude toward the main pair of electrodes 230e, and another part of the fourth pair of electrodes 230d may protrude in a direction perpendicular to the said part of the fourth pair of electrodes 230d.

[0215] The second transmissive region TA2 may be positioned between one of the first pair of electrodes 230a and the second pair of electrodes 230b, the third pair of electrodes 230c, and the fourth pair of electrodes 230d. The second transmissive region TA2 may have the same shape and size as the shape and size of the first transmissive region TA1.

[0216] The third transmissive region TA3 may be disposed between one of the first pair of electrodes 230a and the second pair of electrodes 230b, the third pair of electrodes 230c, the fourth pair of electrodes 230d, and the main pair of electrodes 230e. Here, the third transmissive region TA3 may have a shape different from the shape of the second transmissive region TA2.

[0217] In each of the first pixel region PA1-1, the second pixel region PA1-2, the third pixel region PA2-1, and the fourth pixel region PA2-2, one or more pixels may be disposed. For example, the first pixel PXa1 may be disposed in the first pixel region PA1-1, and the second pixel PXa2 may be disposed in the second pixel region PA1-2. In addition, one or more third pixels PXc1 are disposed in the third pixel region PA2-1, and one or more fourth pixels PXc2 may be disposed in the fourth pixel region PA2-2. In addition, the main pixel PXm may be disposed in the main pixel region PA3. The above pixels are the same as or similar to the pixels in the above description.

[0218] Figure 17 is a cross-sectional view of a device 400 for manufacturing a display device 1 according to some example embodiments. Figure 18 is Figure 17 a perspective view of a first mask assembly 420A of Figure 19 is a plan view showing a part of a first mask sheet 422A of Figure 17 Figure 20 is a plan view showing a part of a second mask sheet 422B of Figure 17

[0219] Referring to Figures 17 to 20 , the display panel 10 of the display device 1 may be manufactured by using the device 400 for manufacturing a display device.​​

[0220] The apparatus 400 for manufacturing the display device 1 may include a chamber 410, a first mask assembly 420A, a second mask assembly 420B, a first support 430, a second support 440, a deposition source 450, a magnetic force generator 460, a vision part 470, and a pressure regulator 480.

[0221] The chamber 410 may include a space therein and may have an opening part. Herein, a gate valve 411 may be provided at the opening part of the chamber 410 to open / close the opening part.

[0222] The first mask assembly 420A may be selectively in the chamber 410. Herein, the first mask assembly 420A may include a first mask frame 421A and a first mask sheet 422A. The first mask frame 421A includes a plurality of frames connected to each other and may have an opening therein. Herein, the first mask frame 421A may include one opening or a plurality of openings distinguished from each other. In this case, the first mask frame 421A may be formed as a grille such as a window frame. The first mask sheet 422A may be fixed to the first mask frame 421A and be in a tensioned state. Herein, the first mask sheet 422A may have a first opening 422A-1 through which a deposition material may pass.

[0223] The first mask sheet 422A may include the first opening 422A-1 through which the deposition material passes to form the first pair of electrodes 230a or the second pair of electrodes 230b described above.

[0224] The first opening 422A-1 may have a shape corresponding to the shape of the first pixel region PA1-1 or the second pixel region PA1-2. For example, the first opening 422A-1 may have a rectangular shape, a square shape, or a rhombus shape. In the above case, the deposition material that has passed through the first opening 422A-1 is deposited on the substrate 100 to form the first pair of electrodes 230a or the second pair of electrodes 230b. When there are a plurality of first openings 422A-1, the plurality of first openings 422A-1 may be spaced apart from each other sufficiently, so that the deposition materials that have passed through each of the first openings 422A-1 may not be connected to other deposition materials after being deposited on the substrate 100.

[0225] The first opening 422A-1 can be arranged to form a counter electrode in a region corresponding to the first display region DA1 of the substrate 100. Specifically, the first opening 422A-1 can be arranged only in the first region AR1-1 of the first mask sheet 422A. In this case, the second region AR1-2 of the first mask sheet 422A may not include additional openings. The first region AR1-1 can correspond to the first display region DA1 of the substrate 100, and the second region AR1-2 can correspond to the second display region DA2 and the third display region DA3 of the substrate 100.

[0226] The second mask assembly 420B can replace the first mask assembly 420A. That is, after the first counter electrodes 230a and the second counter electrodes 230b are formed in the first display region DA1 by using the first mask assembly 420A, the second mask assembly 420B can be used to form the third counter electrodes 230c, the fourth counter electrodes 230d, and the main counter electrode 230e in the second display region DA2 and the third display region DA3.

[0227] The second mask assembly 420B can include a second mask frame 421B and a second mask sheet 422B. The second mask frame 421B is similar to or the same as the first mask frame 421A, and its detailed description is omitted here.

[0228] The second mask sheet 422B can include a second opening 422B-1, a third opening 422B-2, and a fourth opening 422B-3 for forming the third counter electrodes 230c, the fourth counter electrodes 230d, and the main counter electrode 230e.

[0229] The second opening 422B-1 can have the same shape as the shape of the first opening 422A-1. The third opening 422B-2 can have a shape different from the shape of the second opening 422B-1. For example, the third opening 422B-2 can be larger than the second opening 422B-1. In this case, the third opening 422B-2 can have a size corresponding to at least two second openings 422B-1. The second opening 422B-1 can be separated from the third opening 422B-2. Here, the first width W1 between the second opening 422B-1 and the third opening 422B-2 of the second mask sheet 422B is small enough so that the deposition materials that have passed through the second opening 422B-1 and the third opening 422B-2 and are deposited on the substrate 100 can be connected to each other.

[0230] The fourth opening 422B-3 may be connected to the third opening 422B-2. The second width W2 of the second mask sheet 422B between the fourth opening 422B-3 and the third opening 422B-2 is greater than the first width W1, so only a part of the fourth pair of electrodes 230d can be connected to the main pair of electrodes 230e. In this case, due to the portions of the second mask sheet 422B between the second opening 422B-1 and the third opening 422B-2 and between the third opening 422B-2 and the fourth opening 422B-3, when the second mask sheet 422B is tightened, the strength of the second mask sheet 422B can be ensured to a certain extent.

[0231] The second opening 422B-1 to the fourth opening 422B-3 may be in the fourth region AR2-2 of the second mask sheet 422B, and the fourth region AR2-2 corresponds to the second region AR1-2 of the first mask sheet 422A. However, additional openings may not be provided in the third region AR2-1 of the second mask sheet 422B, and the third region AR2-1 corresponds to the first region AR1-1 of the first mask sheet 422A.

[0232] The substrate 100 may be mounted on the first support 430. Here, the first support 430 may adjust the position of the substrate 100. For example, the first support 430 may include a UVW stage.

[0233] The first mask assembly 420A or the second mask assembly 420B may be mounted on the second support 440. Here, similar to the first support 430, the second support 440 may adjust the position of the first mask assembly 420A or the second mask assembly 420B.

[0234] The deposition source 450 may evaporate or sublime the deposition material after accommodating the deposition material to supply the deposition material to the chamber 410. Here, the deposition source 450 may include a heater therein, and the deposition material in the deposition source 450 is heated by using the heater to melt or sublime the deposition material. In the above case, the deposition source 450 may be disposed at the center or corner of the chamber 410. Hereinafter, for convenience of description, the case where the deposition source 450 is at the corner of the chamber 410 will be described in detail below.

[0235] The magnetic force generator 460 in the chamber 410 allows the substrate 100 and the first mask assembly 420A or the substrate 100 and the second mask assembly 420B to be in close contact with each other. Here, the magnetic force generator 460 may include an electromagnet or a permanent magnet that generates a magnetic force.

[0236] The vision part 470 photographs the positions of the first mask assembly 420A and the substrate 100 or the second mask assembly 420B and the substrate 100 in the chamber 410. Herein, the vision part 470 can photograph alignment marks or the like of at least one of the first mask assembly 420A, the second mask assembly 420B, and the substrate 100.

[0237] The pressure regulator 480 can be connected to the chamber 410 to regulate the pressure in the chamber 410. The pressure regulator 480 can include a connecting pipe 481 connected to the chamber 410 and a pump 482 provided on the connecting pipe 481.

[0238] The display device 1 can be manufactured by the device 400 for manufacturing a display device. Herein, the device 400 for manufacturing a display device can manufacture the display device 1 according to one or more embodiments to be described below and the embodiments described above. Hereinafter, for convenience of description, the case where the device 400 for manufacturing the display device 1 manufactures Figure 14 the pixel region of the display panel 10 shown in will be described in detail below. Hereinafter, the same Figure 14 reference numerals as those in the drawings denote the same elements.

[0239] Specifically, the substrate 100 on which the insulating layer is formed and the first mask assembly 420A can be disposed in the chamber 410. Herein, the pixel electrodes and the organic light-emitting layer of the thin-film transistors and the organic light-emitting diodes may have been formed.

[0240] After the substrate 100 and the first mask assembly 420A are respectively mounted on the first support member 430 and the second support member 440, the substrate 100 and the first mask assembly 420A can be photographed by the vision part 470. Thereafter, the substrate 100 and the first mask assembly 420A can be aligned.

[0241] When the deposition source 450 operates and supplies the deposition material, the deposition material can pass through the first opening 422A-1 of the first mask sheet 422A and can be deposited on the organic light-emitting layer and the pixel defining layer of the substrate 100. Herein, the deposition material that has passed through the first opening 422A-1 can form the first pair of electrodes 230a or the second pair of electrodes 230b as described above. Hereinafter, for convenience of description, the case where the deposition material forms the first pair of electrodes 230a will be described in detail.

[0242] When depositing the deposition material as described above, the first pair of electrodes 230a can be arranged in a row. There can be a plurality of rows spaced apart from each other.

[0243] When the above process is completed, the position of at least one of the substrate 100 and the first mask assembly 420A can be changed. For example, after fixing the position of the first mask assembly 420A, the position of the substrate 100 can be changed. According to some example embodiments, after fixing the position of the substrate 100, the position of the first mask assembly 420A can be changed. According to some example embodiments, the positions of both the substrate 100 and the first mask assembly 420A can be changed. Hereinafter, for ease of description, the case where the position of the substrate 100 is changed while the position of the first mask assembly 420A is fixed will be described in detail.

[0244] When the position of the substrate 100 is changed, the first opening 422A-1 can be arranged to correspond to a portion of the substrate 100 where the first pair of electrodes 230a are not formed. That is, the first opening 422A-1 can be arranged between two adjacent first pairs of electrodes 230a.

[0245] After changing the position of the substrate 100, when the deposition source 450 supplies the deposition material, the deposition material can pass through the first opening 422A-1 and can be deposited on the substrate 100. The deposition material that has passed through the first opening 422A-1 can be deposited on the substrate 100 to form the second pair of electrodes 230b. The second pair of electrodes 230b are arranged between the first pair of electrodes 230a and can be connected to the first pair of electrodes 230a via the first contact area CTA1.

[0246] When the above process is completed, the operation of the deposition source 450 is stopped or the deposition source 450 is blocked from supplying the deposition material, and then the internal pressure of the chamber 410 can be maintained at the atmospheric pressure level via the pressure regulator 480.

[0247] After opening the gate valve 411, the first mask assembly 420A exits from the inside of the chamber 410 to the outside, and the second mask assembly 420B can be loaded from the outside of the chamber 410 into the chamber 410. When the second mask assembly 420B is mounted on the second support 440, the second mask assembly 420B and the substrate 100 can be aligned. Additionally, the pressure regulator 480 can maintain the internal pressure of the chamber 410 at a level similar to the vacuum state. The deposition source 450 supplies the deposition material onto the substrate 100 to form the third pair of electrodes 230c, the fourth pair of electrodes 230d, and the main pair of electrodes 230e on the substrate 100.

[0248] Specifically, when forming the third pair of electrodes 230c on the substrate 100, the third pair of electrodes 230c can be connected to one of the first pair of electrodes 230a and the second pair of electrodes 230b. When forming the third pair of electrodes 230c, the second contact area CTA2 can be disposed between the third pair of electrodes 230c and one of the first pair of electrodes 230a and the second pair of electrodes 230b. In the second contact area CTA2, the third pair of electrodes 230c can be arranged on the upper surface of one of the first pair of electrodes 230a and the second pair of electrodes 230b. According to some example embodiments, the third pair of electrodes 230c, the fourth pair of electrodes 230d, and the main pair of electrodes 230e are formed on the substrate 100, and then the first pair of electrodes 230a and the second pair of electrodes 230b are sequentially formed. In this case, one of the first pair of electrodes 230a and the second pair of electrodes 230b can be arranged on the upper surface of the third pair of electrodes 230c.

[0249] When forming the third pair of electrodes 230c and the fourth pair of electrodes 230d as described above, the first width W1 between the second opening 422B-1 and the third opening 422B-2 of the second mask sheet 422B is small enough such that the third pair of electrodes 230c and the fourth pair of electrodes 230d on the substrate 100 can overlap each other to be connected to each other.

[0250] Accordingly, the pairs of electrodes arranged on the substrate 100 can be connected to each other via the contact areas.

[0251] In addition, the apparatus 400 for manufacturing the display device 1 can prevent the pixels in each display area from not emitting light by connecting the pairs of electrodes in the display area DA to each other.

[0252] Figure 21 is a plan view of the arrangement of the pairs of electrodes in the display panel 10 according to some example embodiments. Figure 22 is a plan view showing a part of the second mask sheet 422B according to some example embodiments Figure 17 thereof.

[0253] Referring to Figure 21 and Figure 22 , the display device 1 can be similar to the display device 1 described above with reference to Figures 1 to 14 . Hereinafter, for ease of description, the differences from the arrangement of the pairs of electrodes shown in Figure 14 will be described in detail.

[0254] The first pair of electrodes 230a, the second pair of electrodes 230b, the third pair of electrodes 230c, and the fourth pair of electrodes 230d can be the same as Figure 14The first pair of electrodes 230a, the second pair of electrodes 230b, the third pair of electrodes 230c, and the fourth pair of electrodes 230d are the same. A plurality of main pair of electrodes 230e may be spaced apart from each other and have a strip shape. Here, the plurality of main pair of electrodes 230e may be arranged in the Figure 21 Y direction. In this case, each of the main pair of electrodes 230e may not be connected to another, and one of the plurality of main pair of electrodes 230e may be connected to the plurality of fourth pair of electrodes 230d. Here, each of the main pair of electrodes 230e may be connected to each of the wirings disposed on the side surface of the substrate 100.

[0255] To form the main pair of electrodes 230e, the second mask sheet 422B may include fourth openings 422B-3 spaced apart from each other. Here, the plurality of fourth openings 422B-3 may be arranged to be spaced apart from each other in one direction. A part of the second mask sheet 422B is disposed between adjacent fourth openings 422B-3 to distinguish the adjacent fourth openings 422B-3 from each other.

[0256] In the above case, the deposition material that has passed through the fourth openings 422B-3 may form the main pair of electrodes 230e in the third display region DA3, and as described above, the deposition material that has passed through different fourth openings 422B-3 may be deposited in different regions of the substrate 100 to form different main pair of electrodes 230e from each other.

[0257] Figure 23 is a plan view of the arrangement of the pair of electrodes in the display panel 10 according to some example embodiments. Figure 24 is a plan view showing a part of the second mask sheet 422B according to some example embodiments of the Figure 17 The display device 1 may be similar to the display device 1 described above with reference to

[0258] Referring to Figure 23 and Figure 24 , the display device 1 may be similar to the display device 1 described above with reference to Figures 1 to 14 In the following, for ease of description, the differences from the arrangement of the pair of electrodes shown in Figure 14 will be described in detail.

[0259] The first pair of electrodes 230a, the second pair of electrodes 230b, the third pair of electrodes 230c, and the fourth pair of electrodes 230d may be the same as the first pair of electrodes 230a, the second pair of electrodes 230b, the third pair of electrodes 230c, and the fourth pair of electrodes 230d of the Figure 14 A plurality of main pair of electrodes 230e may be spaced apart from each other. Here, the plurality of main pair of electrodes 230e may be arranged in the Figure 23 Y-axis direction. Specifically, two main pair of electrodes 230e may be in the Figure 23arranged in the X-axis direction. In this case, the two main counter electrodes 230e may not be connected to each other, but separated from each other. The main counter electrodes 230e may not be connected to each other, and some of the plurality of main counter electrodes 230e may be respectively connected to the fourth counter electrodes 230d. Here, each of the main counter electrodes 230e may be connected to each of the wirings arranged on the side surface of the substrate 100.

[0260] To form the main counter electrodes 230e, the second mask sheet 422B may include fourth openings 422B-3 spaced apart from each other. Here, the plurality of fourth openings 422B-3 may be arranged to be spaced apart from each other in one direction and another direction, and each of the plurality of fourth openings 422B-3 has a line shape. A part of the second mask sheet 422B is arranged between adjacent fourth openings 422B-3 to distinguish the adjacent fourth openings 422B-3 from each other. That is, among the plurality of fourth openings 422B-3, two fourth openings 422B-3 are arranged in a column and a plurality of columns each having two fourth openings 422B-3 are arranged in a plurality of rows.

[0261] In the above case, the deposited material that has passed through the fourth openings 422B-3 may form the main counter electrodes 230e in the third display region DA3, and as described above, the deposited material that has passed through different fourth openings 422B-3 may be deposited in different regions of the substrate 100 to form different main counter electrodes 230e from each other.

[0262] According to one or more embodiments, a display panel having an extended display region can be implemented to display an image even in a region where components are arranged, and a display device including the display panel can be implemented. However, the scope of the disclosure is not limited to the above effects.

[0263] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail can be made herein without departing from the spirit and scope defined by the claims and their equivalents.

Claims

1. An apparatus for manufacturing a display device, the apparatus comprising: a chamber including a portion configured to be selectively opened and closed; a first support member in the chamber, the first support member being configured to support a substrate; a mask assembly in the chamber, the mask assembly facing the substrate; a second support member in the chamber, the second support member being configured to support the mask assembly; and a deposition source in the chamber, the deposition source being configured to supply a deposition material onto the substrate, wherein the mask assembly includes a first mask assembly and a second mask assembly that are replaceable with each other, the second mask assembly includes: a mask frame; and a mask sheet mounted on the mask frame, and the mask sheet includes a first opening, a second opening in a portion different from the first opening in the mask sheet, and a third opening in a portion different from the first opening and the second opening in the mask sheet, wherein the second opening is connected to the third opening, the first opening is separated from the second opening and the third opening, the first opening and the second opening have different shapes from each other, and an area of the first opening is smaller than an area of the second opening.

2. The apparatus according to claim 1, wherein, the deposition source is in a corner of the chamber.

3. The apparatus according to claim 1, wherein, the first opening has a square shape and the second opening has a rectangular shape.

4. The apparatus according to claim 1, wherein, at least one of the first support member and the second support member is configured to adjust a position of the substrate relative to the first mask assembly.

5. The device according to claim 1, wherein a plurality of third openings are spaced apart from each other, and each of the plurality of third openings has a line shape.

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