Lower computer system for testing general equipment and testing method of lower computer system

Abstract

The invention discloses a lower computer system for testing general equipment and a testing method thereof, the lower computer system comprises a core module and a plurality of acquisition function modules, and the core module is connected with the plurality of acquisition function modules through an internal data communication bus; the core module comprises a microprocessor MPU and a communication bus module; the communication bus module comprises an external data bus interface connected with an upper computer and an internal data bus interface connected with the acquisition function module; each acquisition function module comprises a plurality of acquisition modules; the system comprises an analog-to-digital converter module, a sensor module with a predetermined function, a low-frequency signal interface module, a radio-frequency signal interface module and a bus type data interface module. And the MPU analyzes the test model data packet sent by the upper computer, selects the acquisition function module according to the test model data packet and tests the to-be-tested equipment. According to the general equipment test lower computer system, a system test resettable function is constructed, and a general signal test capability is formed by using an acquisition function unit on a production line.

Description

Technical Field

[0001] The present invention relates to the technical field of product measurement equipment for flexible production lines, and particularly to a lower computer system for general equipment testing and its testing method. Background Art

[0002] In industrialized assembly line production, performance testing of products is an essential process and also an important link to examine whether the product quality passes. At present, the solution of product testing equipment is to complete the design and production according to the requirements of the test purpose, function, and interface requirements in the product test task book. The test device completed according to this procedure can better meet the simultaneous testing of multiple functions of the product, but it is not universal. Similar function test devices are repeatedly developed and produced, occupying funds and space, and the equipment utilization rate is not high. In order to improve the debugging efficiency of product development and batch production, multiple test devices are generally equipped. Different test devices can be configured according to different control device functions, uses, and interfaces, resulting in low utilization rate of the test device, occupying resources and space. Multifunctional test equipment that can test multiple performances of products mostly has a large volume, inconvenient use, and high cost.

[0003] General test equipment requires an upper computer (referred to as the upper computer) that controls the overall production line and a lower computer (referred to as the lower computer) required for operation and testing at a specific station on the production line to directly control the production equipment and execute the online test function of programmable function reset. The lower computer needs to have multiple test functions to solve the problems of low utilization rate of common test equipment and the need to frequently replace test equipment, strengthen the effective utilization rate of test equipment, improve the capital utilization rate on the production line, and reduce the occupied space of duplicate equipment. Summary of the Invention

[0004] A first aspect of the present invention provides a lower computer system for general equipment testing, and the lower computer system includes: a core module and multiple acquisition function modules, and the core module is connected to the multiple acquisition function modules through an internal data communication bus;

[0005] The core module includes: a microprocessor MPU and a communication bus module;

[0006] The communication bus module includes an external data bus interface connected to the upper computer and an internal data bus interface connected to the acquisition function modules;

[0007] Each of the acquisition function modules includes; an analog-to-digital converter module, a sensor module with a predetermined function, a low-frequency signal interface module, a radio frequency signal interface module, and a bus-type data interface module;

[0008] The microprocessor MPU receives and parses the test model data packet sent by the host computer, selects the acquisition function module according to the test model data packet, and performs the test on the device under test.

[0009] For the lower computer system according to the first aspect of the present invention, the microprocessor MPU is connected to and / or selects the acquisition function module through an internal data bus interface;

[0010] The sensor module includes a motion sensor, a geographical location sensor, a natural environment sensor, a speed sensor, and an electromagnetic radiation sensor;

[0011] The low-frequency signal interface module is connected to the low-frequency signal output port of the device under test;

[0012] The radio frequency signal interface module is connected to the radio frequency signal output port of the device under test;

[0013] The bus-type data interface module is connected to the internal signal data output port of the device under test.

[0014] For the lower computer system according to the first aspect of the present invention, the motion sensor includes: a gravity sensor, a speed sensor, an acceleration sensor, and a vibration sensor;

[0015] The geographical location sensor includes: a Beidou signal receiver, a GPS receiver;

[0016] The natural environment sensor includes: a wind speed and direction sensor, a temperature sensor, a humidity sensor, and a water pressure sensor:

[0017] The bus-type data interface module is used to connect to the bus output port of each parameter data of the device under test; the buses connected by the bus-type data interface module include: a serial port bus, a CAN bus, a MIC bus, a FlexRay bus, or an FC bus.

[0018] For the lower computer system according to the first aspect of the present invention, when using a microprocessor MPU including a built-in analog-to-digital converter, each of the acquisition function modules includes; a sensor module with a predetermined function, a low-frequency signal interface module, a radio frequency signal interface module, and a bus-type data interface module.

[0019] For the test method of the lower computer system according to any one of the foregoing, the method includes the following steps;

[0020] Step 1, after the self-check of the lower computer is started, upload the number and functions of the acquisition function modules of the lower computer to the host computer through an external data communication bus interface;

[0021] Step 2: The lower computer receives the test model data packet sent by the upper computer, parses the test model data packet, and distributes the test requirements of the device under test to each acquisition functional unit through the internal data transmission bus;

[0022] Step 3: The acquisition functional unit uploads the multiple test results of the device under test to the microprocessor MPU after performing analog-to-digital conversion; or the acquisition functional unit directly uploads the multiple test results of the device under test to the microprocessor MPU;

[0023] Step 4: The microprocessor MPU of the acquisition functional unit edits the test results of the device under test into a test result data packet and uploads it to the upper computer through the external data communication bus;

[0024] Step 5: If the lower computer receives the test model data packet sent by the upper computer within the predetermined standby time, it returns to Step 2;

[0025] If the lower computer does not receive the test model data packet sent by the upper computer within the predetermined standby time, the microprocessor MPU enters the standby state.

[0026] As for the test method described in the second aspect of the present invention, Step 1 includes the following sub-steps:

[0027] Step 1.1: The lower computer starts self-check. If the self-check is successful, the lower computer connects to the upper computer through the external data communication bus. If the self-check fails, the lower computer closes the communication bus interface;

[0028] Step 1.2: The upper computer sends a test model data packet to the lower computer with which a communication connection has been established through the external data communication bus. Each data packet includes at least one test item that the lower computer can complete.

[0029] As for the test method described in the second aspect of the present invention, Step 1.2 includes the following sub-steps:

[0030] Step 1.21: The test model data packet contains test algorithms for sensing data of different sensors, and the test algorithms run when the microprocessor MPU receives the sensing signals of the corresponding sensors;

[0031] Step 1.22: The test algorithms include performing preprocessing operations on the sensing signals, setting the gain coefficient of programmable gain amplification, and filtering out out-of-band interference in the frequency domain of the sensing signals;

[0032] Step 1.23: When the output signal of the sensor is an analog signal, start the analog-to-digital converter inside the MPU, or control the analog-to-digital converter outside the MPU to perform analog-to-digital conversion on the input analog signal.

[0033] The testing method as described in the second aspect of the present invention, wherein step 2 includes the following sub-steps:

[0034] Step 2.1, the microprocessor MPU of the lower computer receives and parses the test model data packet, and distributes the parsed test model to the acquisition function module corresponding to the test model through the internal data communication bus. The acquisition function module performs tests according to the test model.

[0035] Step 2.2, the microprocessor MPU receives the test results of the acquisition function module through the internal data transmission bus, and edits the test results by type. The types of test results include: sensor signal digital data, low-frequency signal digital data, and radio frequency signal digital data.

[0036] The testing method as described in the second aspect of the present invention, wherein step 4 includes the following sub-steps:

[0037] Step 4.1, the microprocessor MPU acquires time signals and geographical location signals through sensors, and performs digital transformation on the time signals and geographical location signals.

[0038] Step 4.2, the microprocessor MPU performs processing on the digital time signal, digital geographical location signal, the sensor signal digital data, the low-frequency signal digital data, and the radio frequency signal digital data after digital transformation, and assembles them into a test result data packet.

[0039] Step 4.3, the microprocessor MPU uploads the test result data packet to the upper computer through the external data communication bus.

[0040] The testing method as described in the second aspect of the present invention, wherein the digital data transformation in step 4.2 includes the following sub-steps:

[0041] Step 4.21, for the received sensor signals, low-frequency signals, and radio frequency signals, sample a period of time signal data for preprocessing, and perform multi-period synchronous averaging with the signal to be measured as the reference point in the time domain.

[0042] Step 4.22, judge the reliability of the measurement signal according to the data after synchronous averaging, determine the data acquisition cycle of a predetermined length, and allocate the data acquisition cycle time length and algorithm processing time to the subsequent processing algorithm.

[0043] Step 4.23, remove gross errors and calculate the average value of each measurement signal of multiple measurement results to obtain the amplitude and phase of the measurement signal. Frame the measured amplitude signal and phase signal by time, and assemble them into a test result data packet.

[0044] The method of the present invention has the following advantages: The general-purpose equipment test lower computer system of the present invention designs a system test reset function in terms of the overall structure, uses multiple acquisition function units to form a perfect multi-type signal test capability, enables the test capability of the entire test system through the upper computer, and executes a resetable equipment test system at the production line or the actual test site. Through the methods of standardizing interfaces, configuring drivers, and bus interconnection, the function recombination and flexible expansion test functions based on the acquisition function units are realized, and test equipment that follows the interface specifications can be connected and further expand the test functions. Through the ability to re-determine the test mode by software definition, a test method for various types of equipment independent of equipment categories, test tasks, and data sources is provided, which can well meet the requirements of different equipment and different test scenarios.

[0045] The above description is only an overview of the technical solution of the present invention. In order to be able to more clearly understand the technical means of the present invention, it can be implemented in accordance with the content of the specification. And in order to make the above and other purposes, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given and described in detail in conjunction with the drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Connection block diagram of the general-purpose equipment test lower computer system of the present invention;

[0047] Figure 2 Connection diagram of the general-purpose equipment test lower computer of the present invention;

[0048] Figure 3 Flowchart of the lower computer system test program of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] The present invention provides a general test lower computer architecture, which adopts the system integration theory and the ideas of modularization, combination, and serialization, highlights the plasticity, wide applicability, and agile development of the test data acquisition device, and realizes the independence or low coupling with equipment categories, test tasks, and data sources through the combination of software control around the upper computer and multiple single-function test function units.

[0050] The general test lower computer is an open and general test device, which is part of the general automatic test system. It only provides the software and hardware resources required for equipment testing. Through the software secondary development environment provided by the lower computer and the general physical test interface of the lower computer, the corresponding test interface is used to cross-connect and dock with the device under test. Adding a test program set (TPS) to the lower computer constitutes a complete general automatic test system, which is deployed on the production line or the test area for function inspection, performance testing, parameter adjustment, fault diagnosis, etc. of various equipment. From the perspectives of the usage function requirements, the technical characteristics of the device under test, and the usage operators of the deployment organization, etc., the lower computer needs to mainly meet:

[0051] 1) The overall architecture of the lower computer is universal, meeting the testing requirements of various products.

[0052] 2) The upgrade and expansion capabilities of the lower computer facilitate the upgrade of the test program set (TPS) of typical products to meet the testing requirements of new models;

[0053] 3) Economy of the lower computer: The lower computer should be flexible, customizable and reconfigurable to reduce the overall design, development and procurement costs of the test system.

[0054] The preferred embodiments of the present invention will be described in detail below in conjunction with examples. It should be understood that the following examples are provided only for the purpose of illustration and are not intended to limit the scope of protection of the present invention. Those skilled in the art may make various modifications and substitutions to the present invention without departing from the purpose and spirit of the present invention, and all of these modifications and substitutions fall within the scope of the claims of the present invention.

[0055] Attached Figure 1 The following is a system diagram of a universal device test lower computer of the present invention. The lower computer is connected to the upper computer through an external data bus and performs specific test functions according to the instructions issued by the upper computer.

[0056] A first aspect of the present invention provides a lower computer system for general equipment testing, the lower computer system comprising: a core module and a plurality of acquisition function modules, the core module being connected to the plurality of acquisition function modules via an internal data communication bus;

[0057] The core modules include: microprocessor MPU and communication bus module;

[0058] The communication bus module includes an external data bus interface connected to a host computer and an internal data bus interface connected to the acquisition function module;

[0059] Each of the acquisition function modules includes: an analog-to-digital converter module, a sensor module with a predetermined function, a low-frequency signal interface module, a radio frequency signal interface module and a bus-type data interface module;

[0060] The microprocessor MPU receives and parses the test model data packet sent by the host computer, selects the acquisition function module according to the test model data packet and executes the test on the device to be tested.

[0061] Example 1

[0062] Attached Figure 2 This is the connection diagram of the lower computer for general equipment testing of the present invention;.

[0063] The lower computer system for general equipment testing belongs to the basic layer of the general equipment testing system. The lower computer system for general equipment testing is the ultimate executor of the upper computer instructions and the most front-end data collector.

[0064] The tasks of the lower computer system for general equipment testing include:

[0065] 1) Receive signals from each acquisition function unit using the internal bus;

[0066] 2) Distribute test instructions to the acquisition function unit corresponding to the device under test using the internal bus;

[0067] 3) Conduct two-way interaction with the upper computer using the external bus and network protocol;

[0068] 4) Collect and transform various signals of the device under test according to the test model data packet sent by the upper computer. Parse, packetize, and aggregate the data and then transmit it to the upper computer.

[0069] For the lower computer system as described in the first aspect of the present invention, the microprocessor MPU is connected to and / or selects the acquisition function module through the internal data bus interface;

[0070] The sensor module includes a motion sensor, a geographical location sensor, a natural environment sensor, a speed sensor, and an electromagnetic radiation sensor;

[0071] The low-frequency signal interface module is connected to the low-frequency signal output port of the device under test;

[0072] The radio frequency signal interface module is connected to the radio frequency signal output port of the device under test;

[0073] The bus-type data interface module is connected to the internal signal data output port of the device under test.

[0074] For the lower computer system as described in the first aspect of the present invention, the motion sensor includes: a gravity sensor, a speed sensor, an acceleration sensor, and a vibration sensor;

[0075] The geographical location sensor includes: a Beidou signal receiver, a GPS receiver;

[0076] The natural environment sensor includes: a wind speed and direction sensor, a temperature sensor, a humidity sensor, and a water pressure sensor:

[0077] The bus-type data interface module is used to connect to the bus output port of the various parameter data of the device under test; the buses connected by the bus-type data interface module include: a serial port bus, a CAN bus, a MIC bus, a FlexRay bus, or an FC bus.

[0078] The slave computer system described in the first aspect of the present invention, when using a microprocessor MPU including a built-in analog-to-digital converter, each of the acquisition function modules includes: a sensor module with a predetermined function, a low-frequency signal interface module, a radio frequency signal interface module, and a bus-type data interface module.

[0079] Some common microprocessors MPU include a built-in analog-to-digital converter. When using an MPU with a built-in analog-to-digital converter as the MPU of the present invention, the output terminals of the sensor module with a predetermined function, the low-frequency signal interface module, and the radio frequency signal interface module can be directly connected to the input port of the MPU with a built-in analog-to-digital converter. The built-in analog-to-digital converter of the MPU directly performs A / D conversion on the test signals output by each module according to a predetermined program, and the converted test signal data is processed by the MPU. The bus-type data interface module is connected to the internal data communication bus.

[0080] Appendix Figure 3 is the test program flow chart of the slave computer system of the present invention.

[0081] The test method of the slave computer system described above includes the following steps;

[0082] Step 1, after the self-check of the slave computer is started, upload the number and functions of the acquisition function modules of the slave computer to the host computer through the external data communication bus interface;

[0083] Step 2, the slave computer receives the test model data packet sent by the host computer and parses the test model data packet, and distributes the test requirements of the device under test to each acquisition function unit through the internal data transmission bus;

[0084] Step 3, the acquisition function unit performs analog-to-digital conversion on multiple test results of the device under test and uploads them to the microprocessor MPU; or the acquisition function unit directly uploads multiple test results of the device under test to the microprocessor MPU;

[0085] Step 4, the microprocessor MPU of the acquisition function unit edits the test results of the device under test into a test result data packet and uploads it to the host computer through the external data communication bus;

[0086] Step 5, if the slave computer receives the test model data packet sent by the host computer within the predetermined standby time, return to Step 2;

[0087] If the slave device does not receive the test model data packet sent by the master device within the predetermined standby time, the microprocessor MPU enters the standby state. In the present invention, there can be multiple slave devices connected to the master device through an external data communication bus. Each slave device's acquisition function module can have one or more signal test functions. After the slave device completes the startup self-check, it enters the standby state and communicates with the master device through the external data communication bus. The communication connection includes the number and test functions of the acquisition function modules of the slave device. The master device receives the upload information from the slave device and programs at least one test model data packet according to the number and type of signals to be tested of the device to be tested. The test model data packets are respectively sent to the slave devices with relevant acquisition functions.

[0088] As for the test method described in the second aspect of the present invention, step 1 includes the following sub-steps:

[0089] Step 1.1, the slave device starts the self-check. If the self-check is successful, the slave device connects to the master device through the external data communication bus. If the self-check fails, the slave device closes the communication bus interface.

[0090] Step 1.2, the master device sends a test model data packet to the slave device that has established a communication connection through the external data communication bus. Each data packet includes at least one test item that a slave device can complete.

[0091] As for the test method described in the second aspect of the present invention, 1.2 includes the following sub-steps:

[0092] Step 1.21, the test model data packet contains test algorithms for sensing data of different sensors. The test algorithms run when the microprocessor MPU receives the sensing signals of the corresponding sensors.

[0093] Step 1.22, the test algorithms include performing preprocessing operations on the sensing signals, setting the gain coefficient of the programmable gain amplifier, and filtering out the out-of-band interference in the frequency domain of the sensing signals.

[0094] Step 1.23, when the output signal of the sensor is an analog signal, start the analog-to-digital converter inside the MPU, or control the analog-to-digital converter outside the MPU to perform analog-to-digital conversion on the input analog signal.

[0095] The lower computer is composed of a microcontroller and a data acquisition module, and it completes functions such as test configuration, data acquisition, analog-to-digital conversion, and assembling into test data packets for uploading to the upper computer; the upper computer manages multiple lower computers, and completes functions such as test task decomposition, test configuration distribution, test data aggregation and sorting, and test data visualization analysis. Each lower computer includes multiple acquisition function modules, and the acquisition function modules of each lower computer can be the same or different acquisition function modules. The collaborative operation of multiple lower computers is used to solve complex general tests. This general test equipment configuration reduces the difficulty of the overall system design, improves the openness, combinability, and reconfigurability of the system, and adapts to diverse test scenarios.

[0096] In order to ensure the continuous and reliable operation of the test system composed of multiple acquisition units, for a test task, using 3 to 5 acquisition function units can basically meet most test task scenarios. Therefore, for the accuracy and reliability of the test, it is appropriate to have 3 - 5 acquisition function units for each lower computer. Different combinations of lower computers with different test functions can be used to form general test systems for various different requirements.

[0097] The general test system architecture of the present invention includes: based on a data transmission bus, through test configuration, several data acquisition devices with "function definition and flexible combination" are formed into a test system, and relying on the test configuration to drive different acquisition devices and their internal modules to complete the specified functions, thus forming the capabilities of the test system.

[0098] As for the lower computer system described in the first aspect of the present invention, the microprocessor MPU of each lower computer is connected to and controls the multiple acquisition function units through an independent internal data transmission bus.

[0099] The microprocessor tests the electrical signals of sensors or other data signal interfaces according to the corresponding test algorithms of the device under test, using the signals collected by the analog-to-digital converter (A / D), and infers physical quantities based on the electrical signals. Specifically, it includes: the upper computer sends a test model data packet to the lower computer, and the microprocessor of the lower computer converts the test model data packet into a test control signal and sends it to each acquisition function module through the internal data communication bus. The analog-to-digital converter (A / D) is used to test one or several electrical signals on the corresponding signal acquisition function module, and infers physical quantities based on the electrical signals, providing each performance parameter of the device under test.

[0100] The microcontroller of the data acquisition device receives and parses the test model data packet and the test algorithm data packet of this data acquisition device. The algorithm data packet is specifically designed for a specific test project to generate an optimized data processing method. The parameter measurement unit of the present invention includes: a sensor module, an audio signal interface module, a video signal interface module, and a bus-type data interface module;

[0101] The sensor includes: a natural environment sensor, a speed sensor, an electrical signal sensor, and an electromagnetic radiation signal sensor; the natural environment sensor includes: a wind speed and direction sensor, a temperature sensor, a humidity sensor, and a rainfall sensor.

[0102] In the test model data packet issued by the host computer, there are algorithms for different types and different mode test signals, which are used to perform preliminary signal processing on the sensing signals of the above-mentioned various types of sensors in the MPU of the lower computer. Taking the test algorithm of the audio or electrical signal sensor as an example, first set the signal preprocessing operation process, and the signal preprocessing operation process includes: designing the gain coefficient of the programmable gain amplifier to amplify the input signal to meet the dynamic measurement range requirements of the signal to be measured, setting an anti-aliasing filter to filter out out-of-band interference, and using an A / D converter to perform analog-to-digital conversion of the input data. Then shape the waveform to meet the requirements of the microprocessor. The microprocessor performs preprocessing, algorithm operation, and input / output device response on the audio or electrical signal.

[0103] For example, when performing Fourier transform analysis on the full-cycle sampled audio signal, try to make the analysis spectral line fall on twice the frequency of the signal to avoid the fence effect. Assume that the audio signal is x(t), the frequency is f0, the sampling frequency is fs, the number of sampling points is N, the time length is T, and the frequency sampling interval is Δf. According to the Fourier transform principle, the relationship between T and Δf is as follows

[0104] Δf = fs / N = 1 / T

[0105] In order to make the analysis signal fall at f0, f0 and Δf must satisfy:

[0106] Z = f0 / Δf (2)

[0107] Where: Z is a positive integer.

[0108] Let the period of the audio signal x(t) be T0, then the relationship between the time length T and T0 is as follows:

[0109]

[0110] Only when the time length T of the number of sampling points N is an integer multiple of the period T0 of the audio signal x(t), can the analysis spectral line fall on the frequency of the signal to obtain an accurate spectrum. Therefore, with the frequency f of the signal to be measured as a reference, the sampling frequency dynamically and real-time tracks the signal frequency:

[0111] fs = n * f,

[0112] n is an integer, and oversampling technology is adopted during the sampling process to reduce the quantization noise of the A / D and the design index of the anti-aliasing filter.

[0113] Embodiment 2

[0114] The lower computer is an execution resource pool for collecting the measured signals of the product under test or other devices, specifically implementing the data acquisition task, and is also the integration layer of the acquisition functional units. Each acquisition functional unit is interconnected with the MPU through an internal data communication bus. The lower computer can provide a high-speed analog-to-digital converter (A / D) set between the acquisition functional unit and the MPU for analog-to-digital conversion processing of specific test signals, laying a foundation for the acquisition of the data acquisition module. A microprocessor with a built-in high-speed analog-to-digital converter (A / D) can also be used to perform analog-to-digital conversion on the test signals according to the data acquisition model data packet distributed by the upper computer, and the acquisition functional units are connected according to specific requirements to achieve function expansion. According to the different types of data collected, the acquisition work modules can be divided into bus data acquisition modules, sensor data acquisition modules, etc.

[0115] The acquisition functional unit is the front-end part of the entire test system. Each lower computer consists of acquisition functional units with definable functions and variable quantities, and realizes interconnection and interoperability through a data transmission bus to jointly complete the entire test task.

[0116] As for the test method described in the second aspect of the present invention, the 2 includes the following sub-steps:

[0117] Step 2.1, the microprocessor MPU of the lower computer receives and parses the test model data packet, and distributes the parsed test model to the acquisition functional module corresponding to the test model through the internal data communication bus, and the acquisition functional module performs tests according to the test model;

[0118] Step 2.2, the microprocessor MPU receives the test results of the acquisition functional module through the internal data transmission bus, and edits the test results by type. The types of test results include: digitized data of sensor signals, digitized data of low-frequency signals, and digitized data of radio frequency signals.

[0119] As for the test method described in the second aspect of the present invention, the step 4 includes the following sub-steps:

[0120] Step 4.1, the microprocessor MPU obtains time signals and geographical location signals through sensors, and performs digitization transformation on the time signals and the geographical location signals;

[0121] Step 4.2, the microprocessor MPU processes the digitized digital time signals, digital geographical location signals, the digitized data of the sensor signals, the digitized data of the low-frequency signals, and the digitized data of the radio frequency signals, and compiles them into a test result data packet;

[0122] Step 4.3, the microprocessor MPU uploads the test result data packet to the host computer via the external data communication bus.

[0123] In the test method as described in the second aspect of the present invention, the digital data transformation in step 4.2 includes the following sub-steps:

[0124] Step 4.21, for the received sensor signals, low-frequency signals and radio frequency signals, sample the signal data for a period of time for preprocessing, and perform multi-period synchronous averaging in the time domain with the signal to be measured as the reference point;

[0125] Step 4.22, judge the reliability of the measurement signal according to the data after synchronous averaging, determine the data acquisition period of a predetermined length, and allocate the data acquisition period time length and algorithm processing time to the subsequent processing algorithms;

[0126] Step 4.23, remove the gross error and average the various measurement signals of multiple measurement results to obtain the amplitude and phase of the measurement signal, process the measured amplitude signal and phase signal by time framing, and assemble them into a test result data packet.

[0127] Step 4.3 includes the following sub-steps:

[0128] Step 4.31, the microprocessor MPU adds time marks and / or geographical mark marks to the digital data of the sensor signal, the digital data of the low-frequency signal and the digital data of the radio frequency signal;

[0129] Step 4.32, segment the data processed in step 4.11 according to the data byte length of the data packet required by the bus standard, and add start and end symbols;

[0130] Step 4.33, the microprocessor MPU uploads the assembled test result data packet to the host computer.

[0131] In the signal preprocessing algorithm, sample the audio data for a period of time for signal preprocessing, perform multi-period synchronous averaging in the time domain with the center frequency point of the signal to be measured as the reference point, judge the frequency range and stability of the audio signal according to the data after synchronous averaging, and then allocate reasonable data acquisition time and algorithm processing time to the subsequent processing algorithms. For example, perform synchronous averaging on the audio signal every 4 frequency cycles to make the final signal tend to an ideal synchronous averaging signal. Using the above method, perform STFT on the audio signal every 4 cycles, then remove the gross error and average the various parameters of each STFT measurement result to obtain the amplitude and phase of the required frequency, and then correct the amplitude and phase to obtain the final result, thereby determining the frequency range and stability of the audio signal. This audio signal can be the engine vibration signal or the vibration frequency emitted during equipment operation.

[0132] The acquisition function unit is responsible for acquiring signals according to instructions and then performing the process of assembling them into data packets by the MPU. This process includes framing the sampled data, adding time and geographical area data information, segmenting according to a predetermined bit length, adding start and end address codes, etc. Finally, a test result data packet is formed and uploaded through the external data communication bus.

[0133] The acquisition program mechanism of the acquisition function unit is divided into two acquisition modes according to different types of acquisition objects:

[0134] Passive acquisition, such as various buses, where the external DUT sends data. Each time data sent by the DUT is received, the program will judge whether this frame of data conforms to the configuration information. If the received data is the data required within the parsed configuration, the message will be sent to the program in the encoding / decoding function area for the first parsing and the first packetization. Therefore, the upload rate of this type of signal is the same as the rate sent by the DUT.

[0135] Active acquisition, such as voltage and digital input / output signals. Even without an external signal source, this type of signal can collect and upload the floating voltage of the wire harness as the acquired data. Therefore, after being configured with a specific sampling rate, the acquisition frequency of this type of signal is determined by the configuration. The MPU will acquire the voltage and digital input / output information connected to the wire harness at this frequency and send the acquired data to the encoding / decoding function area for packetization.

[0136] (2) Encoding / decoding function area

[0137] After the acquisition function area acquires data, the acquired and parsed data will be sent to the MPU for encoding and stored in the FIFO in a specific format here.

[0138] The data packets assembled and stored in the FIFO are uploaded according to this data stream and shared through the external bus Flexray. Therefore, each slave computer can equally store all the data acquired by the acquisition function units. These data are uploaded to the host computer in the order of first in first out through Ethernet. The host computer then unpacks and encapsulates them into a database form according to the packed format.

[0139] Although the present invention has been described in detail with general descriptions and specific embodiments above, based on the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of protection required by the present invention.

Claims

1. A lower computer system for general device testing, characterized in that, The described lower computer system includes: a core module and multiple acquisition function modules, and the core module is connected to the multiple acquisition function modules through an internal data communication bus; The core module includes: a microprocessor MPU and a communication bus module; The communication bus module includes an external data bus interface connected to the upper computer and an internal data bus interface connected to the acquisition function module; Each of the acquisition function modules includes: an analog-to-digital converter module, a sensor module with a predetermined function, a low-frequency signal interface module, a radio frequency signal interface module, and a bus-type data interface module; The microprocessor MPU receives and parses the test model data packet sent by the upper computer, selects the acquisition function module according to the test model data packet, and performs the test on the device under test.

2. The slave computer system according to claim 1, wherein The microprocessor MPU is connected to and / or selects the acquisition function module through an internal data bus interface; The sensor module includes a motion sensor, a geographical location sensor, a natural environment sensor, a speed sensor, and an electromagnetic radiation sensor; The low-frequency signal interface module is connected to the low-frequency signal output port of the device under test; The radio frequency signal interface module is connected to the radio frequency signal output port of the device under test; The bus-type data interface module is connected to the internal signal data output port of the device under test.

3. The slave computer system according to claim 2, wherein The motion sensor includes: a gravity sensor, a speed sensor, an acceleration sensor, and a vibration sensor; The geographical location sensor includes: a Beidou signal receiver, a GPS receiver; The natural environment sensor includes: a wind speed and direction sensor, a temperature sensor, a humidity sensor, and a water pressure sensor; The bus-type data interface module is used to connect to the bus output port of each parameter data of the device under test; the buses connected by the bus-type data interface module include: a serial port bus, a CAN bus, a MIC bus, a FlexRay bus, or an FC bus.

4. The slave computer system according to claim 1, wherein When using a microprocessor MPU including a built-in analog-to-digital converter, each of the acquisition function modules includes: a sensor module with a predetermined function, a low-frequency signal interface module, a radio frequency signal interface module, and a bus-type data interface module.

5. A test method using the slave computer system described in any one of claims 1-4, characterized in that, The method includes the following steps; Step 1, after the self-check of the lower computer is started, upload the number and functions of the acquisition function modules of the lower computer to the upper computer through the external data communication bus interface; Step 2, the lower computer receives the test model data packet sent by the upper computer and parses the test model data packet, and distributes the test requirements of the device under test to each acquisition function unit through the internal data transmission bus; Step 3, the acquisition function unit performs analog-to-digital conversion on multiple test results of the device under test and uploads them to the microprocessor MPU; or the acquisition function unit directly uploads multiple test results of the device under test to the microprocessor MPU; Step 4, the microprocessor MPU of the acquisition function unit edits the test results of the device under test into a test result data packet and uploads it to the upper computer through the external data communication bus; Step 5, if the lower computer receives the test model data packet sent by the upper computer within the predetermined standby time, return to Step 2; If the slave computer does not receive the test model data packet sent by the master computer within the predetermined standby time, the microprocessor MPU enters the standby state.

6. The test method according to claim 5, characterized in that The said step 1 includes the following sub-steps: Step 1.1, the slave computer starts self-check. If the self-check is successful, the slave computer connects to the master computer through the external data communication bus. If the self-check fails, the slave computer closes the communication bus interface. Step 1.2, the master computer sends the test model data packet to the slave computer with which the communication connection is established through the external data communication bus. Each data packet includes at least one test item that the slave computer can complete.

7. The test method according to claim 6, characterized in that, The said step 1.2 includes the following sub-steps: Step 1.21, the test model data packet contains the test algorithms for the sensing data of different sensors, and the test algorithms run when the microprocessor MPU receives the sensing signals of the corresponding sensors. Step 1.22, the test algorithms include performing preprocessing operations on the sensing signals, setting the gain coefficient of the programmed gain amplification, and filtering out the out-of-band interference in the frequency domain of the sensing signals. Step 1.23, when the output signal of the sensor is an analog signal, start the analog-to-digital converter inside the MPU, or control the analog-to-digital converter outside the MPU to perform analog-to-digital conversion on the input analog signal.

8. The test method according to claim 5, characterized in that The said step 2 includes the following sub-steps: Step 2.1, the microprocessor MPU of the slave computer receives and parses the test model data packet, and distributes the parsed test model to the acquisition function module with the corresponding acquisition function for the test model through the internal data communication bus. The acquisition function module conducts tests according to the test model. Step 2.2, the microprocessor MPU receives the test results of the acquisition function module through the internal data transmission bus, and edits the test results by type. The types of the test results include: digitalized data of sensor signals, digitalized data of low-frequency signals, and digitalized data of radio frequency signals.

9. The test method according to claim 8, characterized in that The said step 4 includes the following sub-steps: Step 4.1, the microprocessor MPU obtains the time signal and the geographical location signal through the sensor, and performs digital transformation on the time signal and the geographical location signal. Step 4.2, the microprocessor MPU processes the digital time signal, digital geographical location signal, the digitalized data of the sensor signals, the digitalized data of the low-frequency signals, and the digitalized data of the radio frequency signals after digital transformation, and compiles them into a test result data packet. Step 4.3, the microprocessor MPU uploads the test result data packet to the master computer through the external data communication bus.

10. The test method according to claim 9, wherein The digital data transformation in the said step 4.2 includes the following sub-steps: Step 4.21, for the received sensor signals, low-frequency signals, and radio frequency signals, sample a period of time signal data for preprocessing, and perform multi-period synchronous averaging with the signal to be measured as the reference point in the time domain. Step 4.22, judge the reliability of the measurement signal according to the data after synchronous averaging, determine the data acquisition cycle of a predetermined length, and allocate the data acquisition cycle time length and algorithm processing time for the subsequent processing algorithms. Step 4.23, perform gross error removal and averaging on each measurement signal of the multiple measurement results to obtain the amplitude and phase of the measurement signal. Process the measured amplitude signal and phase signal in frames according to time and assemble them into a test result data packet.

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