Low power consumption control method and system for controller

Abstract

The present invention relates to the field of energy-saving computing, and discloses a low-power control method and system for a controller, which is used to implement prediction-sleep-wake-response full-link hardware in the controller. By real-time acquisition of the timing state data of the controlled object, the predicted sleep window value is dynamically generated using a predictive collaborative computing unit, and intelligent scheduling of sleep and wake-up is achieved, effectively reducing the power consumption of the controller. At the same time, combined with threshold comparison, DMA data transmission optimization and other technologies, data processing efficiency is improved and invalid data transmission is reduced. In the wake-up mechanism, an asynchronous wake-up circuit and an interrupt request mechanism are adopted to ensure that power is quickly restored and control response is executed when a valid instruction is received, thereby ensuring the real-time performance of the system. The present invention integrates prediction algorithms, hardware acceleration and intelligent scheduling technologies, which significantly reduces power consumption and extends device battery life while ensuring controller performance.

Description

Technical Field

[0001] The present invention relates to the field of energy-saving computing, and in particular to a low-power consumption control method and system for a controller. Background Art

[0002] With the explosive growth of IoT devices, controller energy consumption has become a core bottleneck restricting their development. These devices typically rely on coin-cell batteries, which require a 5-10 year operating lifespan, placing stringent demands on average daily power consumption. Existing technologies primarily reduce power consumption through the following approaches:

[0003] Hardware circuit optimization: Using depletion-mode MOSFET to build an active startup circuit reduces startup losses to microwatt levels;

[0004] Software strategy optimization: shut down useless peripherals, enable chip DC / DC converters instead of LDOs, and use RTC instead of timers;

[0005] Low-power protocols: Multi-protocol chips such as Zigbee and Thread use sleep mode to reduce RF energy consumption;

[0006] Communication timing optimization: For example, Difu’s “half-sleep, half-wake” mechanism (100ms working / 100ms sleeping) reduces receiving power consumption by 50%.

[0007] However, these solutions still have significant shortcomings in predictive control, hardware-level power management, and dynamic response accuracy:

[0008] Existing solutions rely on fixed time window sleep or simple threshold judgment, and cannot dynamically adjust the sleep window according to the state of the controlled object;

[0009] Although existing low-power protocols support sleep, the receive window duty cycle is fixed;

[0010] Traditional solutions rely on software interrupt response and clock gating: interrupt response delay > 500μs; clock gating standby leakage current still reaches 3-5μA;

[0011] The MCU must be involved in synchronizing and filtering data from multiple sensors, resulting in frequent wake-up. The phantom switch must initialize unused GPIO ports to prevent leakage, increasing software complexity.

[0012] Therefore, we propose a low-power control method and system for a controller to solve the above problems. Summary of the Invention

[0013] The present invention provides a low-power control method and system for a controller, which are used to implement prediction-sleep-wake-up-response full-link hardware in the controller.

[0014] A first aspect of the present invention provides a low-power control method for a controller, the low-power control method for the controller comprising: real-time collection of timing state data of a controlled object and storage in a hardware queue register group; inputting the data in the hardware queue register group into a prediction collaborative calculation unit, the unit being composed of a digital logic circuit solidified in an integrated circuit and outputting a predicted sleep window value; executing a PREDSLP instruction in a processor instruction set to write the predicted sleep window value into a sleep configuration register; generating a gated pipeline state signal through a dynamic instruction gating unit based on the value of the sleep configuration register; generating a control signal for a receiving module through a programmable timing generator based on the value of the sleep configuration register, including: extracting the lower 8 bits of the sleep configuration register value through a shift register group to generate a sleep coefficient value;

[0015] The system clock is divided into a 100ms period signal by a clock divider circuit as a reference timing signal. The sleep coefficient value and the reference timing signal are input into a programmable counter to generate an extended sleep timing signal that satisfies the following requirements:

[0016] ;

[0017] When the value of the sleep configuration register is less than the safety threshold, the hardware timestamp aligner performs the following: reading the predicted event occurrence time in the event queue; activating the wake-up circuit 10ms before the event occurs to generate a 10ms precise wake-up pulse; selecting the extended sleep timing signal or the precise wake-up pulse through the multiplexer circuit to generate the final receive control signal; when the receiving module captures a valid instruction, it sends an interrupt request to the CPU through the asynchronous wake-up circuit, restores the power supply of the instruction fetch circuit and the decoding circuit, and executes the control response.

[0018] Optionally, in a first implementation method of the first aspect of the present invention, it includes: collecting temperature, pressure, and displacement sensor data to generate a channel data packet; inputting the channel data packet into a threshold comparator circuit, eliminating data that exceeds the physical range, and outputting a valid data queue; synchronizing the valid data queue from the sensor clock domain to the system clock domain to generate a synchronization data packet; based on the real-time computing requirements of the predicted collaborative computing unit, the DMA controller writes the synchronization data packet into a designated storage partition of the hardware queue register group to generate a timing state data matrix.

[0019] Optionally, in a second implementation method of the first aspect of the present invention, it includes: extracting timing state data from a hardware queue register group through a parallel multiplexer and converting it into a fixed-point data stream; inputting the fixed-point data stream into a shift-accumulator array, performing a differential operation of a preset fractional order α, and outputting a fractional-order differential value; inputting the fractional-order differential value into a hysteresis loop parameter lookup table, and outputting a hysteresis response flag; and fusing the fractional-order differential value and the hysteresis response flag through a window generation state machine to generate a predicted sleep window value.

[0020] Optionally, in a third implementation method of the first aspect of the present invention, it includes: identifying the PREDSLP opcode through an instruction decoder circuit to generate a register operation enable signal; converting it into the physical storage address of the sleep configuration register through an address mapping table circuit according to the register number field; loading the predicted sleep window value into the data bus channel, writing it to the target physical storage address under the control of the register operation enable signal, and generating a register write completion flag; according to the register write completion flag, switching the system from the running state to the predicted sleep state through the power consumption state controller.

[0021] Optionally, in a fourth implementation method of the first aspect of the present invention, it includes: comparing the sleep configuration register value with a preset threshold voltage in real time through a voltage comparator circuit to generate a power supply control signal; when the power supply control signal is at a high level, controlling the first MOS tube array to physically disconnect the power path of the finger fetch circuit to generate a sleep state of the finger fetch circuit; when the power supply control signal is at a high level, controlling the second MOS tube array to physically disconnect the power path of the decoding circuit to generate a sleep state of the decoding circuit; and fusing the sleep state of the finger fetch circuit and the sleep state of the decoding circuit through a hardware state encoder to output a 2-bit gated pipeline state signal.

[0022] Optionally, in a fifth implementation method of the first aspect of the present invention, it includes: the baseband processor of the receiving module performs cyclic redundancy check circuit verification on the received data packet to generate a valid instruction flag signal; the valid instruction flag signal is input into the edge detection circuit to generate a wake-up trigger pulse; the wake-up trigger pulse drives the power gate driver to output the instruction fetch circuit power enable signal and the decoding circuit power enable signal; when the power supply is restored, a non-maskable interrupt vector number is generated by the interrupt controller hardware and written into the interrupt vector register; the valid instruction is transferred from the receiving buffer to the executor control register through the direct memory access channel to generate a copy of the instruction to be executed; after the power supply of the instruction fetch circuit is restored, the CPU reads the vector number from the interrupt vector register, jumps to the hard-coded interrupt service routine, reads the copy of the instruction to be executed in the executor control register, and outputs a control response signal.

[0023] A second aspect of the present invention provides a low-power control system for a controller, comprising: an acquisition module for real-time acquisition of timing state data of a controlled object and storage in a hardware queue register group; a sleep module for inputting the data in the hardware queue register group into a prediction collaborative calculation unit, the unit being composed of a digital logic circuit solidified in an integrated circuit and outputting a predicted sleep window value; a write module for executing a PREDSLP instruction in a processor instruction set and writing the predicted sleep window value into a sleep configuration register; a gating module for generating a gated pipeline state signal through a dynamic instruction gating unit according to the value of the sleep configuration register; and a recovery module for generating a control signal for a receiving module through a programmable timing generator based on the value of the sleep configuration register, comprising: extracting the lower 8 bits of the sleep configuration register value through a shift register group to generate a sleep coefficient value.

[0024] The system clock is divided into a 100ms period signal by a clock divider circuit as a reference timing signal. The sleep coefficient value and the reference timing signal are input into a programmable counter to generate an extended sleep timing signal that satisfies the following requirements:

[0025] ;

[0026] When the value of the sleep configuration register is less than the safety threshold, the hardware timestamp aligner performs the following: reading the predicted event occurrence time in the event queue; activating the wake-up circuit 10ms before the event occurs to generate a 10ms precise wake-up pulse; selecting the extended sleep timing signal or the precise wake-up pulse through the multiplexer circuit to generate the final receive control signal; and distributing the module, which is used to send an interrupt request to the CPU through the asynchronous wake-up circuit when the receiving module captures a valid instruction, restore the power supply of the instruction fetch circuit and the decoding circuit, and execute the control response.

[0027] The mechanism of this invention is as follows: through the three-layer collaboration of algorithm hardening (fractional-order differential prediction), instruction customization (PREDSLP), and physical isolation (MOSFET power gating), the entire predictive sleep decision-making, execution, and response process is decentralized to the digital logic circuitry, completely avoiding software stack energy consumption and achieving the unity of nanoampere standby current and millisecond-level response. Its core is the deep coupling of control theory (modeling the hysteresis characteristics of fractional-order differentials) with hardware architecture to form a self-closed-loop, low-power control path.

[0028] Beneficial effects: The sleep window is completely driven by the real-time state of the controlled object, completely avoiding the energy waste caused by fixed cycles; the dual modes dynamically complement each other, reducing invalid wake-ups by more than 70% while ensuring low event response latency;

[0029] Static power consumption is reduced from microamperes to nanoamperes, achieving a two-order-of-magnitude improvement in energy efficiency. Interrupt response speed is increased by 10 times, meeting the stringent timing determinism requirements of industrial control.

[0030] Sensor data processing is done without MCU intervention, reducing software wake-up frequency. Control responses skip the operating system recovery process, achieving millisecond-level real-time control of "wake-up and execute";

[0031] Dual-mode redundancy ensures 100% effective capture of commands, and is especially suitable for complex working conditions such as industrial vibration and temperature changes.

[0032] In summary, the present invention does not require processor scheduling throughout the entire process from data collection and state prediction to power management, subverting the software stack-dominated operating mode in traditional low-power solutions and achieving the coexistence of nanoampere-level standby current and millisecond-level event response in the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of a low power consumption control method of a controller according to an embodiment of the present invention;

[0034] Figure 2 Schematic diagram of a low-power control system of a controller in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] An embodiment of the present invention provides a low-power control method and system for a controller, which is used to implement prediction-sleep-wake-response full-link hardware in the controller. The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 , an embodiment of the low power consumption control method of the controller in the embodiment of the present invention includes:

[0037] 101. Hardware cache construction: collect the time sequence status data of the controlled object in real time through the sensor interface circuit and store it in the hardware queue register group;

[0038] It is understandable that the execution subject of the present invention can be a low-power control system of a controller, or a terminal or a server, which is not limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0039] It should be noted that the hardware structure design for industrial motor temperature control uses a sensor interface circuit using TI's ADS1118 16-bit ADC chip to create a 4-channel differential input interface, supporting a ±2.048V range (corresponding to the -50°C to 150°C range of a PT100 temperature sensor). The interface circuit integrates an instrumentation amplifier (INA128) and an RC low-pass filter (50Hz cutoff frequency) to eliminate electromagnetic interference from the motor.

[0040] Queue register group: Uses the built-in Block RAM resources of Xilinx Artix-7 FPGA and is configured as a 128×32-bit ring buffer. Each register group contains:

[0041] Timestamp register: 32-bit system clock count (accuracy 10μs);

[0042] Temperature value register: 16-bit fixed-point number (higher 12 bits are integers, lower 4 bits are decimals);

[0043] Status flag register: 8-bit fault code (overtemperature / abnormal vibration, etc.);

[0044] Data acquisition process, timing trigger: a sampling pulse is generated every 10ms (synchronized by a hardware timer) and an ADC conversion is started (conversion time 128μs).

[0045] Data preprocessing: The ADC raw value (0 to 32768) is converted to a °C value by a hardware multiplier × 0.015625 (implemented by a 6-bit right shift). A status flag is set if the value exceeds the range.

[0046] Circular write mechanism: The write pointer automatically increments. When the pointer reaches 0x7F, it wraps around to 0x00 and the old data is overwritten (the most recent 1.28s of data is retained).

[0047] Low power optimization features, dynamic power gating: when idle, the ADC reference voltage source is turned off (saving 3.5mA current), and only the register group is kept powered (leakage current <1μA).

[0048] Clock gating technology: Automatically shuts down the sensor interface clock after data storage is complete (reducing dynamic power consumption by 42%).

[0049] Abnormal data compression: When the temperature changes ≤ 0.5°C for 5 consecutive times, the incremental storage mode is enabled (only the change + time difference is recorded).

[0050] 102. Prediction Collaborative Hardware Computation: The data in the hardware queue register group is input into the Prediction Collaborative Computation Unit (PCCU). This unit is composed of dedicated digital logic circuits embedded in the integrated circuit, executes the physical prediction algorithm of the non-machine learning model, and outputs the predicted sleep window value.

[0051] It should be noted that, based on the industrial motor temperature control scenario, the PCCU hardware architecture is:

[0052] Core computing unit: uses dual-channel arithmetic logic unit (ALU) for parallel computing. The main channel performs temperature change rate calculation (ΔT / Δt), and the auxiliary channel calculates the second-order derivative (d 2 T / dt 2 The hardware is implemented using a custom 55nm ASIC, including:

[0053] Differential calculation circuit: reads the latest temperature value (16-bit fixed-point number) from the register group every 10ms and subtracts it from the previous data (delay 3ns);

[0054] Proportional multiplier: multiplies ΔT by the preset coefficient K (K=0.12, corresponding to the motor heat capacity of 125J / ℃), and outputs the accumulated power;

[0055] Threshold comparator: When the calculation result is ≥ the safety threshold (85°C), the over-temperature flag is triggered;

[0056] Prediction algorithm solidification:

[0057] Implementing physical thermodynamics models: ;

[0058] in, =100℃ (motor insulation limit), Take the sliding average of the last five sampling points (to suppress noise);

[0059] Real-time calculation process, data input: extract 10 consecutive temperature values ​​(time span 100ms) from the hardware queue register group with a depth of 128;

[0060] Automatically filter abnormal points: If the deviation of a certain point is greater than ±3°C (vibration interference), the previous value replacement mechanism is activated;

[0061] Physics Prediction Execution:

[0062] Step 1: Calculate the instantaneous rate of change ( is the data 100ms ago);

[0063] Step 2: Match the preset coefficients through the hardware lookup table (LUT):

[0064] like >5℃ / s→coefficient α=0.8 (forced cooling mode);

[0065] If 0.5< ≤5℃ / s→α=1.2 (linear prediction);

[0066] Step 3: Output the predicted value, ;

[0067] Output constraints:

[0068] The minimum value is limited to 10ms (to prevent false triggering);

[0069] The maximum value is limited to 600s (compatible with the device in standby mode);

[0070] The high 8 bits of the 16-bit output register are integer seconds, and the low 8 bits are 0.1 second precision;

[0071] Low power optimization features:

[0072] Event-driven computing: Operations are started only when the register group update flag is set (static power consumption < 5μW);

[0073] Data stream compression: When 5 consecutive When the temperature is less than 0.2℃, it automatically switches to incremental calculation mode (power consumption is reduced by 63%).

[0074] Adaptive clock gating: Shuts down the clock tree immediately after a compute unit completes its operation (reducing dynamic power consumption by 42%).

[0075] Dedicated hardware embedded with thermodynamic models enables microsecond-level physical predictions, eliminating the energy consumption associated with frequent wake-up cycles in traditional MCU solutions. A key innovation lies in combining sliding average filtering with adaptive coefficients, achieving sub-milliwatt power consumption while maintaining prediction accuracy, providing highly reliable input for subsequent sleep decisions.

[0076] 103. Extended instruction set control: execute the PREDSLP special instruction in the processor instruction set to write the predicted sleep window value into the sleep configuration register;

[0077] It should be noted that the hardware architecture design:

[0078] Special instruction definition: The PREDSLP instruction is a 32-bit RISC-V extension instruction (Opcode is customized to 0x7B) and belongs to the "privileged instruction set" extension. Its function is to write the predicted sleep window value (16-bit fixed-point number, unit 10ms) from general register a0 to the sleep configuration register (SCR). Instruction format:

[0079] PREDSLPa0;

[0080] The upper 16 bits are reserved, and the lower 16 bits store the sleep window value (for example, 0x00C8 means 2 seconds of sleep).

[0081] Sleep Configuration Register (SCR): mapped to memory address 0x4000_8000, 32 bits wide, the lower 16 bits store the sleep window value, and the upper 16 bits retain the status flag (wake-up interrupt trigger bit).

[0082] Operation process (taking the predicted sleep window = 2 seconds as an example):

[0083] Forecast value preparation:

[0084] The PCCU calculates the sleep window to be 2000ms (corresponding to the hexadecimal value 0x00C8) and stores it in general register a0.

[0085] Instruction execution:

[0086] The processor executes the PREDSLPa0 instruction:

[0087] Decoding stage: Identify the 0x7B opcode and activate the SCR write path.

[0088] Execution stage: latch the lower 16 bits of a0 (0x00C8) into the lower 16 bits of SCR.

[0089] Register Update:

[0090] The SCR value is updated to 0x0000_00C8, triggering subsequent operations:

[0091] If the value is greater than the threshold (1 second), the DIG unit turns off the power supply to the CPU instruction fetch / decode circuit;

[0092] The programmable timing generator synchronously receives the SCR value and dynamically adjusts the receive window duty cycle.

[0093] Low-power optimization features, single-cycle completion: Hardware directly connects the SCR and register bus, and instruction execution takes only one clock cycle (20ns at 50MHz), saving 87% latency compared to traditional memory-mapped IO.

[0094] Static power consumption control: SCR adopts high threshold voltage (HVT) cell design, with quiescent current as low as 0.5μA.

[0095] Safety check: Automatically check the value range (10ms~600s) before writing, and trigger an abnormal interrupt if it exceeds the limit.

[0096] Hardware-level hibernation parameter injection is achieved through custom instructions, eliminating the multi-instruction overhead of traditional store-load-write operations. The key innovation lies in using the SCR as an extension of the processor register space, combined with the modular nature of the RISC-V instruction set, to reduce control power consumption to the microjoule level while ensuring real-time performance.

[0097] 104. Pipeline circuit gating: Based on the value of the sleep configuration register, the dynamic instruction gating unit (DIG) performs the following operations: when the value is greater than the threshold, the power supply to the CPU's instruction fetch circuit and decoding circuit is turned off; when the value is less than the threshold, the instruction fetch circuit and decoding circuit are kept active; and a gated pipeline status signal is generated;

[0098] It should be noted that the DIG hardware architecture design:

[0099] Gating cell architecture: A latch-based gating cell (Latch-based Gating Cell) is used, consisting of a level-sensitive latch and an enable signal control circuit. When the sleep configuration register (SCR) value exceeds 1 second (threshold), the clock AND gate is triggered to shut down the instruction fetch / decode circuit clock signal; simultaneously, the PMOS power switch cuts off the power supply (3.3V→0V), and the static leakage current is less than 0.8μA.

[0100] Status signal generator: The integrated comparator circuit monitors the SCR value in real time and outputs two signals:

[0101] GATE_STAT1: instruction fetch circuit gate status (high = active);

[0102] GATE_STAT2: decoding circuit gate state (high = active);

[0103] Dynamic gating process (taking the sleep window = 2 seconds as an example):

[0104] Threshold judgment: SCR value 0x00C8 (2 seconds) > threshold 0x0064 (1 second), the DIG unit enables gate operation.

[0105] The clock and power are shut down synchronously: Clock gating: The latch captures the low-level enable signal, blocking the clock tree from transmitting to the instruction fetch / decoding circuit; Power gating: The PMOS switch cuts off the power supply, and the power consumption of the instruction fetch circuit drops sharply from 15mW to 0.2mW.

[0106] Status signal update: Generate GATE_STAT1=0, GATE_STAT2=0, marking the pipeline entering sleep mode.

[0107] Energy efficiency optimization design, hierarchical shutdown strategy: instruction fetch circuit: shut down after 50ns delay (to avoid instruction prefetch conflicts); decoding circuit: shut down immediately (no dynamic tasks);

[0108] Wake-up pre-synchronization mechanism: Maintains power to the latch state refresh circuit during sleep to ensure that clock phase synchronization is restored within 5μs upon wake-up.

[0109] The performance data is shown in Table 1 below:

[0110] Table 1

[0111]

[0112] Through hardware-level clock / power dual gating, non-essential circuits are completely shut down during steady-state motor operation. The key innovation lies in combining latch-type gating units with a hierarchical shutdown strategy. This ensures real-time wake-up (<5μs) while keeping pipeline standby power consumption to microwatts, achieving over 98% energy savings compared to traditional solutions.

[0113] 105. Dynamic generation of communication timing: Based on the value of the sleep configuration register, the programmable timing generator generates the control signal of the receiving module, including: when the value is greater than the safety threshold, outputting the extended sleep timing signal (receive window duty cycle ≤ 5%); when the value is less than the safety threshold, outputting the precise wake-up timing signal (activating the receiving circuit 10ms before the predicted event occurs);

[0114] It should be noted that the programmable timing generator uses a dual-clock domain architecture, integrating a 32kHz low-power clock (running in sleep mode) and a 50MHz system clock (running in active mode). The operating mode is dynamically switched using a 16-bit value (in 10ms units) in the Sleep Configuration Register (SCR), with a safety threshold set to 2000ms (corresponding to SCR value 0x00C8).

[0115] Control signal logic:

[0116] When the SCR value is greater than 2000ms (temperature stable state), the extended sleep sequence is triggered:

[0117] Generates a square wave with a period of 400ms and a receiving window of 20ms (duty cycle = 5%). The receiving module is activated only within the 20ms window.

[0118] When the SCR value is ≤ 2000ms (temperature mutation risk), the precise wake-up sequence is triggered:

[0119] Based on the overheating time point predicted by the PCCU, a 50ms activation window is generated 10ms in advance (if the overheating time is predicted to be t=5000ms, the receiving circuit is started at t-10ms=4990ms).

[0120] Dynamic timing generation process, threshold judgment: The timing generator reads the SCR value every 10ms (for example: SCR = 0x012C → sleep window = 3000ms > 2000ms).

[0121] Mode switch:

[0122] Extended sleep mode: The RX_EN signal with a period of 400ms and a pulse width of 20ms is output. The receiving module only works for 20ms every 400ms.

[0123] Precision wake-up mode: Real-time calculation of activation time = predicted event timestamp - 10ms (if the motor is predicted to overheat at 6050ms, a high level RX_EN is output at 6040ms for 50ms).

[0124] Power consumption optimization: The 50MHz clock tree is turned off during sleep mode, leaving only the 32kHz clock power supply (quiescent current 1.2μA).

[0125] By dynamically switching the receive timing strategy, ultra-low duty cycle (5%) monitoring is achieved during motor steady-state, ensuring 10ms-level wake-up accuracy even under sudden change risks. A key innovation lies in combining real-time calculation of predicted event timestamps, reducing communication energy consumption to less than 17% of traditional polling solutions.

[0126] 106. Hardware interrupt recovery: When the receiving module captures a valid instruction, it sends an interrupt request to the CPU through the asynchronous wake-up circuit, restores the power supply to the instruction fetch circuit and decoding circuit, and executes the control response.

[0127] It should be noted that the asynchronous wake-up circuit design and interrupt trigger mechanism:

[0128] When the receiving module (NRF52840) captures the "Emergency Stop" command (0xAA55), it triggers a high-level pulse (≥5μs width) through GPIO13. The asynchronous wake-up circuit uses a level-sensitive latch to immediately activate the interrupt request line (IRQ) when a high level is detected, regardless of the CPU sleep state.

[0129] Power restoration logic:

[0130] The wake-up circuit outputs two control signals:

[0131] Clock enable signal: directly connected to the dynamic instruction gating unit (DIG) to restore the clock supply (50MHz) to the instruction fetch / decode circuit;

[0132] Power enable signal: controls the PMOS switch (SI2312 chip) to restore 3.3V power to the CPU pipeline circuit within 200ns;

[0133] Interrupt handling process, interrupt capture:

[0134] When the motor overheats, the cloud sends a shutdown command (command code 0xAA55). The receiving module captures the command within the precise wake-up window (within the 10ms activation period) and triggers an asynchronous wake-up signal.

[0135] Status recovery:

[0136] Power recovery: After the PMOS switch is turned on, the power supply to the instruction fetch and decoding circuits increases from 0.15mW to 15mW (taking 1.5μs).

[0137] Pipeline activation: The DIG unit is de-gated, generating GATE_STAT = 0x3 (the upper 2 bits indicate that the instruction fetch / decode circuit is activated);

[0138] Interrupt response: The CPU resumes execution from the sleep address 0x8000F000, jumps to the interrupt vector table (address 0x00000000), and calls the emergency shutdown service routine: turns off the motor drive power (IO pin is set to low level); starts the cooling fan (PWM duty cycle 100%); and sends status code 0xE0 to the cloud (via the SPI interface).

[0139] The performance indicators are shown in Table 2 below:

[0140] Table 2

[0141]

[0142] Scenario: When a motor stalls and overheats, the entire process from command capture to shutdown takes ≤ 54μs, significantly faster than traditional polling solutions. The asynchronous wake-up circuit consumes only 0.8μA of quiescent current, eliminating excess energy consumption during sleep.

[0143] This embodiment uses hardware-level asynchronous wake-up circuitry and state machine control to complete the complete response chain from sleep to execution within 5μs. The core innovation lies in the co-design of level-sensitive latches and power gating, ensuring μs-level interrupt response while keeping standby power consumption to microamperes.

[0144] See also Figure 1 Another embodiment of the low power consumption control method of the controller in the embodiment of the present invention includes:

[0145] 101. Hardware cache construction: collect the time sequence status data of the controlled object in real time through the sensor interface circuit and store it in the hardware queue register group;

[0146] Specifically, the temperature, pressure, and displacement sensor data are collected simultaneously through the parallel ADC interface to generate a channel data packet; the channel data packet is input into the threshold comparator circuit to eliminate the data that exceeds the physical range and output the valid data queue; the valid data queue is synchronized from the sensor clock domain to the system clock domain through the dual-port asynchronous FIFO memory to generate a synchronization data packet; according to the real-time computing requirements of the predictive collaborative computing unit (PCCU), the DMA controller writes the synchronization data packet into the specified storage partition of the hardware queue register group to generate a timing state data matrix (the timing state data matrix is ​​used as the input of 102).

[0147] It should be noted that the sensor interface configuration and parallel ADC acquisition:

[0148] Using three independent ADC modules (ADC1 / 2 / 3) for synchronous sampling:

[0149] ADC1 channel 5 (PA0) is connected to a temperature sensor (PT100, range -40~125℃);

[0150] ADC2 channel 6 (PA1) is connected to the pressure sensor (0-10MPa);

[0151] ADC3 channel 7 (PA2) connects to the displacement sensor (0-100mm);

[0152] Configure TIM3 timer trigger (100kHz sampling rate), 12-bit resolution;

[0153] Output channel data packet format:

[0154] [Temperature ADC value (16 bit) | Pressure ADC value (16 bit) | Displacement ADC value (16 bit)];

[0155] Threshold screening circuit, range protection design:

[0156] Threshold comparator parameters (based on LM393):

[0157] Temperature threshold: 0.88V (-40°C) ~ 3.0V (125°C);

[0158] Pressure threshold: 0.5V (0MPa) ~ 2.5V (10MPa);

[0159] Displacement threshold: 0.3V (0mm) ~ 3.0V (100mm);

[0160] Hardware implementation: A hysteresis comparator circuit is used; resistor configuration: R1 = 20kΩ, R2 = 4.3kΩ, R3 = 11.2kΩ, R4 = 46kΩ; out-of-range data is marked as 0xFFFF and is discarded in real time by the FPGA logic circuit;

[0161] Clock domain synchronization, asynchronous FIFO design:

[0162] Dual-port FIFO parameters: depth 1024 words (18-bit width); write clock: sensor clock domain (100kHz); read clock: system clock domain (72MHz);

[0163] Synchronization mechanism: Gray code pointer conversion avoids metastability; empty / full flags are synchronized across clock domains; output synchronization data packet format is consistent with input;

[0164] Data matrix generation, DMA hardware acceleration:

[0165] Configure DMA2 Stream0: Source address: FIFO read port (0x40026000); Destination address: Hardware queue register group (0x2001FC00); Transfer mode: Burst transfer (4 packets at a time);

[0166] Register group partition:

[0167] 0x2001FC00-0x2001FC7F: temperature data area (128 words);

[0168] 0x2001FC80-0x2001FCFF: pressure data area (128 words);

[0169] 0x2001FD00-0x2001FD7F: displacement data area (128 words);

[0170] Conditions for triggering PCCU calculation: When the amount of data in a partition is ≥ 64 groups, the status register flag is set.

[0171] 102. Prediction Collaborative Hardware Computation: The data in the hardware queue register group is input into the Prediction Collaborative Computation Unit (PCCU). This unit is composed of dedicated digital logic circuits embedded in the integrated circuit, executes the physical prediction algorithm of the non-machine learning model, and outputs the predicted sleep window value.

[0172] Specifically, the timing state data is extracted from the hardware queue register group through a parallel multiplexer and converted into a fixed-point data stream; the fixed-point data stream is input into a shift-accumulator array, a differential operation of a preset fractional order α is performed, and a fractional-order differential value is output; the fractional-order differential value is input into a hysteresis loop parameter lookup table, and a hysteresis response flag is output based on the Preisach hysteresis model; the fractional-order differential value and the hysteresis response flag are fused through a window generation state machine to generate a predicted sleep window value (as input to step 103) and write it into the output register.

[0173] It should be noted that, in this scenario, the controlled object is the temperature of a heating furnace, and the sensor data includes temperature (range 0-100°C), pressure (0-10kPa), and displacement (0-50mm). The PCCU (Predictive Collaborative Computing Unit) executes the physical prediction algorithm through dedicated digital logic circuits and outputs the predicted sleep window value. The specific implementation is as follows:

[0174] Data extraction and fixed-point conversion, input data source: hardware queue register group stores timing state data matrix, including the latest 64 sets of sampling data (sampled once every 100ms):

[0175] Temperature data: 32 sets of fixed-point numbers (Q16 format, 16-bit integer part, 16-bit decimal part), ranging from 0 to 100°C (25.5°C is converted to 0x19800000).

[0176] The parallel multiplexer extracts data from the register group: selects the temperature channel data stream (highest priority) and outputs the fixed-point data stream through a 4:1 multiplexer. The conversion time is ≤50ns.

[0177] Fractional differential operation, shift-accumulator array configuration:

[0178] The preset fractional order α=0.7 (for slow dynamic characteristics of temperature changes).

[0179] The array consists of 8 shift-accumulate units in parallel, each performing fractional differentiation:

[0180] ;

[0181] The weight coefficient Solidified in ROM ( =0.7, =0.2, =0.08, =0.02).

[0182] Output example: Input the temperature data stream [25.5, 26.0, 26.2]°C. After calculation, the output fractional-order difference value is 0.15 (fixed-point number 0x00018000), and the operation delay is 200ns.

[0183] Generation of hysteresis response flag, hysteresis loop parameter lookup table: Based on the Preisach hysteresis model, the lookup table stores 256 entries corresponding to hysteresis responses of different differential value ranges.

[0184] Parameter definition: Temperature rising threshold = 0.1°C / ms, falling threshold = 0.08°C / ms.

[0185] Logical judgment: If the fractional-order difference value ≥ the rising threshold (0.15 > 0.1), the output hysteresis response flag bit 1 (indicating accelerated temperature rise); otherwise, the output is 0.

[0186] Hardware implementation: The lookup table is implemented using a combinational logic circuit (AND gate array) with an access time of 20ns.

[0187] Dormant window value generation, window generation state machine: The state machine contains three states (IDLE, CALC, OUTPUT), and the dormant window is calculated based on the differential value and flag bit fusion.

[0188] Fusion rule: If the flag bit = 1 (accelerated rise), the sleep window = basic window × (1 - difference value) × safety factor.

[0189] If the flag bit = 0 (stable), the sleep window = basic window × 1.2 (extended sleep).

[0190] Specific calculation: basic window = 100ms, input differential value 0.15, flag bit 1, output sleep window value 85ms (fixed-point number 0x55).

[0191] Write output register: Store the value through the 32-bit output register (address 0x4000F000), and the write time is 10ns.

[0192] 103. Extended instruction set control: execute the PREDSLP special instruction in the processor instruction set to write the predicted sleep window value into the sleep configuration register;

[0193] Specifically, instruction decoding trigger: the PREDSLP opcode is identified through the instruction decoder circuit, and a register operation enable signal is generated; address mapping conversion: according to the register number field in the PREDSLP instruction, it is converted into the physical storage address of the sleep configuration register through the address mapping table circuit; data bus transmission: the predicted sleep window value is loaded into the dedicated data bus channel, and written to the target physical storage address under the control of the register operation enable signal, and a register write completion flag is generated; low power state switching: according to the register write completion flag, the system is switched from the running state to the predicted sleep state through the power state controller (trigger condition of 104).

[0194] It should be noted that the dedicated instructions integrate:

[0195] PREDSLP instruction encoding: 0xF1A0_000X (the upper 16 bits are the operation code, and the lower 4 bits X are the target register number);

[0196] Sleep configuration register address: 0x4000_01F0 (32-bit register, stores the sleep window value);

[0197] Power state controller: integrated into the power management unit (PWR), supports switching from running state (4.2mA) to predicted sleep state (1.3μA);

[0198] Instruction execution flow, instruction decoding trigger:

[0199] When the CPU executes the PREDSLP R2 instruction (R2 stores the predicted value 85ms / 0x55):

[0200] The instruction decoder recognizes the opcode 0xF1A0 and generates a register operation enable signal (active high).

[0201] Clock synchronization delay: ≤3ns (system clock 72MHz);

[0202] Address mapping translation:

[0203] Register number field analysis: Extract the lower 4 bits of the instruction 0x2 (corresponding to R2);

[0204] Address mapping table hardware implementation: Input register number: 0x2 → Mapping table output physical address: 0x4000_01F8 (offset +8, because each sleep register occupies 4 bytes);

[0205] Conversion time: realized by combinational logic circuit, delay 2ns;

[0206] Data bus transmission, data transmission path:

[0207] [R2 register] →|dedicated 32-bit bus| →[sleep configuration register];

[0208] Key timing parameters:

[0209] Register enable signal width: 10 clock cycles (about 139ns);

[0210] Data setup time: 0x55 value loading is completed 5ns before the rising edge of the enable signal;

[0211] Write completion flag generation: set on the falling edge of the enable signal (flag address 0x4000_01FF);

[0212] Low power state switching, power state controller action:

[0213] After detecting the write completion flag, the state switching sequence is started;

[0214] Execution order:

[0215] Turn off the core voltage regulator (VCORE from 1.2V to 0.9V);

[0216] Freeze the system clock (HCLK / PCLK stop);

[0217] Keep the backup domain powered (RTC keeps running);

[0218] Switching time: 8μs (from flag setting to entering Stop mode);

[0219] Energy consumption comparison (input predicted value 85ms) is shown in Table 3 below:

[0220] Table 3

[0221]

[0222] 104. Pipeline circuit gating: Based on the value of the sleep configuration register, the dynamic instruction gating unit (DIG) performs the following operations: when the value is greater than the threshold, the power supply to the CPU's instruction fetch circuit and decoding circuit is turned off; when the value is less than the threshold, the instruction fetch circuit and decoding circuit are kept active; and a gated pipeline status signal is generated;

[0223] Specifically, threshold hardware comparison: a voltage comparator circuit compares the sleep configuration register value with a preset threshold voltage in real time to generate a power supply control signal; instruction fetch circuit gating: when the power supply control signal is high, the first MOS transistor array is controlled to physically disconnect the power supply path of the instruction fetch circuit, generating a sleep state for the instruction fetch circuit; decoding circuit gating: when the power supply control signal is high, the second MOS transistor array is controlled to physically disconnect the power supply path of the decoding circuit, generating a sleep state for the decoding circuit; state signal encoding: a hardware state encoder is used to fuse the sleep state of the instruction fetch circuit and the sleep state of the decoding circuit, and output a 2-bit gated pipeline state signal (as a basis for interrupt recovery) to the pipeline state register.

[0224] It should be noted that the core parameters are:

[0225] Sleep configuration register address: 0x4000_01F0 (32 bits, stores the predicted sleep window value);

[0226] Threshold voltage: 1.0V (corresponding to the value 0x32, i.e. 50ms threshold);

[0227] MOS tube array: SI2301 MOSFET (on-resistance 0.1Ω, off-leakage current <1μA);

[0228] System supply voltage: 1.2V (CPU core voltage);

[0229] Gating execution flow, threshold hardware comparison:

[0230] When the sleep configuration register value is 0x64 (100ms):

[0231] The voltage comparator (LM393) converts the register value DAC to 1.8V (full scale 3.3V corresponds to 200ms);

[0232] Compared with the preset threshold voltage 1.0V (0x32), a high-level power supply control signal (logic 1) is output;

[0233] Response time: 20ns (typical);

[0234] The instruction fetch circuit is gated, and the power supply control signal drives the first MOS tube array (Q1-Q4):

[0235] Physically disconnect the 1.2V power supply path of the instruction fetch circuit;

[0236] The current drops from 4.2mA in the running state to 0.9mA in the sleeping state;

[0237] The status register marks the instruction fetch circuit as dormant (status bit FETCH_SLP = 1);

[0238] Decoding circuit gate control, synchronous control of the second MOS tube array (Q5-Q8):

[0239] Disconnect the 1.2V power supply of the decoding circuit;

[0240] The current dropped from 3.8mA to 0.85mA;

[0241] Status flag DECODE_SLP=1;

[0242] Status signal encoding, hardware status encoder (74HC148) input:

[0243] FETCH_SLP=1, DECODE_SLP=1 → Output encoding "11b";

[0244] Write to the pipeline status register (address 0x4000_01F4 lower 2 bits);

[0245] Coding delay: ≤5ns;

[0246] The test data is shown in Table 4 below:

[0247] Table 4

[0248]

[0249] 105. Dynamic generation of communication timing: Based on the value of the sleep configuration register, the programmable timing generator generates the control signal of the receiving module, including: when the value is greater than the safety threshold, outputting the extended sleep timing signal (receive window duty cycle ≤ 5%); when the value is less than the safety threshold, outputting the precise wake-up timing signal (activating the receiving circuit 10ms before the predicted event occurs);

[0250] Specifically, the sleep coefficient calculation is as follows: the lower 8 bits of the sleep configuration register value are extracted through the shift register group to generate the sleep coefficient value; the basic beat generation is as follows: the system clock is divided into a 100ms period signal through the clock division circuit as the reference timing signal; the dynamic cycle extension is as follows: the sleep coefficient value and the reference timing signal are input into the programmable counter to generate the extended sleep timing signal, which satisfies:

[0251] ;

[0252] Precise wake-up alignment: When the sleep configuration register value is less than the safety threshold, the hardware timestamp aligner performs the following operations: reading the predicted event occurrence time in the event queue; activating the wake-up circuit 10ms before the event occurs to generate a 10ms precise wake-up pulse; signal synthesis output: selecting the extended sleep timing signal or the precise wake-up pulse through the multiplexer circuit to generate the final receive control signal to the module.

[0253] It should be noted that the sleep coefficient calculation input is: sleep configuration register value (for example: predicted sleep window 85ms → hexadecimal value 0x55);

[0254] operate:

[0255] The shift register group extracts the lower 8 bits: 0x55 & 0xFF = 0x55 (decimal 85);

[0256] Sleep coefficient value (Sleep_Coeff) = 0x55 (directly used in subsequent calculations);

[0257] Basic beat generation, hardware configuration:

[0258] Clock divider parameters: Input 72MHz system clock, division ratio 720 → output 100Hz signal (period 100ms);

[0259] Base timing signal (Base_CLK): 100ms square wave, 50% duty cycle;

[0260] Dynamic cycle extension, condition: sleep value 85ms > safety threshold 50ms → trigger extended sleep mode;

[0261] Programmable counter operation:

[0262] ;

[0263] Receive window opening time: fixed at 100ms (duty cycle calculation: 100ms / 8500ms × 100% ≈ 1.18%);

[0264] Output signal: Generate a 100ms receiving window every 8.5 seconds, and close the receiving circuit for the rest of the time;

[0265] Precise wakeup alignment, condition: if the sleep value drops to 30ms (0x1E) < 50ms → trigger precise wakeup mode;

[0266] Hardware timestamp aligner operation:

[0267] Read the predicted event queue (for example, a temperature mutation event is expected to occur at t+205ms);

[0268] Activate the wake-up circuit at t+195ms (10ms in advance);

[0269] Generate a wake-up pulse with a width of 10ms (high level is valid);

[0270] Signal synthesis output, multiplexer logic:

[0271] Sleep value > 50ms: Select the extended sleep timing signal (duty cycle 1.18%);

[0272] Sleep value ≤ 50ms: Select precise wake-up pulse (10ms width);

[0273] Final output:

[0274] RX_EN pin of the control module (SX1276): starts receiving when the level is high;

[0275] The performance test data (25°C environment) are shown in Table 5 below:

[0276] Table 5

[0277]

[0278] 106. Hardware interrupt recovery: When the receiving module captures a valid instruction, it sends an interrupt request to the CPU through the asynchronous wake-up circuit, restores the power supply to the instruction fetch circuit and decoding circuit, and executes the control response.

[0279] Specifically, instruction validity verification: the baseband processor of the receiving module performs cyclic redundancy check (CRC) circuit verification on the received data packet to generate a valid instruction flag signal; asynchronous wake-up trigger: the valid instruction flag signal is input into the edge detection circuit to generate a wake-up trigger pulse; power recovery control: the wake-up trigger pulse drives the power gate driver to output the instruction fetch circuit power enable signal and the decoding circuit power enable signal; interrupt vector generation: when the power is restored, the interrupt controller hardware generates a non-maskable interrupt vector number and writes it into the interrupt vector register; control instruction pass-through: the valid instruction is transferred from the receive buffer to the executor control register through the direct memory access (DMA) channel to generate a copy of the instruction to be executed; interrupt service jump: after the power supply of the instruction fetch circuit is restored, the CPU reads the vector number from the interrupt vector register, jumps to the hard-coded interrupt service routine, reads the copy of the instruction to be executed in the executor control register, and outputs a control response signal to the executor.

[0280] It should be noted that the scenario setting is a heating furnace temperature control system, the CPU is in a predicted sleep state (the instruction fetch / decode circuit is powered off), the sleep configuration register value is 85ms (0x55), and the system clock is 72MHz. The module is SX1276 (LoRa communication).

[0281] Verify the validity of the command, the module receives the command:

[0282] Receive data packet: 0x3A 01 25 00 3C (command header 0x3A, set temperature 25°C, target value 60°C);

[0283] CRC check: The baseband processor performs a CRC-16 check (polynomial 0x1021), calculates the checksum 0x4F29, and matches it with the last two bytes of the data packet → generating a valid instruction flag signal (high level).

[0284] Response time: < 500μs (accelerated by hardware CRC circuit);

[0285] Asynchronous wake-up trigger, edge detection circuit (SN74LVC1G17):

[0286] Input valid instruction flag signal (rising edge) → output 10μs width wake-up trigger pulse;

[0287] Key parameters: Propagation delay of 15ns, meeting fast wake-up requirements;

[0288] Power recovery control, power gate driver (TPS22918 load switch):

[0289] Wake-up pulse drives MOS tube array:

[0290] The first path: turns on the power supply of the instruction fetch circuit (enable signal FETCH_PWR_EN=1);

[0291] The second path: turns on the decoding circuit power supply (enable signal DECODE_PWR_EN=1);

[0292] Current change: Sleep state 1.2μA → Recovery state 4.2mA (completed within 20μs);

[0293] Interrupt vector generation, interrupt controller (NVIC hardware module):

[0294] When power is restored, a non-maskable interrupt vector number 0x0000_000F (the highest priority) is generated.

[0295] Write to the interrupt vector register (address 0xE000_ED08);

[0296] Latency: < 100ns (hardware direct path);

[0297] Control instruction pass-through, DMA channel transmission (STM32 DMA2):

[0298] Source address: receive buffer 0x2000_8000;

[0299] Target address: actuator control register 0x4000_2000 (heating power adjustment register);

[0300] Transmission content: Valid instruction 0x25 (25°C) → Generate a copy of the instruction to be executed;

[0301] Transmission time: 2μs (burst transmission mode);

[0302] Interrupt service jump, CPU response process:

[0303] After the power supply of the instruction fetch circuit is restored, the vector number 0x0000_000F is read from 0xE000_ED08;

[0304] Jump to the hardcoded ISR entry address 0x0800_1F00;

[0305] The ISR reads the actuator control register value 0x25 and outputs a PWM control signal to the heater (duty cycle 40%).

[0306] Total response delay: from wake-up to output control signal ≤ 50μs;

[0307] The performance test data (25°C environment) are shown in Table 6 below:

[0308] Table 6

[0309]

[0310] In this embodiment of the present invention, a parallel ADC interface (ADC1 / 2 / 3) is used to synchronously collect temperature, pressure, and displacement data, and a hysteresis comparator circuit is combined to achieve hardware-level outlier elimination. An asynchronous FIFO design (1024-word depth, Gray code pointer) solves the problem of cross-clock domain transmission, improving data synchronization efficiency by 3 times. Furthermore, out-of-range data (marked as 0xFFFF) is eliminated in real time through the FPGA to ensure the reliability of subsequent calculations. The fractional-order differential operation (α=0.7) and the Preisach hysteresis model are solidified in the digital logic circuit, and a 200ns delay is achieved through an 8-unit shift-accumulator array. Real-time calculation; the window generation state machine dynamically adjusts the sleep window based on the differential value and the hysteresis flag (shortened to 85ms when the temperature accelerates), achieving a prediction accuracy of ±5ms, significantly better than traditional timed sleep strategies; the development of a dedicated PREDSLP instruction (encoded 0xF1A0_000X) enables direct writing of predicted values ​​into the sleep configuration register through a hardware address mapping table (register number to physical address conversion delay 2ns); a dual MOS transistor array (SI2301) physically powers down the instruction fetch / decode circuits, and combined with the hardware state encoder outputs a 2-bit gating signal ("11b" indicates dual circuit sleep).

[0311] The low power consumption control method of the controller in the embodiment of the present invention is described above. The low power consumption control system of the controller in the embodiment of the present invention is described below. Figure 2An embodiment of the low-power control system of the controller in the embodiment of the present invention includes: an acquisition module 201, which is used to collect the timing status data of the controlled object in real time and store it in a hardware queue register group; a sleep module 202, which is used to input the data in the hardware queue register group into a prediction collaborative calculation unit, which is composed of a digital logic circuit solidified in an integrated circuit and outputs a predicted sleep window value; a write module 203, which is used to execute the PREDSLP instruction in the processor instruction set and write the predicted sleep window value into the sleep configuration register; a gating module 204, which is used to generate a gated pipeline state signal through a dynamic instruction gating unit according to the value of the sleep configuration register; a recovery module 205, which is used to generate a control signal for a receiving module through a programmable timing generator based on the value of the sleep configuration register; and a distribution module 206, which is used to send an interrupt request to the CPU through an asynchronous wake-up circuit when the receiving module captures a valid instruction, restore the power supply of the instruction fetch circuit and the decoding circuit, and execute a control response.

[0312] In this embodiment of the present invention, a predictive collaborative computing unit outputs a predicted sleep window value, enabling accurate prediction of system sleep time based on the controlled object's sequential state data, avoiding unnecessary continuous operation and effectively reducing system power consumption. By utilizing digital logic circuits embedded in the integrated circuit to form the predictive collaborative computing unit and executing specific processor instruction set instructions (PREDSLP) to write to the sleep configuration register, some control logic is hardware-based, reducing complex software operations and computational overhead. Based on the sleep configuration register value, a dynamic instruction gating unit generates a gated pipeline state signal, enabling dynamic gating of the pipeline. This flexible control approach allows real-time adjustment of the pipeline's operating state based on the system's actual operating status, effectively reducing pipeline power consumption without impacting system functionality. A receiving module control signal is generated based on the sleep configuration register value. When the receiving module captures a valid instruction, an asynchronous wake-up circuit sends an interrupt request to the CPU, restoring power to the instruction fetch and decode circuits and executing a control response. This ensures timely system response when needed while preventing the system from remaining in a high-power active state for extended periods, achieving a good balance between power consumption and response speed.

[0313] The present invention also provides a low-power control device for a controller, which includes a memory and a processor. The memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor executes the steps of the low-power control method for the controller in the above-mentioned embodiments.

[0314] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions, which, when executed on a computer, cause the computer to execute the steps of the low-power control method of the controller.

[0315] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0316] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0317] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low power consumption control method for a controller, characterized in that: The low power consumption control method of the controller includes: Collect the time sequence status data of the controlled object in real time and store it in the hardware queue register group; Inputting the data in the hardware queue register group into a prediction collaborative computing unit, which is composed of a digital logic circuit embedded in an integrated circuit and outputs a predicted sleep window value; Executing a PREDSLP instruction in a processor instruction set to write the predicted sleep window value into a sleep configuration register; According to the value of the sleep configuration register, a gated pipeline state signal is generated by executing the dynamic instruction gating unit; Based on the value of the sleep configuration register, the programmable timing generator generates the control signals for the receiving module, including: The lower 8 bits of the sleep configuration register value are extracted through the shift register group to generate the sleep coefficient value; The system clock is divided into a 100ms period signal through a clock division circuit as a reference timing signal; The sleep coefficient value and the reference timing signal are input into the programmable counter to generate an extended sleep timing signal, which satisfies: ； When the sleep configuration register value is less than the safety threshold, the hardware timestamp aligner performs the following: Read the event occurrence time in the predicted event queue; Activate the wake-up circuit 10ms before the event occurs and generate a 10ms precise wake-up pulse; The extended sleep timing signal or the precise wake-up pulse is selected through a multiplexer circuit to generate the final receiving control signal; When the receiving module captures a valid instruction, it sends an interrupt request to the CPU through the asynchronous wake-up circuit, restores the power supply of the instruction fetch circuit and the decoding circuit, and executes the control response.

2. The low power consumption control method of the controller according to claim 1, characterized in that: include: Collect temperature, pressure, and displacement sensor data and generate channel-specific data packets; Inputting the channelized data packets into a threshold comparator circuit, removing data exceeding the physical range, and outputting a valid data queue; Synchronize the valid data queue from the sensor clock domain to the system clock domain to generate synchronization data packets; According to the real-time computing requirements of the predicted collaborative computing unit, the DMA controller writes the synchronization data packet into the specified storage partition of the hardware queue register group to generate a timing state data matrix.

3. The low power consumption control method of the controller according to claim 2, characterized in that: include: Extract the timing state data from the hardware queue register group through a parallel multiplexer and convert it into a fixed-point data stream; Inputting the fixed-point data stream into a shift-accumulator array, performing a differential operation of a preset fractional order α, and outputting a fractional-order differential value; Inputting the fractional-order difference value into a hysteresis loop parameter lookup table and outputting a hysteresis response flag; The fractional-order difference value and the hysteresis response flag are fused through the window generation state machine to generate the predicted sleep window value.

4. The low power consumption control method of the controller according to claim 3, characterized in that: include: The instruction decoder circuit identifies the PREDSLP operation code and generates a register operation enable signal; According to the register number field, the address mapping table circuit converts the address into the physical storage address of the sleep configuration register; Load the predicted sleep window value into the data bus channel, write it into the target physical storage address under the control of the register operation enable signal, and generate a register write completion flag; According to the register write completion flag, the system is switched from the running state to the predicted sleep state through the power state controller.

5. The low power consumption control method of the controller according to claim 4, characterized in that: include: The voltage comparator circuit compares the sleep configuration register value with the preset threshold voltage in real time to generate a power supply control signal; When the power supply control signal is at a high level, the first MOS transistor array is controlled to physically disconnect the power supply path of the instruction fetch circuit, thereby generating a dormant state of the instruction fetch circuit; When the power supply control signal is at a high level, the second MOS transistor array is controlled to physically disconnect the power supply path of the decoding circuit, thereby generating a dormant state for the decoding circuit; The hardware state encoder fuses the sleep state of the instruction fetch circuit and the sleep state of the decoding circuit to output a 2-bit gated pipeline state signal.

6. The low power consumption control method of the controller according to claim 5, characterized in that: include: The baseband processor of the receiving module performs a cyclic redundancy check circuit verification on the received data packet and generates a valid instruction flag signal; Input the valid instruction flag signal into the edge detection circuit to generate a wake-up trigger pulse; The wake-up trigger pulse drives the power gate driver, outputting the power supply enable signal of the instruction fetch circuit and the power supply enable signal of the decoding circuit; When the power is restored, the interrupt controller hardware generates a non-maskable interrupt vector number and writes it into the interrupt vector register. Transferring valid instructions from the receive buffer to the executor control register via the direct memory access channel to generate a copy of the instruction to be executed; After the power supply to the instruction fetch circuit is restored, the CPU reads the vector number from the interrupt vector register, jumps to the hard-coded interrupt service routine, reads the copy of the instruction to be executed in the executor control register, and outputs a control response signal.

7. A low power consumption control system of a controller, characterized in that: The low power consumption control system of the controller includes: The acquisition module is used to collect the time sequence state data of the controlled object in real time and store it in the hardware queue register group; A sleep module, configured to input the data in the hardware queue register group into a prediction collaborative computing unit, which is composed of a digital logic circuit embedded in an integrated circuit and outputs a predicted sleep window value; A writing module, configured to execute a PREDSLP instruction in a processor instruction set to write the predicted sleep window value into a sleep configuration register; A gating module, configured to generate a gating pipeline state signal by executing a dynamic instruction gating unit according to the value of the sleep configuration register; The recovery module is used to generate the control signal of the receiving module through the programmable timing generator based on the value of the sleep configuration register, including: The lower 8 bits of the sleep configuration register value are extracted through the shift register group to generate the sleep coefficient value; The system clock is divided into a 100ms period signal through a clock division circuit as a reference timing signal; The sleep coefficient value and the reference timing signal are input into the programmable counter to generate an extended sleep timing signal, which satisfies: ； When the sleep configuration register value is less than the safety threshold, the hardware timestamp aligner performs the following: Read the event occurrence time in the predicted event queue; Activate the wake-up circuit 10ms before the event occurs and generate a 10ms precise wake-up pulse; The extended sleep timing signal or the precise wake-up pulse is selected through a multiplexer circuit to generate the final receiving control signal; The distribution module is used to send an interrupt request to the CPU through the asynchronous wake-up circuit when the receiving module captures a valid instruction, restore the power supply of the instruction fetch circuit and the decoding circuit, and execute the control response.

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