Vector optimization algorithm translation method and device oriented to RISC-V vector extension platform

Abstract

The invention provides a vector optimization algorithm translation method and device oriented to an RISC-V vector extension platform, and relates to the technical field of computer software cross-architecture translations. The method comprises the steps that source codes of vector optimization algorithms written by other platforms and translation cues are input into a large language model; outputting a translation code of a vector optimization algorithm oriented to the RISC-V vector extension platform; the translated codes are input into a compiler to be compiled; under the condition that compiling succeeds, a compiling product is linked to the test suite to obtain an executable program, and unit testing is conducted on the executable program on the RISC-V vector extension device; and under the condition that the unit test is passed, determining that the translation code is a first version of correct translation code of a vector optimization algorithm oriented to the RISC-V vector extension platform. According to the method, a vector optimization algorithm written by using a special vector language for other platforms is efficiently translated to the RISC-V vector extension platform.

Description

Technical Field

[0001] The present invention relates to the technical field of computer software cross-architecture translation, and particularly to a method and device for translating vector optimization algorithms for RISC-V vector extension platforms. Background Art

[0002] Translating vector optimization algorithms written in their dedicated vector languages in existing high-performance algorithm libraries to the RISC-V vector extension platform is a key path for building a high-performance RISC-V software ecosystem.

[0003] Currently, cross-architecture code translation mainly adopts a direct instruction mapping scheme. Direct instruction mapping means that by establishing a mapping relationship between instructions in different hardware dedicated vector languages, the dedicated vector language of other platforms is translated into the dedicated vector language of RISC-V vector extension during compilation, so that algorithms optimized for other platforms can be automatically translated to the RISC-V vector extension platform.

[0004] However, cross-platform instruction mapping schemes usually rely on developers to maintain mapping rules, and the instruction scales of each platform are huge, which leads to shortcomings in the coverage of vector instruction operations in existing cross-platform instruction mapping schemes. For example, the neon2rvv library only supports 60% (2627 / 4369) of neon instructions to be mapped to RISC-V vector extension instructions, resulting in inefficient translation. Summary of the Invention

[0005] The present invention provides a method and device for translating vector optimization algorithms for RISC-V vector extension platforms to solve the problem of how to efficiently translate vector optimization algorithms written in the dedicated vector languages of other platforms to the RISC-V vector extension platform.

[0006] The present invention provides a method for translating vector optimization algorithms for RISC-V vector extension platforms, including the following steps: Input the source code of the vector optimization algorithm written in the dedicated vector programming language of other platforms and translation prompts for the RISC-V vector extension platform into a large language model, and output the translation code of the vector optimization algorithm for the RISC-V vector extension platform; Input the translation code into a compiler for compilation for the RISC-V vector extension platform; In the case of successful compilation, obtain the compilation product output by the compiler, link the compilation product to a test suite to obtain an executable program, and perform unit tests on the executable program on a RISC-V vector extension device; When the unit test passes, it is determined that the translated code is the correct first version of the vector optimization algorithm for the RISC-V vector extension platform.

[0007] In some embodiments, inputting the source code of the vector optimization algorithm written in other platform-specific vector programming languages and the translation prompt words for the RISC-V vector extension platform into the large language model to output the translated code of the vector optimization algorithm for the RISC-V vector extension platform includes: Based on the source code and the translation prompt words, the large language model uses retrieval-augmented generation technology to query and retrieve in the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database, and outputs the translated code of the vector optimization algorithm for the RISC-V vector extension platform.

[0008] In some embodiments, the method further includes: Performing a performance test on the correct first version of the translated code on a RISC-V vector extension device to obtain the performance data of the correct first version of the translated code; Inputting the optimization prompt words including register usage information, the performance data, and the correct first version of the translated code into the large language model, and the large language model performs N iterations of optimization on the correct first version of the translated code according to the performance data and the register usage information to obtain N versions of the correct translated code; N is a positive integer; Selecting the final correct translated code of the vector optimization algorithm from the correct first version of the translated code and the N versions of the correct translated code.

[0009] In some embodiments, the method further includes: When the compilation fails, obtaining the compilation error information output by the compiler; Inputting the first correction prompt words including the compilation error information into the large language model, and the large language model corrects the translated code according to the compilation error information.

[0010] In some embodiments, the method further includes: When the unit test fails, obtaining the test error information; Inputting the second correction prompt words including the test error information into the large language model, and the large language model corrects the translated code according to the test error information.

[0011] In some embodiments, the method further includes: According to the RISC-V Vector Extension Specification Document and the RISC-V Vector Intrinsics Document, the RISC-V vector instruction knowledge base is constructed in a block-by-block manner.

[0012] The present invention also provides a vector optimization algorithm translation device for a RISC-V vector extension platform, including the following modules: A processing module, configured to input the source code of a vector optimization algorithm written in a vector programming language specific to other platforms and translation prompts for the RISC-V vector extension platform into a large language model, and output translation code of the vector optimization algorithm for the RISC-V vector extension platform; A compilation module, configured to input the translation code into a compiler for compilation for the RISC-V vector extension platform; A testing module, configured to, in the case of successful compilation, obtain the compilation product output by the compiler, link the compilation product to a test suite to obtain an executable program, and perform unit testing on the executable program on a RISC-V vector extension device; A determination module, configured to, in the case of passing the unit test, determine that the translation code is the first version of the correct translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the method for translating a vector optimization algorithm for a RISC-V vector extension platform as described in any one of the above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method for translating a vector optimization algorithm for a RISC-V vector extension platform as described in any one of the above is implemented.

[0015] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, the method for translating a vector optimization algorithm for a RISC-V vector extension platform as described in any one of the above is implemented.

[0016] The method and device for translating a vector optimization algorithm for a RISC-V vector extension platform provided by the present invention replace the mapping rules with a large language model, are superior to traditional translation schemes based on mapping rules in terms of the quality and performance of the generated vector code, and do not require manual translation by domain experts, significantly reducing the difficulty and workload of translating a large-scale algorithm library to the RISC-V vector extension platform, and realizing the efficient translation of a vector optimization algorithm written in a vector language specific to other platforms to the RISC-V vector extension platform. Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is one of the schematic flowcharts of the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention.

[0019] Figure 2 It is the second schematic flowchart of the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention.

[0020] Figure 3 It is the schematic structural diagram of the vector optimization algorithm translation device for the RISC-V vector extension platform provided by the present invention.

[0021] Figure 4 It is the schematic structural diagram of the electronic device provided by the present invention. Detailed implementation manners

[0022] Vector hardware is a processor component that achieves efficient parallel computing through the Single Instruction Multiple Data (SIMD) architecture. Its core design goal is to perform the same operation on multiple data elements through one instruction, thereby significantly improving the processing ability of compute-intensive tasks. As the programming interface of such hardware, vector instructions allow software to optimize performance using the acceleration capabilities of vector hardware. This parallel optimization mode is particularly suitable for fields such as scientific computing, signal processing, machine learning, and graphics rendering. Its advantages lie in reducing the number of instruction decoding times, optimizing sequential memory access, and improving cache utilization, and it has become a key technology for modern high-performance computing.

[0023] At the high-level language level, there are mainly three types of methods for optimizing software performance using vector instructions: directly writing algorithms in a high-level language and relying on the compiler to automatically vectorize and generate vector instructions; writing optimization algorithms using the general vector language of vector hardware; writing optimization algorithms using the dedicated vector language of specific hardware.

[0024] High-level Languages and Auto-vectorization: Developers write algorithms in high-level languages and rely on the auto-vectorization function of the compiler to convert scalar code into vector instructions. This method has the widest range of applications. Developers only need to focus on the algorithm logic without having to understand the underlying hardware details. However, the implementation of the computational load cannot be optimally mapped to hardware instructions, making it difficult to fully utilize hardware resources to achieve the best performance.

[0025] General-purpose Vector Languages: Through cross-platform vector programming libraries (such as Google Highway, the C++ standard library std::simd), developers directly write vectorized algorithm logic using abstract vector types and operations. The cross-platform vector programming library adapts to different hardware instruction sets during compilation and generates corresponding vector instructions. This method avoids direct binding to specific hardware instruction sets and at the same time provides stronger optimization capabilities than compiler auto-vectorization. However, the vector operation semantics abstracted for general computing needs are not fully suitable for the computing needs of specific domains, and the performance advantages of special hardware cannot be fully exploited.

[0026] Special-purpose Vector Languages: Through vector built-in functions provided by hardware manufacturers (such as AVX Intrinsics for x86, NEON Intrinsics for ARM, RISC-V Vector Intrinsics), developers directly write vectorized algorithm logic using the vector built-in functions of the target hardware. This method has the best optimization effect. However, compared with high-level languages and general-purpose vector languages, the special-purpose vector built-in functions of each platform are not compatible with each other, and algorithm optimization needs to be implemented separately for different platforms.

[0027] In the current software ecosystem, hardware-specific special-purpose vector languages have been widely used for low-level optimizations in fields such as high-performance computing, multimedia processing, and AI inference. For example, high-performance algorithm libraries such as FFmpeg and OpenCV deeply rely on such optimizations, and their support for mainstream instruction set architectures such as ARM Neon and x86 SSE / AVX has been quite mature. However, the adaptation progress of the RISC-V vector extension (RISC-V Vector) still lags significantly behind that of x86 / ARM: on the one hand, the RISC-V software ecosystem started relatively late and the number of developers is limited; on the other hand, the open-source and extensible characteristics of the RISC-V instruction set architecture also increase the difficulty of software development, adaptation, and optimization.

[0028] Translating the vector optimization algorithms written in its special-purpose vector language in existing high-performance algorithm libraries to the RISC-V vector extension platform is the key path to building a high-performance RISC-V software ecosystem.

[0029] Currently, cross-architecture code translation mainly adopts the direct instruction mapping scheme. Direct instruction mapping means that by establishing the mapping relationship of instructions in different hardware-specific vector languages, the specific vector language of other platforms is translated into the specific vector language of the RISC-V vector extension during compilation, so that the algorithms optimized for other platforms can be automatically translated to the RISC-V vector extension platform. For example, neon2rvv and sse2rvv use the specific vector language of the RISC-V vector extension in the form of c++ header files to describe the vector instructions in the ARM Neon and Intel SSE specific vector languages respectively. When the algorithms optimized for the above hardware platforms are compiled together with the corresponding header files (neon2rvv / sse2rvv), RISC-V vector extension instructions can be generated to optimize performance.

[0030] The defects of the prior art are mainly reflected in two aspects: function and performance. (1) In terms of function The instructions that the existing solutions can map are limited: Cross-platform instruction mapping solutions usually rely on developers to maintain mapping rules, and the instruction scales of each platform are huge, which leads to short boards in the coverage of vector instruction operations in the existing cross-platform instruction mapping solutions. For example, the neon2rvv library only supports 60% (2627 / 4369) of the neon instructions to be mapped to RISC-V vector extension instructions.

[0031] The existing solutions have defects in the compatibility of the vector type system: The variable-length vector types of the RISC-V vector extension are usually restricted due to the design of high-level languages and compilers during use. For example, member variables of variable-length vector types cannot be declared in classes or structures. This is incompatible with the encapsulation and usage methods of vector types in the existing algorithm libraries, and the existing mapping solutions cannot solve the compatibility problem of the vector type system.

[0032] (2) In terms of performance The existing solutions cannot make full use of the RISC-V vector extension features: The semantic gap caused by architectural differences. The RISC-V vector extension uses dynamic-length vector registers (128 bit~65536 bit) and supports the register grouping function, which is significantly different from the fixed-length vector registers used by Neon / SSE. The existing solutions only use the mapping scheme with a fixed length (128 / 256bit) and do not consider the differences in the available vector register numbers between different platforms, resulting in their inability to make full use of the vector register resources of the RISC-V vector extension and causing waste of computing power; The existing solutions directly map the fixed-length vector programming model to the variable-length RISC-V vector extension, failing to make full use of the features of the RISC-V vector extension programming model such as vector configuration instructions (such as setvl), resulting in performance loss.

[0033] Existing solutions introduce additional overhead: differences in the coverage of instruction functions. A single instruction on other platforms may not have a direct mapped instruction in the RISC-V vector extension and needs to be implemented using a combination of multiple RISC-V vector extension instructions. For example, the vector shuffle instruction in SSE / Neon needs to be disassembled into a combination of vrgather and vslide in the RISC-V vector extension, which will additionally increase the number of instructions and lead to performance degradation. Moreover, the mapping scheme is at a relatively low level and may miss optimization opportunities. For example, the unique strided load (vlseg / vsseg) and indexed load (vluxei) instructions in the RISC-V vector extension can optimize irregular data access, but there are no related operations on other platforms. The code generated by the mapping scheme still follows the continuous memory access mode of the source platform, missing the deep optimization opportunities that require platform adaptation from the initial stage of algorithm design, resulting in unnecessary performance overhead.

[0034] To address the above problems, the present invention provides a method for translating vector optimization algorithms for the RISC-V vector extension platform. It uses a large language model to replace the mapping rules, analyzes the semantics of the code on other platforms using the large language model to obtain the algorithm-level semantics, and uses the large language model to generate translation code for the RISC-V vector extension platform, realizing the translation of RISC-V vector extension code based on the large language model.

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0036] Figure 1 It is one of the flow schematic diagrams of the method for translating vector optimization algorithms for the RISC-V vector extension platform provided by the present invention. As Figure 1 shown, the present invention provides a method for translating vector optimization algorithms for the RISC-V vector extension platform, including the following steps: Step 110, input the source code of the vector optimization algorithm written in a vector programming language specific to other platforms and the translation prompt words for the RISC-V vector extension platform into the large language model, and output the translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0037] Specifically, large language models (LLMs) have the ability to understand semantics at the algorithm level and perceive context. Therefore, LLMs are used to build code translation agents to replace the mapping rule-based or manual translation solutions.

[0038] The source code of a vector optimization algorithm written in another platform-specific vector programming language and translation prompts for the RISC-V vector extension platform are input into the large language model. The translation prompts include code translation tasks for the RISC-V vector extension platform. The large language model translates the source code according to the code translation tasks, that is, analyzes the original vector operation semantics and algorithm functions based on the source code information, and outputs the translated code of the vector optimization algorithm for the RISC-V vector extension platform.

[0039] In some embodiments, to help the large language model make full use of the features of the RISC-V vector extension architecture and thus improve the performance of the translated vector optimization code for the RISC-V vector extension platform, the large language model is used to analyze the data length in a specific loop structure, and translation prompts are used to guide the large language model to automatically insert instructions related to dynamic vector length control.

[0040] Step 120: Input the translated code into a compiler for compilation for the RISC-V vector extension platform.

[0041] Specifically, an RISC-V cross-compilation toolchain is built. The toolchain includes a compiler, an assembler, a linker, and a standard library, and is used to check the syntactic correctness of the algorithm implementation and generate an executable program. The translated code is input into the compiler for compilation for the RISC-V vector extension platform.

[0042] Step 130: In the case of successful compilation, obtain the compilation product output by the compiler, link the compilation product to a test suite to obtain an executable program, and perform unit tests on the executable program on the RISC-V vector extension device.

[0043] Specifically, a test suite for evaluating the functional correctness and performance of the translated code is written. The specific process can be as follows: Retrieve the built-in (Intrinsic) functions of other platforms and the RISC-V vector extension platform on an open-source code hosting platform to obtain an open-source algorithm library with existing vector optimizations. Extract the vector optimization code for different platforms and their corresponding test codes from it to form a test case set, and use a test framework (such as Google Test) to compile the test case set into a test suite for unit testing and performance testing.

[0044] In the case of successful compilation, the compilation product output by the compiler is obtained. The compilation product is linked to the test suite to obtain an executable program, and unit tests are performed on the executable program on the RISC-V vector extension device to evaluate the functional correctness of the translated code.

[0045] Step 140, in the case where the unit test passes, it is determined that the translated code is the first version of the correct translated code for the vector optimization algorithm for the RISC-V vector extension platform.

[0046] Specifically, in the case where the unit test passes, it is considered that the translated code output by the large language model is the first version of the correct translated code for the vector optimization algorithm for the RISC-V vector extension platform.

[0047] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention uses a large language model instead of a mapping rule, which is superior to the traditional mapping rule-based translation scheme in terms of the quality and performance of the generated vector code, and does not require manual translation by domain experts, significantly reducing the difficulty and workload of translating a large-scale algorithm library to the RISC-V vector extension platform, and realizing the efficient translation of vector optimization algorithms written in other platform-specific vector languages to the RISC-V vector extension platform.

[0048] In some embodiments, the source code of the vector optimization algorithm written in other platform-specific vector programming languages and the translation prompt words for the RISC-V vector extension platform are input into the large language model, and the translation code of the vector optimization algorithm for the RISC-V vector extension platform is output, including: According to the source code and the translation prompt words, the large language model uses the retrieval-augmented generation technology to query and retrieve in the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database, and outputs the translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0049] Specifically, according to the RISC-V vector extension specification (Specification) document and the RISC-V vector intrinsic (Intrinsic) document, a RISC-V vector instruction knowledge base is constructed. Among them, the RISC-V vector extension specification defines vector operations and their functions. The RISC-V vector intrinsic document defines the call format of the RISC-V vector extension-specific language (vector types and operations) at the high-level language level.

[0050] The overhead (the number of clock cycles required to execute the instruction) of the vector extension instruction is obtained according to the processor hardware manual or measured by a benchmark test used in the hardware device, and the RISC-V vector instruction overhead database is constructed accordingly.

[0051] The large language model queries and retrieves in the RISC-V vector instruction knowledge base using retrieval-augmented generation technology according to the source code and translation prompts, learns the vector operation functions and call formats in the RISC-V vector instruction knowledge base, effectively makes up for the lack of knowledge of the RISC-V vector extension instruction set in the large language model, solves the limitation problem of the mapping scheme relying on manual instruction coverage, and guides the large model to fully understand and use the special operations of the RISC-V vector extension platform, thereby improving the accuracy of generating the dedicated language for the RISC-V vector extension platform.

[0052] The large language model queries and retrieves in the RISC-V vector instruction overhead database using retrieval-augmented generation technology according to the source code and translation prompts, obtains the overhead of specific instructions for the large language model to refer to, guides the large language model to use instruction combinations with lower overhead to meet the requirements of the vectorization algorithm, thereby optimizing the performance of the vectorization algorithm.

[0053] In some embodiments, to help the large language model learn and understand the RISC-V vector extension programming model and improve the code translation quality, combined with excellent cases of RISC-V vector extensions in the open source community, specific programming paradigms for RISC-V vector extensions are provided for the large language model.

[0054] Since the large language model has limitations on the length of the input and the length of the translation prompts should not be too long, therefore, a small number of specific programming paradigms for RISC-V vector extensions are provided to the large language model through the translation prompts, and a large number of specific programming paradigms for RISC-V vector extensions are provided to the large language model through the RISC-V vector instruction knowledge base.

[0055] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention provides RISC-V vector extension vector instruction information for the large language model through the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database, helps it select appropriate instructions, improves the correctness and performance of code translation, reduces the LLM call overhead, and avoids the hallucination problem that may occur in the LLM.

[0056] In some embodiments, the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention further includes: Construct the RISC-V vector instruction knowledge base in a block-by-block manner according to the RISC-V vector extension specification document and the RISC-V vector built-in document.

[0057] Specifically, since the RISC-V vector extension specification document and the RISC-V vector built-in document are relatively large in length, the RISC-V vector instruction knowledge base is constructed in a block-by-block manner. The specific construction process is as follows: First, split the RISC-V vector extension specification document into sections according to different functions (such as memory access / logical operations / arithmetic operations, etc.). Then, select the corresponding built-in functions in the RISC-V vector built-in document according to the instructions included in the section and add them to the section. Finally, encode each section into a vector using a pre-trained model and store it in the database in units of sections, so as to obtain the RISC-V vector instruction knowledge base. The RISC-V vector instruction knowledge base allows the large language model to retrieve the instruction operations in the document and their corresponding built-in function calls in the way of keyword matching.

[0058] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention is stored classified according to different functions, making the structure of the RISC-V vector instruction knowledge base clear, facilitating quick positioning of target instructions, and reducing interference from irrelevant information. Directly associate the instruction descriptions in the specification document with the corresponding built-in functions to form a complete mapping, avoiding manual cross-querying between documents by developers and improving the usage efficiency.

[0059] In some embodiments, the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention further includes: In the case of compilation failure, obtain the compilation error information output by the compiler; Input the first correction prompt word including the compilation error information into the large language model, and the large language model corrects the translation code according to the compilation error information.

[0060] Specifically, compile the translation code generated by the large language model, introduce a compilation information feedback mechanism, obtain the compilation error information output by the compiler in the case of compilation failure, feedback the compilation error information to the large language model through the first correction prompt word, and the large language model corrects the translation code according to the compilation error information, so as to generate a new translation code.

[0061] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention, in the case of compilation failure, feeds back the compilation error information to the large language model, and the large language model corrects the translation code according to the compilation error information, providing timely correctness feedback to the large language model, thereby improving the correctness of subsequent translation codes.

[0062] In some embodiments, the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention further includes: In the case of unit test failure, obtain the test error information; Input the second correction prompt word including the test error information into the large language model, and the large language model corrects the translation code according to the test error information.

[0063] Specifically, unit tests are performed on the executable program on the RISC-V vector extension device, a test information feedback mechanism is introduced, test error information is obtained when the unit test fails, and the test error information is fed back to the large language model through the second correction prompt word. The large language model corrects the translated code according to the test error information, thereby generating new translated code.

[0064] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention, when the unit test fails, by feeding back the test error information to the large language model, the large language model corrects the translated code according to the test error information, providing timely correctness feedback to the large language model, thereby improving the correctness of the subsequent translated code.

[0065] In some embodiments, the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention further includes: Performing a performance test on the first version of the correctly translated code on the RISC-V vector extension device to obtain the performance data of the first version of the correctly translated code; Inputting the optimization prompt word including register usage information, the performance data, and the first version of the correctly translated code into the large language model, and the large language model performs N iterations of optimization on the first version of the correctly translated code according to the performance data and the register usage information to obtain N versions of the correctly translated code; N is a positive integer; Selecting the final correctly translated code of the vector optimization algorithm from the first version of the correctly translated code and the N versions of the correctly translated code.

[0066] Specifically, enable the test suite on the RISC-V vector extension device to perform a performance test on the first version of the correctly translated code to obtain the performance data of the first version of the correctly translated code. Combine compilation technology to statically analyze the register usage of the core code to obtain the register usage information.

[0067] Input the optimization prompt word including register usage information, the performance data of the first version of the correctly translated code, and the first version of the correctly translated code into the large language model, and the large language model optimizes the first version of the correctly translated code according to the performance data of the first version of the correctly translated code and the register usage information to obtain the second version of the correctly translated code.

[0068] Enable the test suite on the RISC-V vector extension device to perform performance testing on the correctly translated code of the second version, and obtain the performance data of the correctly translated code of the second version. Input the optimization prompt words including register usage information, the performance data of the correctly translated code of the second version, and the correctly translated code of the second version into the large language model. The large language model optimizes the correctly translated code of the second version based on the performance data of the correctly translated code of the second version and the register usage information to obtain the correctly translated code of the third version.

[0069] And so on, perform N iterative optimizations in total to obtain N versions of correctly translated code.

[0070] From the correctly translated code of the first version and the N versions of correctly translated code, that is, the N + 1 versions of correctly translated code, screen out the finally correctly translated code of the vector optimization algorithm to complete the tasks of code translation and optimization. For example, use the version with the best performance as the finally correctly translated code.

[0071] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention provides the register usage information to the large language model through optimization prompt words, guides the large language model through mechanisms such as loop unrolling / register grouping, helps the large language model make full use of the characteristics of the RISC-V vector extension architecture, thereby improving the performance of the vector optimization code on the translated RISC-V vector extension platform; introduces a performance feedback mechanism, feeds back the performance data of the correctly translated code to the large language model, provides timely performance feedback to the large language model, and iteratively improves the optimization effect.

[0072] Figure 2 It is the second schematic diagram of the process of the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention. As Figure 2 shown, the present invention provides a vector optimization algorithm translation method for the RISC-V vector extension platform, including the following steps: Step 201, input the source code written in other platform-specific vector programming languages and the translation prompt words for the RISC-V vector extension platform into the large model. At this time, the large language model analyzes the original vector operation semantics and algorithm functions according to the source code information.

[0073] Step 202, select appropriate RISC-V vector extension vector operations by querying and retrieving the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database in multiple rounds.

[0074] Step 203, output the translation code of the vector optimization algorithm for the RISC-V vector extension platform and save it to a file.

[0075] Step 204: Input the translation code into the compiler for compilation targeting the RISC-V vector extension platform. If the compilation fails, execute Step 205; if the compilation succeeds, execute Step 206.

[0076] Step 205: Obtain the compilation error information output by the compiler. Input the first correction prompt word including the compilation error information into the large language model, and the large language model corrects the translation code according to the compilation error information.

[0077] Step 206: Obtain the compilation product output by the compiler, link the compilation product to the test suite to obtain an executable program, and perform unit tests on the executable program on the RISC-V vector extension device to evaluate the functional correctness of the translation code. If the unit test fails, execute Step 207; if the unit test passes, determine that the translation code is the first version of the correct translation code of the vector optimization algorithm for the RISC-V vector extension platform, and execute Step 208.

[0078] Step 207: Obtain the test error information. Input the second correction prompt word including the test error information into the large language model, and the large language model corrects the translation code according to the test error information.

[0079] Step 208: Perform a performance test on the first version of the correct translation code on the RISC-V vector extension device to obtain the performance data of the first version of the correct translation code.

[0080] Step 209: Input the optimization prompt word including register usage information, the performance data of the first version of the correct translation code, and the first version of the correct translation code into the large language model. The large language model performs N iterations of optimization on the first version of the correct translation code according to the performance data of the first version of the correct translation code and the register usage information to obtain N versions of the correct translation code.

[0081] Step 210: Select the correct translation code with the best performance from the first version of the correct translation code and the N versions of the correct translation code as the final correct translation code of the vector optimization algorithm.

[0082] The vector optimization algorithm translation device for the RISC-V vector extension platform provided by the present invention will be described below. The vector optimization algorithm translation device for the RISC-V vector extension platform described below can be correspondingly referred to the vector optimization algorithm translation method for the RISC-V vector extension platform described above.

[0083] Figure 3 It is a schematic structural diagram of the vector optimization algorithm translation device for the RISC-V vector extension platform provided by the present invention, as Figure 3As shown in the figure, the present invention provides a vector optimization algorithm translation device for a RISC-V vector extension platform, including the following modules: A processing module 310, configured to input the source code of a vector optimization algorithm written in a vector programming language specific to other platforms, as well as translation prompt words for the RISC-V vector extension platform, into a large language model, and output translation code of the vector optimization algorithm for the RISC-V vector extension platform; A compilation module 320, configured to input the translation code into a compiler for compilation for the RISC-V vector extension platform; A testing module 330, configured to, when the compilation is successful, obtain the compilation product output by the compiler, link the compilation product to a test suite to obtain an executable program, and perform unit testing on the executable program on a RISC-V vector extension device; A determination module 340, configured to, when the unit test passes, determine that the translation code is the first version of the correct translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0084] In some embodiments, the processing module 310 is specifically configured to: According to the source code and the translation prompt words, the large language model uses retrieval-augmented generation technology to query and retrieve in a RISC-V vector instruction knowledge base and a RISC-V vector instruction overhead database, and output translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0085] In some embodiments, the device further includes an iterative optimization module, and the iterative optimization module is configured to: Perform a performance test on the first version of the correct translation code on a RISC-V vector extension device to obtain performance data of the first version of the correct translation code; Input an optimization prompt word including register usage information, the performance data, and the first version of the correct translation code into the large language model, and the large language model performs N iterations of optimization on the first version of the correct translation code according to the performance data and the register usage information to obtain N versions of the correct translation code; N is a positive integer; Screen out the final correct translation code of the vector optimization algorithm from the first version of the correct translation code and the N versions of the correct translation code.

[0086] In some embodiments, the device further includes a first correction module, and the first correction module is configured to: When the compilation fails, obtain the compilation error information output by the compiler; Input the first correction prompt word including the compilation error message into the large language model, and the large language model corrects the translated code according to the compilation error message.

[0087] In some embodiments, the device further includes a second correction module, and the second correction module is configured to: Obtain test error information when the unit test fails; Input the second correction prompt word including the test error information into the large language model, and the large language model corrects the translated code according to the test error information.

[0088] In some embodiments, the device further includes a construction module, and the construction module is configured to: Construct the RISC-V vector instruction knowledge base in a block-by-block manner according to the RISC-V vector extension specification document and the RISC-V vector built-in document.

[0089] It should be noted here that the vector optimization algorithm translation device for the RISC-V vector extension platform provided by the present invention can implement all the method steps implemented in the above method embodiments, and can achieve the same technical effects. The same parts and beneficial effects as those in the method embodiments will not be specifically described in this embodiment.

[0090] Figure 4 is a schematic structural diagram of an electronic device provided by the present invention. As Figure 4 shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430, and a communication bus 440. Among them, the processor 410, the communication interface 420, and the memory 430 communicate with each other through the communication bus 440. The processor 410 can call the logical instructions in the memory 430 to execute the vector optimization algorithm translation method for the RISC-V vector extension platform. The method includes: inputting the source code of the vector optimization algorithm written in a vector programming language dedicated to other platforms and the translation prompt word for the RISC-V vector extension platform into the large language model, and outputting the translated code of the vector optimization algorithm for the RISC-V vector extension platform; inputting the translated code into a compiler for compilation for the RISC-V vector extension platform; in the case of successful compilation, obtaining the compilation product output by the compiler, linking the compilation product to a test suite to obtain an executable program, and performing unit tests on the executable program on the RISC-V vector extension device; in the case of passing the unit test, determining that the translated code is the first correct translated code of the vector optimization algorithm for the RISC-V vector extension platform.

[0091] In addition, when the logical instructions in the above-mentioned memory 430 can be implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0092] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the above-mentioned various methods. The method includes: inputting the source code of the vector optimization algorithm written in a vector programming language specific to other platforms and the translation prompt words for the RISC-V vector extension platform into a large language model, and outputting the translation code of the vector optimization algorithm for the RISC-V vector extension platform; inputting the translation code into a compiler for compilation for the RISC-V vector extension platform; in the case of successful compilation, obtaining the compilation product output by the compiler, linking the compilation product to a test suite to obtain an executable program, and performing unit tests on the executable program on a RISC-V vector extension device; in the case of passing the unit tests, determining that the translation code is the first version of the correct translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0093] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a vector optimization algorithm translation method for a RISC-V vector extension platform provided by the above-mentioned various methods. The method includes: inputting the source code of the vector optimization algorithm written in a dedicated vector programming language of other platforms and translation prompt words for the RISC-V vector extension platform into a large language model, and outputting the translation code of the vector optimization algorithm for the RISC-V vector extension platform; inputting the translation code into a compiler for compilation for the RISC-V vector extension platform; in the case of successful compilation, obtaining the compilation product output by the compiler, linking the compilation product to a test suite to obtain an executable program, and performing unit tests on the executable program on a RISC-V vector extension device; in the case of passing the unit tests, determining that the translation code is the first correct translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0094] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0095] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for translating vector optimization algorithms for RISC-V vector extension platforms, characterized in that Including: Input the source code of the vector optimization algorithm written in another platform-specific vector programming language and the translation prompt words for the RISC-V vector extension platform into the large language model, and output the translated code of the vector optimization algorithm for the RISC-V vector extension platform; Input the translated code into a compiler for compilation for the RISC-V vector extension platform; In the case of successful compilation, obtain the compilation product output by the compiler, link the compilation product to a test suite to obtain an executable program, and perform unit testing on the executable program on the RISC-V vector extension device; In the case of passing the unit test, determine that the translated code is the first version of the correct translated code of the vector optimization algorithm for the RISC-V vector extension platform.

2. The method for translating a vector optimization algorithm for a RISC-V vector extension platform according to claim 1, wherein The inputting the source code of the vector optimization algorithm written in another platform-specific vector programming language and the translation prompt words for the RISC-V vector extension platform into the large language model, and outputting the translated code of the vector optimization algorithm for the RISC-V vector extension platform includes: According to the source code and the translation prompt words, the large language model uses retrieval-augmented generation technology to query and retrieve in the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database, and outputs the translated code of the vector optimization algorithm for the RISC-V vector extension platform.

3. The method for translating a vector optimization algorithm for a RISC-V vector extension platform according to claim 1, characterized in that The method further includes: Perform a performance test on the first version of the correct translated code on the RISC-V vector extension device to obtain the performance data of the first version of the correct translated code; Input the optimization prompt words including register usage information, the performance data, and the first version of the correct translated code into the large language model, and the large language model performs N iterations of optimization on the first version of the correct translated code according to the performance data and the register usage information to obtain N versions of the correct translated code; N is a positive integer; Select the final correct translated code of the vector optimization algorithm from the first version of the correct translated code and the N versions of the correct translated code.

4. The vector optimization algorithm translation method for the RISC-V vector extension platform according to claim 1, characterized in that The method further includes: In the case of compilation failure, obtain the compilation error information output by the compiler; Input the first correction prompt words including the compilation error information into the large language model, and the large language model corrects the translated code according to the compilation error information.

5. The method for translating a vector optimization algorithm for a RISC-V vector extension platform according to claim 1, characterized in that The method further includes: In the case of the unit test not passing, obtain the test error information; Input the second correction prompt words including the test error information into the large language model, and the large language model corrects the translated code according to the test error information.

6. The method for translating a vector optimization algorithm for a RISC-V vector extension platform according to claim 2, characterized in that The method further includes: Construct the RISC-V vector instruction knowledge base in a block manner according to the RISC-V vector extension specification document and the RISC-V vector built-in document.

7. A vector optimization algorithm translation device for the RISC-V vector extension platform, characterized in that, Including: A processing module, configured to input the source code of a vector optimization algorithm written in a vector programming language specific to other platforms and translation prompts for the RISC-V vector extension platform into a large language model, and output translated code of the vector optimization algorithm for the RISC-V vector extension platform; A compilation module, configured to input the translated code into a compiler for compilation for the RISC-V vector extension platform; A testing module, configured to, when the compilation is successful, obtain the compilation product output by the compiler, link the compilation product to a test suite to obtain an executable program, and perform unit testing on the executable program on a RISC-V vector extension device; A determination module, configured to, when the unit testing passes, determine that the translated code is the first version of the correct translated code of the vector optimization algorithm for the RISC-V vector extension platform.

8. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the vector optimization algorithm translation method for the RISC-V vector extension platform according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the vector optimization algorithm translation method for the RISC-V vector extension platform according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the vector optimization algorithm translation method for the RISC-V vector extension platform according to any one of claims 1 to 6.

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