Vector optimization algorithm translation method and device for RISC-V vector extension platform

Abstract

The application provides a vector optimization algorithm translation method and device for a RISC-V vector expansion platform, and relates to the technical field of computer software cross-architecture translation, and the method comprises the following steps: inputting source code of a vector optimization algorithm written by other platforms and a translation prompt into a large language model, and outputting translation code of the vector optimization algorithm for the RISC-V vector expansion platform; inputting the translation code into a compiler for compilation; in the case of successful compilation, linking the compilation product to a test suite to obtain an executable program, performing unit testing on the executable program on a RISC-V vector expansion device; and in the case of passing the unit testing, determining that the translation code is the first version of correct translation code of the vector optimization algorithm for the RISC-V vector expansion platform. The application realizes efficient translation of a vector optimization algorithm written by using a special vector language of other platforms to the RISC-V vector expansion platform.

Description

Technical Field

[0001] This invention relates to the field of computer software cross-architecture translation technology, and in particular to a vector optimization algorithm translation method and apparatus for the RISC-V vector extension platform. Background Technology

[0002] Translating vector optimization algorithms written in the dedicated vector languages ​​of existing high-performance algorithm libraries to the RISC-V vector extension platform is a key path to building a RISC-V high-performance software ecosystem.

[0003] Currently, cross-architecture code translation primarily employs the direct instruction mapping (DIM) approach. DIM refers to establishing mapping relationships between instructions in different hardware-specific vector languages, translating the dedicated vector languages ​​of other platforms into the RISC-V Vector Extensions (RISC-V) dedicated vector language at compile time. This allows algorithms optimized for other platforms to be automatically translated to the RISC-V RISC-V platform.

[0004] However, cross-platform instruction mapping schemes typically rely on developers to maintain mapping rules, and the instruction set of each platform is enormous. This results in shortcomings in the coverage of vector instruction operations in existing cross-platform instruction mapping schemes. For example, the neon2rvv library only supports mapping 60% (2627 / 4369) of neon instructions to RISC-V vector extension instructions, which leads to inefficient translation. Summary of the Invention

[0005] This invention provides a method and apparatus for translating vector optimization algorithms for the RISC-V vector extension platform, which solves the problem of how to efficiently translate vector optimization algorithms written in other platform-specific vector languages ​​to the RISC-V vector extension platform.

[0006] This invention provides a vector optimization algorithm translation method for the RISC-V vector extension platform, comprising the following steps:

[0007] The large language model takes the source code of the vector optimization algorithm written in other platform-specific vector programming languages ​​and the translation prompt words for the RISC-V vector extension platform as input, and outputs the translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0008] The translated code is then input into a compiler for compilation targeting the RISC-V Vector Extensions platform;

[0009] If compilation is successful, the compiler output is obtained. The compiler output is linked to the test suite to obtain an executable program. Unit tests are performed on the executable program on a RISC-V vector extension device.

[0010] If the unit tests pass, it is determined that the translated code is the first correct translation of the vector optimization algorithm for the RISC-V vector extension platform.

[0011] In some embodiments, the step of taking the source code of the vector optimization algorithm written in another platform-specific vector programming language and the translation prompt words for the RISC-V Vector Extensions platform as input to a large language model, and outputting translation code for the vector optimization algorithm for the RISC-V Vector Extensions platform, includes:

[0012] Based on the source code and the translation prompts, the large language model uses retrieval-enhanced generation technology to query and retrieve data from the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database, and outputs the translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0013] In some embodiments, the method further includes:

[0014] Performance tests were performed on the first version of the correctly translated code on a RISC-V vector extension device to obtain performance data for the first version of the correctly translated code.

[0015] The optimization hints, including register usage information, the performance data, and the first version of the correct translation code are input into the large language model. The large language model performs N iterations of optimization on the first version of the correct translation code based on the performance data and register usage information to obtain N versions of the correct translation code; where N is a positive integer.

[0016] From the first version of the correct translation code and the N versions of the correct translation code, the final correct translation code of the vector optimization algorithm is selected.

[0017] In some embodiments, the method further includes:

[0018] In the event of compilation failure, obtain the compilation error information output by the compiler;

[0019] The first correction prompt word, including the compilation error information, is input into the large language model, and the large language model corrects the translation code based on the compilation error information.

[0020] In some embodiments, the method further includes:

[0021] If a unit test fails, obtain the test error information;

[0022] The second correction prompt word, which includes the test error information, is input into the large language model, and the large language model corrects the translation code based on the test error information.

[0023] In some embodiments, the method further includes:

[0024] Based on the RISC-V Vector Extension Specification document and the RISC-V Vector Built-in Documentation, the RISC-V Vector Instruction Knowledge Base is constructed using a block-based approach.

[0025] This invention also provides a vector optimization algorithm translation device for the RISC-V vector extension platform, comprising the following modules:

[0026] The processing module is used to input the source code of the vector optimization algorithm written in other platform-specific vector programming languages ​​and the translation prompt words for the RISC-V vector extension platform into the large language model, and output the translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0027] The compilation module is used to input the translated code into the compiler for compilation for the RISC-V Vector Extensions platform;

[0028] The test module is used to obtain the compilation artifacts output by the compiler when the compilation is successful, link the compilation artifacts to the test suite to obtain the executable program, and perform unit tests on the executable program on the RISC-V Vector Extensions device.

[0029] A determination module is used to determine, if the unit tests pass, that the translated code is the first version of the correct translated code for the vector optimization algorithm for the RISC-V vector extension platform.

[0030] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a vector optimization algorithm translation method for the RISC-V vector extension platform as described above.

[0031] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a vector optimization algorithm translation method for the RISC-V vector extension platform as described above.

[0032] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements a vector optimization algorithm translation method for the RISC-V vector extension platform as described above.

[0033] The vector optimization algorithm translation method and apparatus provided by this invention for the RISC-V vector extension platform replaces mapping rules with a large language model, which is superior to traditional mapping rule-based translation schemes in terms of the quality and performance of the generated vector code. Moreover, it does not require manual translation by domain experts, which significantly reduces the difficulty and workload of translating large-scale algorithm libraries to the RISC-V vector extension platform, and enables efficient translation of vector optimization algorithms written in other platform-specific vector languages ​​to the RISC-V vector extension platform. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1 This is one of the flowcharts illustrating the vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention.

[0036] Figure 2 This is the second flowchart illustrating the vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention.

[0037] Figure 3 This is a schematic diagram of the vector optimization algorithm translation device for the RISC-V vector extension platform provided by the present invention.

[0038] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0039] Vector hardware is a processor component that achieves efficient parallel computing through a Single Instruction Multiple Data (SIMD) architecture. Its core design goal is to significantly improve the processing power of computationally intensive tasks by performing the same operation on multiple data elements with a single instruction. Vector instructions serve as the programming interface for this type of hardware, allowing software to utilize its acceleration capabilities to optimize performance. This parallel optimization model is particularly suitable for fields such as scientific computing, signal processing, machine learning, and graphics rendering. Its advantages lie in reducing the number of instruction decoding operations, optimizing continuous memory access, and improving cache utilization, making it a key technology in modern high-performance computing.

[0040] At the high-level language level, there are three main methods for optimizing software performance using vector instructions: directly writing algorithms in a high-level language and relying on the compiler to automatically vectorize and generate vector instructions; writing optimization algorithms using a general-purpose vector language for vector hardware; and writing optimization algorithms using a dedicated vector language specific to particular hardware.

[0041] High-level languages ​​and automatic vectorization: Developers use high-level languages ​​to write algorithms and rely on the compiler's automatic vectorization function to convert scalar code into vector instructions. This method has the widest applicability. Developers only need to focus on the algorithm logic without understanding the underlying hardware details. However, the implementation of computational load cannot be optimally mapped to hardware instructions, making it difficult to fully utilize hardware resources to achieve the best performance.

[0042] General-purpose vector languages: Through cross-platform vector programming libraries (such as Google Highway and the C++ standard library std::simd), developers directly write vectorized algorithmic logic using abstract vector types and operations. The cross-platform vector programming library adapts to different hardware instruction sets at compile time, generating corresponding vector instructions. This method avoids direct binding to specific hardware instruction sets and provides stronger optimization capabilities than compiler-automatic vectorization. However, the vector operation semantics abstracted for general computing needs are not entirely suitable for the computing needs of specific domains and cannot fully leverage the performance advantages of special hardware.

[0043] Dedicated vector languages: These languages ​​utilize built-in vector functions provided by hardware manufacturers (such as AVX Intrinsics for x86, NEON Intrinsics for ARM, and RISC-V Vector Intrinsics) to directly write vectorized algorithm logic using the target hardware's built-in vector functions. This method offers the best optimization results, but compared to high-level languages ​​and general-purpose vector languages, the dedicated vector functions for different platforms are incompatible, requiring separate algorithm optimizations for each platform.

[0044] In the current software ecosystem, hardware-specific vector languages ​​are widely used for low-level optimization in high-performance computing, multimedia processing, and AI inference. For example, high-performance algorithm libraries such as FFmpeg and OpenCV heavily rely on such optimizations, and their support for mainstream instruction set architectures such as ARM Neon and x86 SSE / AVX is already quite mature. However, the adaptation progress of RISC-V Vector Extensions lags significantly behind x86 / ARM: on the one hand, the RISC-V software ecosystem started later, and the number of developers is limited; on the other hand, the open-source and scalable nature of the RISC-V instruction set architecture also increases the difficulty of software development, adaptation, and optimization.

[0045] Translating vector optimization algorithms written in the dedicated vector languages ​​of existing high-performance algorithm libraries to the RISC-V vector extension platform is a key path to building a RISC-V high-performance software ecosystem.

[0046] Currently, cross-architecture code translation primarily employs the direct instruction mapping (DIM) approach. DIM refers to establishing mapping relationships between instructions in different hardware-specific vector languages, translating the proprietary vector languages ​​of other platforms into RISC-V Vector Extensions (RISC-V) at compile time. This allows algorithms optimized for other platforms to be automatically translated to the RISC-V RISC-V platform. For example, neon2rvv and sse2rvv, using C++ header files, describe vector instructions in ARM Neon and Intel SSE proprietary vector languages, respectively. When algorithms optimized for these hardware platforms are compiled together with the corresponding header files (neon2rvv / sse2rvv), RISC-V RISC-V instructions can be generated, thereby optimizing performance.

[0047] The shortcomings of existing technologies are mainly reflected in two aspects: functionality and performance.

[0048] (1) Functional aspects

[0049] Existing solutions can only map a limited number of instructions: Cross-platform instruction mapping solutions usually rely on developers to maintain mapping rules, while the instruction set of each platform is huge. This results in a shortcoming in the coverage of vector instruction operations in existing cross-platform instruction mapping solutions. For example, the neon2rvv library only supports mapping 60% (2627 / 4369) of neon instructions to RISC-V vector extension instructions.

[0050] Existing solutions have shortcomings in compatibility with vector type systems: the variable-length vector types extended by RISC-V are often subject to certain restrictions in use due to the design of high-level languages ​​and compilers; for example, variable-length vector type member variables cannot be declared within classes or structs. This is incompatible with the encapsulation and usage methods of vector types in existing algorithm libraries, and existing mapping schemes cannot solve the compatibility problem of vector type systems.

[0051] (2) Performance aspects

[0052] Existing solutions fail to fully utilize the features of RISC-V vector extensions due to semantic gaps caused by architectural differences. RISC-V vector extensions employ dynamically sized vector registers (128-bit to 65536-bit) and support register grouping, significantly differing from the fixed-length vector registers used in Neon / SSE. Existing solutions only use fixed-length (128 / 256-bit) mapping schemes and fail to consider the differences in the number of available vector registers across different platforms, resulting in underutilization of RISC-V vector extension vector register resources and wasted computational power. Furthermore, existing solutions directly map fixed-length vector programming models to variable-length RISC-V vector extensions, failing to fully utilize features of the RISC-V vector extension programming model such as vector configuration instructions (e.g., `setvl`), leading to performance losses.

[0053] Existing solutions introduce additional overhead due to differences in instruction functionality coverage. Individual instructions on other platforms may not have direct mappings in RISC-V Vector Extensions, requiring combinations of multiple RISC-V Vector Extension instructions. For example, the vector shuffle instruction in SSE / Neon needs to be broken down into a combination of vrgather and vslide in RISC-V Vector Extensions, increasing the number of instructions and leading to performance degradation. Furthermore, the mapping scheme is at a lower level, potentially missing optimization opportunities. For instance, RISC-V Vector Extensions' unique straddle load (vlseg / vsseg) and index load (vluxei) instructions can optimize irregular data access, but these operations are not available on other platforms. The code generated by the mapping scheme still uses the continuous memory access pattern of the source platform, losing the deep optimization opportunities that require platform adaptation from the early stages of algorithm design, resulting in unnecessary performance overhead.

[0054] To address the aforementioned problems, this invention provides a vector optimization algorithm translation method for the RISC-V Vector Extensions platform. It uses a large language model instead of mapping rules, analyzes the semantics of other platform codes using the large language model to obtain algorithm-level semantics, and generates translation code for the RISC-V Vector Extensions platform using the large language model, thus achieving RISC-V Vector Extensions code translation based on a large language model.

[0055] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0056] Figure 1 This is one of the flowcharts illustrating the vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention, such as... Figure 1 As shown, this invention provides a vector optimization algorithm translation method for the RISC-V vector extension platform, comprising the following steps:

[0057] Step 110: Input the source code of the vector optimization algorithm written in a vector programming language specific to other platforms, and the translation prompts for the RISC-V vector extension platform into the large language model, and output the translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0058] Specifically, Large Language Models (LLMs) have the ability to understand semantics at the algorithm level and perceive context. Therefore, LLMs can be used to build code translation agents to replace solutions based on mapping rules or manual translation.

[0059] The source code of the vector optimization algorithm written in a vector programming language specific to other platforms, along with translation prompts for the RISC-V vector extension platform, are input into the large language model. The translation prompts include code translation tasks for the RISC-V vector extension platform. The large language model translates the source code according to the code translation tasks, that is, it analyzes the semantics of the original vector operations and the algorithm functions based on the source code information, and outputs the translated code of the vector optimization algorithm for the RISC-V vector extension platform.

[0060] In some embodiments, to help large language models fully utilize the features of the RISC-V Vector Extension architecture and thereby improve the performance of translated RISC-V Vector Extension platform vector optimization code, the large language model is used to analyze the data length in specific loop structures, and translation prompts are used to guide the large language model to automatically insert dynamic vector length control related instructions.

[0061] Step 120: Input the translated code into the compiler for compilation for the RISC-V Vector Extensions platform.

[0062] Specifically, a RISC-V cross-compilation toolchain is built, which includes a compiler, assembler, linker, and standard library. This toolchain is used to check the syntactic correctness of the algorithm implementation and generate executable programs. The translated code is then input into the compiler for compilation targeting the RISC-V Vector Extensions platform.

[0063] Step 130: If compilation is successful, obtain the compilation artifacts output by the compiler, link the compilation artifacts to the test suite to obtain the executable program, and perform unit tests on the executable program on the RISC-V Vector Extensions device.

[0064] Specifically, a test suite is developed to evaluate the functional correctness and performance of the translated code. The process can involve: retrieving built-in functions from other platforms and the RISC-V vector extension platform on an open-source code hosting platform to obtain existing open-source algorithm libraries for vector optimization. Vector optimization code and its corresponding test code for different platforms are then extracted to form a test case set. This test case set is then compiled into a test suite using a testing framework (such as Google Test) for unit testing and performance testing.

[0065] If compilation is successful, the compiler output is obtained. The compiled output is linked to the test suite to obtain the executable program. Unit tests are performed on the executable program on a RISC-V Vector Extensions device to evaluate the functional correctness of the translated code.

[0066] Step 140: If the unit tests pass, determine that the translated code is the first version of the correct translated code for the vector optimization algorithm for the RISC-V vector extension platform.

[0067] Specifically, if the unit tests pass, the translated code output by the large language model is considered to be the first version of the correct translated code of the vector optimization algorithm for the RISC-V vector extension platform.

[0068] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention replaces mapping rules with a large language model, which outperforms traditional mapping rule-based translation schemes in terms of the quality and performance of the generated vector code. Moreover, it eliminates the need for manual translation by domain experts, significantly reducing the difficulty and workload of translating large-scale algorithm libraries to the RISC-V vector extension platform. This enables the efficient translation of vector optimization algorithms written in other platform-specific vector languages ​​to the RISC-V vector extension platform.

[0069] In some embodiments, the source code of a vector optimization algorithm written in a vector programming language specific to other platforms, along with translation prompts for the RISC-V Vector Extensions platform, is input into the large language model, and the output is translation code for the vector optimization algorithm for the RISC-V Vector Extensions platform, including:

[0070] Based on the source code and translation prompts, the large language model uses retrieval-enhanced generation techniques to query and retrieve data from the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database, outputting translated code for vector optimization algorithms for the RISC-V vector extension platform.

[0071] Specifically, a RISC-V vector instruction knowledge base is constructed based on the RISC-V Vector Extension Specification document and the RISC-V Vector Intrinsic document. The RISC-V Vector Extension Specification defines vector operations and their functions. The RISC-V Vector Intrinsic document defines the calling format of the RISC-V Vector Extension-specific language (vector types and operations) at the high-level language level.

[0072] The overhead of vector extension instructions (the number of clock cycles required to execute the instruction) is measured based on the processor hardware manual or benchmarks used in the hardware device, and a RISC-V vector instruction overhead database is constructed accordingly.

[0073] Based on the source code and translation prompts, the large language model uses retrieval enhancement generation technology to query and retrieve data from the RISC-V vector instruction knowledge base. It learns the vector operation functions and calling formats in the RISC-V vector instruction knowledge base, effectively making up for the large language model's lack of knowledge about the RISC-V vector extension instruction set. This solves the limitation of the mapping scheme relying on manual instruction overriding, guides the large model to fully understand and use the special operations of the RISC-V vector extension platform, and thus improves the accuracy of generating RISC-V vector extension platform-specific language.

[0074] Based on the source code and translation prompts, the large language model uses retrieval enhancement generation technology to query and retrieve the overhead of specific instructions in the RISC-V vector instruction overhead database. This provides the large language model with references, guiding it to use lower-overhead instruction combinations to meet the requirements of the vectorization algorithm, thereby optimizing the performance of the vectorization algorithm.

[0075] In some embodiments, to help large language models learn and understand the RISC-V vector extension programming model and improve code translation quality, specific programming paradigms for RISC-V vector extensions are provided for large language models by combining excellent RISC-V vector extension examples from the open-source community.

[0076] Since large language models have limitations on the length of input, the length of translation prompts should not be too long. Therefore, a small number of RISC-V vector extension-specific programming examples are provided to the large language model through translation prompts, while a large number of RISC-V vector extension-specific programming examples are provided to the large language model through the RISC-V vector instruction knowledge base.

[0077] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention provides RISC-V vector extension vector instruction information for large language models through the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database, helping them to select appropriate instructions, improve code translation accuracy and performance, reduce LLM call overhead, and avoid the illusion problem that may occur in LLM.

[0078] In some embodiments, the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention further includes:

[0079] Based on the RISC-V Vector Extension Specification document and the RISC-V Vector Built-in Documentation, a RISC-V Vector Instruction Knowledge Base is constructed using a block-based approach.

[0080] Specifically, due to the large size of the RISC-V vector extension specification document and the RISC-V vector built-in document, a block-based approach was adopted to construct the RISC-V vector instruction knowledge base. The specific construction process is as follows:

[0081] First, the RISC-V vector extension specification document is divided into sections based on different functions (such as memory access, logical operations, and arithmetic operations). Then, based on the instructions contained in each section, corresponding built-in functions are selected from the RISC-V vector built-in document and added to the section. Finally, on a section-by-section basis, a pre-trained model is used to encode each section into vectors and store them in a database, thus obtaining the RISC-V vector instruction knowledge base. The RISC-V vector instruction knowledge base allows large language models to retrieve instruction operations and their corresponding built-in function calls from documents using keyword matching.

[0082] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention stores instructions categorized by different functions, resulting in a clear RISC-V vector instruction knowledge base structure. This facilitates rapid location of target instructions and reduces interference from irrelevant information. Instruction descriptions in the specification documents are directly associated with their corresponding built-in functions, forming a complete mapping and avoiding manual cross-referencing between documents, thus improving efficiency.

[0083] In some embodiments, the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention further includes:

[0084] In the event of compilation failure, obtain the compilation error information output by the compiler;

[0085] The first correction prompt, which includes the compilation error information, is input into the large language model, which then corrects the translated code based on the compilation error information.

[0086] Specifically, the translation code generated by the large language model is compiled, and a compilation information feedback mechanism is introduced. In the event of compilation failure, the compilation error information output by the compiler is obtained, and the compilation error information is fed back to the large language model through the first correction prompt word. The large language model corrects the translation code based on the compilation error information, thereby generating new translation code.

[0087] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention, in the event of compilation failure, feeds back the compilation error information to the large language model. The large language model corrects the translation code based on the compilation error information, providing timely correctness feedback to the large language model, thereby improving the correctness of subsequent translation code.

[0088] In some embodiments, the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention further includes:

[0089] If a unit test fails, obtain the test error information;

[0090] The second correction prompt, which includes test error information, is input into the large language model, which then corrects the translation code based on the test error information.

[0091] Specifically, unit tests are performed on the executable program on a RISC-V vector extension device. A test information feedback mechanism is introduced to obtain test error information when the unit test fails. The test error information is fed back to the large language model through a second correction prompt word. The large language model corrects the translation code based on the test error information, thereby generating new translation code.

[0092] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention, when unit tests fail, feeds back the test error information to a large language model. The large language model corrects the translation code based on the test error information, providing timely correctness feedback to the large language model, thereby improving the correctness of subsequent translation code.

[0093] In some embodiments, the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the present invention further includes:

[0094] Performance tests were performed on the first version of the correctly translated code on a RISC-V vector extension device to obtain performance data for the first version of the correctly translated code.

[0095] The optimization hints, including register usage information, performance data, and the first version of the correct translation code are input into the large language model. The large language model performs N iterations of optimization on the first version of the correct translation code based on the performance data and register usage information, resulting in N versions of the correct translation code; N is a positive integer.

[0096] From the first version of the correct translation code and N versions of the correct translation code, the final correct translation code for the vector optimization algorithm is selected.

[0097] Specifically, a test suite was enabled on a RISC-V vector extension device to perform performance tests on the first version of the correctly translated code, obtaining performance data for the first version of the correctly translated code. Static analysis of the register usage in the core code was combined with compiler techniques to obtain register usage information.

[0098] The optimization hints, including register usage information, performance data of the first version of the correct translation code, and the first version of the correct translation code are input into the large language model. The large language model optimizes the first version of the correct translation code based on the performance data and register usage information to obtain the second version of the correct translation code.

[0099] On a RISC-V vector extension device, a test suite was enabled to perform performance tests on the second version of the correct translation code, obtaining performance data for the second version. Optimization hints including register usage information, the performance data of the second version of the correct translation code, and the second version of the correct translation code itself were input into a large language model. The large language model optimized the second version of the correct translation code based on the performance data and register usage information, resulting in the third version of the correct translation code.

[0100] This process is repeated N times to obtain N versions of the correct translated code.

[0101] From the first correctly translated code and N other correctly translated code versions (i.e., N+1 versions), the final correctly translated code using the vector optimization algorithm is selected to complete the code translation and optimization task. For example, the version with the best performance is chosen as the final correctly translated code.

[0102] The vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention provides register usage information to a large language model through optimization prompts, guiding the large language model to fully utilize the characteristics of the RISC-V vector extension architecture through mechanisms such as loop unrolling and register grouping, thereby improving the performance of the translated RISC-V vector extension platform vector optimization code; a performance feedback mechanism is introduced to feed back the performance data of the correctly translated code to the large language model, providing timely performance feedback and iteratively improving the optimization effect.

[0103] Figure 2 This is the second flowchart illustrating the vector optimization algorithm translation method for the RISC-V vector extension platform provided by this invention. Figure 2 As shown, this invention provides a vector optimization algorithm translation method for the RISC-V vector extension platform, comprising the following steps:

[0104] Step 201 involves inputting source code written in a vector programming language specific to other platforms and translation prompts for the RISC-V vector extension platform into the large language model. At this point, the large language model analyzes the semantics of the original vector operations and the algorithmic functionality based on the source code information.

[0105] Step 202: Select appropriate RISC-V vector extension vector operations by querying and retrieving the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database in multiple rounds.

[0106] Step 203: Output the translation code of the vector optimization algorithm for the RISC-V vector extension platform and save it to a file.

[0107] Step 204: Input the translated code into the compiler for compilation targeting the RISC-V Vector Extensions platform. If compilation fails, proceed to step 205; if compilation succeeds, proceed to step 206.

[0108] Step 205: Obtain the compilation error information output by the compiler. Input the first correction prompt word, including the compilation error information, into the large language model, and the large language model corrects the translated code based on the compilation error information.

[0109] Step 206: Obtain the compiled output from the compiler, link the compiled output to the test suite to obtain the executable program, and perform unit tests on the executable program on the RISC-V Vector Extensions device to evaluate the functional correctness of the translated code. If the unit tests fail, proceed to step 207; if the unit tests pass, it is determined that the translated code is the first version of the correct translated code for the vector optimization algorithm for the RISC-V Vector Extensions platform, and proceed to step 208.

[0110] Step 207: Obtain test error information. Input the second correction prompt word, including the test error information, into the large language model. The large language model corrects the translation code based on the test error information.

[0111] Step 208: Perform performance testing on the first version of the correctly translated code on a RISC-V vector extension device to obtain performance data for the first version of the correctly translated code.

[0112] Step 209: Input the optimization hints including register usage information, the performance data of the first version of the correct translation code, and the first version of the correct translation code into the large language model. The large language model performs N iterations of optimization on the first version of the correct translation code based on the performance data of the first version of the correct translation code and the register usage information to obtain N versions of the correct translation code.

[0113] Step 210: Select the best-performing correct translation code from the first version of the correct translation code and N versions of the correct translation code as the final correct translation code for the vector optimization algorithm.

[0114] The vector optimization algorithm translation device for the RISC-V vector extension platform provided by the present invention will be described below. The vector optimization algorithm translation device for the RISC-V vector extension platform described below can be referred to in correspondence with the vector optimization algorithm translation method for the RISC-V vector extension platform described above.

[0115] Figure 3 This is a schematic diagram of the vector optimization algorithm translation device for the RISC-V vector extension platform provided by the present invention, as shown below. Figure 3 As shown, this invention provides a vector optimization algorithm translation device for the RISC-V vector extension platform, comprising the following modules:

[0116] The processing module 310 is used to input the source code of the vector optimization algorithm written in a vector programming language for other platforms and the translation prompt words for the RISC-V vector extension platform into the large language model, and output the translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0117] The compilation module 320 is used to input the translated code into the compiler for compilation for the RISC-V Vector Extensions platform;

[0118] Test module 330 is used to obtain the compilation product output by the compiler when the compilation is successful, link the compilation product to the test suite to obtain an executable program, and perform unit tests on the executable program on a RISC-V vector extension device.

[0119] The determination module 340 is used to determine, if the unit test passes, that the translated code is the first version of the correct translated code for the vector optimization algorithm for the RISC-V vector extension platform.

[0120] In some embodiments, the processing module 310 is specifically used for:

[0121] Based on the source code and the translation prompts, the large language model uses retrieval-enhanced generation technology to query and retrieve data from the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database, and outputs the translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0122] In some embodiments, the apparatus further includes an iterative optimization module, the iterative optimization module being used to:

[0123] Performance tests were performed on the first version of the correctly translated code on a RISC-V vector extension device to obtain performance data for the first version of the correctly translated code.

[0124] The optimization hints, including register usage information, the performance data, and the first version of the correct translation code are input into the large language model. The large language model performs N iterations of optimization on the first version of the correct translation code based on the performance data and register usage information to obtain N versions of the correct translation code; where N is a positive integer.

[0125] From the first version of the correct translation code and the N versions of the correct translation code, the final correct translation code of the vector optimization algorithm is selected.

[0126] In some embodiments, the apparatus further includes a first correction module, the first correction module being configured to:

[0127] In the event of compilation failure, obtain the compilation error information output by the compiler;

[0128] The first correction prompt word, including the compilation error information, is input into the large language model, and the large language model corrects the translation code based on the compilation error information.

[0129] In some embodiments, the apparatus further includes a second correction module, the second correction module being configured to:

[0130] If a unit test fails, obtain the test error information;

[0131] The second correction prompt word, which includes the test error information, is input into the large language model, and the large language model corrects the translation code based on the test error information.

[0132] In some embodiments, the apparatus further includes a construction module, the construction module being configured to:

[0133] Based on the RISC-V Vector Extension Specification document and the RISC-V Vector Built-in Documentation, the RISC-V Vector Instruction Knowledge Base is constructed using a block-based approach.

[0134] It should be noted that the vector optimization algorithm translation device for the RISC-V vector extension platform provided by the present invention can implement all the method steps implemented in the above method embodiments and can achieve the same technical effect. Therefore, the parts and beneficial effects that are the same as those in the method embodiments will not be described in detail here.

[0135] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 4 As shown, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communications bus 440, wherein the processor 410, the communications interface 420, and the memory 430 communicate with each other through the communications bus 440. Processor 410 can call logic instructions in memory 430 to execute a vector optimization algorithm translation method for the RISC-V vector extension platform. This method includes: inputting the source code of the vector optimization algorithm written in a vector programming language specific to another platform, along with translation prompts for the RISC-V vector extension platform, into a large language model; outputting translation code for the vector optimization algorithm for the RISC-V vector extension platform; inputting the translation code into a compiler for compilation for the RISC-V vector extension platform; if compilation is successful, obtaining the compiled output; linking the compiled output to a test suite to obtain an executable program; performing unit tests on the executable program on a RISC-V vector extension device; and if the unit tests pass, determining that the translation code is the first correct translation code for the vector optimization algorithm for the RISC-V vector extension platform.

[0136] Furthermore, the logical instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0137] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the vector optimization algorithm translation method for the RISC-V vector extension platform provided by the above methods. The method includes: inputting the source code of the vector optimization algorithm written in a vector programming language for other platforms and translation prompts for the RISC-V vector extension platform into a large language model, and outputting translation code of the vector optimization algorithm for the RISC-V vector extension platform; inputting the translation code into a compiler for compilation for the RISC-V vector extension platform; if the compilation is successful, obtaining the compilation product output by the compiler; linking the compilation product to a test suite to obtain an executable program; performing unit tests on the executable program on a RISC-V vector extension device; if the unit tests pass, determining that the translation code is the first version of the correct translation code of the vector optimization algorithm for the RISC-V vector extension platform.

[0138] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements a translation method for a vector optimization algorithm for the RISC-V vector extension platform provided by the methods described above. This method includes: inputting the source code of a vector optimization algorithm written in a vector programming language specific to another platform, along with translation prompts for the RISC-V vector extension platform, into a large language model; outputting translation code for the vector optimization algorithm for the RISC-V vector extension platform; inputting the translation code into a compiler for compilation for the RISC-V vector extension platform; if compilation is successful, obtaining the compilation product output by the compiler; linking the compilation product to a test suite to obtain an executable program; performing unit tests on the executable program on a RISC-V vector extension device; and if the unit tests pass, determining that the translation code is the first version of the correct translation code for the vector optimization algorithm for the RISC-V vector extension platform.

[0139] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0140] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A vector optimization algorithm translation method for the RISC-V vector extension platform, characterized in that, include: The large language model takes the source code of the vector optimization algorithm written in other platform-specific vector programming languages ​​and the translation prompt words for the RISC-V vector extension platform as input, and outputs the translation code of the vector optimization algorithm for the RISC-V vector extension platform. The translated code is then input into a compiler for compilation targeting the RISC-V Vector Extensions platform; If compilation is successful, the compiler output is obtained. The compiler output is linked to the test suite to obtain an executable program. Unit tests are performed on the executable program on a RISC-V vector extension device. If the unit tests pass, it is determined that the translated code is the first correct translation code of the vector optimization algorithm for the RISC-V vector extension platform; The method further includes: Performance tests were performed on the first version of the correctly translated code on a RISC-V vector extension device to obtain performance data for the first version of the correctly translated code. The optimization hints, including register usage information, the performance data, and the first version of the correct translation code are input into the large language model. The large language model performs N iterations of optimization on the first version of the correct translation code based on the performance data and register usage information to obtain N versions of the correct translation code; where N is a positive integer. From the first version of the correct translation code and the N versions of the correct translation code, the final correct translation code of the vector optimization algorithm is selected.

2. The vector optimization algorithm translation method for the RISC-V vector extension platform according to claim 1, characterized in that, The process of inputting the source code of the vector optimization algorithm written in a vector programming language specific to other platforms, and the translation prompt words for the RISC-V Vector Extensions platform into a large language model, and outputting translation code for the vector optimization algorithm for the RISC-V Vector Extensions platform, includes: Based on the source code and the translation prompts, the large language model uses retrieval-enhanced generation technology to query and retrieve data from the RISC-V vector instruction knowledge base and the RISC-V vector instruction overhead database, and outputs the translation code of the vector optimization algorithm for the RISC-V vector extension platform.

3. The vector optimization algorithm translation method for the RISC-V vector extension platform according to claim 1, characterized in that, The method further includes: In the event of compilation failure, obtain the compilation error information output by the compiler; The first correction prompt word, including the compilation error information, is input into the large language model, and the large language model corrects the translation code based on the compilation error information.

4. The vector optimization algorithm translation method for the RISC-V vector extension platform according to claim 1, characterized in that, The method further includes: If a unit test fails, obtain the test error information; The second correction prompt word, which includes the test error information, is input into the large language model, and the large language model corrects the translation code based on the test error information.

5. The vector optimization algorithm translation method for the RISC-V vector extension platform according to claim 2, characterized in that, The method further includes: Based on the RISC-V Vector Extension Specification document and the RISC-V Vector Built-in Documentation, the RISC-V Vector Instruction Knowledge Base is constructed using a block-based approach.

6. A vector optimization algorithm translation device for the RISC-V vector extension platform, characterized in that, include: The processing module is used to input the source code of the vector optimization algorithm written in other platform-specific vector programming languages ​​and the translation prompt words for the RISC-V vector extension platform into the large language model, and output the translation code of the vector optimization algorithm for the RISC-V vector extension platform. The compilation module is used to input the translated code into the compiler for compilation for the RISC-V Vector Extensions platform; The test module is used to obtain the compilation artifacts output by the compiler when the compilation is successful, link the compilation artifacts to the test suite to obtain the executable program, and perform unit tests on the executable program on the RISC-V Vector Extensions device. A determination module is used to determine, if the unit tests pass, that the translated code is the first version of the correct translated code for the vector optimization algorithm for the RISC-V vector extension platform; The device further includes an iterative optimization module, which is used for: Performance tests were performed on the first version of the correctly translated code on a RISC-V vector extension device to obtain performance data for the first version of the correctly translated code. The optimization prompts including register usage information, the performance data, and the first version of the correct translation code are input into the large language model. The large language model performs N iterations of optimization on the first version of the correct translation code based on the performance data and register usage information to obtain N versions of the correct translation code. N is a positive integer; From the first version of the correct translation code and the N versions of the correct translation code, the final correct translation code of the vector optimization algorithm is selected.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the vector optimization algorithm translation method for the RISC-V vector extension platform as described in any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the vector optimization algorithm translation method for the RISC-V vector extension platform as described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the vector optimization algorithm translation method for the RISC-V vector extension platform as described in any one of claims 1 to 5.

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