A data processing system, method, electronic device, and storage medium

Abstract

The application discloses a data processing system, method, electronic equipment and storage medium, and relates to the technical field of computers. The original input data is preprocessed into multiple groups of target input data through a data input module, and is input into multiple iteration calculation units to obtain to-be-calculated data and an encoding identifier. When the encoding identifier indicates that the to-be-calculated data needs to be pre-inverted, the to-be-calculated data is pre-inverted to obtain to-be-calculated inverted data. The subsequent iteration calculation unit only needs to perform target calculation on the to-be-calculated inverted data to obtain a data processing result. That is, the iteration calculation unit only needs to perform a small amount of data bit inversion on the to-be-calculated inverted data through target calculation to obtain the data processing result. The number of times of data bit inversion in target calculation is reduced, dynamic inversion power consumption is reduced, and, compared with the power consumption reduction mode in the related art, the application does not need high-difficulty chip back-end layout and wiring, and can guarantee the performance and power consumption reduction effect of the chip.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing system, method, electronic device, and storage medium. Background Technology

[0002] In today's digital development, the application of algorithms is becoming increasingly widespread, and the requirements for power consumption are becoming more and more stringent, highlighting the importance of low-power data processing. The third-generation secure hash algorithm (Secure Hash Algorithm 3, or SHA-3 for short) is the latest generation of secure hash algorithms. Since the algorithm generates high dynamic flipping power consumption during data processing, how to reduce the dynamic flipping power consumption of data processing has become a key research topic.

[0003] In related technologies, dynamic voltage regulation is typically employed to adjust the supply voltage in cycles. However, implementing dynamic voltage regulation on the chip running the algorithm requires designing multiple power supply lines, which increases the difficulty of back-end chip layout and routing. It also increases parasitic effects caused by voltage switching, which is detrimental to ensuring chip performance and power consumption reduction. Summary of the Invention

[0004] This application provides a data processing system, method, electronic device, and storage medium to at least solve the problem in the related art that the algorithm power consumption reduction method increases the difficulty of chip back-end layout and routing, which is not conducive to ensuring chip performance and power consumption reduction effect.

[0005] This application provides a data processing system, including: a data input module and an iterative calculation module, wherein the iterative calculation module includes multiple iterative calculation units;

[0006] The data input module is used to acquire the raw input data to be processed, perform data preprocessing on the raw input data to convert the raw input data into multiple sets of target input data, and input the multiple sets of target input data into multiple iterative calculation units respectively;

[0007] The iterative calculation unit is used to determine the data to be calculated and the encoding identifier based on the target input data and the output result of the previous iterative calculation unit when it receives any set of target input data and the output result of the previous iterative calculation unit; when the encoding identifier indicates that the data to be calculated meets the preset pre-flipping condition, the data to be calculated is pre-flipped to convert the data to be calculated into the inverted data to be calculated; the target calculation is performed on the inverted data to be calculated, and the obtained target calculation result is input as the output result to the next iterative calculation unit;

[0008] The target calculation includes flipping the data bits of the inverted data to be calculated, and the output of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

[0009] This application also provides a data processing method, applied to any of the above-mentioned data processing systems, the method comprising:

[0010] Obtain the raw input data to be processed;

[0011] The original input data is preprocessed to convert it into multiple sets of target input data, and then the multiple sets of target input data are input into multiple iterative calculation units respectively.

[0012] Based on the iterative calculation unit, the data to be calculated and the encoding identifier are determined according to the target input data and the output result of the previous iterative calculation unit;

[0013] If the encoded identifier indicates that the data to be calculated meets the preset pre-flipping conditions, the data to be calculated is pre-flipped to convert the data to be calculated into the inverted data to be calculated.

[0014] Perform target calculations on the inverted data to be calculated, and input the target calculation result as the output into the next iteration calculation unit;

[0015] The target calculation includes flipping the data bits of the inverted data to be calculated, and the output of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

[0016] This application also provides a data processing apparatus, including:

[0017] The acquisition module is used to acquire the raw input data to be processed.

[0018] The data preprocessing module is used to preprocess the raw input data to convert it into multiple sets of target input data, and then input the multiple sets of target input data into multiple iterative calculation units respectively.

[0019] The determination module is used to determine the data to be calculated and the encoding identifier based on the target input data and the output result of the previous iteration calculation unit, according to the iterative calculation unit.

[0020] The flipping module is used to pre-flip the data to be calculated when the encoded identifier indicates that the data to be calculated meets the preset pre-flipping conditions, so as to convert the data to be calculated into the inverted data to be calculated.

[0021] The calculation module is used to perform target calculations on the inverted data to be calculated, and input the obtained target calculation result as the output result to the next iteration calculation unit. The target calculation includes data bit flipping on the inverted data to be calculated. The output result of the last iteration calculation unit in the iteration calculation module is the data processing result corresponding to the original input data.

[0022] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above data processing methods.

[0023] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described data processing methods.

[0024] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described data processing methods.

[0025] By means of this application, the original input data is preprocessed into multiple sets of target input data through the data input module, and then input into multiple iterative calculation units to obtain the data to be calculated and the encoding identifier. When the encoding identifier indicates that the data to be calculated needs to be pre-flipped, the data to be calculated is pre-flipped to obtain the inverted data to be calculated. The subsequent iterative calculation unit only needs to perform target calculation on the inverted data to obtain the data processing result. That is, the iterative calculation unit only needs to perform a small number of data bit flips on the inverted data to be calculated through target calculation to obtain the data processing result, which reduces the number of data bit flips in the target calculation and reduces the power consumption of dynamic flipping. Compared with the power reduction methods in related technologies, this application does not require complicated chip back-end layout and routing, and can ensure the chip performance and power reduction effect. Attached Figure Description

[0026] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the interaction flow of the data processing system provided in the embodiments of this application;

[0028] Figure 2 This is a schematic diagram of the structure of the data processing system provided in the embodiments of this application;

[0029] Figure 3This is a schematic diagram of the structure of the iterative calculation unit provided in the embodiments of this application;

[0030] Figure 4 This is a schematic diagram of the structure of the encoding identifier determination unit provided in the embodiments of this application;

[0031] Figure 5 A schematic diagram of the structure of an exemplary register module provided in an embodiment of this application;

[0032] Figure 6 This is a schematic diagram of the structure of an exemplary data processing system provided in the embodiments of this application;

[0033] Figure 7 A flowchart illustrating the data processing method provided in an embodiment of this application;

[0034] Figure 8 This is a schematic diagram of the structure of the data processing apparatus provided in the embodiments of this application;

[0035] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0037] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0038] With the rapid pace of digital development, improving chip performance presents greater challenges to power management. The third-generation Secure Hash Algorithm 3 (SHA-3) is widely used in security scenarios such as data encryption and digital signatures. However, the sponge structure and high-frequency iterative operation mechanism of the SHA-3 algorithm generate significant dynamic flipping power consumption during data processing, thus reducing chip performance.

[0039] In related technologies, dynamic voltage regulation is generally used, adjusting the supply voltage in cycles. However, implementing dynamic voltage regulation on the operating chip requires designing multiple power supply lines, which increases the difficulty of back-end chip layout and routing, and also increases parasitic effects caused by voltage switching. Alternatively, a clock-gated SHA3 architecture can be used, but this method increases the latency of the critical path, thereby reducing computational performance.

[0040] This application discloses a data processing system, method, electronic device, and storage medium, relating to the field of computer technology. By preprocessing the original input data through a data input module to obtain multiple sets of target input data, and then inputting these sets of target input data into multiple iterative calculation units to obtain the data to be calculated and an encoding identifier, the data to be calculated is pre-flipped based on the encoding identifier to obtain the inverted data to be calculated. Subsequent iterative calculation units only need to perform target calculations on the inverted data to obtain the data processing result. That is, the iterative calculation unit only needs to perform a small number of data bit flips on the inverted data to obtain the data processing result, reducing the number of data bit flips in the target calculation and lowering dynamic flip power consumption. Compared to power reduction methods in related technologies, this application does not require complex chip back-end layout and routing, and can guarantee both chip performance and power reduction effects.

[0041] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] This application provides a data processing system for transmitting raw input data from a data input module to an iterative calculation module for calculation.

[0043] like Figure 1 The diagram shown is an interactive flow diagram of the data processing system provided in an embodiment of this application. The system includes a data input module and an iterative calculation module, and the iterative calculation module includes multiple iterative calculation units.

[0044] The data input module is used to acquire the raw input data to be processed. In the SHA-3 algorithm, the raw input data can be any data of any size that needs to be encrypted. The raw input data is preprocessed to convert it into multiple sets of target input data, which are then input to multiple iterative computation units. The iterative computation unit, upon receiving any set of target input data and the output of the previous iterative computation unit, determines the data to be computed and the encoding identifier based on these two parameters. If the encoding identifier indicates that the data to be computed meets a preset pre-flipping condition, the data to be computed is pre-flipped to convert it into inverted data. The inverted data is then used for target computation, and the resulting target computation is input as the output to the next iterative computation unit. The target computation includes bit flipping of the inverted data. The output of the last iterative computation unit in the iterative computation module is the data processing result corresponding to the raw input data.

[0045] It should be noted that the data processing system provided in this application embodiment exhibits a significant power consumption reduction effect when applied to data encryption processing scenarios. Taking the SHA-3 algorithm implemented by the data processing system provided in this application embodiment as an example, the original input data to be processed is the data to be encrypted, such as user privacy data, data to be compressed, or verification data. This algorithm consists of four cryptographic hash functions: SHA3-224, SHA3-256, SHA3-384, and SHA3-512, and two extensible output functions SHAKE-128 and SHAKE-256. The absorption rate, capacity, hash output length, and mapping relationship with the Keccak-f function of the SHA-3 algorithm are shown in Table 1 below.

[0046] Table 1

[0047]

[0048] Table 1 shows the operation parameters of the six sub-algorithms of the SHA-3 algorithm. The bit rate or absorption rate (Rate, abbreviated as r) represents the minimum data unit length for operation. As can be seen from the table, there are five different bit rates r among the six sub-algorithms, meaning that the data sent from the previous stage must be grouped according to length r before the algorithm operation. SHA3-224, SHA3-256, SHA3-384, and SHA3-512 are fixed-length hash algorithms, outputting a hash value of a fixed number of bytes, while SHAKE128 and SHAKE256 are variable-length hash algorithms, with the output length determined by the parameters. The hash output length, or digest length, represents the byte length of the final hash value generated by the algorithm. The capacity (Capacity, abbreviated as c) reflects the size of the algorithm's internal state; the larger the value, the stronger the algorithm's security and collision resistance. The Keccak-f function mapping relationship reveals the core operation logic of the algorithm, where Keccak[n] indicates the use of a Keccak-f function with a capacity of n bits, "M" represents the original input message, and "||" represents string concatenation.

[0049] The data input module is used to acquire the raw input data to be processed. In the SHA-3 algorithm, the raw input data can be any data of any size that needs to be encrypted. Data preprocessing is performed on the raw input data, including message padding according to the algorithm's rules, converting the raw input data into multiple sets of target input data, and inputting these sets of target input data into multiple iterative calculation units contained in the iterative calculation module. Each iterative calculation unit, upon receiving any set of target input data and the output result of the previous iterative calculation unit, determines the data to be calculated and the encoding identifier based on these two parameters. The data is flipped within the iterative calculation unit, i.e., 0. Flipping a bit to 1 and flipping a bit to 0 can reduce bit flipping (data bit flipping) during target computation due to the complex logic of the iterative computation unit. This results in a large number of bit flips and high power consumption. Therefore, pre-flipping can be performed using a simple hardware circuit with low power consumption to reduce the number of bit flips (data bit flips) generated during target computation and thus reduce dynamic power consumption. So, the preset flipping condition is determined by an encoding identifier. If the encoding identifier indicates that the data to be computed meets the preset pre-flipping condition, the data to be computed is pre-flipped to convert it into the inverted data to be computed. The iterative computation unit performs target computation on the inverted data to be computed and inputs the target computation result as the output to the next iterative computation unit.

[0050] Based on the above embodiments, such as Figure 2 The diagram shown is a structural schematic of a data processing system provided in an embodiment of this application. As one possible implementation, in one embodiment, the data input module includes:

[0051] The acquisition unit is used to acquire the original input data to be processed and determine the relationship between the input bit width of the original input data and the minimum data unit length of the target computing unit. When the input bit width of the original input data is less than the minimum data unit length of the target computing unit, the original input data is processed by data aggregation to obtain input data to be filled with a length equal to the minimum data unit length.

[0052] The padding unit is used to fill the input data with valid messages, resulting in grouped data whose length is an integer multiple of the length of the smallest data unit.

[0053] A grouping unit is used to group the data to be grouped, resulting in multiple sets of target input data.

[0054] The iterative calculation unit includes the target calculation unit.

[0055] Specifically, the input bit width in the acquisition unit is generally 32 bits or 64 bits, depending on the data bit width of the bus interface. The minimum data unit length of the target computing unit refers to the bit width of the minimum data unit of input data required in a single calculation when the target computing unit performs iterative operations. The specific value is determined by the type of algorithm. For example, when the target computing unit uses SHA3-224(M) in Table 1, the minimum data unit length of the target computing unit is the absorption rate r (1152) of SHA3-224(M). When the input bit width of the original input data is less than the minimum data unit length of the target computing unit, the original input data is concatenated into a large block of data that conforms to the minimum data unit length of the target computing unit through data aggregation. This data is the input data to be filled.

[0056] Specifically, effective message padding in padding units refers to adding a sequence of binary bits to the end of the data or at specific positions according to the specific rules corresponding to the algorithm type, so that the data length is an integer multiple of the minimum data unit length, thus obtaining the data to be grouped. The effective message padding rule corresponding to the SHA-3 algorithm is to add binary bits to the end of the data, specifically including: first adding one 1 bit, then padding with several 0 bits, and finally adding binary bits to identify the original data length, so that the total length of the padded data is exactly an integer multiple of the minimum data unit length, that is, an integer multiple of the rate parameter r.

[0057] Specifically, the grouping unit divides the data to be grouped into equal-length groups according to the minimum data unit length of the target computation unit, generating multiple sets of target input data that can be directly input into the iterative computation module. In the SHA-3 algorithm, the grouping unit divides the padded data to be grouped into multiple groups according to the minimum data unit length value of the target computation unit, and each group is independently input into the iterative computation module.

[0058] Accordingly, the acquisition unit can determine the relationship between the input bit width of the original input data and the minimum data unit length of the target computation unit, and then perform data aggregation processing on the original input data based on the determination result to achieve data concatenation. The filling unit can effectively fill the input data to be filled according to the specific filling rules corresponding to different algorithm types, improving the accuracy of effective data filling. The grouping unit can precisely group the filled data into equal-length groups according to the minimum data unit length to generate standard target input data, providing ideal input data for the iterative computation module, ensuring that subsequent iterative computation units can operate normally, and laying the foundation for improving computational efficiency.

[0059] Accordingly, in one embodiment, the acquisition unit is further configured to directly use the original input data as the input data to be filled when the input bit width of the original input data is equal to the minimum data unit length of the target computing unit.

[0060] Correspondingly, when the input bit width of the original input data is equal to the length of the smallest data unit of the target computing unit, data aggregation processing can be ignored, reducing the waste of resources caused by unnecessary operations when the original input data meets the requirements.

[0061] Accordingly, in one embodiment, the filling unit is specifically used to obtain the algorithm type of the target computing unit; determine the valid message filling rule according to the algorithm type; and perform valid message filling on the input data to be filled according to the valid message filling rule.

[0062] In this context, the target computation unit refers to the part of the iterative computation module that performs the algorithmic logic operations. In the SHA-3 algorithm implementation, the target computation unit refers to the computation module containing the KECCAK-f function. Different algorithm types correspond to different target computation units, and also to different effective message filling rules. Effective message filling rules refer to data filling rules that meet the algorithm requirements, can be correctly identified, processed, and achieve the expected function. The filled data content has clear semantics and can be effectively utilized by the system. Effective message filling requires adding a binary bit sequence to the end or a specific position of the input data to be filled, so that the data length reaches an integer multiple of the minimum data unit length, resulting in the data to be grouped.

[0063] Accordingly, finding the corresponding filling rules by obtaining the algorithm type of the target computing unit effectively improves the accuracy of data filling, gives the system good compatibility, and also enhances data security.

[0064] Accordingly, in one embodiment, the grouping unit is specifically used to group the data to be grouped according to the minimum data unit length to obtain multiple initial grouped data; and to fill each initial grouped data with invalid messages to obtain multiple target input data.

[0065] Specifically, the grouping unit is used to obtain the sub-function of the target calculation unit; determine the target length of the target input data based on the sub-function; and fill each initial group of data with invalid messages based on the target length of the target input data to obtain multiple sets of target length target input data.

[0066] Invalid message padding is used to expand the data to be grouped to the target length by padding with invalid data, thus ensuring that the target input data length conforms to the algorithm rules of the sub-function. The sub-function refers to the core operation function in the target computation unit. For example, the sub-function of the target computation unit SHA3-224(M) is the KECCAK-f function. Different sub-functions correspond to different input data length requirements; for example, the target input data length for the KECCAK-f function is 1600. The grouping unit determines the target length of the target input data by obtaining the sub-function of the target computation unit. The grouping unit first groups the data to be grouped according to the minimum data unit length, obtaining multiple initial grouped data sets. Then, based on the determined target length, invalid message padding is performed on each initial grouped data set to generate multiple sets of target input data with consistent lengths that meet the computation requirements of the target computation unit, which are then input into the iterative computation module.

[0067] Correspondingly, by filling in invalid information, calculation errors caused by insufficient data length are reduced, and the reliability of data processing is improved.

[0068] Based on the above embodiments, such as Figure 3 The diagram shown is a structural schematic of an iterative calculation unit provided in an embodiment of this application. As one possible implementation, in one embodiment, the iterative calculation unit includes:

[0069] The XOR unit is used to perform an XOR operation on the target input data and the output of the previous iteration calculation unit to obtain the data to be calculated.

[0070] The encoding identifier determination unit is used to perform an XOR operation on the data to be calculated and the output of the previous iteration calculation unit to obtain the target XOR result, and determine the encoding identifier based on the target XOR result.

[0071] An inverter is used to pre-flip the data to be calculated when the encoded identifier indicates that the data to be calculated meets the preset pre-flipping condition, so as to convert the data to be calculated into the inverted data to be calculated, and write the inverted data to be calculated and the encoded identifier into a register.

[0072] Registers are used to cache inverted data to be calculated and encoding identifiers;

[0073] The target calculation unit is used to access registers to obtain the data to be calculated from the registers, convert it into the inverted data to be calculated, perform target calculation on the inverted data to be calculated, and input the obtained target calculation result as the output result into the next iteration calculation unit.

[0074] Specifically, the iterative calculation module contains multiple iterative calculation units. The output of the previous iterative calculation unit refers to the result produced by the target calculation unit after completing the previous round of iterative calculation. The XOR unit performs a bitwise XOR operation between the target input data and the output of the previous iterative calculation unit, and the result is the data to be calculated. The input values ​​of the first XOR unit are the first group of target input data and the initial value. The initial value is all 0, that is, the initial value is a binary encoded sequence with all zeros of the target length.

[0075] Specifically, the encoding identifier is a 1-bit binary control signal. When m=0, the data to be calculated remains unchanged. When m=1, meaning the data to be calculated does not meet the preset pre-flipping condition, the data to be calculated is the bitwise inverted result of the original data, resulting in the inverted data to be calculated. The chip's dynamic power consumption is mainly due to the multiple dynamic signal flips during the target calculation process. Since the encoding identifier indicates that the data to be calculated meets the preset pre-flipping condition, the inverter is used to pre-flip the data to be calculated. The dynamic power consumption generated by the inverter's pre-flipping is much less than the dynamic power consumption generated by using the algorithm for target calculation. Before performing target calculation, the encoding identifier determines whether the number of data bit flips is greater if the data to be calculated is pre-flipped before the target calculation, or if the number of data bit flips is greater if no pre-flipping is performed, based on the difference between the data to be calculated and the target calculation result. This allows for flexible selection of the encoding method that minimizes dynamic power consumption.

[0076] Specifically, the dynamic power consumption generated by the pre-flipping of the inverter is much less than the dynamic power consumption generated by the algorithm's target calculation. The inverter has a simple structure, small load capacitance, and short-circuit current duration during each flip, resulting in low power consumption. However, the target calculation of the algorithm relies on a complex circuit of multiple cascaded logic gates, which triggers a large number of concurrent bit flips during operation, resulting in a cascading effect and a significant increase in the flip rate. Therefore, the dynamic power consumption generated by the algorithm's target calculation far exceeds the dynamic power consumption generated by the pre-flipping using the inverter. Thus, this system pre-flips the data to be calculated based on the encoding identifier, reducing the dynamic power consumption generated by the algorithm's target calculation. When the encoding identifier indicates that the data to be calculated meets the preset pre-flipping condition, the data to be calculated is pre-flipped using an inverter, inverting each bit of the data in parallel to convert it into inverted data, and then writing the inverted data and the encoding identifier into a register. For example, if the original value of signal A is 8'b0000_0010, and it needs to be updated to 8'b1111_0100 after the target calculation in the next clock cycle, then a total of 6 bits will be flipped, including 1-0 and 0-1, which can be simplified as generating 6 sets of dynamic power consumption. To reduce dynamic power consumption, this application uses the following scheme: First, an additional 1 bit of encoding (encoding identifier), i.e., m bits, is added. The relationship between the actual data value and the encoding bit is as follows: When m=0, the encoded value (data to be calculated) is equal to the original value; when m=1, each bit of the encoded value is equal to the bit inverted of the corresponding bit of the original value. 8'b1111_0100 can be represented in the following two ways: the first is m=0, the encoded value EN_D=8'b1111_0100; the second is m=1, the encoded value EN_D=8'b0000_1011. If this application adopts the second representation, the original value of signal A is 8'b0000_0010. In the next clock cycle, after the target calculation, it needs to be updated to 8'b1111_0100. Then, a total of 3 bits are flipped, including 1 flipped to 0 and 0 flipped to 1. This includes 2 data bit flips and 1 encoding bit flip, which can be simplified as generating 3 sets of dynamic power consumption, thus achieving power consumption reduction.

[0077] When performing the KECCAK-f function operation in the SHA-3 algorithm, the data is all 1600 bits. Therefore, the flipping involves multiple bit flips, resulting in dynamic power consumption. To reduce power consumption, data encoding is used during data storage between every two rounds of KECCAK-f function calculations, i.e., adding m encoded bits.

[0078] Specifically, the sub-functions in the target computation unit are determined by the type of algorithm. The target computation unit first accesses registers, obtaining the inverted data to be computed or the data to be computed that does not meet the pre-flipping condition from the registers as input data. In the target computation unit, the corresponding target computation is performed according to the sub-function to obtain the target computation result, which is then input as the output to the next iteration computation unit. In the target computation unit, the data to be computed or the inverted data to be computed will be flipped according to the target computation of the algorithm, resulting in dynamic power consumption. For example, the sub-function of the SHA-3 algorithm is the KECCAK-f function, and the formula for the KECCAK-f function is shown below:

[0079]

[0080] in, This represents the process of XORing the five bits in each of the two columns surrounding a given bit, and then XORing it with that bit. This indicates a cyclic shift of 25 lanes. This indicates a fixed transposition of the Slice. This indicates that bits are combined on row. This indicates that some bits of Lane(0,0) are modified. This indicates the iteration round. The SHA-3 algorithm has 24 iteration rounds, which indicates the current round. During computation, the encoded value (data to be computed / inverted data to be computed) EN_D is used to perform the above function calculation. After the calculation is completed, the output data is denoted as F_out, which is the target calculation result. The output value m remains the same as the input value, m_out = m_in, where m_out is the output value of the encoded identifier and m_in is the input value of the encoded identifier.

[0081] Correspondingly, the XOR unit and the encoding identifier determination unit can dynamically determine the encoding identifier and judge whether it is necessary to reduce dynamic switching power consumption by pre-flipping, providing a basis for judgment on reducing dynamic switching power consumption. The inverter pre-flips the data, reducing the power consumption of subsequent dynamic switching caused by the algorithm. The register's buffering function ensures the stability of data transmission, reduces dynamic power consumption, and improves the system's energy efficiency and reliability.

[0082] Accordingly, in one embodiment, the encoding identifier determination unit includes multiple XOR calculation basic units, which are used to perform XOR calculations on each data bit of the data to be calculated and the output result of the previous iteration calculation unit in parallel to obtain a target XOR result; wherein the number of data bits of the data to be calculated and the output result of the previous iteration calculation unit are the same; the adder is used to determine the number of difference data bits between the data to be calculated and the output result of the previous iteration calculation unit according to the target XOR result, and to determine the encoding identifier according to the relationship between the number of difference data bits and a preset threshold.

[0083] Specifically, the adder is used to determine the target bit width of the binary register of the target XOR result based on the number of data bits of the data to be calculated; during the XOR calculation of multiple XOR calculation basic units, the number of difference data bits is accumulated based on the target XOR result of each data bit in the binary register; the target monitoring bit is determined based on the target bit width of the binary register and a preset threshold; when the target monitoring bit indicates that the number of difference data bits is greater than the preset threshold, the encoding identifier is determined to be the target encoding; when the encoding identifier is the target encoding, the data to be calculated meets the preset pre-flip condition.

[0084] Specifically, the number of data bits in the data to be calculated and the output result of the previous iteration calculation unit are the same and correspond one-to-one. Each data bit corresponds to the target XOR result obtained by XORing. The target XOR result is input into the carry-lookahead adder for accumulation calculation, accumulating the number of difference data bits. The maximum value of the accumulated result is the total number of data bits in the data to be calculated and the output result of the previous iteration calculation unit, and the minimum value is 0. The target bit width is the number of binary bits that can represent the total number of data bits in the data to be calculated and the output result of the previous iteration calculation unit. The preset threshold is the number of data bits in the data to be calculated and the output result of the previous iteration calculation unit. Half of the total number, the binary bits in the binary register that can represent the preset threshold value are the target monitoring bits. In the process of accumulating the number of difference data bits, when all the target monitoring bits are 1, it indicates that the number of difference data bits is greater than the preset threshold. That is, when the number of signal flips generated by using the inverted data to be calculated obtained by the inverter to perform the target calculation corresponding to the algorithm is less than the number of signal flips generated by directly using the original data to be calculated to perform the target calculation, the preset pre-flip condition is met. The dynamic power consumption of the chip can be reduced by the encoding mode of data inversion, that is, the encoding identifier is determined as the target encoding, that is, the encoding identifier is set to 1.

[0085] For example, such as Figure 4The diagram shown is a structural schematic of the encoding identifier determination unit provided in an embodiment of this application. The hardware architecture of this encoding identifier calculation method consists of multiple XOR units, a carry-lookahead adder (CSA), and an encoding identifier update module. The inputs of multiple XOR units are the output of the previous iteration calculation unit and the data to be calculated. The output of the previous iteration calculation unit and the data to be calculated are XORed bit by bit. The target XOR result is input to the carry-lookahead adder for accumulation calculation, accumulating the number of difference data bits. The binary register in the carry-lookahead adder can represent the number of difference data bits. Since the difference data bits are represented by binary numbers, they can represent half of the total number of data bits of the data to be calculated and the output of the previous iteration calculation unit. The corresponding binary bits are the target monitoring bits. When all target monitoring bits are 1, it indicates that the number of difference data bits is greater than the preset threshold, indicating that more than half of the bits need to be flipped. The binary register is used to update the encoding flag, updating the value of the encoding flag to the inverse of the encoding flag value of the previous set of target calculation results, that is, 0 becomes 1 and 1 becomes 0. When the number of difference data bits is less than the preset threshold, the value of the encoding flag remains unchanged and is output to the register of the register module. For example, there are 1600 single-bit XOR units, where F_out is the output value of the previous round of function f (iterative calculation unit), i.e., the output result of the previous iteration calculation unit, function f is the sub-function of the target calculation unit, and is initialized with all zeros in the first round, Xor is the data to be calculated, Xor = F_out group_n, where This represents the XOR operation, where `group_n` represents multiple sets of target input data. The XOR value of 1600 bits, i.e., the target XOR result, is calculated using CSA accumulation, denoted as `sum_a`. `sum_a` has a maximum value of 1600 and a minimum value of 0, and can therefore be represented by a binary register with a total bit width of 11. Half the total number of bits in the data to be calculated and the output result of the previous iteration is half the total number of bits (1600), hence the preset threshold is 895. Due to the characteristics of the carry-lookahead adder, each bit of the addition result can be calculated independently. Only bits 9 to 7 of `sum_a` are calculated, denoted as `add_3`, which is the target monitoring bit; other bits are not calculated. This method saves some logic resources. Generate a new m value. If add_3=3'b111, meaning each bit of the target monitoring bit is 1, then add>895, indicating that the data to be calculated that needs to be flipped and the data bits of the output result of the previous iteration calculation unit exceed half of the total number. At this time, update the output value of the encoding identifier m to the opposite value of the m value output by the previous group of data. Here, m_pre_out represents the m value output by the previous group of data, that is, m_out=!m_pre_out, where ! represents inversion, that is, 0 is flipped to 1 and 1 is flipped to 0. Otherwise, m retains the m value output by the previous group of data, that is, m_out= m_pre_out.

[0086] For example, such as Figure 5 The diagram shown is a schematic representation of an exemplary register module provided in an embodiment of this application. The register module includes an inverter and a register. The inverter outputs the data to be calculated directly on one hand, and on the other hand, it inverts all bits of the data to be calculated to obtain the inverted data to be calculated. At the multiplexer, the encoding identifier is used to determine whether a preset pre-flip condition is met. When the encoding identifier meets the pre-flip condition, i.e., m=1, the inverted data to be calculated and the encoding identifier are input into the register of the register module. When the encoding identifier does not meet the pre-flip condition, the data to be calculated and the encoding identifier are input into the register of the register module.

[0087] Accordingly, by dynamically selecting the value of the encoding identifier based on the relationship between the number of difference data bits represented by the target XOR result and the preset threshold, the signal toggle method with lower dynamic power consumption can be flexibly selected, improving the accuracy of system power consumption optimization. By determining whether a pre-toggle is triggered based on the preset threshold, the resource consumption of full data computation is avoided, improving real-time performance and system efficiency.

[0088] Based on the above embodiments, as an implementable approach, in one embodiment, the iterative calculation unit is further configured to:

[0089] If the encoded identifier indicates that the data to be calculated does not meet the preset pre-flipping conditions, the target calculation is performed directly on the data to be calculated, and the obtained target calculation result is input as the output result into the next iteration calculation unit.

[0090] Specifically, when the number of signal flips generated by using the inverted data to be calculated obtained by the inverter to perform the target calculation corresponding to the algorithm is greater than the number of signal flips generated by directly using the original data to be calculated to perform the target calculation, the preset pre-flipping condition is not met. The dynamic power consumption generated by flipping the data to be calculated to perform the target calculation is less, so there is no need to perform pre-flipping. Then the data to be calculated is directly input into the target calculation unit for target calculation, and the target calculation result is input into the next iteration calculation unit.

[0091] Accordingly, dynamic decision-making reduces data conversion operations and flexibly adjusts processing paths, reducing unnecessary signal flipping and power consumption while ensuring data processing accuracy.

[0092] Based on the above embodiments, as one implementable approach, in one embodiment, the iterative calculation module further includes:

[0093] The extrusion unit is used to extrude the output of the last iteration calculation unit when the length of the output of the last iteration calculation unit is greater than the minimum data unit length of the target calculation unit, so as to decompose the output of the iteration calculation unit into multiple output sub-results.

[0094] The length of the output sub-result is equal to the length of the smallest data unit, and the data processing result includes multiple output sub-results.

[0095] Specifically, the squeezing unit primarily normalizes the output data of the final iteration calculation unit. When the length of the output result generated by the final iteration calculation unit exceeds the minimum data unit length of the target calculation unit, the squeezing unit initiates the squeezing process. Based on the data output rules corresponding to the algorithm, the output result generated by the final iteration calculation unit is processed, decomposing the excessively long output result into multiple output sub-results of equal length. The length of each output sub-result is consistent with the minimum data unit length, and these multiple sets of output sub-results together constitute the data processing result.

[0096] For example, such as Figure 6The diagram shown is a schematic representation of an exemplary data processing system provided in this application embodiment. It mainly includes the following steps: First, for the original input data, determine the relationship between the input bit width of the original input data and the minimum data unit length of the target computing unit. When the input bit width of the original input data is less than the minimum data unit length of the target computing unit, aggregate the original input data to obtain input data to be filled. When the input bit width of the original input data is equal to the minimum data unit length of the target computing unit, directly use the original input data as the input data to be filled. Then, fill the input data to be filled with valid messages according to the valid message filling rules of the determined algorithm type of the target computing unit to obtain data to be grouped with a length equal to an integer multiple of the minimum data unit length. Group the data to be grouped according to the minimum data unit length to obtain multiple initial grouped data. Then, fill each initial grouped data with invalid messages to obtain multiple sets of target input data. The above process belongs to the data input module, and the output result of the data input module is multiple sets of target input data. Then, multiple sets of target input data are input to the iterative calculation module. The iterative calculation module includes multiple iterative calculation units, an extrusion unit, and a result output module. Each iterative calculation unit consists of an XOR unit, an encoding identifier determination unit, an inverter, a register, and a target calculation unit. The inverter and register together form a register module. The system first inputs the initial value and the first set of target input data into the XOR unit to obtain the data to be calculated. Then, the initial value and the data to be calculated are input into the encoding identifier determination unit to obtain the target XOR result. The encoding identifier is determined based on the target XOR result. When the encoding identifier indicates that the data to be calculated meets a preset pre-flip condition, the data to be calculated is pre-flipped to obtain the inverted data to be calculated. The inverted data to be calculated and the encoding identifier are written into the register. Then, the inverted data to be calculated is input into the target calculation unit for target calculation. When the encoding identifier indicates that the data to be calculated does not meet the preset pre-flip condition, the data to be calculated and the encoding identifier are written into the register, and target calculation is performed. The target calculation result is input to the next iterative calculation unit. The second group inputs the target calculation results of the first group of iterative calculation units and the target input data of the second group into the XOR unit for calculation. The remaining process is the same as the first group of iterative units, and so on until all the target input data is input.

[0097] In the SHA-3 algorithm's processing flow, both the iterative computation unit and the extrusion unit are completed in series using the KECCAK-f function (target computation unit). The iterative computation unit absorbs the target input data and performs corresponding data processing. The input of the extrusion unit is the final target computation result output by the iterative computation unit. First, it truncates the current state according to the hash output length corresponding to the algorithm. For example, in SHA3-224, it takes 224 bits as the initial hash fragment. If more output is needed, the KECCAK-f function is executed again on the current state. Then, bits of the new hash output length are truncated and appended to the output. By repeatedly calling the KECCAK-f function and truncating fragments, multiple corresponding output sub-results are finally obtained.

[0098] Correspondingly, the problem of the output length exceeding the limit of the last iteration calculation unit can be solved by extruding the unit, decomposing the output into standardized sub-results, and ensuring the uniformity of data format.

[0099] Based on the above embodiments, as one implementable approach, in one embodiment, the system further includes:

[0100] The results output module is used to perform summary processing on the data processing results according to the encoding identifier, so as to obtain the target summary value of the data processing results and output the target summary value.

[0101] Specifically, the result output module performs digest processing on the output of the last iterative calculation unit. Digest processing refers to using algorithms to compress the data processing results into a fixed-length target digest value. The target digest value is a unique identifier for data integrity verification, identity authentication, etc. It also provides standardized data input for the next step of the operation. Based on the length of the output data, the length of the output digest value and whether to perform a subsequent extrusion stage are determined, and the final result is output. For example, the encoded value is determined based on m. When m is 0, the encoded value EN_D = Xor; when m is 1, the encoded value EN_D = ~Xor, where ~ represents a bitwise inversion operation. Xor is implemented in parallel using 1600 inverters. The encoded value EN_D and m bits are then input into a register. When outputting the digest value, the encoded value needs to be converted back to its original value. That is, when m is 1, the encoded value is bitwise inverted and assigned to the output digest value digest = ~EN_D; when m is 0, the encoded value is directly assigned to the output digest value digest = EN_D.

[0102] Correspondingly, the extrusion unit can provide standardized input data for the next step of data processing, reducing dynamic power consumption caused by non-standard data, shortening the overall processing time, improving system efficiency, and ensuring the compatibility, efficiency, and security of the data processing system.

[0103] Based on the varying power consumption impact of each bit in the algorithm, it is precisely divided into high- and low-power sensitive regions. For example, critical path data directly involved in the core operations (θ, ρ, π, χ, ι) of the KECCAK-f function in the SHA-3 algorithm are classified as high-sensitivity regions because signal flips directly affect the computation results. Fill bits and non-core operational auxiliary data, whose signal flips have minimal impact on power consumption, can be classified as low-power sensitive regions. Different encoding strategies are adopted for different regions. High-sensitivity regions strictly adhere to the original encoding rules to ensure the accuracy of the algorithm, while low-sensitivity regions can have more relaxed restrictions, allowing for higher flip thresholds to reduce unnecessary encoding flips and thus reduce logic resource consumption. While ensuring the correct operation of the SHA-3 algorithm, this approach achieves refined management of power consumption and logic resources, improving the adaptability and efficiency of the solution in different hardware environments and application scenarios. For example, the SHA-3 algorithm divides regions based on the difference in the impact of bits on the correctness of the operation and power consumption. Key bits directly involved in the core operations (θ / ρ / π / χ / ι) of the KECCAK-f function, such as bits involved in column XOR in the θ operation and the first byte causing a chain reaction of row state changes in the χ operation, have high signal flipping frequencies and directly affect the correctness of the hash result; these are classified as a high-sensitivity region, accounting for approximately 40%. Auxiliary data such as message padding bits and the last byte of non-critical lanes, whose flipping impact on power consumption is less than 30% and allows for delayed processing, are classified as a low-sensitivity region, accounting for 60%. Precise division is achieved through a pre-stored address mapping table in the chip combined with a dynamic configuration register. For the high-sensitivity region, the system provided in this application performs pre-flipping to ensure operational accuracy. For the low-sensitivity region, the preset threshold is relaxed from half the total number of data bits to 70% of the total number of data bits, and pre-flipping is only performed when add_3 ≥ 1120, reducing logic resource consumption.

[0104] The data processing system provided in this application includes a data input module and an iterative calculation module. The iterative calculation module includes multiple iterative calculation units. The data input module is used to acquire the raw input data to be processed, perform data preprocessing on the raw input data to convert it into multiple sets of target input data, and input the multiple sets of target input data into the multiple iterative calculation units respectively. The iterative calculation unit is used to determine the data to be calculated and the encoding identifier based on the target input data and the output result of the previous iterative calculation unit when it receives any set of target input data and the output result of the previous iterative calculation unit. If the encoding identifier indicates that the data to be calculated meets the preset pre-flipping condition, the data to be calculated is pre-flipped to convert it into inverted data to be calculated. The inverted data to be calculated is then used for target calculation, and the obtained target calculation result is input as the output result to the next iterative calculation unit. The target calculation includes flipping the data bits of the inverted data to be calculated, and the output result of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the raw input data. The system provided by the above solution preprocesses the original input data into multiple sets of target input data through the data input module, and inputs them into multiple iterative calculation units to obtain the data to be calculated and the encoded identifier. When the encoded identifier indicates that the data to be calculated needs to be pre-flipped, the data to be calculated is pre-flipped to obtain the inverted data to be calculated. Subsequent iterative calculation units only need to perform target calculations on the inverted data to obtain the data processing result. That is, the iterative calculation unit only needs to perform a small number of data bit flips on the inverted data to obtain the data processing result through target calculations, reducing the number of data bit flips in the target calculation and reducing dynamic flip power consumption. Compared with the power reduction methods in related technologies, this application does not require complex chip back-end layout and routing, and can ensure the chip performance and power reduction effect. Furthermore, the acquisition unit can determine the relationship between the input bit width of the original input data and the minimum data unit length of the target calculation unit, and then perform data aggregation processing on the original input data according to the judgment result to realize data splicing. The filling unit can effectively fill the input data to be filled according to the specific filling rules corresponding to different algorithm types, improving the accuracy of effective data filling. The grouping unit can precisely group the padded data into equal-length groups according to the minimum data unit length, generating standard target input data. This provides ideal input data for the iterative calculation module, ensuring the normal operation of subsequent iterative calculation units and laying the foundation for improved computational efficiency. When the input bit width of the original input data is equal to the minimum data unit length of the target calculation unit, data aggregation processing can be ignored, reducing resource waste caused by unnecessary operations when the original input data meets the requirements. Finding the corresponding padding rule by obtaining the algorithm type of the target calculation unit effectively improves the accuracy of data processing, gives the system good compatibility, and enhances data security.This reduces computational errors caused by insufficient data length, improving the reliability of data processing. The XOR unit and encoding identifier determination unit dynamically determine the encoding identifier, judging whether pre-flipping is needed to reduce dynamic flipping power consumption, providing a basis for reducing dynamic flipping power consumption. The inverter pre-flips the data, reducing subsequent dynamic flipping power consumption caused by the algorithm. The register's buffering function ensures the stability of data transmission, reduces dynamic power consumption, and improves system energy efficiency and reliability. By dynamically selecting the value of the encoding identifier based on the relationship between the number of difference data bits represented by the target XOR result and a preset threshold, the signal flipping method with lower dynamic power consumption can be flexibly selected, improving the accuracy of system power optimization. Determining whether pre-flipping is triggered by a preset threshold avoids resource consumption from all data computations, improving real-time performance and system efficiency. Dynamic decision-making reduces data conversion operations and flexibly adjusts the processing path, reducing unnecessary signal flipping and power consumption while ensuring data processing accuracy. The extrusion unit solves the problem of the output result exceeding the length limit of the final iteration calculation unit, decomposing the output result into standardized sub-results to ensure data format uniformity. The extrusion unit can provide standardized input data for subsequent data processing, reducing dynamic power consumption caused by non-standard data, shortening the overall processing time, improving system efficiency, and ensuring the compatibility, efficiency, and security of the data processing system.

[0105] Through the above description of the embodiments, those skilled in the art can clearly understand that the system according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0106] This application provides a data processing method applied to the data processing system provided in the above embodiments. The execution subject of this application embodiment is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, and other electronic devices that can be used for data processing.

[0107] like Figure 7 The diagram shown is a flowchart illustrating a data processing method provided in an embodiment of this application. The method includes:

[0108] Step 701: Obtain the raw input data to be processed;

[0109] Step 702: Perform data preprocessing on the original input data to convert the original input data into multiple sets of target input data, and input the multiple sets of target input data into multiple iterative calculation units respectively;

[0110] Step 703: Based on the iterative calculation unit, determine the data to be calculated and the encoding identifier according to the target input data and the output result of the previous iterative calculation unit;

[0111] Step 704: If the encoded identifier indicates that the data to be calculated meets the preset pre-flipping conditions, the data to be calculated is pre-flipped to convert the data to be calculated into the inverted data to be calculated.

[0112] Step 705: Perform target calculation on the inverted data to be calculated, and input the obtained target calculation result as the output result into the next iteration calculation unit;

[0113] The target calculation includes flipping the data bits of the inverted data to be calculated, and the output of the last iterative calculation unit in the iterative calculation module is the data processing result corresponding to the original input data.

[0114] For a description of the features in the embodiments corresponding to the data processing method, please refer to the relevant descriptions in the embodiments corresponding to the data processing system, which will not be repeated here.

[0115] Embodiments of this application also provide a data processing apparatus for executing the data processing method provided in the above embodiments.

[0116] like Figure 8 The diagram shown is a structural schematic of a data processing apparatus provided in an embodiment of this application. The data processing apparatus 80 includes an acquisition module 801, a data preprocessing module 802, a determination module 803, a flipping module 804, and a calculation module 805.

[0117] The system comprises the following modules: an acquisition module for acquiring the raw input data to be processed; a data preprocessing module for preprocessing the raw input data to convert it into multiple sets of target input data, which are then input into multiple iterative computation units; a determination module for determining the data to be computed and the encoding identifier based on the target input data and the output of the previous iterative computation unit; a flipping module for pre-flipping the data to be computed when the encoding identifier indicates that the data to be computed meets a preset pre-flipping condition, converting it into inverted data; and a computation module for performing target computation on the inverted data and inputting the result as the output to the next iterative computation unit. The target computation includes bit flipping of the inverted data, and the output of the last iterative computation unit in the iterative computation module is the data processing result corresponding to the raw input data.

[0118] For a description of the features in the embodiment corresponding to the data processing device, please refer to the relevant description in the embodiment corresponding to the data processing method, which will not be repeated here.

[0119] Embodiments of this application also provide an electronic device, such as... Figure 9 The diagram shown is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, including a processor 10 and a memory 20. The memory 20 stores a computer program, and the processor 10 is configured to run the computer program to perform the steps in any of the above-described data processing method embodiments.

[0120] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above data processing method embodiments when it is run.

[0121] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0122] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above data processing method embodiments.

[0123] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above data processing method embodiments.

[0124] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0125] The data processing system, method, electronic device, and storage medium provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A data processing system, characterized in that, include: A data input module and an iterative calculation module, wherein the iterative calculation module includes multiple iterative calculation units: The data input module is used to acquire the raw input data to be processed, perform data preprocessing on the raw input data to convert the raw input data into multiple sets of target input data, and input the multiple sets of target input data into the multiple iterative calculation units respectively; The iterative calculation unit is used to determine the data to be calculated and the encoding identifier based on the target input data and the output result of the previous iterative calculation unit when it receives any set of target input data and the output result of the previous iterative calculation unit. When the encoded identifier indicates that the data to be calculated meets the preset pre-flipping conditions, the data to be calculated is pre-flipped to convert the data to be calculated into inverted data to be calculated. The target calculation is performed on the inverted data to be calculated, and the target calculation result is input as the output result into the next iteration calculation unit; The target calculation includes flipping the data bits of the inverted data to be calculated, and the output of the last iteration calculation unit in the iterative calculation module is the data processing result corresponding to the original input data. The iterative calculation unit includes: The XOR unit is used to perform an XOR operation on the target input data and the output result of the previous iteration calculation unit to obtain the data to be calculated. The encoding identifier determination unit is used to perform an XOR operation on the data to be calculated and the output result of the previous iteration calculation unit to obtain a target XOR result, and determine the encoding identifier based on the target XOR result; An inverter is used to pre-flip the data to be calculated through hardware circuitry when the encoded identifier indicates that the data to be calculated meets a preset pre-flipping condition, so as to convert the data to be calculated into inverted data to be calculated, and write the inverted data to be calculated and the encoded identifier into a register. A register is used to cache the inverted data to be calculated and the encoded identifier; The target calculation unit is used to access the register to obtain the data to be calculated from the register, convert it into inverted data to be calculated, perform target calculation on the inverted data to be calculated, and input the obtained target calculation result as the output result to the next iteration calculation unit.

2. The data processing system according to claim 1, characterized in that, The data input module includes: The acquisition unit is used to acquire the raw input data to be processed and determine the relationship between the input bit width of the raw input data and the minimum data unit length of the target computing unit. When the input bit width of the raw input data is less than the minimum data unit length of the target computing unit, the raw input data is subjected to data aggregation processing to obtain input data to be filled with a length equal to the minimum data unit length. A padding unit is used to pad the input data to be filled with valid messages to obtain grouped data whose length is an integer multiple of the length of the smallest data unit; A grouping unit is used to group the data to be grouped to obtain multiple sets of target input data; The iterative calculation unit includes the target calculation unit.

3. The data processing system according to claim 2, characterized in that, The acquisition unit is further configured to: When the input bit width of the original input data is equal to the minimum data unit length of the target computing unit, the original input data is directly used as the input data to be filled.

4. The data processing system according to claim 2, characterized in that, The filling unit is specifically used for: Obtain the algorithm type of the target computing unit; Based on the algorithm type, determine the valid message filling rules; The input data to be filled is filled with valid messages according to the valid message filling rules.

5. The data processing system according to claim 2, characterized in that, The grouping unit is specifically used for: The data to be grouped is grouped according to the minimum data unit length to obtain multiple initial grouped data; Invalid messages are filled into each initial group of data to obtain multiple sets of target input data.

6. The data processing system according to claim 5, characterized in that, The grouping unit is specifically used for: Obtain the sub-functions of the target computing unit; The target length of the target input data is determined based on the sub-function. Based on the target length of the target input data, invalid messages are padded to each initial group of data to obtain multiple groups of target length target input data.

7. The data processing system according to claim 1, characterized in that, The encoding identifier determination unit includes: Multiple XOR calculation basic units are used to perform XOR calculations on each data bit of the data to be calculated and the output result of the previous iteration calculation unit in parallel to obtain the target XOR result; wherein the number of data bits of the data to be calculated and the output result of the previous iteration calculation unit are the same; An adder is used to determine the number of difference data bits between the data to be calculated and the output result of the previous iteration calculation unit based on the target XOR result, and to determine the encoding identifier based on the relationship between the number of difference data bits and a preset threshold.

8. The data processing system according to claim 7, characterized in that, The adder is specifically used for: The target bit width of the binary register of the target XOR result is determined based on the number of data bits of the data to be calculated. During the XOR calculation process of the multiple XOR calculation basic units, the number of difference data bits is accumulated based on the target XOR result of each data bit in the binary register; The target monitoring bit is determined based on the target bit width of the binary register and the preset threshold. When the number of differential data bits represented by the target monitoring bit is greater than the preset threshold, the encoding identifier is determined to be the target encoding; Wherein, when the encoding identifier is the target encoding, the data to be calculated satisfies the preset pre-flipping condition.

9. The data processing system according to claim 1, characterized in that, The iterative calculation unit is also used for: If the encoded identifier indicates that the data to be calculated does not meet the preset pre-flipping condition, the target calculation is directly performed on the data to be calculated, and the obtained target calculation result is input as the output result to the next iteration calculation unit.

10. The data processing system according to claim 1, characterized in that, The iterative calculation module further includes: The extrusion unit is used to perform extrusion processing on the output result of the last iteration calculation unit when the length of the output result of the last iteration calculation unit is greater than the minimum data unit length of the target calculation unit, so as to decompose the output result of the iteration calculation unit into multiple output sub-results; The length of the output sub-result is equal to the length of the minimum data unit, and the data processing result includes the multiple output sub-results.

11. The data processing system according to claim 1, characterized in that, The system also includes: The result output module is used to perform summary processing on the data processing result according to the encoding identifier to obtain the target summary value of the data processing result, and output the target summary value.

12. A data processing method, applied to the data processing system as described in any one of claims 1 to 11, characterized in that, The method includes: Obtain the raw input data to be processed; The original input data is preprocessed to convert it into multiple sets of target input data, and the multiple sets of target input data are respectively input into multiple iterative calculation units; Based on the iterative calculation unit, the data to be calculated and the encoding identifier are determined according to the target input data and the output result of the previous iterative calculation unit; When the encoded identifier indicates that the data to be calculated meets the preset pre-flipping conditions, the data to be calculated is pre-flipped to convert the data to be calculated into inverted data to be calculated. The target calculation is performed on the inverted data to be calculated, and the target calculation result is input as the output result into the next iteration calculation unit; The target calculation includes flipping the data bits of the inverted data to be calculated, and the output of the last iteration calculation unit in the iterative calculation module is the data processing result corresponding to the original input data. The iterative calculation unit includes: The XOR unit is used to perform an XOR operation on the target input data and the output result of the previous iteration calculation unit to obtain the data to be calculated. The encoding identifier determination unit is used to perform an XOR operation on the data to be calculated and the output result of the previous iteration calculation unit to obtain a target XOR result, and determine the encoding identifier based on the target XOR result; An inverter is used to pre-flip the data to be calculated through hardware circuitry when the encoded identifier indicates that the data to be calculated meets a preset pre-flipping condition, so as to convert the data to be calculated into inverted data to be calculated, and write the inverted data to be calculated and the encoded identifier into a register. A register is used to cache the inverted data to be calculated and the encoded identifier; The target calculation unit is used to access the register to obtain the data to be calculated from the register, convert it into inverted data to be calculated, perform target calculation on the inverted data to be calculated, and input the obtained target calculation result as the output result to the next iteration calculation unit.

13. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for implementing the steps of the data processing method as described in claim 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data processing method as described in claim 12.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the data processing method as described in claim 12.

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