Test circuit, display panel and display device

Abstract

The invention discloses a test circuit, a display panel and a display device. The test circuit comprises a substrate; the first wire layer is arranged on the substrate, and the first wire layer comprises first wires extending in the first direction; the second wire layer is located on the side, away from the substrate, of the first wire layer, the second wire layer comprises a second wire extending in the second direction, the second wire comprises an overlapping section, and the orthographic projection of the overlapping section on the substrate and the orthographic projection of the first wire layer on the substrate are at least partially overlapped; and the electrostatic discharge part is arranged on at least one side of the overlapping section in the second direction, and the electrostatic discharge part is used for discharging static electricity of the second wire. In the test circuit provided by the embodiment of the invention, the electrostatic discharge part is arranged on at least one side of the overlapping section in the second direction, and the electrostatic discharge part can discharge the static electricity on the second wire, so that the problem that the static electricity is conducted to the overlapping section to break down the first wire is solved.

Description

[0001] This application is a divisional application based on the invention with application number: 202210549077.9, application date: May 20, 2022, the applicant is Kunshan Guoxian Optoelectronics Co., Ltd., and the invention name is "Test circuit, display panel and display device". Technical Field

[0002] The present application relates to the display field, and in particular to a test circuit, a display panel and a display device. Background Art

[0003] With the continuous updating of display panel technology, small-size display panels are gradually developing towards being thin and light, with a high screen-to-body ratio, ultra-narrow bezels, or even bezel-free. Display panels with traditional structures usually include a display area and a non-display area located around the display area. In display technology, a multi-layer circuit structure is set up to reduce the size of the non-display area. However, the multi-layer circuit structure will cause the display panel to have poor anti-static damage capabilities. There will be capacitance between the two stacked wires, and static electricity may break down the wire through the capacitance, resulting in a low yield of the display panel. Summary of the invention

[0004] Embodiments of the present application provide a test circuit, a display panel, and a display device, aiming to improve the yield of the display panel.

[0005] An embodiment of the first aspect of the present application provides a test circuit, which includes: a substrate; a first wire layer, which is arranged on the substrate, the first wire layer includes a first wire extending along a first direction; a second wire layer, which is located on a side of the first wire layer away from the substrate, the second wire layer includes a second wire extending along a second direction, the second wire includes an overlapping segment, and the orthographic projection of the overlapping segment on the substrate and the orthographic projection of the first wire layer on the substrate are arranged to overlap; an electrostatic release portion, which is arranged on at least one side of the overlapping segment in the second direction, and the electrostatic release portion is used to release static electricity of the second wire.

[0006] According to an implementation scheme of the first aspect of the present application, the electrostatic release portion includes a release conductor, the release conductor includes a main body and an electrostatic release end arranged at one end of the main body, and at least part of the electrostatic release end has an orthographic projection on the substrate that at least partially overlaps with the orthographic projection of the second conductor on the substrate.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the release wire and the second wire are insulated from each other or the release wire and the second wire are connected via a via.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, the release wire is arranged in the first wire layer.

[0009] According to any of the foregoing embodiments of the first aspect of the present application, the number of electrostatic discharge terminals is multiple, and the multiple electrostatic discharge terminals are arranged side by side and spaced apart along the second direction and connected to the main body portion. The orthographic projections of each electrostatic discharge terminal on the substrate respectively overlap at least partially with the orthographic projection of the second wire on the substrate.

[0010] According to any of the foregoing embodiments of the first aspect of the present application, along the direction away from the main body portion, the extension width of the electrostatic discharge terminal in the second direction gradually decreases.

[0011] According to any of the foregoing embodiments of the first aspect of the present application, the electrostatic discharge portion further includes a discharge capacitor, and the discharge capacitor includes a first electrode plate and a second electrode plate stacked along the thickness direction of the substrate, and one of the first electrode plate and the second electrode plate is electrically connected to the discharge wire.

[0012] According to any of the foregoing embodiments of the first aspect of the present application, the first electrode plate and the discharge wire are both located in the first wire layer and are connected to each other.

[0013] According to any of the foregoing embodiments of the first aspect of the present application, the second electrode plate is located in the third wire layer, and the third wire layer is located between the first wire layer and the second wire layer.

[0014] According to any of the foregoing embodiments of the first aspect of the present application, there are at least two discharge wires, and the electrostatic discharge terminals of the at least two discharge wires are located on both sides of the overlapping section in the second direction, and the first electrode plate is connected between the discharge wires where the electrostatic discharge terminals located on both sides of the overlapping section in the second direction are located.

[0015] According to any of the foregoing embodiments of the first aspect of the present application, the overlapping area of the orthographic projections of the first electrode plate and the second electrode plate on the substrate is greater than or equal to the overlapping area of the overlapping section and the orthographic projection of the first wire on the substrate.

[0016] According to any of the foregoing embodiments of the first aspect of the present application, the number of the second wires is multiple, and the overlapping sections of the multiple second wires are arranged at intervals along the first direction, and electrostatic discharge portions are arranged on at least one side in the second direction of the overlapping sections of each second wire.

[0017] According to any of the foregoing embodiments of the first aspect of the present application, the discharge capacitors of the multiple electrostatic discharge portions are connected in parallel with each other.

[0018] According to any of the foregoing embodiments of the first aspect of the present application, the second electrode plates of the discharge capacitors of the multiple electrostatic discharge portions are connected in parallel with each other.

[0019] According to any of the foregoing embodiments of the first aspect of the present application, the test circuit further includes a power supply wire, and the second electrode plate is connected to the power supply wire.

[0020] According to any of the foregoing embodiments of the first aspect of the present application, the overlapping area of the overlapping segment and the first wire in the positive projection on the substrate is greater than or equal to 450 μm 2 .

[0021] According to any of the foregoing embodiments of the first aspect of the present application, the line width of the first wire is greater than or equal to 30 μm, and the line width of the second wire is greater than or equal to 15 μm.

[0022] According to any of the foregoing embodiments of the first aspect of the present application, the electrostatic discharge part includes a transistor, the transistor includes a source electrode, a drain electrode and a gate electrode, and the drain electrode and the gate electrode are in communication with each other;

[0023] The test circuit further includes a power supply signal line, one of the source electrode and the drain electrode of the transistor is electrically connected to the second wire, and the other is electrically connected to the power supply signal line.

[0024] According to any of the foregoing embodiments of the first aspect of the present application, the power supply signal line includes a first signal line, the source electrode is electrically connected to the second wire, the drain electrode is electrically connected to the first signal line, and the voltage on the second wire is greater than V Gh +n|V Th |, where V Gh is the voltage on the first signal line, V Th is the conduction voltage between the source electrode and the drain electrode of the transistor, and n is the number of transistors connected between the second wire and the first signal line.

[0025] According to any of the foregoing embodiments of the first aspect of the present application, the power supply signal line includes a second signal line, the source electrode is electrically connected to the second signal line, the drain electrode is electrically connected to the second wire, and the voltage on the second wire is less than V GL -m|V Th |, where V GL is the voltage on the second signal line, V Th is the conduction voltage between the source electrode and the drain electrode of the transistor, and m is the number of transistors connected between the second wire and the second signal line.

[0026] According to any of the foregoing embodiments of the first aspect of the present application, there are two or more transistors connected between the second wire and the power supply signal line.

[0027] According to any of the foregoing embodiments of the first aspect of the present application, the source electrode and the drain electrode are located in the second wire layer.

[0028] According to any of the foregoing embodiments of the first aspect of the present application, the gate electrode is located in the first wire layer.

[0029] According to any of the foregoing embodiments of the first aspect of the present application, it further includes a chip pad and a test pad, and at least part of the second wire is connected between the chip pad and the test pad;

[0030] At least one electrostatic discharge portion is located on one side of the chip pad away from the overlapping segment of the second wire it is connected to, and / or at least one electrostatic discharge portion is located between the overlapping segment and the test pad.

[0031] An embodiment of the second aspect of the present application further provides a display panel, including the test circuit of any of the above-mentioned first aspect embodiments.

[0032] According to the implementation manner of the second aspect of the present application, the display panel includes a display area and a cutting area, and at least part of the test circuit is located in the display area or the cutting area.

[0033] According to any of the above-mentioned implementation manners of the second aspect of the present application, at least part of the first wire is located in the cutting area.

[0034] According to any of the above-mentioned implementation manners of the second aspect of the present application, at least part of the electrostatic discharge portion is located in the cutting area.

[0035] According to any of the above-mentioned implementation manners of the second aspect of the present application, the first wire is a detection wire and is used to transmit data control signals.

[0036] According to any of the above-mentioned implementation manners of the second aspect of the present application, the second wire includes a clock wire.

[0037] An embodiment of the second aspect of the present application further provides a display device, formed by the display panel of any of the above-mentioned first aspect embodiments.

[0038] In the test circuit provided by the embodiment of the present application, the test circuit includes a substrate and a first wire layer, a second wire layer, and an electrostatic discharge portion provided on the substrate. The first wire layer includes a first wire, and the second wire layer includes a second wire. Since the first wire and the second wire extend in different directions, an overlapping segment of the second wire overlaps at least part of the first wire. The second wire layer is located on the side of the first wire layer away from the substrate. During the preparation process of the second wire layer, since the second wire layer is exposed to the air, static electricity is likely to be generated on the second wire layer. Since the overlapping segment of the second wire layer and the first wire layer are arranged to overlap at least part of each other, a parasitic capacitance is generated between the overlapping segment and the first wire layer, and static electricity is easily discharged through the overlapping segment to break down the first wire, resulting in poor connection of the first wire. In the test circuit provided by the embodiment of the present application, an electrostatic discharge portion is provided on at least one side of the overlapping segment in the second direction, and the electrostatic discharge portion can release the static electricity on the second wire, thereby improving the problem that static electricity is conducted to the overlapping segment to break down the first wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] By reading the following detailed description of the non-limiting embodiments with reference to the accompanying drawings, other features, objects, and advantages of the present application will become more obvious. Among them, the same or similar reference numerals represent the same or similar features, and the drawings are not drawn to actual scale.

[0040] Figure 1 A top view schematic diagram of a display panel according to an embodiment of the present application;

[0041] Figure 2 is Figure 1 A partial enlarged view of the Q region in one example;

[0042] Figure 3 is Figure 2 A partial cross-sectional view taken at F-F in;

[0043] Figure 4 is Figure 2 A partial enlarged structural schematic diagram of the P region in;

[0044] Figure 5 In another embodiment Figure 2 A partial enlarged structural schematic diagram of the P position in;

[0045] Figure 6 In yet another embodiment Figure 2 A partial enlarged structural schematic diagram of the P position in;

[0046] Figure 7 In yet another embodiment Figure 1 A partial enlarged structural schematic diagram of the Q position in;

[0047] Figure 8 is Figure 7 A partial enlarged structural schematic diagram of the I position in;

[0048] Figure 9 is Figure 7 A partial enlarged structural schematic diagram of the I position in another embodiment;

[0049] Figure 10 In yet another embodiment Figure 7 A partial enlarged structural schematic diagram of the I position in;

[0050] Figure 11 In still another embodiment Figure 7 A partial enlarged structural schematic diagram of the I position in;

[0051] Explanation of reference numerals:

[0052] 100, display panel; 100a, test circuit;

[0053] 10, substrate;

[0054] 20, first wire layer; 21, first wire;

[0055] 30, second wire layer; 31, second wire; 311, overlapping section;

[0056] 40. Electrostatic discharge part; 41. Discharge wire; 411. Electrostatic discharge end; 412. Main body part; 42. Discharge capacitor; 421. First electrode plate; 422. Second electrode plate; 43. Transistor; 431. Source electrode; 432. Drain electrode; 433. Gate electrode;

[0057] 50. Third wire layer;

[0058] 60. Power signal line; 61. First signal line; 62. Second signal line;

[0059] 70. Test pad;

[0060] 80. Chip pad;

[0061] AA. Display area; NA. Non-display area; GP. Chip pad area; CA. Cutting area; LA. Wiring area; CP. Test pad area;

[0062] X. First direction; Y. Second direction; Z. Thickness direction. Detailed implementation manners

[0063] The features and exemplary embodiments of various aspects of the present application will be described in detail below. For the purpose of making the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0064] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0065] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0066] With the continuous update of display panel technology, small-sized display panels are gradually developing towards being thinner, lighter, having a higher screen-to-body ratio, ultra-narrow bezels, and even borderless. To narrow the bezel of a display device, in related technologies, a lighting test (Cell Test; CT) circuit is disposed on the display panel on a side of an integrated circuit (IC) pin of the display device away from the display area. After the CT test is completed, the CT circuit is selectively removed by secondary cutting.

[0067] When the CT circuit is disposed below the IC pin, a scan control signal line (such as a clock signal line) will overlap with a detection wire included in the CT circuit, which results in a parasitic capacitance being formed between the scan control signal line and the detection wire. The detection wire includes, for example, a red test line for testing red sub-pixels, a green test line for testing green sub-pixels, and a blue test line for testing blue sub-pixels.

[0068] The inventors found that during the preparation process of the display panel, the scan control signal line is above the detection wire, that is, the scan control signal is prepared after the detection wire is prepared. And the scan control signal line is exposed to the air for a period of time during the manufacturing process, which makes it extremely easy for static electricity to accumulate on the scan control signal line. The static electricity will charge the parasitic capacitance formed between the scan control signal line and the detection wire. When the charge amount on the parasitic capacitance is large enough, according to ΔV = ΔQ / C, where ΔV is the voltage difference at the overlapping position of the scan control signal line and the detection wire, ΔQ is the charge amount, and C is the capacitance. When the voltage difference is large, it is extremely easy to break down the detection wire, resulting in a micro short circuit between the scan control signal line and the detection wire, and in subsequent manufacturing processes, due to heat generated by the short circuit of the trace, the display device has an abnormal screen and cannot work.

[0069] The inventors further studied and found that in the detection wire, especially in the red test line and the green test line, due to the smaller line width of the red test line and the green test line, the plate area of the parasitic capacitance is smaller. According to ΔV = ΔQ / C, the voltage difference will be larger, so the red test line and the green test line are more likely to be broken down.

[0070] To solve the above problems, embodiments of the present application provide a test circuit, a display panel, and a display device. The following will describe each embodiment of the display panel and the display device with reference to the accompanying drawings.

[0071] An embodiment of the present application provides a display panel, which may be an Organic Light Emitting Diode (OLED) display panel.

[0072] Please refer to Figures 1 to 3 , Figure 1 which shows a top view schematic diagram of a display panel 100 according to an embodiment of the present application, Figure 2 showing an example of Figure 1 a partial enlarged view of the Q area in Figure 3 and Figure 2 a cross-sectional view taken along F-F in

[0073] As Figures 1 to 3 shown, the display panel 100 provided by the embodiment of the present application includes a test circuit 100a.

[0074] There are various ways to arrange the test circuit 100a. Please continue to refer to Figures 1 to 3 , the test circuit 100a for the display panel 100 provided by the embodiment of the present application includes: a substrate 10, a first wire layer 20, a second wire layer 30, and an electrostatic discharge part 40; the first wire layer 20 is disposed on the substrate 10, and the first wire layer 20 includes a first wire 21 extending along a first direction; the second wire layer 30 is located on a side of the first wire layer 20 away from the substrate 10, the second wire layer 30 includes a second wire 31 extending along a second direction, the second wire 31 includes an overlapping section 311, and the orthographic projection of the overlapping section 311 on the substrate 10 and the orthographic projection of the first wire layer 20 on the substrate 10 are overlapped; the electrostatic discharge part 40 is disposed on at least one side of the overlapping section 311 in the second direction, and the electrostatic discharge part 40 is used to release the static electricity of the second wire 31.

[0075] In the test circuit 100a for the display panel 100 provided in the embodiment of the present application, the display panel 100 includes a substrate 10 and a first wire layer 20, a second wire layer 30 and an electrostatic release unit 40 arranged on the substrate 10. The first wire layer 20 includes a first wire 21, and the second wire layer 30 includes a second wire 31. Since the first wire 21 and the second wire 31 extend in different directions, the overlapping section 311 of the second wire 31 at least partially overlaps with the first wire 21. The second wire layer 30 is located on the side of the first wire layer 20 away from the substrate 10. During the preparation process of the second wire layer 30, since the second wire layer 30 is exposed to the air, static electricity is easily generated on the second wire layer 30. Since the overlapping section 311 of the second wire layer 30 and the first wire layer 20 are at least partially overlapped, a parasitic capacitance is generated between the overlapping section 311 and the first wire layer 20, and static electricity is easy to break through the first wire 21 through the overlapping section 311, thereby causing poor connection of the first wire 21. In the test circuit 100a provided in the embodiment of the present application, an electrostatic release portion 40 is provided on at least one side of the overlapping section 311 in the second direction. The electrostatic release portion 40 can release static electricity on the second wire 31 , thereby improving the problem of static electricity being transmitted to the overlapping section 311 and breaking through the first wire 21 .

[0076] There are many ways to set the substrate 10. Optionally, the substrate 10 includes a substrate, which can be made of a light-transmitting material such as glass or polyimide (PI). The substrate 10 can also include a support layer located on the side of the substrate away from the first wire layer 20, and the support layer can include a steel plate layer and / or a foam layer. A buffer layer and other layer structures can also be set between the substrate and the first wire layer 20.

[0077] There are many ways to set the first wire 21, for example, the first wire 21 is the detection wire CT. There are many ways to set the second wire 31, for example, the second wire 31 is the scanning control signal line GIP.

[0078] In these optional embodiments, the static electricity on the scanning control signal line GIP can be released through the static electricity release unit 40, which can reduce the amount of static electricity transmitted to the overlapping section 311, thereby improving the problem of the detection wire CT being broken down.

[0079] Optionally, the detection wire CT includes a first detection wire CT-R, a second detection wire CT-G, and a third detection wire CT-B. At least a portion of the first detection wire CT-R, the second detection wire CT-G, and the third detection wire CT-B extend along the first direction, and a portion of the first detection wire CT-R, the second detection wire CT-G, and the third detection wire CT-B extending along the first direction are arranged side by side along the second direction.

[0080] Optionally, the second wire 31 includes overlapping segments 311 that respectively overlap with the first detection wire CT-R, the second detection wire CT-G, and the third detection wire CT-B. The electrostatic discharge portion 40 is located on at least one side of all the overlapping segments 311 in the second direction to reduce the risk of being transmitted to any one of the overlapping segments 311 and breaking down any one of the first detection wire CT-R, the second detection wire CT-G, and the third detection wire CT-B.

[0081] Optionally, the scan control signal line GIP includes a first signal line ECK1, a second signal line ECK2, a third signal line SIN, a fourth signal line SCK1, and a fifth signal line SCK2. At least a part of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2 extends in the second direction, and the parts of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2 that extend in the second direction are arranged side by side in the first direction. Overlapping segments 311 are provided on each of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2, and electrostatic discharge portions 40 are provided on at least one side in the second direction of the overlapping segments 311 of each of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2.

[0082] Optionally, an insulating layer is provided between the first wire layer 20 and the second wire layer 30 to ensure insulation between the first wire 21 and the second wire 31 and prevent short-circuit connection between the first wire 21 and the second wire 31.

[0083] Optionally, please continue to refer to Figures 1 to 3 , the display panel 100 further includes a display area AA and a non-display area NA surrounding the display area AA. Both the first wire 21 and the overlapping segments 311 are located in the non-display area NA.

[0084] Please refer to Figures 2 to 4 , Figure 4 is Figure 2 a schematic diagram of a partial enlarged structure of the P region in

[0085] As Figures 2 to 4 shown, in some alternative embodiments, the electrostatic discharge portion 40 includes a discharge wire 41. The discharge wire 41 includes a main body portion 412 and an electrostatic discharge end 411 provided at one end of the main body portion 412, and at least a part of the orthographic projection of the electrostatic discharge end 411 on the substrate 10 overlaps at least partially with the orthographic projection of the second wire 31 on the substrate 10.

[0086] In these alternative embodiments, the positive projections of the static - electricity - releasing end 411 of the releasing wire 41 and the second wire 31 at least partially overlap, so that static electricity can be conducted to the static - electricity - releasing end 411 and released through the static - electricity - releasing end 411. Moreover, the setting method of the static - electricity - releasing part 40 is simple, which is convenient for the preparation of the static - electricity - releasing part 40.

[0087] There are various connection methods between the releasing wire 41 and the second wire 31. For example, an insulating layer is provided between the releasing wire 41 and the second wire 31, and the releasing wire 41 and the second wire 31 can be insulated from each other and form a parasitic capacitance setting.

[0088] Alternatively, in some other alternative embodiments, an insulating layer is provided between the releasing wire 41 and the second wire 31, and an opening is provided on the insulating layer. The releasing wire 41 and the second wire 31 are connected through a via hole, that is, the releasing wire 41 and the second wire 31 are electrically connected, so that the static electricity on the second wire 31 can be directly conducted to the releasing wire 41 and released through the releasing wire 41.

[0089] There are various setting methods for the layer position of the releasing wire 41. Optionally, the releasing wire 41 can be arranged on the same layer as the first wire 21, that is, the releasing wire 41 is located in the first - wire layer 20, so that the releasing wire 41 can be prepared synchronously with the first wire 21, which can simplify the preparation method of the display template and improve the preparation efficiency of the test circuit 100a. In some other alternative embodiments, the releasing wire 41 and the first wire 21 can also be arranged on different layers.

[0090] There are various setting methods for the static - electricity - releasing end 411. As Figure 4 shown, each releasing wire 41 can include a static - electricity - releasing end 411.

[0091] In some other alternative embodiments, please refer to Figure 2 and Figure 5 , Figure 5 which is a schematic diagram of a partial enlarged structure at P in another embodiment Figure 2 in.

[0092] In some other alternative embodiments, as Figure 2 and Figure 5 shown, the number of the static - electricity - releasing ends 411 is multiple. The multiple static - electricity - releasing ends 411 are arranged side - by - side at intervals along the second direction and connected to the main body part 412. The positive projections of the respective static - electricity - releasing ends 411 on the substrate 100 at least partially overlap with the positive projection of the second wire 31 on the substrate 100.

[0093] In these alternative embodiments, by connecting a plurality of electrostatic discharge terminals 411 to the main body portion 412, and each electrostatic discharge terminal 411 is overlapped with the second wire 31, the discharge ability of the discharge wire 41 can be improved, so that the discharge wire 41 can discharge more static electricity.

[0094] Please refer to Figure 2 and Figure 6 , Figure 6 is another embodiment Figure 2 is a schematic diagram of a partially enlarged structure at P in

[0095] In some alternative embodiments, as Figure 2 and Figure 6 shown, along the direction away from the main body portion 412, the extension width of the electrostatic discharge terminal 411 in the second direction gradually decreases. This can further improve the electrostatic discharge ability of the electrostatic discharge terminal 411.

[0096] Please continue to refer to Figure 2 , in some alternative embodiments, the electrostatic discharge portion 40 further includes a discharge capacitor 42. The discharge capacitor 42 includes a first electrode plate 421 and a second electrode plate 422 stacked along the thickness direction of the substrate 10, and one of the first electrode plate 421 and the second electrode plate 422 is electrically connected to the discharge wire 41.

[0097] In these alternative embodiments, the discharge wire 41 is connected to the first electrode plate 421 or the second electrode plate 422 of the discharge capacitor 42, so that static electricity can be conducted by the discharge wire 41 and stored in the discharge capacitor 42, which can improve the electrostatic discharge ability of the electrostatic discharge portion 40.

[0098] There are various setting positions for the first electrode plate 421 and the second electrode plate 422. In some alternative embodiments, the first electrode plate 421 and the discharge wire 41 are both located in the first wire layer 20 and are electrically connected. Such a setting enables the first electrode plate 421, the discharge wire 41, and the first wire 21 to be fabricated and formed in the same process step, which can effectively improve the fabrication efficiency of the test circuit 100a.

[0099] Optionally, the second electrode plate 422 is located in the third wire layer 50, and the third wire layer 50 is located between the first wire layer 20 and the second wire layer 30. That is, the second electrode plate 422 is located on the side of the third wire layer 50 facing the substrate 10. During the fabrication process of the test circuit 100a, when the second wire layer 30 is exposed to the air, it can prevent the second electrode plate 422 from being exposed to the air, thereby avoiding the accumulation of static electricity on the second electrode plate 422, so that the discharge capacitor 42 can store more static electricity accumulated on the second wire 31.

[0100] In some other embodiments, the third wire layer 50 can also be located between the first wire layer 20 and the substrate 10.

[0101] Optionally, a first insulating layer is provided between the first wire layer 20 and the third wire layer 50, and a second insulating layer is provided between the third wire layer 50 and the second wire layer 30 to ensure that the first wire 21, the first electrode plate 421, the second wire 31, and the second electrode plate 422 are insulated from each other in pairs.

[0102] In some optional embodiments, there are at least two release wires 41, and the static electricity release ends 411 of the at least two release wires 41 are located on both sides of the overlapping section 311 in the second direction.

[0103] In these optional embodiments, release wires 41 are correspondingly provided on both sides of the overlapping section 311 in the second direction. Therefore, the static electricity generated on both sides of the overlapping section 311 in the second direction can be reduced from being conducted to the position where the overlapping section 311 is located, further improving the static electricity release ability of the static electricity release portion 40 and improving the problem that the first wire 21 is broken down.

[0104] Optionally, the first electrode plate 421 is connected between the release wires 41 where the two static electricity release ends 411 located on both sides of the overlapping section 311 in the second direction are located. This enables the static electricity generated on both sides of the overlapping section 311 in the second direction to be conducted to the release capacitor 42, further improving the static electricity release ability of the static electricity release portion 40 and better improving the problem that the first wire 21 is broken down.

[0105] In some optional embodiments, the overlapping area of the overlapping section 311 and the projection of the first wire 21 on the substrate 10 is greater than or equal to 450μm 2 . For example, the overlapping area of the overlapping section 311 and the projection of the first wire 21 on the substrate 10 is 15μm×30μm; or the overlapping area of the overlapping section 311 and the projection of the first wire 21 on the substrate 10 is 15μm×45μm; or the overlapping area of the overlapping section 311 and the projection of the first wire 21 on the substrate 10 is 15μm×60μm. In these optional embodiments, the larger the overlapping area of the overlapping section 311 and the projection of the first wire 21 on the substrate 10, the larger the parasitic capacitance C formed between the overlapping section 311 and the first wire 21. According to ΔV = ΔQ / C, the pressure difference formed between the overlapping section 311 and the first wire 21 is smaller, and it is less likely to be broken down.

[0106] Optionally, the line width of the first wire 21 is greater than 30μm. The line width of the second wire 31 is usually 15μm. When the line width of the first wire 21 is greater than 30μm, it can ensure that the overlapping area of the overlapping section 311 and the projection of the first wire 21 on the substrate 10 is greater than or equal to 450μm 2 , and it is less likely to be broken down. Optionally, the line width of the second wire 31 is greater than or equal to 15μm.

[0107] In some alternative embodiments, the overlapping area of the orthographic projections of the first electrode plate 421 and the second electrode plate 422 on the substrate 10 is greater than or equal to the overlapping area of the overlapping section 311 and the first wire 21 on the substrate 10. This enables the capacitance of the discharge capacitor 42 to be greater than the capacitance of the parasitic capacitor formed by the overlapping section 311 and the first wire 21, further reducing the load at the parasitic capacitor and thus improving the problem of the first wire 21 being broken down.

[0108] There are various ways to set the number of the second wires 31. For example, the number of the second wires 31 can be only one.

[0109] In some other alternative embodiments, the number of the second wires 31 is multiple. For example, as described above, the second wires 31 may include a first signal line ECK1, a second signal line ECK2, a third signal line SIN, a fourth signal line SCK1, and a fifth signal line SCK2. The first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2 all include an overlapping section 311, and the overlapping sections 311 of the first signal line ECK1, the second signal line ECK2, the third signal line SIN, the fourth signal line SCK1, and the fifth signal line SCK2 are arranged at intervals along a first direction. That is, the overlapping sections 311 of the multiple second wires 31 are arranged at intervals along the first direction, and an electrostatic discharge portion 40 is provided on at least one side of each overlapping section 311 of the second wires 31 in a second direction.

[0110] In these alternative embodiments, the number of the second wires 31 is multiple, and the second wires 31 all overlap with the first wire 21 to form overlapping sections 311. The overlapping sections 311 of each second wire 31 overlap with different positions of the first wire 21, and there is a risk of the different positions of the first wire 21 being broken down by the parasitic capacitor. In this embodiment, an electrostatic discharge portion 40 is provided on at least one side of each overlapping section 311 in the second direction, which can improve the risk of different positions on the first wire 21 being broken down.

[0111] Optionally, the second electrode plates 422 of the discharge capacitors 42 of the multiple electrostatic discharge portions 40 are connected in parallel with each other. This enables the static electricity on different second electrode plates 422 to conduct to each other, further improving the static electricity discharge ability of the electrostatic discharge portion 40.

[0112] In some alternative embodiments, the test circuit 100a further includes a power supply line Vdd, and the second electrode plate 422 is connected to the power supply line. The power supply line has the characteristic of stable signal, enabling the signal on the discharge capacitor 42 to be stable and avoiding the disturbance caused by the unstable signal of the discharge capacitor 42.

[0113] Please refer to Figure 1 、 Figures 7 to 9 , Figure 7In yet another embodiment Figure 1 is a schematic diagram of a partial enlarged structure at Q in Figure 8 Figure 7 is a schematic diagram of a partial enlarged structure at I in Figure 9 Figure 7 is a schematic diagram of a partial enlarged structure at I in another embodiment.

[0114] In some other embodiments, such as Figure 1 Figures 7 to 9 shown, the electrostatic discharge part 40 includes a transistor 43, the transistor 43 includes a source electrode 431, a drain electrode 432 and a gate electrode 433, and the drain electrode 432 and the gate electrode 433 are interconnected; the test circuit 100a further includes a power supply signal line 60, and one of the source electrode 431 and the drain electrode 432 of the transistor 43 is electrically connected to the second wire 31, and the other is electrically connected to the power supply signal line 60.

[0115] In these alternative embodiments, when static electricity is generated on the second wire 31, the static electricity on the second wire 31 can be conducted to the power supply signal line 60 through the transistor 43. The type of the transistor 43 can be an N-type transistor or a P-type transistor. In the embodiments of the present application, the transistor 43 is taken as an example of a P-type transistor for illustration.

[0116] There are various ways to set the power supply signal line 60, such as Figure 8 shown, the power supply signal line 60 can be the first signal line 61, the source electrode 431 is electrically connected to the second wire 31, and the drain electrode 432 is electrically connected to the first signal line 61. For example, when there are n transistors 43 connected between the second wire 31 and the first signal line 61, if the voltage V 31 on the second wire 31 is greater than V Gh + n|V Th |, then n transistors 43 are turned on, and the voltage on the second wire 31 will pass through n transistors 43 to the first signal line 61. Therefore, the voltage V 31 on the second wire 31 is less than or equal to V Gh + n|V Th |. Where V Gh is the voltage on the first signal line 61. For example, the first signal line 61 is a high-level signal line, V Gh is 7V, and V Th is the conduction voltage between the source electrode 431 and the drain electrode 432 of the transistor 43.

[0117] In these alternative embodiments, by reasonably setting the number of transistors 43, that is, by changing the number of n in V Gh + n|V Th |, the voltage V 31 on the second wire 31 can be limited to an appropriate voltage value. ​​​

[0118] In some other embodiments, as Figure 9 shown, the power supply signal line 60 may be the second signal line 62, the source 431 is electrically connected to the second signal line 62, and the drain 432 is electrically connected to the second wire 31.

[0119] In these alternative embodiments, when there are m transistors 43 connected between the second wire 31 and the second signal line 62, if the voltage V on the second wire 31 31 is less than V GL -m|V Th |, then the m transistors 43 are turned on, and the voltage of the second signal line 62 will pass through the m transistors 43 to the second wire 31. Therefore, the voltage V on the second wire 31 31 is greater than or equal to V GL -m|V Th |, where V GL is the voltage on the second signal line 62. For example, the second signal line 62 is a low-level signal line, V GL is -7V, and V Th is the conduction voltage between the source 431 and the drain 432 of the transistor 43.

[0120] In these alternative embodiments, by reasonably setting the number of transistors 43, that is, by changing the number of m in V GL -m|V Th |, the voltage V on the second wire 31 31 can be limited to a suitable voltage value.

[0121] Please refer to Figure 7 and Figure 10 , Figure 10 is a schematic diagram of the partial enlarged structure at I in Figure 7 in another embodiment.

[0122] Optionally, as Figure 7 and Figure 10 shown, the power supply signal line 60 may include both the first signal line 61 and the second signal line 62. In these embodiments, when the electrostatic potential energy on the second wire 31 is higher than that of the first signal line 61, the static electricity can be conducted to the first signal line 61. When the static electricity on the second wire 31 is lower than that of the first signal line 61, the holes on the second signal line 62 can be conducted to the second wire 31 and neutralize the static electricity on the second wire 31 to reduce the static electricity. The static voltage on the second wire 31 is greater than or equal to V GL -|V Th |, and less than or equal to V Gh +|V Th |.

[0123] Optionally, as Figure 11As shown, there are more than two transistors 43 connected between the second wire 31 and the power signal wire 60. For example, two transistors 43 are provided between the second wire 31 and the second signal wire 62, and two transistors 43 are provided between the second wire 31 and the first signal wire 61. Then, the static voltage on the second wire 31 is greater than or equal to V GL -2|V Th |, and less than or equal to V Gh +2|V Th |. The static potential on the second wire 31 can be limited within a smaller range.

[0124] Optionally, the source electrode 431 and the drain electrode 432 are located in the second wire layer 30, so that the second wire 31 can be fabricated in the same process as the source electrode 431 and the drain electrode 432, and it is convenient for the second wire 31 to be connected to the source electrode 431 or the drain electrode 432.

[0125] Optionally, the gate electrode 433 is located in the first wire layer 20, so that the gate electrode 433 can be fabricated in the same process as the first wire 21, which helps to improve the fabrication efficiency of the test circuit 100a.

[0126] Optionally, the transistor 43 further includes a first semiconductor portion, and the test circuit 100a further includes a driving transistor TFT. The driving transistor TFT includes a second semiconductor portion. The first semiconductor portion and the second semiconductor portion are arranged on the same layer, so that the first semiconductor portion and the second semiconductor portion can be fabricated in the same process, which can further improve the fabrication efficiency of the test circuit 100a.

[0127] Optionally, the source electrode 431 and the drain electrode 432 of the driving transistor can be arranged on the same layer as the source electrode 431 and the drain electrode 432 of the transistor 43. The gate electrode 433 of the driving transistor can be arranged on the same layer as the gate electrode 433 of the transistor 43, which can further improve the fabrication efficiency of the test circuit 100a.

[0128] In some alternative embodiments, the test circuit 100a further includes a chip pad 80 and a test pad 70, and at least a part of the second wire 31 is connected between the chip pad 80 and the test pad 70.

[0129] There are various arrangement positions of the electrostatic discharge portion 40. For example, at least one electrostatic discharge portion 40 is located on one side of the overlapping section of the chip pad 80 away from the second wire 31 connected thereto to discharge the static electricity generated on the chip pad 80.

[0130] And / or, at least one electrostatic discharge portion 40 is located between the overlapping section 311 and the test pad 70. It can discharge the static electricity generated by the test pad 70 and reduce the amount of static electricity conducted from the test pad 70 to the overlapping section 311.

[0131] And / or, at least one electrostatic discharge portion 40 is located between the overlapping section 311 and the chip pad 80, which can reduce the amount of static electricity conducted from the chip pad 80 to the overlapping section 311.

[0132] Optionally, please continue to refer to Figure 3 , in the direction away from the display area AA, the non-display area NA includes a chip pad area GP, a cutting area CA, a routing area LA, and a test pad area CP arranged in sequence. The chip pad 80 is located in the pad area GA, the first wire 21 is located in the routing area LA, and the test pad 70 is located in the test pad area CP. When cutting the display panel 100 to form a display panel, the routing area LA and the test pad area CP can be cut away to achieve a narrow border design of the display panel.

[0133] In some alternative embodiments, the display panel 100 further includes a cutting area CA, and at least part of the test circuit 100a is located in the cutting area CA. When cutting the display panel 100 to form a display device, at least part of the test circuit 100a can be cut away, which can reduce the area of the non-display area of the display device and achieve a narrow border design of the display device.

[0134] Optionally, the electrostatic discharge portion 40 is located in the cutting area CA. When cutting the display panel 100 to form a display device, the electrostatic discharge portion 40 can be cut away, which can reduce the area of the non-display area of the display device and achieve a narrow border design of the display device.

[0135] Optionally, the display panel 100 can be a display mother board including a plurality of display areas AA, and the display mother board includes the above-mentioned cutting area CA. When processing the display mother board to form a display board for preparing a display screen, the above-mentioned electrostatic discharge portion 40 can be cut, that is, the display board for preparing a display screen may not include the electrostatic discharge portion 40.

[0136] Optionally, in some other embodiments, the display panel 100 can also be a display board for preparing a display screen, that is, the display panel 100 does not include the cutting area CA, and the electrostatic discharge portion 40 can also be located in the non-cutting area of the display panel 100, that is, the electrostatic discharge portion 40 can be a display board for preparing a display screen.

[0137] In some alternative embodiments, the first wire 21 is located in the cutting area CA. When cutting the display panel 100 to form a display device, the first wire 21 can be cut away, which can reduce the area of the non-display area of the display device and achieve a narrow border design of the display device.

[0138] As described above, the first wire 21 can be a detection wire and is used to transmit a control signal. The first wire 21 is used to perform a lighting test on the display device before the display device is formed by cutting. Since the first wire 21 is not required during the use of the display device, the first wire 21 can be located in the cutting area CA.

[0139] An embodiment of the present invention further provides a display device. The display device includes the display panel of any one of the above first aspect embodiments. Therefore, the display device provided by the second aspect embodiment of the present invention has the beneficial effects of the display panel of any one of the above first aspect embodiments, which will not be elaborated herein.

[0140] The display device in the embodiment of the present invention includes, but is not limited to, devices with a display function such as mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control devices, smart landline phones, consoles, etc.

[0141] According to the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to only the specific embodiments. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A test circuit, characterized in that, include: substrate; A first wire layer, disposed on the substrate, the first wire layer comprising first wires extending along a first direction; A second conductor layer is located on a side of the first conductor layer away from the substrate, the second conductor layer includes a second conductor extending along a second direction, the second conductor includes an overlapping segment, and an orthographic projection of the overlapping segment on the substrate overlaps with an orthographic projection of the first conductor layer on the substrate; an electrostatic release portion, disposed on at least one side of the overlapping section in the second direction, the electrostatic release portion being used to release static electricity of the second conductive line; The electrostatic discharge unit includes a transistor, the transistor includes a source, a drain and a gate, and the drain and the gate are electrically connected; The test circuit further comprises a power signal line, one of the source and the drain of the transistor is electrically connected to the second wire, and the other is electrically connected to the power signal line; The power supply signal line includes a first signal line, the source electrode is electrically connected to the second wire, the drain electrode is electrically connected to the first signal line, and the voltage on the second wire is greater than V Gh +n|V Th |, where V Gh is the voltage on the first signal line, V Th is the conduction voltage between the source and drain electrodes of the transistor, and n is the number of transistors connected between the second wire and the first signal line; And / or, the power supply signal line includes a second signal line, the source is electrically connected to the second signal, the drain is electrically connected to the second wire, and the voltage on the second wire is less than V GL -m|V Th |, where V GL is the voltage on the second signal line, V Th is the conduction voltage between the source and the drain of the transistor, and m is the number of transistors connected between the second wire and the second signal line.

2. The test circuit according to claim 1, characterized in that, The overlapping area of the overlapping segment and the orthographic projection of the first conductor on the substrate is greater than or equal to 450 μm 2 ; And / or, the line width of the first conductive line is greater than or equal to 30 μm, and the line width of the second conductive line is greater than or equal to 15 μm.

3. The test circuit according to claim 1, wherein Two or more transistors are connected between the second conductive line and the power signal line.

4. The test circuit according to claim 1, characterized in that The source electrode and the drain electrode are located in the second wiring layer.

5. The test circuit according to claim 1, characterized in that The gate is located in the first conductive line layer.

6. The test circuit according to claim 1, wherein Also comprising a chip pad and a test pad, at least part of the second wire is connected between the chip pad and the test pad; At least one of the electrostatic release portions is located on a side of the chip pad away from the overlapping section of the second conductive line connected thereto; And / or, at least one of the electrostatic release portions is located between the overlapping section and the test pad.

7. A display panel, characterized in that, The display panel comprises the test circuit according to any one of claims 1-6.

8. The display panel according to claim 7, wherein The display panel includes a display area and a cutting area, and at least a portion of the test circuit is located in the display area or the cutting area.

9. The display panel according to claim 8, wherein, The first conductive wire is located in the cutting area; and / or, the electrostatic release portion is located in the cutting area; And / or, the first wire is a detection wire and is used to transmit a data control signal; And / or, the second conductor includes a clock conductor.

10. A display device, characterized in that, Comprising a display panel as described in any one of claims 7 to 9.

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