Programmable frequency divider applied to JESD204B / C

Abstract

The invention relates to a programmable frequency divider applied to JESD204B / C. The programmable frequency divider comprises a prescaler which realizes 1 / 2 / 4 dynamic frequency division through a closed-loop feedback structure; according to the 12-bit main frequency divider, the duty ratio of odd-even frequency division is controlled by a 11-stage asynchronous CML frequency-halving chain and a separation DFF0 module; the frequency dividing ratio N is equal to DIV Nlt; 11: 0gt; 2, the odd number frequency division duty ratio is automatically adjusted to (N + 1) / 2N; the cascade noise optimization comprises the following steps of: resampling by using an input clock fin through a retiming trigger (RetimeDFF1 / 2); according to the pulse generator, the number K of pulses output by a four-stage counter is equal to Pulsecount; 3: 0gt; a decimal value; and the output mode circuit supports three-mode direct connection. According to the programmable frequency divider, the HBT process CML unit and the emitter follower are adopted for buffering; and the high-precision clock synchronization requirements of JESD204B / C systems such as a 5G base station and a millimeter wave radar can be met.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency divider circuit design, and particularly to a programmable frequency divider applied to JESD204B / C. Background Art

[0002] As the sampling rate of analog-to-digital converters (ADCs) breaks through the Gbps level, traditional parallel interfaces based on low-voltage differential signaling (LVDS) are difficult to meet the requirements of high-speed data transmission. The problem of high-speed data synchronization transmission between multi-channel ADCs and FPGAs has become increasingly prominent. In this context, the JESD204B interface protocol proposed by the Solid State Technology Association provides an innovative solution to the above technical bottleneck.

[0003] SYSREF is a global reference signal for system-level synchronization in the JESD204B / C standard. Its frequency usually needs to have an integer division relationship with the system master clock (Device Clock) and needs to meet the subclass requirements specified in the JESD204B / C protocol (e.g., Subclass 1 / 2 requires periodic SYSREF). When multiple devices share the same clock source, it is necessary to generate SYSREF with consistent phases within their respective chips to avoid synchronization deviations caused by transmission delays. Therefore, a frequency divider is required to convert the high-frequency system clock (Device Clock) into a SYSREF frequency that complies with the protocol specifications, and it is necessary to ensure the programmable division ratio characteristic of the frequency divider to support precise control of the triggering interval of SYSREF pulses. Its design directly affects the synchronization accuracy and reliability of the JESD204B / C system, especially in high-speed and multi-channel scenarios.

[0004] Therefore, it is necessary to propose a programmable frequency divider with multiple-mode outputs and high-speed wideband to be applicable to the JESD204B / C system to overcome the above technical problems. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a programmable frequency divider applied to JESD204B / C, including cascaded: Prescaler: A closed-loop feedback is formed by two D flip-flops and two multiplexers (MUX1, MUX2). The input clock fin is connected to the CLK terminal of the first D flip-flop and the input terminal of MUX1. The output of MUX1 drives the D terminal of the second D flip-flop. The output buffer is fed back to MUX2, and the output of MUX2 is fed back to the D terminal of the first D flip-flop to output fpre_div; 12-bit Programmable Divider: 11-stage asynchronous CML divide-by-two modules (DFF1~DFF11) are cascaded. The CLK terminal of DFF1 is driven by fpre_div. The Q output terminal of the i-th stage (2≤i≤10) divide-by-two circuit DFFi is connected to the clock input terminal of the (i + 1)-th stage divide-by-two circuit TFFi+1 and one input terminal of the i-th AND gate ANDi. Separate DFF0 module: The least significant bit S0 of the preset signal is connected to the preset S terminal of the divide-by-two module DFF0 with preset. Its Q terminal and the Q terminal of DFF1 drive the reset logic chain through an exclusive-OR gate XOR. Reset Logic Chain: It includes multiple AND gates and retimed D flip-flops. Among them, AND gates AND1~AND10 are cascaded for detection. The other input terminal of the i-th stage (1≤i≤9) AND gate ANDi is connected to the output terminal of the (i + 1)-th stage AND gate ANDi+1. The output terminal of AND1 is connected to the data input D terminal of the retimed D flip-flop Retime DFF1. The output is synchronized by the retimed flip-flop Retime DFF1 to generate a global set signal CD. Output Channel: The Q output terminal of Retime DFF1 is connected to the clock input CLK terminal of the divide-by-two circuit Div_2 DFF. After division by two, it is output from the Q output terminal of Div_2 DFF. The Q output terminal of Div_2 DFF is connected to the data input D terminal of the retimed D flip-flop Retime DFF2. The clock input CLK terminal of Retime DFF2 is connected to the initial input clock fin. The Q output terminal of Retime DFF2 outputs the divided frequency signal fdiv. Pulse Generator: 4-stage CML divide-by-two modules are cascaded. The first stage CLK terminal is driven by fdiv. The output of the last stage AND gate chain (AND1~AND3) controls the TFF module to generate pulses. Output Mode Selection Circuit: Through the combination of MUX1~MUX4 and AND gates, it selects to directly pass fdiv, pulse signal or fSYSREFQ output.

[0006] In an embodiment of the present invention, the closed-loop feedback of the prescaler realizes dynamic frequency division: MUX1 selects fin or the Q output of the first D flip-flop; MUX2 selects the Q of the second D flip-flop or the feedback signal of the output buffer.

[0007] In an embodiment of the present invention, the 12-bit programmable divider satisfies: the division ratio N = (DIV_N<11:0>) + 2; when N is odd, the duty cycle of fdiv ≠ 50%.

[0008] In an embodiment of the present invention, in the reset logic chain: the second input terminal of ANDi (i = 1~9) is connected to the output terminal of ANDi+1; the CLK terminals of Retime DFF1 / 2 are directly connected to the initial clock fin.

[0009] In one embodiment of the present invention, the CML frequency division by two module includes: a preset differential conversion circuit (inverter chain I1 - I2 driving MOS transistors M1 - M2); a master - slave latch (sampling transistors Q3 - Q4 / Q9 - Q10 + cross - coupled transistors Q5 - Q6 / Q11 - Q12); an emitter - follower output buffer (Q1 - Q2).

[0010] In one embodiment of the present invention, the logic in the output mode selection circuit includes the following three modes: Mode 1: MUX1 selects a high level → AND4 directly passes fdiv → MUX3 selects the Retime DFF output; Mode 2: MUX1 selects TFF Q → AND4 generates N pulses → MUX3 selects a high level; Mode 3: MUX4 directly passes fSYSREFQ.

[0011] In one embodiment of the present invention, the tail current source of the CML frequency division by two module is composed of bias transistors Q21 - Q26, and the Bias voltage drives the bases uniformly.

[0012] In one embodiment of the present invention, the number of pulses K of the pulse generator is equal to the decimal value of Pulse_count<3:0> (range 1 - 16, note: no pulses are output when all are 0), as follows Figure 7 shown; where the hardware implementation logic is that the number of falling edges output by AND1 = the decimal value of Pulse_count, and each falling edge triggers the TFF to generate a pulse.

[0013] In one embodiment of the present invention, the overall frequency division range covers 2 - 16380 (prescaler × main frequency divider), and the duty - cycle accuracy is ±1%.

[0014] In one embodiment of the present invention, the duty cycle during odd - numbered frequency division is (N + 1) / 2N.

[0015] The above technical solution of the present invention has the following advantages compared with the prior art: The programmable frequency divider of the present invention is based on a CML divide-by-two circuit with a set function. By cascading and multiplexing it, a 12-bit programmable frequency divider and a pulse generator are realized. Then, by combining a prescaler and an output mode selection circuit, a programmable frequency divider with multiple output modes that can implement signal generator, pulse generator, and repeater modes is formed, expanding the frequency division ratio range and output modes of the frequency divider composed of traditional pulse counters. At the same time, the requirements for different duty cycles of odd and even frequency divisions of the 12-bit programmable frequency divider can be realized. When dividing by an odd number, the duty cycle of the divided signal is not equal to 50%. In order to increase the maximum operating frequency of the frequency divider, an HBT process with a high cut-off frequency and low phase noise is adopted to improve the traditional divide-by-two circuit, introducing an output buffer circuit to reduce the output load of the node and further increase the operating frequency. Therefore, this type of programmable frequency divider has a high maximum operating frequency, a wide frequency division range, and selectable output modes, and is suitable for JESD204B / C systems. Moreover, further, it has irreplaceability in scenarios of system clock management in actual high-speed data conversion systems, high-end test and measurement instruments, medical imaging equipment, optical communication systems, aerospace avionics, etc. >10GHz, especially meeting the stringent synchronization requirements of JESD204B / C Subclass 1 for periodic SYSREF. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the content of the present invention easier to be clearly understood, the present invention will be further described in detail below with reference to the specific embodiments of the present invention and the accompanying drawings.

[0017] Figure 1 is a schematic structural diagram of the programmable frequency divider of the present invention applied to JESD204B / C; Figure 2 is a schematic structural diagram of the prescaler of the present invention; Figure 3 is a schematic structural diagram of the 12-bit programmable frequency divider of the present invention; Figure 4 is a schematic structural diagram of the CML divide-by-two circuit with a set function of the present invention; Figure 5 is a schematic structural diagram of the pulse generator and the output mode selection circuit of the present invention; Figure 6 is a schematic timing diagram of the implementation principle of the duty cycle (N + 1) / 2N = 66.6% when the frequency division ratio N = 3 of the present invention; Figure 7 is a corresponding diagram of the number of pulses K of the pulse generator of the present invention and the decimal value of Pulse_count<3:0>; Figure 8It is the corresponding diagram of the implementation mode selection logic of the output mode selection circuit in the present invention. Detailed implementation manners

[0018] As Figure 1 shown, this embodiment provides a programmable frequency divider applied to JESD204B / C, which internally includes a cascaded prescaler, a 12-bit programmable frequency divider, a pulse generator, and an output mode selection circuit.

[0019] It can implement the functions of a signal generator, a pulse generator, and a repeater, output various mode signals, be applied to the JESD204B / C system, and achieve a high speed, a wide frequency division range, and a flexible and controllable frequency division ratio.

[0020] The circuit structure of the prescaler is as Figure 2 shown, and it includes two CML-structured D flip-flops and two 1-bit multiplexers. It is used to perform prescaling on the input signal, select the prescaling value based on the input signal frequency, and select the output signal of the multiplexer through the signal PRE_DIV<1:0> signal, and can select to divide the input signal by 1, 2, or 4. The input signal fin is input to the clock CLK terminals of the two CML-structured D flip-flops and the signal input terminal of the first 1-bit multiplexer MUX1; the output Q terminal of the first D flip-flop is connected to the other signal input terminal of the first 1-bit multiplexer MUX1; the signal output terminal of the first 1-bit multiplexer MUX1 is connected to the data D terminal of the second D flip-flop and the input terminal of the output buffer Buffer; the output Q terminal of the second D flip-flop is connected to the signal input terminal of the second 1-bit multiplexer MUX2; the output terminal of the output buffer Buffer outputs the prescaled signal fpre_div, and at the same time, it is connected to the other signal input terminal of the second 1-bit multiplexer MUX2; the signal output terminal of the second 1-bit multiplexer MUX2 is connected to the data D terminal of the first D flip-flop, forming a feedback path to achieve frequency division of the input signal.

[0021] Specifically, the frequency division logic is: 00: MUX1 selects fin → direct output (1 division) 01: MUX1 selects the Q output of DFF1 → DFF2 performs 2 division → outputs a 2-divided signal 10: MUX2 selects the fpre_div feedback signal → DFF1 and DFF2 are cascaded to achieve 4 division The circuit structure of the 12-bit programmable frequency divider is as Figure 3As shown, it includes a 12-bit pulse counter and a reset logic detection circuit. The 12-bit pulse counter includes 11 divide-by-two modules with preset that are cascaded using asynchronous logic, and controls the odd / even division ratio by separating the least significant bit. Each divide-by-two circuit DFF includes a CLK input terminal (i.e., the clock input terminal), an S input terminal (i.e., the preset terminal), a CD input terminal (i.e., the preset control terminal), and a Q output terminal. The clock input terminal of the first divide-by-two circuit DFF1 is connected to the clock signal fpre_div generated after prescaling. The Q output terminal of the i-th (2 ≤ i ≤ 10) divide-by-two circuit DFFi is connected to the clock input terminal of the (i + 1)-th divide-by-two circuit TFFi+1 and one input terminal of the i-th AND gate ANDi. The Q output terminal of the last divide-by-two circuit DFF11 is only connected to one input terminal of the 10th AND gate AND10. The preset S terminals of the i-th (1 ≤ i ≤ 11) divide-by-two circuits DFFi are respectively connected to the preset signals Si. The output Q terminal of the first divide-by-two circuit DFF1 is connected to one input terminal of the exclusive OR gate XOR. The least significant bit S0 of the preset signal is separated and connected to the preset S terminal of the divide-by-two module DFF0 with preset. The output Q terminal of DFF0 is connected to the other input terminal of the exclusive OR gate XOR. The output terminal of XOR is connected to one input terminal of the first AND gate AND1. The reset logic detection circuit is composed of multiple AND gates and retimed D flip-flops, and controls the set control signal CD by detecting the output signals of each divide-by-two module. Since the stages of the frequency divider are not directly driven by the input clock, there will be an accumulation of phase noise generated by cascading. Therefore, a retimed D flip-flop is used to retime the output clock so that the phase noise is only determined by it. The other input terminal of the i-th (1 ≤ i ≤ 9) AND gate ANDi is connected to the output terminal of the (i + 1)-th AND gate ANDi+1. The output terminal of the first AND gate AND1 is connected to the data input D terminal of the retimed D flip-flop Retime DFF1. The clock input CLK terminal of Retime DFF1 is connected to the initial input clock fin. The output Q terminal of Retime DFF1 is connected to the input terminal of the inverter INV and the clock input CLK terminal of the divide-by-two module DFF0 with preset. The output terminal of INV is connected to the set control CD terminal of the i-th (1 ≤ i ≤ 11) divide-by-two circuit DFFi to control the input of the preset signal, and further control the working state of the divide-by-two circuit.After passing through the retimed D flip-flop, the output signal then passes through a separate stage of a divide-by-two circuit, and finally the output signal achieves 12-bit programmable frequency division. The Q output of RetimeDFF1 is connected to the clock input CLK of the divide-by-two circuit Div_2 DFF. After frequency division by two, it is output from the Q output of Div_2 DFF. The Q output of Div_2 DFF is connected to the data input D of the retimed D flip-flop Retime DFF2. The clock input CLK of Retime DFF2 is connected to the initial input clock fin, and the Q output of Retime DFF2 outputs the frequency-divided signal fdiv.

[0022] The cumulative phase noise of the 11-stage asynchronous frequency division chain among them is > -120 dBc / Hz @ 1 MHz offset. Use RetimeDFF1 / 2 to resample the frequency-divided signal with pure fin, and the output phase noise фout = фfin, which has nothing to do with the cascaded chain. The effect is that the phase noise is optimized to -152 dBc / Hz (5 GHz input, 0.13μm HBT process).

[0023] In this example, due to the separation of the least significant bit in the 12-bit pulse counter, when the 12-bit pulse counter is actually loaded, it is for bits 1 to 11. The signal is divided by two once after passing through the logic detection circuit to obtain the output signal after 12-bit frequency division. Therefore, when considering the counting period of the pulse counter, the complete counting period should be the period during which the reset signal experiences two changes from low level to high level. It can be understood that the divide-by-two circuit DFF is a loadable CML divide-by-two circuit. After receiving the load signal that meets the loading condition, it allocates load values to each stage of the divide-by-two circuit DFF based on the preset division ratio. The initial output value of the Q output terminal of each stage of the divide-by-two circuit DFF is the above-mentioned load value. Under the action of the clock signal received at the clock input terminal of each stage of the divide-by-two circuit DFF, the Q output terminal of each stage of the divide-by-two circuit DFF will be adjusted accordingly. It can be understood that the clock signal received at the clock input terminal of the first-stage divide-by-two circuit DFF1 is the signal output by the clock source, and for other divide-by-two circuits, such as the second-stage divide-by-two circuit DFF2 to the eleventh-stage divide-by-two circuit DFF11, the clock signal received at the clock input terminal is the signal corresponding to the actual output value output by the Q output terminal of its previous-stage divide-by-two circuit DFF. Exemplarily, if the division ratio is even, the least significant bit S0 is set to 0. The working process of the pulse counter is as follows: First, set the 11-bit pin input to (S11S10...S2S1)B. When starting to count, the counting state will be the same as the state when the reset signal is high level, that is, all the initial values will be inverted. Subsequently, the pulse counter starts to perform an increment operation and counts up to a total of (S11S10...S2S1)B counting states. After passing through the retiming D flip-flop and delaying for one clock cycle, the final pulse count value S is (S11S10...S2S1)B + 1. The above process is repeated in the second reset period. Therefore, the total division ratio is (S11S10...S2S1S0)B + 2. If the division ratio is odd, the least significant bit is set to S01. In the first reset period, it counts up to a total of (S11S10...S2S1)B + 1 counting states. After passing through the retiming D flip-flop and delaying for one clock cycle, the final pulse count value s is (S11S10...S2S1)B + 2. The counting in the second reset period is the same as when the division ratio is even, and the pulse count value S is (S11S10...S2S1)B + 1. Therefore, the total division ratio is (S11S10...S2S1S0)B + 2. Generally speaking, if the 12-bit load pin value is set to (S11S10...S2S1S0)B, the final division ratio is (S11S10...S2S1S0)B + 2. It should be noted that when it is odd, the duty cycle of the divided signal is not equal to 50%.

[0024] Specifically, the division ratio calculation: Programming value DIV_N<11:0> = S11 S10... S1 S0 (binary); Actual division ratio N = (S11~S0)2 + 2; Among them, the duty cycle control: when N is even (S0 = 0), the output duty cycle is 50%; among them, DFF0 is forced to output a high level → the XOR gate is equivalent to a buffer → the reset signal is aligned with the rising edge of the clock; When N is odd (S0 = 1), the output duty cycle is (N + 1) / 2N (for example, when N = 5, the duty cycle is 60%); specifically, DFF0 introduces a half-cycle delay → the duty cycle is automatically adjusted to (N + 1) / 2N.

[0025] For example, the timing example (N = 3) (duty cycle 66.6%) is as follows Figure 6 shown; The CML frequency divider circuit structure with set is as Figure 4As shown, it includes a preset circuit, a master-slave latch, a set control circuit and an output buffer circuit. Its main structure is a CML-structured D flip-flop, which is composed of two cascaded CML latches. The input differential signals CLK+ and CLK- are respectively connected to the bases of Q16, Q18 and Q15, Q19, and the bias voltage Bias is connected to the bases of Q21, Q22, Q23, Q24, Q25, Q26 to ensure the generation of a stable tail current source. The preset signal S is connected to the input terminal of the inverter I1, and the signal SN output from the output terminal of the inverter I1 is connected to the input terminal of the inverter I2 and the gate of the amplification transistor M2. The output terminal of the inverter I2 is connected to the gate of the amplification transistor M1. The sources of M1 and M2 are grounded, and the drains are respectively connected to one end of the resistors R7 and R8, and the other ends of the resistors are connected to the emitters of the bias transistors Q21 and Q22. The collectors of the bias transistors Q21 and Q22 are respectively connected to one end of the pull-up resistors R1 and R2, and the other ends of R1 and R2 are connected to the power supply voltage VDD to realize the differential input of the preset signal. The set control signal CD is connected to the bases of Q17 and Q20. The emitters of Q17 and Q20 are respectively connected to the collectors of the tail current transistors Q23 and Q24. The set control signal controls the input of the preset circuit signal through the differential pair. The emitters of the differential pair Q7 and Q8 are connected to the collector of Q17. The bases of Q7 and Q8 are respectively connected to the collectors of the bias transistors Q21 and Q22. The collectors of Q7 and Q8 are respectively connected to the collectors of Q3 and Q4. The emitters of the differential pair Q13 and Q14 are connected to the collector of Q20. The bases of Q13 and Q14 are respectively connected to the collectors of the bias transistors Q21 and Q22. The collectors of Q13 and Q14 are respectively connected to the collectors of Q9 and Q10 to form a signal path for the transmission of the preset signal. When the CD terminal is at a high level, the frequency divider stops working, and the signal at the S terminal undergoes level conversion through the preset circuit and the output buffer circuit to the output terminal to complete the preset step; when the CD terminal is at a low level, the master-slave latch is in a normal working state, and the circuit enters a divide-by-two state. The CML-structured D flip-flop is composed of two cascaded CML-structured latches. The CML latch circuit is composed of a sampling circuit and a cross-coupling circuit. The signal is differentially input from the bases of the sampling transistors and differentially output from the collectors. The bases of the sampling pair transistors Q3 and Q4 are respectively connected to the collectors of the sampling transistors Q9 and Q10. The emitters of Q3 and Q4 are connected to the collector of Q15. The bases of the sampling pair transistors Q9 and Q10 are respectively connected to the collectors of the sampling transistors Q3 and Q4. The emitters of Q9 and Q10 are connected to the collector of Q18.The sampling tube is connected to the latch tube of the cross-coupling structure, which locks the signal collected at the previous moment and sends the collected signal to the next stage when the clock signal arrives at the next moment. The base of Q5 is connected to the collector of Q6, and the base of Q6 is connected to the collector of Q5 to form a cross-coupled pair of tubes. The collectors of the cross-coupled pair of tubes Q5 and Q6 are respectively connected to the collectors of Q3 and Q4, and the emitters of Q5 and Q6 are connected to the collector of Q16; the base of Q11 is connected to the collector of Q12, and the base of Q12 is connected to the collector of Q11 to form a cross-coupled pair of tubes. The collectors of the cross-coupled pair of tubes Q11 and Q12 are respectively connected to the collectors of Q9 and Q10, and the emitters of Q11 and Q12 are connected to the collector of Q19. The pull-up resistors, the voltage drops generated by which will limit the output swing of the circuit, and the self-resonant condition of the loop is also realized by detecting the current flowing through the resistors. One ends of the pull-up resistors R3 and R4 are respectively connected to the collectors of Q3 and Q4, and the other ends are connected to the power supply voltage VDD. One ends of the pull-up resistors R5 and R6 are respectively connected to the collectors of Q9 and Q10, and the other ends are connected to the power supply voltage VDD. The clock input tube is connected to the tail current tube, which is controlled by an external bias to provide a stable operating current for the circuit. The collector of the tail current tube Q23 is connected to the emitters of the clock input pair of tubes Q15 and Q16 and the emitter of the set control tube Q17. The emitter of Q23 is connected to one end of the resistor R9, and the other end of the resistor R9 is grounded. The collector of the tail current tube Q24 is connected to the emitters of the clock input pair of tubes Q18 and Q19 and the emitter of the set control tube Q20. The emitter of Q24 is connected to one end of the resistor R10, and the other end of the resistor R10 is grounded. An output buffer circuit is added at the output end to reduce the output load of the node and set the output common-mode level, which can further increase the operating frequency. The buffer circuit is actually an emitter follower. The bases of the common-collector amplifier tubes Q1 and Q2 are connected to the collectors of the sampling pair of tubes Q9 and Q10 to form an output signal transmission path. The collectors of Q1 and Q2 are connected to the power supply voltage VDD. The emitters of Q1 and Q2 are respectively connected to the output signal Q- and Q+ terminals, and are also respectively connected to the collectors of Q25 and Q26. The emitters of Q25 and Q26 are respectively connected to one ends of the resistors R11 and R12, and the other ends of R11 and R12 are grounded. The frequency division by two circuit is actually the simplest sequential state machine with only two states (Q = 0, Q = 1). The QN output terminal of the D flip-flop is fed back to the D input, and the output state of the circuit is reversed along with the rising edge (or falling edge) of the clock signal and circulates in 2 states, thus realizing the function of frequency division by two.

[0026] Specifically, the implementation speed advantages of the CML frequency division by two unit module are as follows: the emitter follower reduces the output capacitive reactance (50fF → 5fF); the cross-coupling structure accelerates the flip (delay < 5ps).

[0027] The pulse generator and the output mode selection circuit structure are asFigure 5 As shown, the main structure of the pulse generator is a 4-bit pulse counter, which realizes pulse counting through the combination of 4 two-frequency division modules and AND gates. The output mode selection circuit selects the output mode through the combination of multiple 1-of-2 data selectors and AND gates. The 4-bit pulse counter circuit includes multiple levels of CML two-frequency division circuits DFF with preset, and each level of the two-frequency division circuit DFF includes a CLK input terminal (i.e., the clock input terminal), an S input terminal (i.e., the preset terminal), a CD input terminal (i.e., the preset control terminal), and a Q output terminal. The clock input terminal of the first-level two-frequency division circuit DFF1 is connected to the clock signal fdiv generated after being divided by a 12-bit programmable frequency divider. The Q output terminal of the i-th level (i≥2) two-frequency division circuit DFFi is connected to the clock input terminal of the (i + 1)-th level two-frequency division circuit TFFi+1 and one input terminal of the i-th level AND gate ANDi. The Q output terminal of the last-level two-frequency division circuit DFF is only connected to one input terminal of the third-level AND gate AND3. The output terminal of the third-level AND gate AND3 is connected to the other input terminal of the second-level AND gate AND2. The output terminal of the second-level AND gate AND2 is connected to the other input terminal of the first-level AND gate AND1. The output terminal of the first-level AND gate AND1 is connected to the output terminal of the output buffer Buffer, and the output terminal is connected to the CLK terminal of the two-frequency division module TFF. The output waveform of the Q terminal of the output terminal of TFF determines the output waveform width, and further determines the number of output pulses in the pulse generator mode. The output mode selection circuit includes multiple 1-of-2 data selectors and AND gates. The high-level signal High level is connected to one of the input terminals of the data selectors MUX1 and MUX2. The other input terminals of MUX1 and MUX2 are connected to the output Q terminal of TFF, and the output signal of the pulse generator is transmitted to the subsequent circuit. The output terminal of the data selector MUX1 is connected to one of the input terminals of the AND gate AND4. The other input terminal of AND4 is connected to the output signal fdiv of the frequency divider. The output terminal of AND4 is respectively connected to one of the input terminals of the AND gate AND5 and the data input D terminal of the retiming D flip-flop Retime DFF. The clock CLK terminal of Retime DFF is connected to the initial input signal fin. The output Q terminal of Retime DFF is connected to one of the input terminals of the data selector MUX3. The other input terminal of MUX3 is connected to the output terminal of the data selector MUX2. The output terminal of MUX3 is connected to one of the input terminals of the AND gate AND5. The other input terminal of AND5 is connected to the output terminal of the AND gate AND5. The output terminal of AND5 is connected to one of the input terminals of the data selector MUX4. The other input terminal of MUX4 is connected to the initially provided SYSREFQ signal fSYSREFQ. The output terminal of MUX4 outputs the final output signal fOUT.

[0028] As Figure 5As shown, the programmable frequency divider circuit has three output modes, which are controlled by an output mode selection circuit. Specifically, the mode<1:0> signal controls the 1-of-2 data selector in the output mode selection circuit to select and process the input signal from the previous stage, thereby outputting waveforms of different modes. Mode 1 is the signal generator mode. In this mode, the data selector MUX1 selects to output a high-level signal High level. This signal and the frequency divider output signal fdiv are logically ANDed by the AND gate AND4, and the resulting signal is the same as fdiv. After passing through the retiming D flip-flop Retime DFF, the signal still remains the same as fdiv. The data selector MUX2 selects to output the signal transmitted by the pulse generator, and the data selector MUX3 selects to output the signal at the D terminal of the retiming D flip-flop Retime DFF. The signal output by MUX3 and the signal output by AND4 are logically ANDed, and the resulting output signal is the same as fdiv. MUX4 selects to output the signal output by AND5, so that the final output signal directly outputs the frequency divider output signal, and the output waveform is a continuous pulse. Mode 2 is the pulse generator mode. In this mode, the data selector MUX1 selects to output the signal output by the pulse generator, which is actually a pulse signal. The pulse width is the period of the selected number of pulses N and the fdiv output signal. This signal and the frequency divider output signal fdiv are logically ANDed by the AND gate AND4, and the resulting signal is the pulse signal of the selected number. The pulse duration and frequency are respectively equal to the duty cycle and frequency output by the frequency divider. After passing through the retiming D flip-flop Retime DFF, the signal is the same as the signal output by AND4. The data selector MUX2 selects to output a high-level signal Highlevel, the data selector MUX3 selects to output a high-level signal, and the data selector MUX4 selects to output the signal output by AND5. The signal output by MUX3 and the signal output by AND4 are logically ANDed, and the resulting output signal is the same as the signal output by AND4. Therefore, the final output signal is a 4-bit pulse of the selected number. Mode 3 is the repeater mode. The prescaler and the frequency divider do not work. The data selector MUX4 selects to output the SYSREFREQ signal, so that the circuit directly outputs the SYSREFREQ signal.

[0029] The input clock signal is input to the input terminal of the prescaler, and the prescaler division ratio is controlled by the PRE_DIV<1:0> signal; after the prescaler prescales the input clock, it is input to a 12-bit programmable divider, and the 12-bit programmable divider division ratio is controlled by the DIV_N<11:0> signal; the signal after being divided by the 12-bit programmable divider is simultaneously input to the pulse generator module and the output mode selection module; the pulse generator gates the divider and outputs a selectable number of 4-bit pulses, and the pulse duration and frequency are respectively equal to the duty cycle and frequency of the divider output, and the number of output pulses is controlled by the Pulse_count<3:0> signal; the signal passing through the pulse generator, the signal passing through the 12-bit programmable divider, and the SYSREFREQ signal are input to the output mode selection circuit together, and which signal to output is controlled by the Mode_select<1:0> signal.

[0030] Specifically, Figure 5 The pulse generator on the left implements pulse control logic: the Q output terminals of DFF1~DFF4 → the input terminals of the AND gate chain (AND1~AND3); The output terminal of AND1 → buffer (Buffer) → the CLK terminal of the TFF module.

[0031] Another timing synchronization mechanism: the CLK of the TFF is triggered by the falling edge of the output of AND1; each falling edge → the TFF outputs a complete pulse period; the counter is reset at the rising edge of fdiv to ensure that the pulse burst is strictly aligned with the clock.

[0032] And Figure 5 The output mode selection circuit on the right implements mode selection logic, specifically as follows Figure 8 shown; Another anti-glitch design is that the Mode_select signal is buffered by the fin synchronous register, and the mode switch only occurs at the clock falling edge.

[0033] In summary, the divider in this embodiment is a digital circuit module that divides the input signal frequency into different output signals according to a specific integer ratio. Its core function is to achieve precise frequency division by adjusting the cascaded structure of flip-flops, and it is commonly used in scenarios such as clock synchronization, frequency synthesis, and signal modulation and demodulation. Dividers can be classified into three typical categories according to the circuit structure: current mode logic (CML), injection locking (IL), and true single-phase clock (TSPC), and they show significant differences in key indicators such as power consumption, speed, design complexity, and robustness.

[0034] In the present invention, due to the high number of bits, it is necessary to ensure that each frequency division module has a small delay to ensure the correct overall frequency division function. Therefore, a programmable frequency divider is designed using a CML structure with high-speed characteristics.

[0035] For further illustration, the working process of the frequency divider in this embodiment is a scenario example for generating a 125 MHz SYSREF signal in a 5G base station (system clock fin = 5 GHz): Prescaler: PRE_DIV = 10 (divide by 4) → fpre_div = 1.25 GHz Main frequency division: Target frequency division ratio: 5000 MHz / 125 MHz = 40 → DIV_N = 38 (binary 0010 0110) S0 = 0 (even) → duty cycle 50% Pulse mode: Pulse_count = 0011 (K = 3 pulses) Output mode: Mode_select = 01 (pulse generator mode) → output 3 125 MHz pulses.

[0036] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A programmable frequency divider applied to JESD204B / C, characterized in that, Including cascaded ones: Prescaler: A closed-loop feedback is formed by two D flip-flops and two multiplexers. The input clock fin is connected to the CLK terminal of the first D flip-flop and the input terminal of MUX1. The output of MUX1 drives the D terminal of the second D flip-flop. The output buffer is fed back to MUX2, and the output of MUX2 is fed back to the D terminal of the first D flip-flop, and the output is fpre_div; 12-bit programmable divider: 11-stage asynchronous CML divide-by-two modules are cascaded. The fpre_div drives the CLK terminal of DFF1. The Q output terminal of the divide-by-two circuit DFFi at the i-th stage (2 ≤ i ≤ 10) is connected to the clock input terminal of the divide-by-two circuit TFFi+1 at the i+1-th stage and one of the input terminals of the AND gate ANDi at the i-th stage; Separate DFF0 module: The least significant bit S0 of the preset signal is connected to the preset S terminal of the divide-by-two module DFF0 with preset. Its Q terminal and the Q terminal of DFF1 drive the reset logic chain through an exclusive OR gate XOR; Reset logic chain: It includes multiple AND gates and retimed D flip-flops. Among them, the AND gates AND1~AND10 are cascaded for detection. The other input terminal of the AND gate ANDi at the i-th stage (1 ≤ i ≤ 9) is connected to the output terminal of the AND gate ANDi+1 at the i+1-th stage. The output terminal of AND1 is connected to the data input D terminal of the retimed D flip-flop RetimeDFF1. The output is synchronized by the retimed flip-flop Retime DFF1 to generate a global set signal CD; Output channel: The Q output terminal of Retime DFF1 is connected to the clock input CLK terminal of the divide-by-two circuit Div_2 DFF. After division by two, it is output from the Q output terminal of Div_2 DFF. The Q output terminal of Div_2 DFF is connected to the data input D terminal of the retimed D flip-flop Retime DFF2. The clock input CLK terminal of Retime DFF2 is connected to the initial input clock fin. The Q output terminal of Retime DFF2 outputs the divided signal fdiv; Pulse generator: 4-stage CML divide-by-two modules are cascaded. The fdiv drives the first-stage CLK terminal, and the output of the last-stage AND gate chain controls the TFF module to generate pulses; Output mode selection circuit: Through the combination of MUX1~MUX4 and AND gates, it selects to directly pass fdiv, pulse signal or fSYSREFQ output.

2. The programmable frequency divider according to claim 1, characterized in that: The closed-loop feedback of the prescaler realizes dynamic frequency division: MUX1 selects fin or the Q output of the first D flip-flop; MUX2 selects the Q of the second D flip-flop or the feedback signal of the output buffer.

3. The programmable frequency divider according to claim 1, wherein: The 12-bit programmable divider satisfies: The division ratio N = (DIV_N<11:0>) + 2; When N is odd, the duty cycle of fdiv ≠ 50%.

4. The programmable frequency divider according to claim 1, wherein: In the reset logic chain: The second input terminal of ANDi (i = 1~9) is connected to the output terminal of ANDi+1; The CLK terminals of Retime DFF1 / 2 are directly connected to the initial clock fin.

5. The programmable frequency divider according to claim 1, wherein: At the same time, the CML divide-by-two module includes: A preset differential conversion circuit; A master-slave latch; An emitter follower output buffer.

6. The programmable frequency divider according to claim 1, characterized in that: The logic in the output mode selection circuit includes the following three modes: Mode 1: MUX1 selects the high level → AND4 directly passes fdiv → MUX3 selects the output of the Retime DFF; Mode 2: MUX1 selects the TFF Q → AND4 generates N pulses → MUX3 selects the high level; Mode 3: MUX4 directly passes fSYSREFQ.

7. The programmable frequency divider according to claim 5, wherein: The tail current source of the CML frequency divider by two module is composed of bias transistors Q21 - Q26, and the Bias voltage drives the bases uniformly.

8. The programmable frequency divider according to claim 1, wherein: The number of pulses K of the pulse generator is equal to the decimal value of Pulse_count<3:0>.

9. The programmable frequency divider according to claim 1, wherein: The overall frequency division range covers 2 to 16380.

10. The programmable frequency divider according to claim 3, wherein: When dividing by an odd number, the duty cycle is (N + 1) / 2N.

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