Transaction model with one frame and multiple packets and without inter-frame flow and verification platform thereof
By designing a transaction model with multiple packets in one frame and no flow between frames and its verification platform, the high-reliability testing problem of FPGA algorithm module is solved, and the rapid and efficient testing of multiple modules is achieved, which improves the testing efficiency and accuracy.
Patent Information
- Application Number
- CN202510536362.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-27
- Publication Date
- 2025-07-25
AI Technical Summary
In the prior art, high reliability testing of FPGA algorithm modules is difficult to achieve, especially the verification platforms of non-particular accumulation modules, matrix multiplication vector modules, matrix inversion modules and covariance matrix calculation modules lack effective methods.
A transaction model and verification platform with multiple frames and non-flow between frames is designed. UVM verification methodology is adopted. Data transmission is realized by combining configuration interfaces, input interfaces and output interfaces. A verification environment generator, test scenario generator and axis packet generator are introduced into the UVM verification platform to build test components to achieve fast and highly reliable testing.
It realizes fast and highly reliable testing of FPGA algorithm modules such as non-particular accumulation modules, matrix multiplication vector modules, matrix inversion modules, and covariance matrix calculation modules, improving testing efficiency and accuracy.
Smart Images
Figure CN120378022A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of signal processing, and particularly relates to a transaction model with multiple packets per frame and no pipelining between frames and its verification platform. Background Art
[0002] In the current field of signal processing, FPGA algorithm modules widely use the standard AXI stream bus as the input / output interface form. For example, most of the algorithm IP cores provided by FPGA manufacturer Xilinx use input and output interfaces in the form of the AXI stream bus, such as the FFT IP core, floating-point operation IP core, and so on.
[0003] The transmission of the standard AXI stream bus is simple and efficient, and consists of four signals: tdata, tvalid, tready, and tlast. Among them, tdata is a multi-bit data line, and tvalid, tready, and tlast are single-bit control lines.
[0004] The AXI stream bus stream data transmission is packet-based, and the tlast signal is used as the mark for the end of each data packet.
[0005] In order to achieve highly reliable testing of FPGA algorithm modules, a verification platform based on UVM is established. UVM is a set of verification methodologies based on the SystemVerilog language launched by Accellera in 2010. It divides the verification platform into test components such as sequence generators, drivers, monitors, scoreboards, reference models, input agents, and output agents. The UVM verification platform has a rigorous structure, complete functions, and high reliability compared with traditional test verification methods, and can achieve relatively ideal test verification effects.
[0006] The high-level verification platform based on the transaction model implemented by the UVM verification methodology requires the establishment of a transaction model of the FPGA module as a prerequisite for building a verification platform for the FPGA module. Due to the complexity of its computing structure, the input and output of the FPGA algorithm module have different transmission structures. Summary of the Invention
[0007] Aiming at the above problems, the object of the present invention is to solve the above problems existing in the prior art, establish a transaction model with multiple packets per frame and no pipelining between frames, and design UVM test components based on this transaction model to implement a general UVM verification platform, which can be used to test many FPGA algorithm modules that conform to the transmission structure of this transaction model, such as non-coherent accumulation modules, matrix-vector multiplication modules, matrix inversion modules, covariance matrix calculation modules, etc.
[0008] To achieve the above object, the technical solution adopted by the present invention is: a transaction model with multiple packets per frame and no pipelining between frames, based on an FPGA algorithm module, including multiple input interfaces, output interfaces, and a configuration interface; the data transmission transaction of the algorithm module is in units of frames. Each transaction first inputs a configuration data packet from the configuration interface of the algorithm module, then inputs several data packets from the input interfaces, and then outputs several data packets from the output interface of the algorithm module. Without waiting for all the input data packets of this frame on the input interface to be input, the data packets can be started to be output on the output interface. However, before all the output data packets of a frame are output, the transmission of the configuration data packet of the next frame cannot be started first, that is, there is no pipelining between frames. The number of data packets on the input interface and the output interface does not need to be equal.
[0009] Except for the clock signal and the reset signal, the configuration interface, input interface, and output interface of the algorithm module need to conform to the AXI stream standard.
[0010] The present invention also provides a verification platform for a transaction model with multiple packets per frame and no pipelining between frames, including preset configuration parameters and multiple test components. The test components include a verification environment generator, a test scenario generator, and an axis data packet generator; The verification environment generator includes a configuration interface agent, several input interface agents, several output interface agents, a reference result generator, and a scoreboard; there is a configuration sequence monitoring channel between the configuration interface agent and the reference result generator, called configuration sequence monitoring channel A; there is a configuration sequence monitoring channel between the configuration interface agent and the scoreboard, called configuration sequence monitoring channel B; there is an input sequence monitoring channel between each input interface agent and the reference result generator, an output sequence monitoring channel between each output interface agent and the scoreboard, and a reference sequence transmission channel between the reference result generator and the scoreboard; The test scenario generator is connected to the configuration interface agent and the input interface agent respectively through virtual configuration sequences, and each time it generates an axis data packet by calling the data packet generator; The axis data packet generator can generate axis configuration data packets and axis input data packets, and input them to the configuration interface agent and the input interface agent respectively through the test scenario generator.
[0011] The configuration interface agent includes an axis configuration sequence generator, an axis configuration interface driver, an axis bus monitor, and there is a configuration sequence occurrence channel between the configuration sequence generator and the configuration interface driver; Axis configuration interface driver: Wait for a packet to be available in the configuration sequence occurrence channel. When a configuration packet is obtained, drive the data, along with the tvalid and tlast signals, onto the axis configuration interface according to the axis protocol.
[0012] The input interface agent: Each input interface agent has an axis input interface; the input interface agent includes an axis input sequence generator, an axis input interface driver, and an axis bus monitor, and there is an input sequence occurrence channel between the input sequence generator and the input interface driver. Axis input interface driver: Wait for a packet to be available in the input sequence occurrence channel. When an input packet is obtained, drive the data, along with the tvalid and tlast signals, onto the axis input interface according to the axis protocol.
[0013] The output interface agent: Each output interface agent has an axis output interface. The output interface agent includes an axis output interface driver and an axis bus monitor; the axis output interface driver drives the tready signal according to a preset intermittent mode; the axis bus monitor is common to the axis input interface and the axis output interface. It uses the tlast signal as the end marker of the packet, grabs one packet on the axis bus each time, and inserts it into the monitoring channel.
[0014] The reference result generator waits for a packet to be available in the configuration sequence monitoring channel A. When a configuration packet is obtained, it starts receiving input packets for one frame. It waits for a packet to be available in the input sequence monitoring channel. When the specified number of input packets for that frame is obtained, it calls the algorithm reference model of the algorithm module to calculate the reference result packet and sends it to the reference sequence transmission channel.
[0015] The algorithm reference model is the reference model of the algorithm module under test. It receives one configuration packet and a number of input packets for one frame each time, and calculates a number of reference result packets according to the specified algorithm. When there are multiple input interfaces and multiple output interfaces, it receives the specified number of input packets on each input interface, and generates the specified number of reference packets on each output interface.
[0016] The scoreboard waits for a data packet to be available in the configuration sequence monitoring channel B. After obtaining a configuration data packet, it starts receiving output data packets for one frame, and waits for data packets to be available in the output sequence monitoring channel and the reference sequence transmission channel. When the specified number of output data packets and reference result data packets for this frame are obtained, the two types of data packets are compared one by one, and a conclusion on whether the test is correct is determined according to the comparison result. When there are multiple output interfaces, the specified number of output data packets and reference data packets are received and compared for each output interface, and the test is considered correct only when all the comparisons on all output interfaces are correct. Then, the test conclusion is printed and displayed, or printed to a file.
[0017] The test scenario generator is provided with a virtual configuration sequence, which is hooked to the sequence generator of the configuration interface agent, and several virtual sequences are established according to the number of input interfaces, which are hooked to the sequence generators of each input interface agent. Each time the test scenario generator generates an axis data packet by calling the axis data packet generator, generates data packets for each input interface according to the predetermined number of packets, and transmits them to the sequence generators of each input interface agent through the virtual sequence channel.
[0018] The axis data packet generator: Can generate an axis configuration data packet according to the specified configuration data packet length and configuration data range, or read data from the specified data file to form an axis configuration data packet; Can generate several axis input data packets according to the specified data packet length and data range, or read data from the specified data file to form several axis input data packets.
[0019] The configuration parameters include: the number of input interfaces of the module under test; the number of output interfaces of the module under test; the configuration data packet length on the configuration interface; each configuration data range or specific data file on the configuration interface; the number of test frames; the number of input data packets for one frame of each input interface; the number of output data packets for one frame of each input interface; the test data packet length of each input interface; the test data range or specific data file of each input interface; the tready intermittent mode of each output interface.
[0020] Compared with the prior art, the technical solution adopted by the present invention has the following beneficial effects: The present invention establishes an FPGA algorithm module transaction model with multiple packets per frame and no inter-frame pipelining, which can be applied to many FPGA algorithm modules such as non-coherent accumulation modules, matrix-vector multiplication modules, matrix inversion modules, covariance matrix calculation modules, etc. Based on this transaction model, UVM test components are designed, and a verification platform test framework based on the UVM verification methodology is established to achieve fast and highly reliable testing of FPGA algorithm modules that conform to this transaction model. Description of the Drawings
[0021] Figure 1 This is a schematic diagram of the FPGA algorithm module framework for one frame with multiple packets in this embodiment.
[0022] Figure 2 This is a schematic diagram of the composition of the AXI stream bus signals in this embodiment.
[0023] Figure 3 This is a schematic diagram of the AXI stream bus timing in this embodiment.
[0024] Figure 4 This is a schematic diagram of the transmission of the one frame with multiple packets transaction model in this embodiment.
[0025] Figure 5 This is a schematic diagram of the structure of the verification platform for the one frame with multiple packets transaction model in this embodiment. Detailed Implementation Manner
[0026] The technical solution of the present invention will be further explained and described below in conjunction with the accompanying drawings of the specification and specific embodiments.
[0027] 1. Transaction Model of One Frame with Multiple Packets and No Inter-frame Pipelining A transaction model of one frame with multiple packets and no inter-frame pipelining, the FPGA algorithm module it faces has an interface framework as Figure 1 shown. In addition to each input interface and output interface, the algorithm module also has a configuration interface. Except for the clock signal and the reset signal, the configuration interface, all input interfaces and output interfaces of the algorithm module comply with the AXI stream standard.
[0028] The AXI stream bus signals are as Figure 2 shown, and are composed of four signals: tdata, tvalid, tready, and tlast. tdata is a multi-bit data line, and tvalid, tready, and tlast are single-bit control lines. The tdata, tvalid, and tlast signals are transmitted from the sending module to the receiving module, and the tready signal is fed back from the receiving module to the sending module.
[0029] The AXI stream bus transmission timing is as Figure 3 shown. The transmission is in units of packets, and the tlast signal is used as the mark for the end of each data packet. When the tlast signal and the tvalid signal are both valid, it indicates that the current tdata is the last data of this data packet.
[0030] A transaction model with multiple packets per frame and no pipelining between frames. In addition to the input interface and output interface, the FPGA algorithm module also has a configuration interface, which also conforms to the AXI stream standard. The data transfer transactions of the algorithm module are frame-based. Each transaction first inputs a configuration data packet from the configuration interface of the algorithm module, then inputs several data packets from the input interface, and then outputs several data packets from the output interface of the algorithm module. It is not necessary to wait for all the input data packets of the frame on the input interface to be input before starting to output data packets on the output interface. However, before all the output data packets of a frame are output, the transmission of the configuration data packet of the next frame cannot be started first, that is, there is no pipelining between frames. The number of data packets on the input interface and the output interface does not need to be equal. The transmission mode of this transaction model is as shown in Figure 4 shown. For simplicity, only one input interface and one output interface are drawn in the figure. The actual module may have multiple input and output interfaces.
[0031] 2. Verification platform for this transaction model According to the UVM verification methodology, a verification platform is established for this transaction model, and its structure is as shown in Figure 5 shown.
[0032] 1) This verification platform has the following customized parameters: ① The number of input interfaces of the device under test; ② The number of output interfaces of the device under test; ③ The length of the configuration data packet on the configuration interface.
[0033] ④ The range of each configuration data (or specific data file) on the configuration interface.
[0034] ⑤ The number of test frames.
[0035] ⑥ The number of input data packets per frame for each input interface; ⑦ The number of output data packets per frame for each input interface; ⑧ The length of the test data packet for each input interface; ⑨ The range of the test data (or specific data file) for each input interface.
[0036] ⑩ The tready intermittent mode for each output interface (continuous high, periodic intermittent high and low, random intermittent high and low, etc.).
[0037] 2) This verification platform has the following test components: ① Verification environment generator: a) Instantiate a configuration interface agent.
[0038] b) According to the number of input interfaces and the number of output interfaces, instantiate several input interface agents and several output interface agents.
[0039] c) Instantiate a reference result generator and a scoreboard.
[0040] d) Establish a configuration sequence monitoring channel between the configuration interface agent and the reference result generator, called configuration sequence monitoring channel A.
[0041] e) Establish a configuration sequence monitoring channel between the configuration interface agent and the scoreboard, called configuration sequence monitoring channel B.
[0042] f) Establish an input sequence monitoring channel between each input interface agent and the reference result generator, an output sequence monitoring channel between each output interface agent and the scoreboard, and a reference sequence transmission channel between the reference result generator and the scoreboard.
[0043] ② Test scenario generator: a) Establish a virtual configuration sequence and attach it to the sequence generator of the configuration interface agent.
[0044] b) Establish a number of virtual sequences according to the number of input interfaces and attach them to the sequence generators of each input interface agent.
[0045] c) Generate data packets for each input interface according to the predetermined number of packets and transmit them through the virtual sequence channel to the sequence generators of each input interface agent.
[0046] d) Generate an axis data packet each time by calling the data packet generator.
[0047] ③ Axis data packet generator: a) Generate an axis configuration data packet according to the specified configuration data packet length and configuration data range, or read data from the specified data file to form an axis configuration data packet.
[0048] b) Generate a number of axis input data packets according to the specified data packet length and data range, or read data from the specified data file to form a number of axis input data packets.
[0049] ④ Axis configuration interface agent: A configuration interface agent. The configuration interface agent instantiates an axis configuration sequence generator, an axis configuration interface driver, and an axis bus monitor, and establishes a configuration sequence generation channel between the configuration sequence generator and the configuration interface driver.
[0050] ⑤ Axis configuration interface driver: Wait for a data packet to be available in the configuration sequence generation channel. When a configuration data packet is obtained, drive the data and the tvalid and tlast signals to the axis configuration interface according to the axis protocol.
[0051] ⑥axis Input Interface Agent: Each input interface has an input interface agent. The input interface agent instantiates an axis input sequence generator, an axis input interface driver, and an axis bus monitor, and establishes an input sequence generation channel between the input sequence generator and the input interface driver.
[0052] ⑦axis Input Interface Driver: Wait for a data packet to be available in the input sequence generation channel. When an input data packet is obtained, drive the data, along with the tvalid and tlast signals, onto the axis input interface according to the axis protocol.
[0053] ⑧axis Output Interface Agent: Each output interface has an output interface agent. The output interface agent instantiates an axis output interface driver and an axis bus monitor.
[0054] ⑨axis Output Interface Driver: Drive the tready signal according to a preset intermittent mode.
[0055] ⑩axis Bus Monitor: The axis bus monitor is common to the axis input interface and the axis output interface. It uses the tlast signal as the end marker of a data packet, grabs one data packet on the axis bus each time, and injects it into the monitoring channel.
[0056] ⑪Reference Result Generator: a) Wait for a data packet to be available in the configuration sequence monitoring channel A.
[0057] b) After obtaining a configuration data packet, start receiving input data packets for one frame and wait for a data packet to be available in the input sequence monitoring channel.
[0058] c) When the specified number of input data packets for the frame is obtained, call the algorithm reference model of the algorithm module to calculate the reference result data packet and send it to the reference sequence transmission channel.
[0059] d) Repeat the above steps.
[0060] ⑫Algorithm Reference Model: It is the reference model of the algorithm module under test. It receives one configuration data packet and a number of input data packets for one frame each time, and calculates a number of reference result data packets according to the specified algorithm. When there are multiple input interfaces and multiple output interfaces, a specified number of input data packets are received on each input interface, and a specified number of reference data packets are generated on each output interface.
[0061] ⑬Scoreboard: a) Wait for a data packet to be available in the configuration sequence monitoring channel B.
[0062] b) After obtaining a configuration data packet, start receiving output data packets for one frame and wait for data packets that can be obtained in the output sequence monitoring channel and the reference sequence transmission channel. c) After obtaining the specified number of output data packets and reference result data packets for this frame, compare the two types of data packets one by one, and determine whether the test is correct according to the comparison results. When there are multiple output interfaces, receive the specified number of output data packets and reference data packets for each output interface and compare them. The test is correct only when all the comparisons on all output interfaces are correct.
[0063] d) Print and display the test conclusion, or print the test conclusion to a file.
[0064] Repeat the above steps.
[0065] Although the present invention has been disclosed above with preferred embodiments, the embodiments and the drawings are not used to limit the present invention. Any person skilled in this art can make various changes or modifications without departing from the spirit and scope of the present invention, but they are still within the protection scope of the present invention. Therefore, the protection scope of the present invention should be defined by the protection scope of the claims of this application.
Claims
1. A transaction model with multiple packets per frame and no pipelining between frames, based on an FPGA algorithm module, characterized in that: It includes multiple input interfaces, output interfaces, and a configuration interface; the data transfer transactions of the algorithm module are in units of frames. Each transaction first inputs a configuration data packet from the configuration interface of the algorithm module, then inputs several data packets from the input interfaces, and then outputs several data packets from the output interface of the algorithm module. Without waiting for all the input data packets of this frame on the input interface to be input, it can start outputting data packets on the output interface. However, before all the output data packets of a frame are output, the transmission of the configuration data packet of the next frame cannot be started first, that is, there is no inter-frame pipelining.
2. The transaction model of one frame with multiple packets and no pipelining between frames according to claim 1, wherein: Except for the clock signal and the reset signal, the configuration interface, input interfaces, and output interfaces of the algorithm module all conform to the AXI stream standard.
3. A transaction model with multiple packets per frame and no pipelining between frames according to claim 1, characterized in that: The number of data packets on the input interface and the output interface does not need to be equal.
4. A verification platform for a transaction model with multiple packets per frame and no pipelining between frames, characterized in that: It includes preset configuration parameters and multiple test components. The test components include a verification environment generator, a test scenario generator, and an axis data packet generator; The verification environment generator includes a configuration interface agent, several input interface agents, several output interface agents, a reference result generator, and a scoreboard; there is a configuration sequence monitoring channel between the configuration interface agent and the reference result generator, which is called configuration sequence monitoring channel A; There is a configuration sequence monitoring channel between the configuration interface agent and the scoreboard, which is called configuration sequence monitoring channel B; there is an input sequence monitoring channel between each input interface agent and the reference result generator, an output sequence monitoring channel between each output interface agent and the scoreboard, and a reference sequence transmission channel between the reference result generator and the scoreboard; The test scenario generator is connected to the configuration interface agent and the input interface agent respectively through virtual configuration sequences, and each time it generates an axis data packet by calling the data packet generator; The axis data packet generator can generate axis configuration data packets and axis input data packets, and input them to the configuration interface agent and the input interface agent respectively through the test scenario generator.
5. The verification platform for a transaction model with multiple packets per frame and no inter-frame pipelining according to claim 4, characterized in that: The configuration interface agent includes an axis configuration sequence generator, an axis configuration interface driver, and an axis bus monitor, and there is a configuration sequence occurrence channel between the configuration sequence generator and the configuration interface driver; axis configuration interface driver: Wait for a data packet to be available in the configuration sequence occurrence channel. When a configuration data packet is obtained, drive the data and the tvalid and tlast signals to the axis configuration interface according to the axis protocol.
6. The verification platform for a transaction model with multiple packets per frame and no inter-frame pipelining according to claim 5, characterized in that: The input interface agent: Each input interface agent has an axis input interface; the input interface agent includes an axis input sequence generator, an axis input interface driver, and an axis bus monitor, and an input sequence generation channel is provided between the input sequence generator and the input interface driver; The axis input interface driver: waits for a packet to be available in the input sequence generation channel. When an input packet is obtained, it drives the data, along with the tvalid and tlast signals, onto the axis input interface according to the axis protocol.
7. The verification platform for a multi-packet-per-frame and non-pipelined inter-frame transaction model according to claim 4, wherein: The output interface agent: Each output interface agent has an axis output interface. The output interface agent includes an axis output interface driver and an axis bus monitor; The axis output interface driver drives the tready signal according to a preset intermittent mode; the axis bus monitor is common to the axis input interface and the axis output interface. It uses the tlast signal as the end marker of the packet, grabs one packet on the axis bus each time, and injects it into the monitoring channel.
8. The verification platform for a multi-packet-per-frame and non-pipelined inter-frame transaction model according to claim 4, wherein: The reference result generator waits for a packet to be available in the configuration sequence monitoring channel A. When a configuration packet is obtained, it starts receiving the input packets of a frame, waits for a packet to be available in the input sequence monitoring channel. When the specified number of input packets of the frame are obtained, it calls the algorithm reference model of the algorithm module to calculate the reference result packet and sends it to the reference sequence transmission channel.
9. The verification platform for a multi-packet-per-frame and non-pipelined inter-frame transaction model according to claim 4, wherein: The algorithm reference model is the reference model of the algorithm module under test. It receives one configuration packet and several input packets of a frame each time, and calculates several reference result packets according to the specified algorithm. When there are multiple input interfaces and multiple output interfaces, it receives the specified number of several input packets on each input interface, and generates the specified number of several reference packets on each output interface.
10. The verification platform for a multi-packet-per-frame and non-pipelined inter-frame transaction model according to claim 4, wherein: The scoreboard waits for a data packet to be available in the configuration sequence monitoring channel B. After obtaining a configuration data packet, it starts receiving output data packets for one frame and waits for data packets to be available in the output sequence monitoring channel and the reference sequence transmission channel. When the specified number of output data packets and reference result data packets for this frame are obtained, the two types of data packets are compared one by one, and a conclusion on whether the test is correct is determined based on the comparison results. When there are multiple output interfaces, the specified number of output data packets and reference data packets are received and compared for each output interface, and the test is considered correct only when all the comparisons on all output interfaces are correct. Then, the test conclusion is printed and displayed, or printed to a file.
11. The verification platform for a multi-packet-per-frame and non-pipelined inter-frame transaction model according to claim 6, characterized in that: The test scenario generator is provided with virtual configuration sequences, which are hooked to the sequence generators of the configuration interface agents, and a number of virtual sequences are established according to the number of input interfaces and hooked to the sequence generators of each input interface agent. Each time the test scenario generator generates an axis data packet by calling the axis data packet generator, generates data packets for each input interface according to a predetermined number of packets, and transmits them to the sequence generators of each input interface agent through the virtual sequence channel.
12. The verification platform for a multi-packet-per-frame and non-pipelined inter-frame transaction model according to claim 4, characterized in that: The axis data packet generator: Can generate an axis configuration data packet according to the specified configuration data packet length and configuration data range, or read data from a specified data file to form an axis configuration data packet; Can generate a number of axis input data packets according to the specified data packet length and data range, or read data from a specified data file to form a number of axis input data packets.
13. The verification platform for a multi-packet-per-frame and non-pipelined inter-frame transaction model according to claim 4, characterized in that: The configuration parameters include: the number of input interfaces of the module under test; the number of output interfaces of the module under test; the configuration data packet length on the configuration interface; each configuration data range or specific data file on the configuration interface; the number of test frames; the number of input data packets per frame for each input interface; the number of output data packets per frame for each input interface; the test data packet length for each input interface; each test data range or specific data file for each input interface; the tready intermittent mode for each output interface.