Low earth orbit satellite network simulation platform and simulation method

Abstract

The invention discloses a low-orbit satellite network simulation platform and a simulation method, and mainly solves the problems that the simulation of a large-scale network and high-speed traffic cannot be supported, the simulation result guarantee degree is low, the development period is long, and the development cost is high in the prior art. The simulation platform comprises an upper computer, a field programmable gate array (FPGA) unit and a switch, wherein the upper computer is connected with a single FPGA unit or a plurality of FPGA units through the switch; the FPGA unit comprises an information extraction and data modification module, a satellite node simulation module and a propagation time delay simulation module and is used for data forwarding and information statistics, and the upper computer comprises a routing table configuration module and a satellite parameter configuration module and is used for configuring a satellite node routing table and satellite parameters. The parallel processing capability of the FPGA is utilized to support verification of network protocols of large-scale satellite constellations and simulation of high-speed traffic, the guarantee degree of simulation results is improved, the development period is shortened, the development cost is reduced, and the method can be used for verification of low-orbit satellite network protocols and simulation of network performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of satellite networks, and particularly relates to a low-earth orbit satellite network simulation platform and method, which can be used for simulating the verification of low-earth orbit satellite network protocols and network performance. Background Art

[0002] Satellite communication is an important part of the next-generation mobile communication network, especially the low-earth orbit satellite communication network with relatively low propagation delay. However, due to the high cost of satellite launch, it is difficult to conduct on-orbit test verification, and complete simulation tests need to be carried out on the ground.

[0003] Existing network simulation platforms are mainly divided into three types: discrete-event-based network simulation, simulation platforms built based on virtualization technology, and dedicated network test benches. Among them:

[0004] For discrete-event-based network simulation, existing discrete-event simulation software such as OPNET is mainly used to construct the network, and mathematical modeling is used to simulate network behavior. This method is simple to implement, but the simulated topology scale is limited by the single-machine performance and cannot be horizontally extended, so it cannot support the simulation of large-scale networks.

[0005] For simulation platforms built based on virtualization technology, virtualization tools are used to create virtual network nodes with resource isolation on physical hosts. Each virtual network node can communicate with each other as a single communication node, so as to simulate the sending and receiving situations of a real network. This platform supports horizontal expansion and can simulate large-scale network scenarios, but the guarantee degree of simulation results is low, and it is difficult to support the simulation of high-speed traffic.

[0006] For dedicated network test benches, the fidelity of test results is high, and they can support the simulation of large-scale network topologies, but they have low flexibility, require secondary development for the target network, and have a long development cycle and high development cost.

[0007] The patent document with the application number 202211522579.9 discloses a satellite network simulation platform that combines pure physical network simulation and pure software simulation. It uses virtualization technology to implement virtual satellite simulation nodes and uses fully programmable switches to implement physical satellite simulation nodes. However, due to the use of virtualization technology in this system, when the number of virtual satellite nodes increases or the simulation traffic increases, a large amount of computing resources will be consumed during simulation, resulting in insufficient computing resources being allocated to each virtual satellite node, leading to inaccurate results; at the same time, because fully programmable switches cannot accurately simulate the inter-satellite transmission delay, the delay simulation results cannot truly reflect the actual situation.

[0008] The patent document with the application number 202210588221.X discloses a low-earth orbit satellite communication network simulation system based on FPGA, which utilizes the large memory and high-speed read and write of HBM to support large-scale node and high-data-rate simulation. However, this system has two deficiencies: one is that it does not simulate the table lookup and exchange behavior of satellites and cannot comprehensively simulate satellite behavior, so the simulation results cannot truly reflect the performance of actual satellites; the other is that the system requires the use of the HBM storage resources of FPGA and cannot utilize other storage resources of FPGA. Therefore, this system can only be deployed on FPGAs with HBM resources and has high requirements for the FPGA model. Summary of the Invention

[0009] The purpose of the present invention is to propose a low-earth orbit satellite network simulation platform and simulation method in view of the above-mentioned deficiencies of the prior art, comprehensively simulate the actual operation of satellites, improve the accuracy of delay simulation, reduce the development cycle, reduce the development cost, and support the verification of network protocols for larger-scale satellite constellations and the simulation of network performance under high-speed traffic.

[0010] The technical idea for implementing the present invention is as follows: by setting multiple satellite nodes on the FPGA to simulate the table lookup and forwarding function of satellites, comprehensively simulate the actual operation of satellites; utilize the parallel processing ability of the FPGA and the clock accuracy accurate to nanoseconds to improve the accuracy of delay simulation; by using reusable table lookup and exchange and delay simulation codes, reduce the development cycle and development cost; by extracting key information from simulation data packets to form key information packets, reduce the resource consumption of a single satellite simulation node, and deploy satellite nodes on multiple FPGAs to simulate more satellite nodes, so that the simulation platform can support the verification of network protocols for larger-scale satellite constellations and the simulation of network performance under high-speed traffic.

[0011] According to the above idea, the technical solution of the present invention includes:

[0012] 1. A low-earth orbit satellite network simulation platform, characterized in that it includes a host computer and a switch, and is further characterized in that it also includes a field programmable gate array (FPGA) unit, and the host computer is connected to a single FPGA unit or multiple FPGA units through the switch; this FPGA unit is responsible for data forwarding and information statistics, and this host computer is responsible for the configuration of the satellite node routing table and satellite parameters.

[0013] Further, the FPGA includes:

[0014] An information extraction and data modification module, which is used to store original simulation data, extract key information and send it to the satellite node simulation module;

[0015] The satellite node simulation module, which consists of multiple satellite simulation nodes, is used to simulate the look-up table forwarding function of satellite nodes, count the processing delay, queuing delay, transmission delay, transmission path, node load, and node packet loss rate, and send the data that has not reached the destination satellite node to the propagation delay simulation module, and send the data that has reached the destination satellite node to the information extraction and data modification module;

[0016] The propagation delay simulation module is used to simulate the propagation delay between satellites and exchange the data to the next satellite node simulation module.

[0017] Furthermore, the host computer includes:

[0018] The routing table configuration module is used to configure the routing table for the satellite node simulation module in the FPGA;

[0019] The satellite parameter configuration module is used to configure the propagation delay of the satellite link in the FPGA, the buffer size of the satellite port, and the setting of the link packet loss rate.

[0020] 2. A method for simulating a low-earth orbit satellite network using the said platform, which is characterized by including:

[0021] S1) The routing table configuration module of the host computer configures the routing table for the satellite node simulation module;

[0022] S2) The satellite parameter configuration module of the host computer configures the parameters such as the propagation delay of the satellite link in the FPGA, the buffer size of the satellite port, and the link packet loss rate;

[0023] S3) The simulation data enters the information extraction and data modification module, and this module extracts the key data such as the packet length, source and destination satellite node numbers, and priority of the data packet, and then combines these data into a key information packet and sends it to the corresponding source satellite node in the satellite node simulation module, and stores the simulation data in the memory;

[0024] S4) The satellite node simulation module receives the key information packet, performs look-up table, forwarding, out-port queuing, and transmission delay simulation on it, and then sends the key information packet to the propagation delay simulation module;

[0025] S5) The propagation delay simulation module performs propagation delay simulation, and after the simulation is completed, sends the key information packet to the corresponding next satellite node in the satellite node simulation module;

[0026] S6) The next satellite node makes a judgment according to the destination satellite node number in the key information packet:

[0027] If the key information packet has not reached the destination satellite node, return to S4);

[0028] If the key information packet reaches the destination satellite node, the key information packet is sent to the information extraction and data modification module;

[0029] S7) After receiving the key information packet, the information extraction and data modification module reads the original data packet corresponding to the key information packet from the memory, modifies it according to the simulated satellite network protocol, and then sends it out.

[0030] Compared with the prior art, the present invention has the following advantages:

[0031] First, since the present invention utilizes the parallel processing ability of FPGA to simulate multiple satellite nodes simultaneously, the simulation platform can support the verification of network protocols for larger-scale satellite constellations and the simulation of network performance;

[0032] Second, since the present invention extracts key information from the simulation data to form data packets in a fixed format, not only greatly compresses the data volume that needs to be stored in the satellite node simulation module and the propagation delay simulation module, enabling the simulation platform to support the simulation of high-speed traffic, but also the above two modules can be reused in the simulation of different network protocols, reducing the hardware cost of the simulation platform and shortening the development cycle and development cost;

[0033] Third, since the present invention utilizes a timer combined with the packet length to simulate the transmission delay and propagation delay of the simulation data, the delay simulation of the simulation platform is not affected by the size of the simulation traffic, and has higher delay simulation accuracy and delay simulation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is the structural diagram of the low-earth orbit satellite network simulation platform of the present invention;

[0035] Figure 2 is the structural block diagram of the FPGA in the simulation platform of the present invention;

[0036] Figure 3 is Figure 2 the structural block diagram of the information extraction and data modification module in

[0037] Figure 4 is Figure 2 the structural block diagram of the satellite node simulation module in

[0038] Figure 5 is Figure 2 the structural block diagram of the propagation delay simulation module in

[0039] Figure 6 is the implementation flowchart of the low-earth orbit satellite network simulation method of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0040] The following further describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0041] Example 1, a low-earth orbit satellite network simulation platform.

[0042] Refer to Figure 1 , this example includes a host computer 1, an FPGA unit 2, and a switch 3, and the host computer is connected to the FPGA unit 2 through the switch 3. The host computer is used to configure the routing table and link parameters of the satellite nodes in the FPGA unit 2; the FPGA unit 2 is used to simulate the table lookup and forwarding of satellite nodes and the transmission propagation delay.

[0043] Refer to Figure 2 , the FPGA includes an information extraction and data modification module 21, a satellite node simulation module 22, and a propagation delay simulation module 23, where:

[0044] The information extraction and data modification module 21 is used to store the original simulation data, extract key information, and send it to the satellite node simulation module 22;

[0045] The satellite node simulation module 22 is composed of multiple satellite simulation nodes, and is used to simulate the table lookup and forwarding function of satellite nodes, count the processing delay, queuing delay, transmission delay, transmission path, node load, and node packet loss rate, and send the data that has not reached the destination satellite node to the propagation delay simulation module 23, and send the data that has reached the destination satellite node to the information extraction and data modification module 21;

[0046] The propagation delay simulation module 23 is used to simulate the propagation delay between satellite stars and exchange data to the next satellite node simulation module 22.

[0047] Refer to Figure 3 , the information extraction and data modification module 21 includes an Ethernet transceiver sub-module 211, a key information extraction sub-module 212, a protocol data processing sub-module 213, and a storage resource 214, where:

[0048] The Ethernet transceiver sub-module 211 is used to receive and send simulation data;

[0049] The key information extraction sub-module 212 is used to extract key information such as packet length, source and destination satellite node numbers, and priority, and form a key information packet to send to the satellite node simulation module 22;

[0050] The protocol data processing sub-module 213 is used to process the simulated completed data packets according to the simulated network protocol and send them out;

[0051] The storage resource 214 is used to store the original simulation data.

[0052] Refer to Figure 4, the satellite node simulation module 22 includes an input port sub-module 221, a parallel-to-serial conversion sub-module 222, a look-up table sub-module 223, a switching sub-module 224, a priority sub-module 225, a transmission delay simulation sub-module 226, an output port sub-module 227, a simulation data statistics sub-module 228, and a timer 229, where:

[0053] The input port sub-module 221 is used to receive key information packets, count the number and size of input data packets and send them to the simulation data statistics sub-module, and send the key information packets to the parallel-to-serial conversion sub-module 222;

[0054] The parallel-to-serial conversion sub-module 222 is used to convert data packets from multiple input ports into serial data packets and send them to the look-up table sub-module 223;

[0055] The look-up table sub-module 223 is used to find the output port through the routing table and send the data packet and the output port number to the switching sub-module 224;

[0056] The switching sub-module 224 is used to send the data packet to the priority sub-module 225 of the corresponding output port according to the output port found by the look-up table sub-module;

[0057] The priority sub-module 225 groups the data packets according to the priority information, sends the data with the highest priority to the transmission delay simulation sub-module 226, deletes the data packets cached in the overflow priority, and at the same time sends the information such as the cache size of each priority queue and the number of overflow data packets to the simulation data statistics sub-module 228;

[0058] The transmission delay simulation sub-module 226 is used to simulate the transmission delay of the data packets sent by the priority sub-module according to the packet length field, count the transmission delay and queuing delay and send them to the simulation data statistics sub-module, and send the data packet to the output port sub-module 227;

[0059] The output port sub-module 227 is used to count the number and size of output data packets, send them to the simulation data statistics module 228, and send the data packet to the propagation delay simulation module 23;

[0060] The simulation data statistics sub-module 228 is used to count the statistical data sent by other sub-modules in the satellite node simulation module 22;

[0061] The timer 229 is used to send the current time information to the switching sub-module 224, the transmission delay simulation sub-module 226, and the output port sub-module 227.

[0062] Refer to Figure 5, the propagation delay simulation module 23 includes a timer 231, a writing sub-module 232, an i-th level memory 233, a reading sub-module 234, a token bucket sub-module 235, and a switching matrix sub-module 236, where:

[0063] The timer 231 is used to send the current time information to each writing sub-module 232 and reading sub-module 234;

[0064] The writing sub-module 232 is used to apply for a token from the token bucket 235 and write the data packet sent by the output port sub-module 227 into the corresponding i-th level memory 233;

[0065] The i-th level memory 233 is used to store the data packets written by the writing sub-module 232 for the reading sub-module 234 to read the data packets;

[0066] The reading sub-module 234 is used to circularly read the data packets in the corresponding i-th level memory 233 and determine whether the remaining propagation delay of the data packet is greater than the circular reading delay of the corresponding i-th level memory 233:

[0067] If not satisfied, the data packet is sent to the corresponding writing sub-module 232 or switching matrix sub-module 236 at the next level, and the token of the data packet is sent to the token bucket 235;

[0068] If satisfied, continue to read the next data packet;

[0069] The token bucket sub-module 235 is used to extract tokens from the token bucket and send them to the writing sub-module 232, and store the tokens sent by the reading sub-module 234 into the token bucket;

[0070] The switching matrix sub-module 236 is used to switch the data packets with the propagation delay simulation completed to the input port sub-module 221 of the next satellite node.

[0071] In this example, the host computer 1 uses any computer that can receive and send data packets through a network port, including but not limited to personal computers, workstations, and servers.

[0072] In this example, the FPGA unit 2 does not limit the chip model used, but this unit needs to have an interface that can be connected to a switch.

[0073] In this example, the switch 3 uses an existing switch, and the switch model is not limited, but the performance parameters of this switch need to meet the requirements of the data exchange rate in the simulation. The host computer 1 is connected to the FPGA unit 2 through the switch, and the host computer 1 and the FPGA unit 2 are connected to any forwarding port of the switch 3 through a network cable or optical fiber.

[0074] Embodiment 2, Low Earth Orbit Satellite Network Simulation Method.

[0075] Refer to Figure 6 , the implementation steps of this example are as follows:

[0076] Step 1, the host computer configures the routing table and parameters.

[0077] 1.1) The user fills in the propagation delay of the satellite link, the buffer size of the satellite port, and the link packet loss rate in the configuration file. The satellite parameter configuration module 12 of the host computer reads and parses the configuration file, and configures the propagation delay, the buffer size of the satellite port, and the link packet loss rate for the satellite node simulation module 22 in the FPGA;

[0078] 1.2) The routing table configuration module 11 of the host computer configures the routing table for the satellite node simulation module 22 in the FPGA:

[0079] 1.2.1) The user provides the satellite constellation topology and the routing generation algorithm to the routing table configuration module 11;

[0080] 1.2.2) The routing table configuration module 11 calculates the routing tables of each satellite node according to the satellite constellation topology and the routing generation algorithm provided by the user;

[0081] 1.2.3) The routing table configuration module 11 sends the routing table to the routing table sub-module 223;

[0082] 1.2.4) The routing table configuration module 11 dynamically generates a new routing table according to the satellite constellation topology and the routing generation algorithm according to the simulation scenario set by the user to replace the current routing table in the look-up table sub-module 223,

[0083] 1.2.5) Repeat step 1.2.4) until the simulation is completed or the user terminates the simulation;

[0084] Step 2, the information extraction and data modification module 21 in the FPGA extracts and combines key information packets.

[0085] 2.1) The Ethernet transceiver sub-module 211 receives the simulation data packets and transfers them to the key information extraction sub-module 212;

[0086] 2.2) The key information extraction sub-module 212 extracts key information such as the packet length, the source and destination satellite node numbers, and the priority, and assigns a data ID to the data packet to form a key information packet;

[0087] 2.3) The key information extraction sub-module 212 stores the simulation data packet in the storage address corresponding to the data ID assigned to it;

[0088] 2.4) The key information extraction sub-module 212 sends the key information packet to the input port sub-module 221 of the corresponding satellite node in the satellite node simulation module 22 according to the source satellite node number in the key information packet.

[0089] Step 3, the satellite node simulation module 22 in the FPGA simulates the key information packet.

[0090] 3.1) The input port sub-module 221 receives the key information packet, extracts the data packet length and data ID and sends them to the simulation data statistics sub-module 228, and sends the data packet to the parallel-to-serial conversion sub-module 222;

[0091] 3.2) The parallel-to-serial conversion sub-module 222 converts the data packets of each input port sub-module 221 into serial data packets and sends them to the look-up table sub-module 223;

[0092] 3.3) The look-up table sub-module 223 extracts the destination satellite node number in the data packet and determines whether the destination satellite node number is equal to the satellite node number where this module is located:

[0093] If they are equal, the data packet is sent to the protocol data processing sub-module 213 to execute Step 5;

[0094] If they are not equal, the output port is found through the routing table, and the data packet and the output port number are sent to the switching sub-module 224 to execute 3.4);

[0095] 3.4) The switching sub-module 224 sends the data packet to the priority sub-module 225 of the corresponding output port according to the output port number;

[0096] 3.5) The priority sub-module 225 sends the data packet with the highest priority to the transmission delay simulation sub-module 226:

[0097] 3.5.1) The priority sub-module 225 extracts the priority and data ID in the data packet, reads the timing information T1 sent by the timer 229, and writes the data packet and the timing information to the end of the queue corresponding to this priority;

[0098] 3.5.2) The priority sub-module 225 determines whether there is a data packet being transmitted in the transmission delay simulation sub-module 226:

[0099] If there is a data packet being transmitted, wait for the data packet transmission to complete;

[0100] If there is no data packet being transmitted, read the timing information T2 sent by the timer 229, and send the data packet and the timing information T2 to the transmission delay simulation sub-module 226 to calculate the queuing delay T of the data packet quene :

[0101] Tquene = T2 - T1;

[0102] 3.5.3) Send the queuing delay T quene and the data ID to the simulation data statistics sub-module 228;

[0103] 3.6) The transmission delay simulation sub-module 226 simulates the transmission delay according to the packet length field of the data packet:

[0104] 3.6.1) The transmission delay simulation module 226 extracts the packet length field L in the data packet and calculates the transmission delay T of the data packet according to the link transmission rate V trans :

[0105]

[0106] 3.6.2) The transmission delay simulation module 226 extracts the timing information T2 and calculates the time T when the data transmission is completed transend :

[0107] T transend = T2 + T trans ;

[0108] 3.6.3) The transmission delay simulation module 226 reads the timing information T3 sent by the timer 229 and judges whether the transmission is completed according to whether T3 is equal to T transend :

[0109] If the transmission is completed, send the data packet to the output port sub-module 227, and send the data ID and T of the data packet trans to the simulation data statistics sub-module 228 and execute step 3.7);

[0110] If the transmission is not completed, wait for the transmission to complete;

[0111] 3.7) The output port sub-module 227 extracts the data packet length and the data ID, and sends them together with the link delay of this output port to the simulation data statistics sub-module 228, and sends the data packet, the link delay of this output port and the next-hop satellite node number to the propagation delay simulation module 23;

[0112] 3.8) The simulation data statistics sub-module 228 receives the statistical data of other sub-modules, classifies them according to the data ID, obtains the input port number, queuing delay, transmission delay and output port number corresponding to the data ID, and sends these statistical information and the corresponding data ID to the host computer.

[0113] Step 4, the propagation delay simulation module 23 in the FPGA simulates the propagation delay.

[0114] The propagation delay simulation module 23 includes an M-level memory 233, and M-level propagation delay simulation is required. The cyclic read and write delays of each level of memory are different. The smaller the level number, the greater the cyclic read and write delay corresponding to this level of memory. Its implementation includes the following:

[0115] 4.1) The write sub-module 232 writes the data packet into the first-level memory 233:

[0116] 4.1.1) The write sub-module 232 extracts the link delay T corresponding to the data packet propa , and calculates the time T when the data packet propagation is completed according to the timing information T4 sent by the timer 231 propaend :

[0117] T propaend = T propa + T4;

[0118] 4.1.2) The write sub-module 232 applies for a token from the token bucket 235, extracts the address in the token, and writes the data packet and the corresponding T propaend into the corresponding address in the first-level memory 233;

[0119] 4.2) Read the data packets in the first-level memory 233 that do not meet the memory cyclic read delay and send them to the next write sub-module 232:

[0120] 4.2.1) The read sub-module 234 sequentially reads the data packets in the first-level memory 233, extracts the corresponding T propaend , and calculates the remaining propagation delay T according to the timing information T5 sent by the read timer 231 propadel :

[0121] T propadel = T propaend - T5;

[0122] 4.2.2) The read sub-module 234 determines whether the remaining propagation delay T propadel is greater than the cyclic read delay T of the first-level memory rw :

[0123] If T propadel is greater than T rw , then return to step 4.2.1);

[0124] If T propadel is not greater than T rw , then execute step 4.2.3);

[0125] 4.2.3) The read sub-module 234 sends the token corresponding to the data packet to the token bucket sub-module 235, and determines whether the next-level module is the write sub-module 232 or the switching matrix 236:

[0126] If it is the write sub-module 232, then the T corresponding to the data packet propadel is used as the new link delay T propa and is sent together with the data packet to the write sub-module 232 corresponding to the next-level memory 233, and return to step 4.1);

[0127] If it is the switching matrix 236, then the data packet is sent to the switching matrix 236, and step 4.3) is executed;

[0128] 4.3) The switching matrix 236 extracts the next-hop satellite node number, and switches the data packet to the satellite node simulation module 22 corresponding to the node number, and return to step 3.

[0129] Step 5, the information extraction and data modification module 21 in the FPGA modifies the original data packet and sends it.

[0130] 5.1) The protocol data processing sub-module 213 receives the data packet sent by the satellite node simulation module 22, and extracts the data ID in the data packet;

[0131] 5.2) The protocol data processing sub-module 213 reads the data packet at the corresponding address from the storage pool 214 according to the data ID, and modifies and sends out the data packet according to the simulated network protocol.

[0132] The above description is only two specific examples of the present invention, and does not constitute any limitation to the present invention. Obviously, for professionals in the field, after understanding the content and principle of the present invention, various modifications and changes in form and details may be made without departing from the principle and structure of the present invention. However, these corrections and changes based on the idea of the present invention are still within the scope of protection of the claims of the present invention.

[0133] It should be noted that the step numbers in the description and claims of the present invention are only for clear description of the implementation scheme of the present invention for easy understanding, and the order of their sequence is not limited.

Claims

1. A low-earth orbit satellite network simulation platform, comprising a host computer (1) and a switch (3), characterized in that, It also includes a Field Programmable Gate Array (FPGA) unit (2), and the host computer is connected to a single FPGA unit or multiple FPGA units through a switch; the FPGA unit is responsible for data forwarding and information statistics, and the host computer is responsible for configuring the satellite node routing table and satellite parameters.

2. The platform according to claim 1, characterized in that, The FPGA unit (2) includes: An information extraction and data modification module (21), which is used to store the original simulation data, extract key information and send it to the satellite node simulation module (22); A satellite node simulation module (22), which consists of multiple satellite simulation nodes, is used to simulate the look-up table forwarding function of satellite nodes, statistically process the processing delay, queuing delay, transmission delay, transmission path, node load, and node packet loss rate, and send the data that has not reached the destination satellite node to the propagation delay simulation module (23), and send the data that has reached the destination satellite node to the information extraction and data modification module (21); A propagation delay simulation module (23), which is used to simulate the propagation delay between satellites and exchange data to the next satellite node simulation module (22).

3. The platform according to claim 1, characterized in that, The host computer (1) includes: A routing table configuration module (11), which is used to configure the routing table for the satellite node simulation module in the FPGA; A satellite parameter configuration module (12), which is used to configure the propagation delay of the satellite link in the FPGA, the buffer size of the satellite port, and the setting of the link packet loss rate.

4. The platform according to claim 2, wherein The information extraction and data modification module (21) includes: An Ethernet transceiver sub-module (211), which is used to receive and send Ethernet data; A key information extraction sub-module (212), which is used to extract key information such as the packet length, source and destination satellite node numbers, and priority according to the simulated network protocol; A protocol data processing sub-module (213), which is used to process the simulated packets according to the simulated network protocol; A storage resource (214), which is used to store the original simulation data.

5. The platform according to claim 2, characterized in that, The satellite node simulation module (22) includes: An input port sub-module (221), which is used to receive key information packets, statistically count the number and size of input data packets and send them to the simulation data statistics sub-module, and send the key information packets to the parallel-to-serial conversion sub-module (222); A parallel-to-serial conversion sub-module (222), which is used to convert the data packets of multiple input ports into serial data packets and send them to the look-up table sub-module (223); A look-up table sub-module (223), which is used to find the output port through the routing table and send the data packet and the output port number to the switching sub-module (224); A switching sub-module (224), which is used to send the data packet to the priority sub-module (225) of the corresponding output port according to the output port found by the look-up table sub-module; A priority sub-module (225), which groups the data packets according to the priority information, sends the data with the highest priority to the transmission delay simulation sub-module (226), deletes the data packets that overflow the priority cache, and at the same time sends information such as the cache size of each priority queue and the number of overflow data packets to the simulation data statistics sub-module (228); The transmission delay simulation sub-module (226) is used to simulate the transmission delay of the data packets sent by the priority sub-module according to the packet length field, count the transmission delay and queuing delay and send them to the simulation data statistics sub-module, and send the data packet to the output port sub-module (227); The output port sub-module (227) is used to count the number and size of the output data packets, send them to the simulation data statistics module (228), and send the data packet to the propagation delay simulation module (23); The simulation data statistics sub-module (228) is used to count the statistical data sent by other sub-modules in the satellite node simulation module (22); The timer (229) is used to send the current time information to the switching sub-module (224), the transmission delay simulation sub-module (226) and the output port sub-module (227).

6. The platform according to any one of claims 2 to 5, characterized in that, The said propagation delay simulation module (23) includes: The timer (231) is used to send the current time information to each writing sub-module (232) and reading sub-module (234); The writing sub-module (232) is used to apply for a token from the token bucket (235) and write the data packet sent by the output port sub-module (227) into the corresponding i-th level memory (233); The i-th level memory (233) is used to store the data packets written by the writing sub-module (232) for the reading sub-module (234) to read the data packets; The reading sub-module (234) is used to circularly read the data packets in the corresponding i-th level memory (233) and judge whether the remaining propagation delay of the data packet is greater than the circular reading delay of the corresponding i-th level memory (233): If not satisfied, send the data packet to the corresponding writing sub-module (232) at the next level or the switching matrix sub-module (236), and send the token of the data packet to the token bucket (235); If satisfied, continue to read the next data packet; The token bucket sub-module (235) is used to extract tokens from the token bucket and send them to the writing sub-module (232), and store the tokens sent by the reading sub-module (234) into the token bucket; The switching matrix sub-module (236) is used to switch the data packets with the transmission delay simulated to the input port sub-module (221) of the next satellite node.

7. A method for simulating a low-earth orbit satellite network using the platform described in claim 1, characterized in that, It includes: S1) The routing table configuration module (11) of the host computer configures the routing table for the satellite node simulation module (22); S2) The satellite parameter configuration module (12) of the host computer configures parameters such as propagation delay, cache size of satellite ports and link packet loss rate for the satellite link in the FPGA; S3) The simulation data entry information extraction and data modification module (21), through which the key data such as its data packet length, source and destination satellite node numbers, and priority are extracted, and then these data are combined into a key information packet and sent to the corresponding source satellite node in the satellite node simulation module (22), and the simulation data is stored in the memory; S4) After the satellite node simulation module (22) receives the key information packet and performs look-up table, forwarding, out-port queuing and transmission delay simulation on it, then sends the key information packet to the propagation delay simulation module (23); S5) The propagation delay simulation module (23) simulates the propagation delay, and after the simulation is completed, sends the key information packet to the corresponding next satellite node in the satellite node simulation module (22); S6) The next satellite node makes a judgment based on the destination satellite node number in the key information packet: If the key information packet has not reached the destination satellite node, return to S4); If the key information packet reaches the destination satellite node, send the key information packet to the information extraction and data modification module (21); S7) After receiving the key information packet, the information extraction and data modification module (21) reads the original data packet corresponding to the key information packet from the memory, modifies it according to the simulated satellite network protocol, and then sends it out.

8. The method according to claim 7, characterized in that, In the above S4), the satellite node simulation module (22) receives the key information packet and simulates table look-up, forwarding, out-port queuing, and transmission delay. Its implementation includes the following: S41) The table look-up sub-module (223) in the satellite node simulation module (22) extracts the destination satellite node number from the data packet, looks up the corresponding entry in the routing table through this satellite node number, obtains the out-port number in this entry, and sends the data packet and the out-port number to the switching sub-module (224); S42) The switching sub-module (224) sends the data packet to the priority sub-module (225) corresponding to the port according to the out-port number; S43) The priority sub-module (225) reads the priority information in the data packet, writes the data packet and the current time of the timer (229) into the queue corresponding to this priority, and judges whether there is a data packet being transmitted in the transmission delay simulation sub-module (226): If there is a data packet being transmitted, wait for the data packet transmission to complete; If there is no data packet being transmitted, read out the data packet with the highest priority from the queue, subtract the time written into the queue from the current time of the timer (229) to obtain the queuing delay and send it to the simulation data statistics sub-module (228), and send the data packet to the transmission delay simulation sub-module (226); S44) The transmission delay simulation sub-module (226) reads the packet length information in the data packet, calculates the transmission delay through the packet length and the transmission rate, and then obtains the time when the data packet transmission is completed, and judges whether the transmission is completed according to the time of the timer (229): If the transmission is not completed, wait for the data packet transmission to complete; If the transmission is completed, send the transmission delay to the simulation data statistics sub-module (228), and send the data packet to the output port sub-module (227).

9. According to the method of claim 7, it is characterized in that: In the above step S1), the routing table configuration module (11) of the upper computer configures the routing table for the satellite node simulation module (22). First, the program in the upper computer generates the current routing table according to the satellite topology and simulation requirements and sends it to the table look-up sub-module (223), and then dynamically generates a new routing table according to the simulated satellite network protocol during the simulation process to replace the current routing table in the table look-up sub-module (223); Repeat this process until the user terminates the simulation. In the step S2), the satellite parameter configuration module (12) of the host computer configures the satellite propagation delay, the cache size of the satellite port, and the link packet loss rate in the FPGA. These are filled in by the user in the configuration file. The satellite parameter configuration module (12) reads and parses the configuration file, and sends the parsed configuration parameters to the FPGA.

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