Data transmission method and equipment based on JTAG protocol

Abstract

The invention relates to the technical field of computers, and particularly provides a data transmission method and device based on a JTAG protocol, and the method comprises the steps: determining the data length of to-be-transmitted data when a test access interface TAP controller is in a shift register state; under the condition that the data length is smaller than a data length threshold value, first target transmission data are stored in a first temporary array, and target state control data are stored in a second temporary array; the first target transmission data and the target state control data are sent, and the data length threshold value is equal to the array length of the first temporary array and the array length of the second temporary array; the first target transmission data comprises the data to be transmitted and bit filling data; the target state control data is used for controlling the TAP controller to switch from a state of keeping the shift register to a target state; the scheme can improve the communication efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a data transmission method and device based on the JTAG protocol. Background Art

[0002] The Joint Test Action Group (JTAG) is a standard interface protocol widely used in the electronics industry; the basic working principle of JTAG is to define a Test Access Port (TAP) controller inside a chip, and by controlling the state of the TAP controller, perform hardware testing, debugging, or firmware upgrade on the electronic device where the chip is located.

[0003] However, there is a problem of low transmission efficiency in the communication process based on the JTAG protocol. Summary of the Invention

[0004] Embodiments of this application provide a data transmission method and device based on the JTAG protocol, which can improve the communication efficiency based on the JTAG protocol.

[0005] In a first aspect, embodiments of this application provide a data transmission method based on the JTAG protocol, including:

[0006] When the Test Access Port (TAP) controller is in the shift register state, determine the data length of the data to be transmitted;

[0007] When the data length is less than the data length threshold, store the first target transmission data in a first temporary array, and store the target state control data in a second temporary array;

[0008] wherein, the data length threshold is equal to the array lengths of the first temporary array and the second temporary array; the first target transmission data includes the data to be transmitted and padding data; the target state control data is used to control the TAP controller to transition from the hold shift register state to the target state;

[0009] Send the first target transmission data and the target state control data.

[0010] By adopting the above technical solution, two temporary arrays capable of storing multiple bits of data configured by the sending end can be used to send multiple bits of data to be transmitted and multiple bits of status control data to the receiving end at one time, achieving the goal of sending multiple bits of data to the receiving end at one time, reducing the data transmission frequency based on the JTAG protocol, and improving the communication efficiency based on the JTAG protocol. On the other hand, when the TAP controller at the receiving end is in the shift register state and the data length of the data to be transmitted is less than the data length threshold, all the status control data required to control the TAP controller at the receiving end to switch from the shift register state to the target state can be sent to the receiving end at one time, so that the receiving end can perform multiple status conversions based on the status control data received at one time, avoiding the interaction overhead caused by frequently sending the status control data for controlling the TAP controller to perform status conversions, and further improving the communication efficiency.

[0011] In one implementable manner, the method further includes:

[0012] When the data length is greater than the data length threshold, store the second target transmission data in the first temporary array; the second target transmission data is the current transmission data in the data to be transmitted; the data length of the second target transmission data is the same as the data length threshold;

[0013] Send the second target transmission data.

[0014] By adopting the above technical solution, when the data length of the data to be transmitted is greater than the data length threshold, multiple bits of data to be transmitted can be sent to the TAP controller at one time, facilitating the rapid transmission of data in the scenario of large data volume data transmission and improving the communication efficiency based on the JTAG protocol in the case of large data volume.

[0015] In one implementable manner, the target state control data includes first state control data and first combined state control data; wherein, the first state control data is used to control the TAP controller to maintain the shift register state; the data length of the first state control data is the same as the data length of the data to be transmitted;

[0016] The first combined state control data is used to control the TAP controller to switch from the shift register state to the target state;

[0017] Storing the target state control data in the second temporary array includes:

[0018] Determine the first state control data;

[0019] Align the first state control data with the right side of the second temporary array and store it in the second temporary array;

[0020] Store each state control data in the first combined state control data into the second temporary array starting from the lower bit of the remaining storage space in the second temporary array.

[0021] By adopting the above technical solution, the first state control data for controlling the TAP controller to maintain the shift register state and the first combined state control data for controlling the TAP controller to transition from the shift register state to the target state can be stored sequentially from the lowest bit in the second temporary array, ensuring that after multiple state control data for controlling the TAP controller to transition from the shift register state to the target state are sent to the TAP controller at one time, during the process of storing the data to be transmitted, the TAP controller is accurately maintained in the shift register state, and after the data storage is completed, the state transition is performed according to the standard process of state transition, improving the communication efficiency while ensuring the accurate control of the state transition of the TAP controller and that the data to be transmitted can be completely stored.

[0022] In an implementable manner, before storing each state control data in the first combined state control data into the second temporary array starting from the lower bit of the remaining storage space in the second temporary array, the method further includes:

[0023] In the case where the length of the first combined state control data is greater than the length of the remaining storage space, expand the second temporary array to obtain an expanded second temporary array;

[0024] Storing each state control data in the first combined state control data into the second temporary array starting from the lower bit of the remaining storage space in the second temporary array includes:

[0025] Store the state data in the first combined state control data that has not been stored in the remaining storage space into the expanded second temporary array starting from the lower bit of the remaining storage space in the expanded second temporary array.

[0026] By adopting the above technical solution, after storing the first state control data for controlling the TAP controller to maintain the shift register state in the second temporary array, if the remaining storage space in the second temporary array is not sufficient to store the state control data for controlling the TAP controller to perform multiple state transitions, expand the second temporary array, so that in the case where the remaining storage space of the second temporary array is insufficient, the state control data for controlling the TAP controller to perform multiple state transitions can be sent to the TAP controller at one time through array expansion, improving the communication efficiency in the case where the storage space of the second temporary array is insufficient.

[0027] In an implementable manner, the method further includes:

[0028] Expand the first temporary array to obtain the expanded first temporary array, where the data lengths of the expanded first temporary array and the expanded second temporary array are the same;

[0029] Starting from the lower bit of the remaining storage space in the expanded first temporary array, store the newly added padding data in the expanded first temporary array.

[0030] By adopting the above technical solution, after the second temporary array is expanded, the first temporary array can be expanded to ensure that the data lengths of the target transmission data and the status control data sent to the TAP controller are the same, ensuring that the TAP controller can completely store the data to be transmitted and accurately execute multiple state conversion processes. On the premise of ensuring the one-time transmission of multiple bits of data, the normal operation of the TAP controller is guaranteed.

[0031] In an implementable manner, the first combined state control data includes second state control data, third state control data, and fourth state control data; among them, the second state control data is used to control the TAP controller to transition from the shift register state, through the first exit register state to the pause register state; the third state control data is used to control the TAP controller to maintain the pause register state; the fourth state control data is used to control the TAP controller to transition from the maintained pause register state to the target state, and the target state is the second exit register state, or the next round of shift register state;

[0032] Store each state control data in the first combined state control data in the second temporary array starting from the lower bit of the remaining storage space in the second temporary array, including:

[0033] Determine the second state control data and store the second state control data in the second temporary array starting from the lower bit of the first remaining storage space in the second temporary array; where the first remaining storage space is the remaining storage space in the second temporary array after storing the first state control data;

[0034] Determine the third state control data and store the third state control data in the second temporary array starting from the lower bit of the second remaining storage space in the second temporary array; where the second remaining storage space is the remaining storage space in the second temporary array after storing the second state control data;

[0035] Determine the fourth state control data and store the fourth state control data in the second temporary array starting from the lower bit of the third remaining storage space in the second temporary array; where the third remaining storage space is the remaining storage space in the second temporary array after storing the third state control data.

[0036] In an implementable manner, the method further includes:

[0037] Store the second combined state control data in a second temporary array; the second combined state control data is used to control the TAP controller to transition from the test logic reset state to the shift register state; the length of the second combined state control data is equal to the length of the second temporary array;

[0038] Send the second combined state control data.

[0039] By adopting the above technical solution, when initializing the TAP controller to make the TAP controller in the test logic reset state, the combined state control data used to control the TAP controller to transition from the test logic reset state to the shift register state can be sent to the TAP controller at one time, so as to reduce the communication frequency between the sending end and the receiving end during the state transition process of controlling the TAP controller to transition from the test logic reset state to the shift register state, and improve the communication efficiency based on the JTAG interface.

[0040] In a second aspect, an embodiment of the present application provides a data transmission method based on the JTAG protocol, including:

[0041] Receive first target transmission data and target state control data; wherein, the first target transmission data includes data to be transmitted and padding data; the target state control data is used to control the TAP controller to transition from the hold shift register state to the target state;

[0042] In response to the target state control data, filter the padding data and store the data to be transmitted.

[0043] By adopting the above technical solution, the data to be transmitted can be obtained at one time, and all the state control data required to control the TAP controller of the receiving end to transition from the hold shift register state to the target state can be obtained, and multiple state transitions can be performed based on the state control data received at one time, avoiding the interaction overhead caused by frequently receiving the state control data sent by the sending end before starting the next data storage, reducing the interaction cost of the receiving end, and improving the communication efficiency and fluency.

[0044] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the methods of the first aspect or the second aspect are implemented.

[0045] In a fourth aspect, an embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, the methods of the first aspect or the second aspect are implemented.

[0046] Fifth aspect, embodiments of the present application provide a computing device, which includes a data sending device and a data receiving device; the data sending device and the data receiving device are electrically connected; the data sending device is used to execute the data transmission method based on the JTAG protocol as in the first aspect, and the data receiving device is used to execute the data transmission method based on the JTAG protocol as in the second aspect.

[0047] In an implementable manner, the data sending device is a baseboard management controller; the receiving device is a programmable logic device.

[0048] It should be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further illustration of the claimed technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other objects, features, and advantages of the present application will become more apparent. The drawings are used to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used to explain the present application together with the embodiments of the present application, and do not constitute a limitation to the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0050] Figure 1 It is a schematic diagram of an implementation scenario of a data transmission method based on the JTAG protocol in an embodiment of the present application.

[0051] Figure 2 It is a flowchart of a data transmission method based on the JTAG protocol in an embodiment of the present application.

[0052] Figure 3 It is a state transition flowchart of a TAP controller in an embodiment of the present application.

[0053] Figure 4 It is a schematic diagram of the process of filling the first temporary array and the second temporary array based on the state transition process of a TAP controller in an embodiment of the present application.

[0054] Figure 5 It is a flowchart of another data transmission method based on the JTAG protocol in an embodiment of the present application.

[0055] Figure 6 It is a schematic diagram of an application scenario of a data transmission method based on the JTAG protocol in a firmware upgrade scenario in an embodiment of the present application.

[0056] Figure 7 It is a flowchart of a firmware upgrade process in an embodiment of the present application.

[0057] Figure 8It is a block diagram of a data transmission device based on the JTAG protocol according to an embodiment of the present application.

[0058] Figure 9 It is a block diagram of another data transmission device based on the JTAG protocol according to an embodiment of the present application.

[0059] Figure 10 It is a schematic diagram of a computer program product according to an embodiment of the present application.

[0060] Figure 11 It is a hardware block diagram of an electronic device according to an embodiment of the present application. Detailed implementation manners

[0061] Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not used to limit the protection scope of the present application.

[0062] It should be understood that the various steps recited in the method embodiments of the present application can be executed in a different order and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present application is not limited in this regard.

[0063] As used herein, the term "including" and its variations are open-ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description. It should be noted that the concepts such as "first" and "second" mentioned in the present application are only used to distinguish different devices, modules or units, and are not used to limit the order of the functions executed by these devices, modules or units or their interdependent relationships.

[0064] It should be noted that the modifications of "one" and "multiple" mentioned in the present application are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly stated in the context, it should be understood as "one or more".

[0065] The names of the messages or information exchanged between multiple devices in the embodiments of the present application are only for illustrative purposes and are not used to limit the scope of these messages or information.

[0066] An embodiment of the present application provides a data transmission method based on the JTAG protocol. The data transmission method based on the JTAG protocol can be applied to a data sender and a data receiver that communicate based on the JTAG protocol. Among them, the sender can be an electronic device, such as a computer or a notebook, etc., or the sender can be a chip that implements the function of a certain functional unit in the electronic device, such as the Baseboard Management Controller (BMC) in a server; at the same time, the receiver can also be an electronic device, or the receiver can also be a chip that implements the function of a certain functional unit in the electronic device, such as the Complex Programmable Logic Device (CPLD) in a server; specifically, it can be determined based on the actual scenario, and the embodiments of the present application do not limit this.

[0067] Exemplarily, Figure 1 FIG. shows a schematic diagram of an implementation scenario of the data transmission method based on the JTAG protocol according to an exemplary embodiment of the present application. As Figure 1 shown, the implementation scenario 100 includes a sender 101 and a receiver 102. Among them, the sender 101 is a computer that sends data based on the JTAG protocol, and the receiver 102 is a chip that receives data based on the JTAG protocol.

[0068] Among them, the JTAG interface of the sender 101 sends data to the JTAG interface in the receiver 102 through three input signal lines. The three input signal lines include: the TDI (Test Data Input) signal line, which is used to send target transmission data to the JTAG interface, such as test data, instruction data, or firmware data; the TMS (Test Mode Select) signal line, which is used to send the status control signal of the TAP controller to the JTAG interface to control the status transition of the TAP controller; the TCK (Test Clock) signal line, which is used to send a clock signal to the JTAG interface; the JTAG interface of the receiver 102 sends communication result data, such as test data and status information, etc., to the JTAG interface of the sender 101 through an output signal line. The output signal line is the TDO (TestData Output) signal line.

[0069] It can be understood that the sender is used to send target transmission data and status control signals to the TAP controller of the receiver based on the data transmission method based on the JTAG protocol provided by the embodiments of the present application;

[0070] The TAP controller at the receiving end is used to obtain target transmission data and status control signals based on the data transmission method based on the JTAG protocol provided in the embodiments of the present application, and perform data storage and status conversion based on the target transmission data and status control signals.

[0071] Figure 2 The flowchart of a data transmission method based on the JTAG protocol according to an exemplary embodiment of the present application is shown. This method can be applied to a data sending end that communicates based on the JTAG protocol, such as Figure 2 As shown, the method of the embodiments of the present application may include:

[0072] S201, when the test access port (TAP) controller is in the shift register state, determine the data length of the data to be transmitted;

[0073] S202, when the data length is less than the data length threshold, store the first target transmission data in the first temporary array and store the target status control data in the second temporary array;

[0074] wherein, the data length threshold is equal to the array lengths of the first temporary array and the second temporary array; the first target transmission data includes the data to be transmitted and padding data; the target status control data is used to control the TAP controller to convert from the hold shift register state to the target state;

[0075] S203, send the first target transmission data and the target status control data;

[0076] In summary, for the data transmission method based on the JTAG protocol provided by the embodiments of the present application, on the one hand, through two temporary arrays configured by the sending end that can store multiple bits of data, multiple bits of data to be transmitted and multiple bits of status control data can be sent to the receiving end at one time, achieving the goal of sending multiple bits of data to the receiving end at one time with low hardware cost, and also reducing the data transmission frequency based on the JTAG protocol, improving the communication efficiency based on the JTAG protocol; on the other hand, when the TAP controller at the receiving end is in the shift register state and the data length of the data to be transmitted is less than the data length threshold, all the status control data required to transmit the data to be transmitted at one time and control the TAP controller at the receiving end to convert from the hold shift register state to the target state can be sent to the receiving end, so that the receiving end can perform multiple status conversions based on the status control data received at one time, avoiding the interaction overhead caused by frequently sending status control data for controlling the TAP controller to perform status conversion, and further improving the communication efficiency and fluency.

[0077] The following Figure 2 elaborates on the specific implementation manners of each in the shown embodiments in detail:

[0078] In S201, the transmitting end determines the data length of the data to be transmitted when the test access interface TAP controller is in the shift register state.

[0079] In an embodiment of the present application, the transmitting end sends state control data to the JTAG interface of the receiving end through the TMS signal line of the JTAG interface to control the TAP controller to switch from the test logic reset (Test-Logic-Reset, TLR) state to the shift register state, wherein the shift register state can be a shift data register (Shift-DR) state, or a shift instruction register (Shift-IR) state; the data to be transmitted can be determined based on the actual application scenario, and the embodiment of the present application does not limit this. For example, in a chip test or debugging scenario, the data to be transmitted is test data and / or instruction data, and in a firmware upgrade scenario, the data to be transmitted is firmware data and / or instruction data.

[0080] It should be noted that in an embodiment of the present application, in order to ensure that the transmitting end can send multi-bit data to the receiving end at one time, it is necessary to configure the data register of the transmitting end to multiple bits, so that the transmitting end can store and send the data to be sent through a temporary array created with the support of the data register; for example, the data register can be configured to 32 bits or 64 bits, and the temporary array that the transmitting end can create includes a first temporary array and a second temporary array, wherein the first temporary array is used to store the data that the transmitting end needs to transmit to the receiving end, and the second temporary array is used to store the state control data that controls the state of the TAP controller.

[0081] In an optional embodiment, the transmitting end sends state control data to the JTAG interface of the receiving end via the TMS signal line to control the process of the TAP controller entering may include: in response to detecting a start instruction input by the user, determining fifth state control data, and storing the fifth state control data in a second temporary array, and sending the fifth state control data to the TAP controller of the receiving end via the TMS signal line of the JTAG interface, wherein the fifth state control data is used to control the TAP controller to enter a test logic reset state; wherein the start instruction may be determined based on an actual application scenario, which is not limited in the embodiments of the present application. By way of example, the start instruction may be a test start instruction, a debug start instruction, or a firmware upgrade start instruction.

[0082] It can be understood that in the embodiments of the present disclosure, the valid data bits of the fifth state control data can ensure that the TMS signal remains high at the rising edges of 5 consecutive clock signals; optionally, when the data length of the valid data bits of the fifth state control data is less than the data length threshold, after storing the fifth state control data in the second temporary array, the remaining storage space in the second temporary array can be filled with padding data, where the data length threshold is the storable data length of a pre-configured data register, so as to ensure that the sending end can send multiple bits of data to be transmitted and multiple bits of state control data at one time.

[0083] It should be noted that after the sending end controls the receiving end to be in the TLR state, the sending end can further control the TAP controller to transition from the TLR state to the shift register state, so as to send the data to be transmitted to the sending end.

[0084] In an optional implementation manner, the process by which the sending end controls the TAP controller to transition from the TLR state to the shift register state may include: storing the second combined state control data in the second temporary array; then, sending the second combined state control data; where the second combined state control data is used to control the TAP controller to transition from the test logic reset state to the shift register state; the length of the second combined state control data is equal to the length of the second temporary array; the combined state control data used to control the TAP controller to transition from the test logic reset state to the shift register state can be sent to the TAP controller at one time when initializing the TAP controller to make it in the test logic reset state, so as to reduce the communication frequency between the sending end and the receiving end during the state transition process of controlling the TAP controller to transition from the test logic reset state to the shift register state and improve the communication efficiency based on the JTAG interface.

[0085] It should be noted that in the embodiments of the present application, the state control data in the second combined state control data can be determined based on the type of the shift register state, and the embodiments of the present application do not limit this; where, when the shift register state is the shift data register state, the second combined state control data includes the sixth state control data for controlling the TAP controller to transition from the TLR state to the Run-Test-Idle state, the seventh state control data for controlling the TAP controller to transition from the test idle state to the Select-DR-Scan state, the eighth state control data for controlling the TAP controller to transition from the Select-DR-Scan state to the Capture-DR state, and the ninth state control data for controlling the TAP controller to transition from the Capture-DR state to the shift data register state.

[0086] When the shift register is in the shift instruction register state, the second combined state control data includes the sixth state control data for controlling the TAP controller to transition from the TLR state to the Run-Test-Idle state, the seventh state control data for controlling the TAP controller to transition from the test idle state to the Select-DR-Scan state, the tenth state control data for controlling the TAP controller to transition from the Select-DR-Scan state to the Select-IR-Scan state, the eleventh state control data for controlling the TAP controller to transition from the Select-IR-Scan state to the Capture-IR state, and the twelfth state control data for controlling the TAP controller to transition from the Capture-IR state to the shift instruction register state.

[0087] In an alternative embodiment, when the shift register is in the shift data register state, the process of the sender storing the second combined state control data in the second temporary array may include: determining the sixth state control data and storing the sixth state control data right-aligned with the second temporary data in the second temporary array, then determining the seventh state control data and storing the seventh state control data in the second temporary array starting from the low bit of the fourth remaining storage space in the second temporary array; further, determining the eighth state control data and storing the eighth state control data in the second temporary array starting from the low bit of the fifth remaining storage space in the second temporary array; furthermore, determining the ninth state control data and storing the ninth state control data in the second temporary array starting from the low bit of the sixth remaining storage space in the second temporary array, where the fourth remaining storage space is the remaining storage space in the second temporary array after storing the sixth state control data, the fifth remaining storage space is the remaining storage space in the second temporary array after storing the eighth state control data, and the sixth remaining storage space is the remaining storage space in the second temporary array after storing the ninth state control data.

[0088] It can be understood that when the shift register is in the shift instruction register state, the process of the sender storing the second combined state control data in the second temporary array is similar to the process of the sender storing the second combined state control data in the second temporary array when the shift register is in the shift data register state, and the embodiments of the present application will not elaborate on this.

[0089] It should be noted that in the embodiments of the present application, the process for the sending end to determine the status control data includes: the JTAG driver of the sending end obtains, from the application layer of the sending end, the status control data for controlling the TAP controller to transition from one state to another state. The status control data includes the status control data values of at least one bit, where the status control data values can be 0 or 1.

[0090] In an alternative embodiment, when the test access port (TAP) controller at the sending end is in the shift register state, the process for determining the data length of the data to be transmitted includes: when it is determined that the TAP controller at the receiving end is in the shift register state, reading the data to be transmitted and determining the data length of the data to be transmitted. For example, during the firmware upgrade process, the data to be transmitted is obtained by the sending end after acquiring the firmware to be upgraded and parsed at the application layer and then transmitted to the driver layer. The application layer of the sending end can respond to the firmware upgrade instruction, read the unparsed firmware to be upgraded from the sending end, or receive the unparsed firmware to be upgraded sent by the receiving terminal device.

[0091] In S202, when the data length is less than the data length threshold, the first target transmission data is stored in the first temporary array, and the target status control data is stored in the second temporary array.

[0092] In the embodiments of the present application, the padding data is used to pad the data bits. After the padding data is transmitted to the TAP controller, it will be filtered by the TAP controller and does not affect the actual data stored in the TAP controller. The target status can be obtained from the application layer of the sending end. Specifically, it can be determined based on actual needs, and the embodiments of the present application do not limit this. The target status control data is the sum of the status control data required for each state transition during the process of controlling the TAP controller to transition from the hold shift register state to the target state. The data length threshold is equal to the array lengths of the first temporary array and the second temporary array. The first target transmission data includes the data to be transmitted and the padding data. The target status control data is used to control the TAP controller to transition from the hold shift register state to the target state.

[0093] In an alternative embodiment, the process for the sending end to store the data to be transmitted and the padding data in the first temporary array may include: storing the data to be transmitted in the first temporary array by right-aligning it with the first temporary array, and storing the padding data in the first temporary array starting from the low bit of the remaining storage space in the first temporary array, where the padding data can be 0 or 1. It can be understood that storing the data to be transmitted in the first temporary array by right-aligning it with the first temporary array by the sending end means that the sending end stores the data to be transmitted in the first temporary array starting from the lowest bit in the first temporary array.

[0094] In an alternative embodiment, the target state control data includes first state control data and first combined state control data; wherein, the first state control data is used to control the TAP controller to maintain the shift register state; the data length of the first state control data is the same as the data length of the data to be transmitted; the first combined state control data is used to control the TAP controller to transition from the shift register state to the target state; then the process of the sending end storing the target state control data in the second temporary array includes: determining the first state control data; then, storing the first state control data in the second temporary array with right alignment; further, storing each state control data in the first combined state control data in the second temporary array starting from the lower bit of the remaining storage space in the second temporary array; the first state control data used to control the TAP controller to maintain the shift register state and the first combined state control data used to control the TAP controller to transition from the shift register state to the target state can be stored sequentially from the lowest bit in the second temporary array, ensuring that after multiple state control data for controlling the TAP controller to transition from the shift register state to the target state are sent to the TAP controller at one time, during the storage process of the data to be transmitted, the TAP controller is precisely maintained in the shift register state, and after the data storage is completed, the state transition is performed according to the standard process of state transition, improving the communication efficiency while ensuring precise control of the state transition of the TAP controller and that the data to be transmitted can be completely stored.

[0095] In an alternative embodiment, the first combined state control data includes second state control data, third state control data, and fourth state control data; wherein, the second state control data is used to control the TAP controller to transition from the shift register state to the pause register state through the first exit register state; the third state control data is used to control the TAP controller to maintain the pause register state, and the fourth state control data is used to control the TAP controller to transition from the maintained pause register state to the target state, the target state being the second exit register state or the next-round shift register state; wherein, before the TAP controller transitions from the maintained pause register state to the next-round shift register state, it needs to first transition to the update register state.

[0096] It can be understood that when the shift register state is the shift data register state, the first exit register state is the first exit data register state (Exit1-DR), the pause register state is the pause data register state (Pause-DR), the second exit register state is the second exit data register state (Exit2-DR), and the update register state is the update data register state (Update-DR); similarly, when the shift register state is the shift instruction register state, the first exit register state is the first exit instruction register state (Exit1-IR), the pause register state is the pause instruction register state (Pause-IR), the second exit register state is the second exit instruction register state (Exit2-IR), and the update register state is the update instruction register state (Update-IR).

[0097] Exemplarily, as Figure 3 shown Figure 3 Fig. shows the state transition flowchart starting from the shift register state in the embodiment of the present application. Among them, the TAP controller starts from the shift register state 301, sequentially passes through the first exit register state 302, the pause register state 303 to enter the second exit data register state 304, and before entering the next round of shift register state 301, passes through the update register state 305; where TMS is the state control data, Figure 3 The shown state transition process is applicable to the state transition process starting from the shift data register state or the shift instruction register state.

[0098] Among them, the process in which the sending end stores each state control data in the first combined state control data in the second temporary array starting from the lower bit of the remaining storage space in the second temporary array includes: determining the second state control data and storing the second state control data in the second temporary array starting from the lower bit of the first remaining storage space in the second temporary array; then, determining the third state control data and storing the third state control data in the second temporary array starting from the lower bit of the second remaining storage space in the second temporary array; further, determining the fourth state control data and storing the fourth state control data in the second temporary array starting from the lower bit of the third remaining storage space in the second temporary array; where the first remaining storage space is the remaining storage space in the second temporary array after storing the first state control data, and the second remaining storage space is the remaining storage space in the second temporary array after storing the second state control data, and the third remaining storage space is the remaining storage space in the second temporary array after storing the third state control data. The state control data for controlling each state transition can be sequentially stored in the second temporary array according to the sequence of state transitions during the process of the TAP controller transitioning from the shift register state to the target state, so that after the TAP controller receives the state control data for controlling multiple state transitions at one time, it can perform multiple state transitions strictly in the sequence of state transitions. On the basis of reducing the interaction frequency during the process of controlling the TAP controller to perform multiple state transitions, the accuracy of controlling the TAP controller to perform state transitions is ensured.

[0099] For example, Figure 4 as shown Figure 4 shows a schematic diagram of the process of filling the first temporary array and the second temporary array in the state transition process based on the TAP controller provided by the embodiment of the present application when the target state is the second exit register state or the next round of shift register state. Among them, for the first temporary array 401, since when maintaining the shift register state (Shift-DR state or Shift-IR state), the data to be transmitted that the TAP controller needs to process is 0101, starting from the lower bit of the first temporary array, the data to be transmitted 0101 is stored in four data bits 4011 in the first temporary array, and then padding data is stored in the remaining storage space in the first temporary array; X, and X can be 0 or 1.

[0100] For the second temporary array 402, since the first state control data for controlling the TAP controller to maintain the shift register state (Shift-DR state or Shift-IR state) is 1000, starting from the low bit of the second temporary array, the first state control data 1000 is stored in four data bits 4021 in the second temporary array. Then, the second state control data and the third state control data are stored starting from the low bit of the remaining storage space of the second temporary array 402, and the second state control data and the third state control data are stored in the corresponding storage positions 4022 in the second temporary array 402. Further, the fourth state control data is stored in the corresponding storage position 4023 in the second temporary array 402; wherein, in the first temporary array, the storage position 4012 corresponding to the storage position 4022 stores padding data, and the storage position 4013 corresponding to the storage position 4023 also stores padding data.

[0101] In an alternative embodiment, the target state control data includes the first state control data and a state control data set. The state control data set includes the state control data for controlling each state transition during the process of transitioning from the shift register state to the target state. The process by which the sending end stores the target state control data in the second temporary array may include: determining the first state control data and the state control data set, and storing the first state control data and the state control data set in the second temporary array starting from the low bit in the order of state transitions.

[0102] It should be noted that the process by which the JTAG driver at the sending end determines the state control data for controlling each state transition may include: the JTAG driver at the sending end obtains the state control data for controlling each state transition from the JTAG application layer at the sending end.

[0103] In an alternative embodiment, before storing each state control data in the first combined state control data in the second temporary array starting from the lower position of the remaining storage space in the second temporary array, the sender may further: in the case where the length of the first combined state control data is greater than the length of the remaining storage space, expand the second temporary array to obtain an expanded second temporary array; wherein, storing each state control data in the first combined state control data in the second temporary array starting from the lower position of the remaining storage space in the second temporary array includes: storing the state data in the first combined state control data that has not been stored in the remaining storage space in the expanded second temporary array starting from the lower position of the remaining storage space in the expanded second temporary array. After storing the first state control data for controlling the TAP controller to maintain the shift register state in the second temporary array, if the remaining storage space in the second temporary array is not sufficient to store the state control data for controlling the TAP controller to perform multiple state transitions, expand the second temporary array, so that in the case where the remaining storage space in the second temporary array is insufficient, the state control data for controlling the TAP controller to perform multiple state transitions can be sent to the TAP controller at one time through array expansion, improving the communication efficiency in the case where the storage space of the second temporary array is insufficient.

[0104] In an alternative embodiment, after expanding the second temporary array, the sender may further: expand the first temporary array to obtain an expanded first temporary array; then, store the newly added padding data in the expanded first temporary array starting from the lower position of the remaining storage space in the expanded first temporary array, wherein the data lengths of the expanded first temporary array and the expanded second temporary array are the same. The first temporary array can be expanded after the second temporary array is expanded to ensure that the data lengths of the target transmission data and the state control data sent to the TAP controller are the same, ensuring that the TAP controller can completely store the data to be transmitted and accurately execute multiple state transition processes, and ensuring the normal operation of the TAP controller on the premise of ensuring one-time transmission of multiple bits of data.

[0105] In an alternative embodiment, after the sender stores the target state control data in the second temporary array, if there is still remaining storage space in the second temporary array, padding data may be stored in the remaining storage space in the second temporary array to ensure that the data lengths of the target transmission data and the state control data sent to the TAP controller at one time are the same.

[0106] In S203, the sender sends the first target transmission data and the target state control data.

[0107] In an embodiment of the present application, after the first temporary array and the second temporary array are both full, the sending end sends the first target transmission data in the first temporary array and the target status control data in the second temporary array to the TAP controller.

[0108] In an alternative embodiment, the process of the sending end sending the first target transmission data and the target status control data includes: the sending end sends the first target transmission data in the first temporary array to the TAP controller through the TDI signal line of the JTAG interface; at the same time, the target status control data in the second temporary array is sent to the TAP controller through the TMS signal line of the JTAG interface.

[0109] It should be noted that in a scenario of communicating based on the JTAG interface, there are cases where data needs to be transmitted in multiple batches, and the data length of each batch of data to be transmitted is much larger than the data length threshold. For example, during the firmware upgrade process, each function or module data in the firmware data needs to be sent to the receiving end in multiple batches, and the data length of each function or module data is much larger than the data length threshold.

[0110] In an alternative embodiment, when the TAP controller is in the shift register state, after determining the data length of the data to be transmitted, if the data length is greater than the data length threshold, the sending end stores the second target transmission data in the first temporary array; then, the second target transmission data is sent; wherein, the second target transmission data is the current transmission data in the data to be transmitted; the data length of the second target transmission data is the same as the data length threshold; multiple bits of the data to be transmitted can be sent to the TAP controller at one time when the data length of the data to be transmitted is greater than the data length threshold, so as to facilitate the fast transmission of data in the scenario of large data volume data transmission, and improve the communication efficiency based on the JTAG protocol in the case of large data volume.

[0111] Optionally, when the data length is greater than the data length threshold, after sending the second target transmission data, the sending end can also repeatedly determine the remaining data in the data to be transmitted as the updated data to be transmitted, and according to the comparison result between the updated data length of the updated data to be transmitted and the data length threshold, repeatedly send the updated second target transmission data to the TAP controller until the updated data length is less than the data length threshold, and send the updated first target transmission data and the target status control data to the TAP controller, so as to facilitate the transmission of a large amount of data in multiple batches in multiple rounds to the receiving end. Since multiple bits of data can be transmitted at one time, the data transmission efficiency in the scenario of large data volume data transmission is further improved.

[0112] In an optional embodiment, when the test access interface TAP controller is in a shift register state, the sending end determines the data length of the data to be transmitted. If the data length is equal to the data length threshold, the data to be transmitted can be stored in a first temporary array; further, the third target transmission data in the first temporary array is sent to the TAP controller.

[0113] It can be understood that, when the data length is greater than or equal to the data length threshold, the sending end can also store the first state control data in the second temporary array, and the data length of the first state control data is the same as the data length threshold, and send the first state control data to the receiving end while sending the second target transmission data, so that the receiving end responds to the first state control data to remain in the shift register state, and then store the current transmission data.

[0114] It should be noted that, in the embodiment of the present application, the process in which the transmitting end executes the data transmission method based on the JTAG protocol provided in the above embodiment is mainly implemented by the driver of the transmitting end driving layer.

[0115] Figure 5 A flow chart of a data transmission method based on the JTAG protocol of an exemplary embodiment of the present application is shown. The method can be applied to a data receiving end that communicates based on the JTAG protocol, such as Figure 5 As shown, the method of the embodiment of the present application may include:

[0116] S501, receiving first target transmission data and target state control data;

[0117] The first target transmission data includes data to be transmitted and padding data, and the target state control data is used to control the TAP controller to switch from the holding shift register state to the target state;

[0118] S502 , in response to the target state control data, filtering the padding data and storing the data to be transmitted.

[0119] In summary, the data transmission method based on the JTAG protocol provided in the embodiment of the present application can obtain the data to be transmitted at one time, as well as control the TAP controller at the receiving end to switch from maintaining the shift register state to the target state, all the state control data required, and perform multiple state transitions based on the state control data received once, thereby avoiding the interaction overhead caused by frequently receiving the state control data sent by the sending end before starting the next data storage, reducing the interaction cost of the receiving end, and improving communication efficiency and fluency.

[0120] It is understandable that, after storing the data to be transmitted, the receiving end may also switch from the shift register state to the target state in response to the target state control data.

[0121] In an alternative embodiment, before the receiving end enters the shift register state, the sending end can also receive the fifth state control data sent by the sending end through the TMS signal line of the JTAG interface, and perform initialization in response to the fifth state control data to enter the test logic reset state.

[0122] Optionally, the receiving end can also receive the second combined state control data sent by the sending end, and in response to the second combined state control data, convert from the test logic reset state to the shift register state; after entering the test logic reset state, it can execute the TAP controller state conversion process to enter the shift register state through the combined state control data received at one time, reducing the interaction frequency with the sending end during the process of converting from the test logic reset state to the shift register state through multiple intermediate states, further reducing the interaction cost, and improving the state conversion efficiency of the receiving end.

[0123] Exemplarily, in the firmware upgrade scenario in the server, as Figure 6 shown, Figure 6 shows a schematic diagram of the application scenario of the data transmission method based on the JTAG protocol provided in the above embodiment in a firmware upgrade scenario. Among them, the server includes a baseboard management controller unit 601 and a complex programmable logic device unit 602. The BMC unit includes a JTAG driver 6011 and a JTAG controller 6012. The JTAG driver 6011 is deployed in the driver layer of the BMC unit, and is used to obtain the firmware to be transmitted from the application layer and execute the data transmission method based on the JTAG protocol provided in the above instance. The JTAG controller 6012 is used to generate and send the TCK signal, TMS signal, and TDI signal required for JTAG communication under the drive of the JTAG driver.

[0124] The CPLD unit includes a TAP controller 6021 and a flash memory (flash) 6022. The TAP controller 6021 is used to receive the state control data (TMS signal) sent by the JTAG controller, perform state conversion and execute operations related to each state. The flash memory 6022 is used to upgrade the firmware of the CPLD unit after the TAP controller receives the firmware data.

[0125] Among them, as Figure 7 shown, the process of firmware upgrade of the CPLD unit in the server can include:

[0126] S701, obtain the firmware to be upgraded;

[0127] Among them, the application layer of the server can respond to the firmware upgrade instruction, read the unparsed firmware to be upgraded from the sending end, or receive the unparsed firmware to be upgraded sent by the terminal device.

[0128] S702, Parse the firmware to be upgraded at the application layer to obtain parsed firmware data, and transmit the parsed firmware data to the driver layer of the BMC unit;

[0129] S703, The JTAG driver in the driver layer of the BMC unit responds to obtaining the parsed firmware data, obtains the fifth state control data from the application layer, and drives the JTAG controller to send the fifth state control data to the TAP controller in the CPLD unit through the TMS signal line of the JTAG interface;

[0130] S704, The JTAG driver obtains the second combined state control data from the application layer and sends it to the TAP controller in the CPLD unit;

[0131] S705, The JTAG driver determines whether the data length of the parsed firmware data is greater than the data length threshold;

[0132] S706, If the data length is greater than the data length threshold, the JTAG driver stores the current transmission data in the parsed firmware data in the first temporary array, and sends it to the TAP controller in the CPLD unit, and, repeatedly determines the remaining data in the parsed firmware data as the updated parsed firmware data, and repeats the above process starting from 706 according to the updated parsed firmware data;

[0133] S707, When the data length is less than the data length threshold, the JTAG driver stores the updated parsed firmware data and padding data in the first temporary array, and stores the target state control data in the second temporary array;

[0134] S708, After the JTAG driver determines that both the first temporary array and the second temporary array are full, it drives the JTAG controller to send the target state control data to the TAP controller in the CPLD unit through the TMS signal line of the JTAG interface, and sends the first target transmission data in the first temporary array to the TAP controller in the CPLD unit through the TDI signal line of the JTAG interface;

[0135] S709, The TAP controller responds to the target state control data, controls the TAP controller to maintain the shift register state, and writes the updated parsed firmware data into the flash memory, and, in response to the target state control data, controls the TAP controller to transition from the shift register state to the target state and filter the padding data;

[0136] S710, The CPLD unit performs firmware upgrade based on all the parsed firmware data in the flash memory.

[0137] An exemplary embodiment of the present application provides a data transmission device based on the JTAG protocol. Figure 8 FIG. Figure 8 shows a schematic block diagram of functional modules of a data transmission device based on the JTAG protocol according to an exemplary embodiment of the present application. As Figure 8 shown, the data transmission device 800 based on the JTAG protocol includes:

[0138] A determination module 801, configured to determine the data length of data to be transmitted when a test access port (TAP) controller is in a shift register state;

[0139] A storage module 802, configured to store first target transmission data in a first temporary array and store target state control data in a second temporary array when the data length is less than a data length threshold;

[0140] wherein, the data length threshold is equal to the array lengths of the first temporary array and the second temporary array; the first target transmission data includes the data to be transmitted and padding data; the target state control data is used to control the TAP controller to transition from the shift register state to a target state;

[0141] A sending module 803, configured to send the first target transmission data and the target state control data.

[0142] Optionally, as Figure 8 shown, the device further includes a processing module 804, configured to:

[0143] store second target transmission data in the first temporary array when the data length is greater than the data length threshold; the second target transmission data is the current transmission data in the data to be transmitted; the data length of the second target transmission data is the same as the data length threshold;

[0144] send the second target transmission data.

[0145] Optionally, the target state control data includes first state control data and first combined state control data; wherein, the first state control data is used to control the TAP controller to maintain the shift register state; the data length of the first state control data is the same as the data length of the data to be transmitted;

[0146] the first combined state control data is used to control the TAP controller to transition from the shift register state to the target state;

[0147] The storage module 802 is configured to:

[0148] determine the first state control data;

[0149] store the first state control data and the second temporary array in the second temporary array in a right-aligned manner;

[0150] Store each state control data in the first combined state control data into the second temporary array starting from the lower bit of the remaining storage space in the second temporary array;

[0151] Optionally, as Figure 8 shown, the apparatus further includes an expansion module 805, configured to:

[0152] When the length of the first combined state control data is greater than the length of the remaining storage space, expand the second temporary array to obtain an expanded second temporary array;

[0153] Storing each state control data in the first combined state control data into the second temporary array starting from the lower bit of the remaining storage space in the second temporary array includes:

[0154] Store the state data in the first combined state control data that has not been stored in the remaining storage space into the expanded second temporary array starting from the lower bit of the remaining storage space in the expanded second temporary array.

[0155] Optionally, the expansion module 805 is further configured to:

[0156] Expand the first temporary array to obtain an expanded first temporary array, where the data lengths of the expanded first temporary array and the expanded second temporary array are the same;

[0157] Store the newly added padding data into the expanded first temporary array starting from the lower bit of the remaining storage space in the expanded first temporary array.

[0158] Optionally, the first combined state control data includes second state control data, third state control data, and fourth state control data; wherein, the second state control data is used to control the TAP controller to transition from the shift register state through the first exit register state to the pause register state; the third state control data is used to control the TAP controller to maintain the pause register state; the fourth state control data is used to control the TAP controller to transition from the maintained pause register state to a target state, and the target state is the second exit register state or the next round of the shift register state;

[0159] The storage module 802 is configured to:

[0160] Determine the second state control data and store the second state control data into the second temporary array starting from the lower bit of the first remaining storage space in the second temporary array; wherein, the first remaining storage space is the remaining storage space in the second temporary array after storing the first state control data;

[0161] Determine the third state control data, and store the third state control data in the second temporary array starting from the lower bit of the second remaining storage space in the second temporary array; wherein, the second remaining storage space is the remaining storage space in the second temporary array after storing the second state control data;

[0162] Determine the fourth state control data, and store the fourth state control data in the second temporary array starting from the lower bit of the third remaining storage space in the second temporary array; wherein, the third remaining storage space is the remaining storage space in the second temporary array after storing the third state control data.

[0163] Optionally, the apparatus further includes a state control module 806, configured to:

[0164] Store the second combined state control data in the second temporary array; the second combined state control data is used to control the TAP controller to transition from the test logic reset state to the shift register state; the length of the second combined state control data is equal to the length of the second temporary array;

[0165] Send the second combined state control data.

[0166] An exemplary embodiment of the present application provides a data transmission apparatus based on the JTAG protocol, Figure 9 which shows a schematic block diagram of functional modules of a data transmission apparatus based on the JTAG protocol according to an exemplary embodiment of the present application. As Figure 9 shown, the data transmission apparatus 900 based on the JTAG protocol includes:

[0167] A receiving module 901, configured to receive first target transmission data and target state control data; wherein, the first target transmission data includes data to be transmitted and padding data; the target state control data is used to control the TAP controller to transition from the hold shift register state to the target state;

[0168] A storage module 902, configured to filter the padding data and store the data to be transmitted in response to the target state control data.

[0169] An exemplary embodiment of the present application further provides a non-transitory computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor of a computer, is used to cause the computer to execute the method according to an embodiment of the present application.

[0170] As Figure 10 shown, an exemplary embodiment of the present application further provides a computer program product 1000, including a computer program 1001, wherein the computer program, when executed by a processor of a computer, is used to cause the computer to execute the method according to an embodiment of the present application.

[0171] An embodiment of the present application further provides a computing device, which includes a data sending device and a data receiving device; the data sending device and the data receiving device are electrically connected; the data sending device is used to execute the data transmission method based on the JTAG protocol performed by the sending end in the above embodiment, and the data receiving device is used to execute the data transmission method based on the JTAG protocol performed by the receiving end in the above embodiment; the computing device is intended to represent electronic devices in various forms of digital electronics, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0172] Optionally, when the computing device is a server, the data sending device is a baseboard management controller; the receiving device is a programmable logic device; specifically, reference may be made to Figure 6 , and the embodiments of the present disclosure will not elaborate on this.

[0173] Reference Figure 11 , the structural block diagram of the computing device 1100 that can be used as the present application will now be described, which is an example of a hardware device that can be applied to various aspects of the present application; as Figure 11 shown, the computing device 1100 includes a computing unit 1101, which can execute various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 1102 or the computer program loaded from the storage unit 1108 into the random access memory (RAM) 1103. In the RAM 1103, various programs and data required for the operation of the computing device 1100 can also be stored. The computing unit 1101, the ROM 1102, and the RAM 1103 are connected to each other through a bus 1104. The input / output (I / O) interface 1105 is also connected to the bus 1104.

[0174] Multiple components in the computing device 1100 are connected to the I / O interface 1105, including: an input unit 1106, an output unit 1107, a storage unit 1108, and a communication unit 1109. The input unit 1106 can be any type of device capable of inputting information into the computing device 1100. The input unit 1106 can receive input digital or character information and generate key signal inputs related to the user settings and / or function controls of the computing device. The output unit 1107 can be any type of device capable of presenting information and can include, but is not limited to, a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 1108 can include, but is not limited to, magnetic disks and optical disks. The communication unit 1109 allows the computing device 1100 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks and can include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a Bluetooth™ device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0175] The computing unit 1101 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1101 executes the various methods and processes described above. For example, in some embodiments, the methods of the exemplary embodiments of the present application can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 1108. In some embodiments, part or all of the computer program can be loaded and / or installed onto the computing device 1100 via the ROM 1102 and / or the communication unit 1109. In some embodiments, the computing unit 1101 can be configured to execute the methods of the exemplary embodiments of the present application in any other suitable manner (e.g., by means of firmware).

[0176] The program code for implementing the methods of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program codes can be executed entirely on the machine, partially on the machine, as an independent software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0177] In the context of this application, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0178] As used in this application, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and / or device that can be used to provide machine instructions and / or data to a programmable processor (e.g., a magnetic disk, an optical disk, a memory, a programmable logic device (PLD)), including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal that can be used to provide machine instructions and / or data to a programmable processor.

[0179] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0180] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user device, or other programmable devices. The computer program or instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless manner. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it may also be an optical medium, such as a digital video disc (DVD); or it may be a semiconductor medium, such as a solid state drive (SSD).

[0181] Although the present application has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A data transmission method based on the JTAG protocol, characterized in that The method includes: When the test access interface TAP controller is in the shift register state, determining the data length of the data to be transmitted; When the data length is less than the data length threshold, storing the first target transmission data in a first temporary array and storing the target state control data in a second temporary array; Wherein, the data length threshold is equal to the array lengths of the first temporary array and the second temporary array; the first target transmission data includes the data to be transmitted and padding data; the target state control data is used to control the TAP controller to transition from maintaining the shift register state to a target state; Sending the first target transmission data and the target state control data.

2. The data transmission method based on the JTAG protocol according to claim 1, characterized in that, The method further includes: When the data length is greater than the data length threshold, storing second target transmission data in the first temporary array; the second target transmission data is the current transmission data in the data to be transmitted; the data length of the second target transmission data is the same as the data length threshold; Sending the second target transmission data.

3. The data transmission method based on the JTAG protocol according to claim 1, wherein The target state control data includes first state control data and first combined state control data; wherein, the first state control data is used to control the TAP controller to maintain the shift register state; the data length of the first state control data is the same as the data length of the data to be transmitted; The first combined state control data is used to control the TAP controller to transition from the shift register state to the target state; The storing the target state control data in the second temporary array includes: Determining the first state control data; Storing the first state control data and the second temporary array in the second temporary array with right alignment; Storing each state control data in the first combined state control data in the second temporary array starting from the low position of the remaining storage space in the second temporary array.

4. The data transmission method based on the JTAG protocol according to claim 3, wherein Before storing each state control data in the first combined state control data in the second temporary array starting from the low position of the remaining storage space in the second temporary array, the method further includes: When the length of the first combined state control data is greater than the length of the remaining storage space, expanding the second temporary array to obtain an expanded second temporary array; The storing each state control data in the first combined state control data in the second temporary array starting from the low position of the remaining storage space in the second temporary array includes: Storing the state data in the first combined state control data that has not been stored in the remaining storage space in the expanded second temporary array starting from the low position of the remaining storage space in the expanded second temporary array.

5. The data transmission method based on the JTAG protocol according to claim 4, wherein The method further includes: Expanding the first temporary array to obtain an expanded first temporary array, wherein the data lengths of the expanded first temporary array and the expanded second temporary array are the same; Starting from the lower bit of the remaining storage space in the expanded first temporary array, store the newly added padding data in the expanded first temporary array.

6. The data transmission method based on the JTAG protocol according to claim 3, characterized in that The first combined state control data includes second state control data, third state control data, and fourth state control data; wherein, the second state control data is used to control the TAP controller to transition from the shift register state, through a first exit register state to the pause register state; the third state control data is used to control the TAP controller to maintain the pause register state; the fourth state control data is used to control the TAP controller to transition from maintaining the pause register state to the target state, and the target state is the second exit register state, or the shift register state of the next round. The storing each state control data in the first combined state control data in the second temporary array starting from the lower bit of the remaining storage space in the second temporary array includes: Determine the second state control data, and store the second state control data in the second temporary array starting from the lower bit of the first remaining storage space in the second temporary array; wherein, the first remaining storage space is the remaining storage space in the second temporary array after storing the first state control data. Determine the third state control data, and store the third state control data in the second temporary array starting from the lower bit of the second remaining storage space in the second temporary array; wherein, the second remaining storage space is the remaining storage space in the second temporary array after storing the second state control data. Determine the fourth state control data, and store the fourth state control data in the second temporary array starting from the lower bit of the third remaining storage space in the second temporary array; wherein, the third remaining storage space is the remaining storage space in the second temporary array after storing the third state control data.

7. The data transmission method based on the JTAG protocol according to claim 1, characterized in that The method further includes: Store second combined state control data in the second temporary array; the second combined state control data is used to control the TAP controller to transition from the test logic reset state to the shift register state; the length of the second combined state control data is equal to the length of the second temporary array. Send the second combined state control data.

8. A data transmission method based on the JTAG protocol, characterized in that, The method includes: Receive first target transfer data and target state control data; wherein, the first target transfer data includes data to be transferred and padding data; the target state control data is used to control the TAP controller to transition from maintaining the shift register state to the target state. In response to the target state control data, filter the padding data and store the data to be transferred.

9. A computing device, characterized in that, The computing device includes a data sending device and a data receiving device; the data sending device and the data receiving device are electrically connected; the data sending device is used to execute the data transmission method based on the JTAG protocol as described in any one of claims 1-7, and the data receiving device is used to execute the data transmission method based on the JTAG protocol as described in claim 8.

10. The computing device according to claim 9, wherein The data sending device is a baseboard management controller; the receiving device is a programmable logic device.

Images