Display device and electronic apparatus

Abstract

A display device and an electronic apparatus are provided. The display device includes a substrate, a repair line disposed on the substrate, an insulating layer covering the repair line, a first thin film transistor disposed in the insulating layer, a first connection line disposed on the insulating layer and overlapping at least a portion of the repair line, and a light emitting element disposed on the first connection line and connected to the first connection line, wherein the insulating layer includes a first groove on the repair line.

Description

[0001] Cross - reference to related applications

[0002] This application is based on and claims the priority of Korean Patent Application No. 10 - 2024 - 0006756, filed with the Korean Intellectual Property Office on January 16, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more embodiments relate to a display device, and more particularly, to a display device including an organic light - emitting diode. Background art

[0004] A display device visually displays data. The display device may include a substrate divided into a display area and a peripheral area. A plurality of light - emitting elements may be provided in the display area. Each of the light - emitting elements may be connected to a corresponding thin - film transistor and further connected to a sub - pixel circuit to receive current.

[0005] In a display device, some light - emitting elements may malfunction due to errors during the manufacturing process. Such malfunctioning light - emitting elements can be repaired to operate correctly. The repair process may require disconnecting the malfunctioning light - emitting element from the corresponding sub - pixel circuit and connecting the light - emitting element to a dummy sub - pixel circuit provided in the peripheral area. In this case, a repair line may be provided, where the repair line overlaps with a part of the wiring of the light - emitting element and a part of the wiring of the dummy sub - pixel circuit. The repair line may extend across the boundary between the display area and the peripheral area. Summary of the invention

[0006] According to one or more embodiments, a display device includes a substrate, a repair line provided on the substrate, an insulating layer covering the repair line, a first thin - film transistor provided in the insulating layer, a first connection line provided on the insulating layer and overlapping at least a part of the repair line, and a light - emitting element provided on the first connection line and connected to the first connection line, wherein the insulating layer includes a first groove on the repair line.

[0007] The part of the first connection line located on the repair line may be disposed in the first groove.

[0008] The first thin - film transistor may include an active layer including a semiconductor, and the repair line may be provided at a layer located under the active layer.

[0009] The first connection line may be disposed in the same layer as the source electrode or the drain electrode of the first thin - film transistor.

[0010] The first distance between the upper surface of the repair line and the upper surface of the insulating layer in the region overlapping with the first groove may be about 20% to about 80% of the second distance between the upper surface of the repair line and the upper surface of the insulating layer in the region outside the first groove.

[0011] The depth of the first groove may be about 20% to about 80% of the thickness of the insulating layer.

[0012] The edge of the repair line and the edge of the first groove are separated from each other by 1 μm or more in one of the first direction and the second direction.

[0013] The display device may further include an adjacent line disposed under the insulating layer and adjacent to the repair line, wherein the distance between the repair line and the adjacent line in one of the first direction and the second direction may be 2 μm or more.

[0014] In a plan view, the repair line may extend in the first direction, and the first connection line may extend in a second direction intersecting the first direction.

[0015] A portion of the repair line may extend in the second direction and overlap with the first connection line.

[0016] The insulating layer may include a first opening extending through the insulating layer located between the portion of the repair line and the portion of the first connection line in the first groove.

[0017] The repair line and the first connection line may fill the first opening in the insulating layer and be in direct contact with each other.

[0018] The first connection line may be disconnected from the first thin film transistor.

[0019] The display device may further include a second thin film transistor spaced apart from the light emitting element and the first thin film transistor and disposed in the insulating layer, and a second connection line connected to the second thin film transistor, wherein the insulating layer may further include a second groove, and wherein the repair line, the second groove, and the second connection line may overlap.

[0020] The insulating layer may include a second opening extending through the insulating layer located between the portion of the repair line and the portion of the second connection line in the second groove, wherein the repair line and the second connection line may fill the second opening in the insulating layer and be in direct contact with each other.

[0021] The display device may include a display area in which a light emitting element, a first thin film transistor, and a first connection line are disposed, and a peripheral area in which a second thin film transistor and a second connection line are disposed, wherein the peripheral area may at least partially surround the display area.

[0022] According to one or more embodiments, a display device includes: a substrate including a display area in which light-emitting elements are arranged and a peripheral area surrounding the display area, a first thin-film transistor disposed on the substrate in the display area, a first connection line disposed on the first thin-film transistor in the display area, a second thin-film transistor disposed on the substrate in the peripheral area, a second connection line disposed on the second thin-film transistor in the peripheral area, a repair line continuously extending across the display area and the peripheral area, and an insulating layer located between the repair line and the first connection line and the second connection line, wherein the repair line is disposed at a layer located under the first thin-film transistor and the second thin-film transistor.

[0023] The repair line may overlap a portion of the first connection line and a portion of the second connection line.

[0024] The insulating layer may include a first groove and a second groove, wherein the first groove overlaps the repair line and the first connection line, and the second groove overlaps the repair line and the second connection line.

[0025] At least one of the depth of the first groove and the depth of the second groove may be about 20% to about 80% of the thickness of the insulating layer.

[0026] The first connection line may be disposed in the same layer as the source electrode or the drain electrode of the first thin-film transistor.

[0027] In a plan view, the repair line may extend in a first direction, and at least one of the first connection line and the second connection line may extend in a second direction intersecting the first direction.

[0028] A portion of the repair line may extend in the second direction and overlap at least one of the first connection line and the second connection line.

[0029] The insulating layer may include a first opening and a second opening extending through the insulating layer, wherein the first opening extends between the repair line and the first connection line, and the second opening extends between the repair line and the second connection line, and the repair line and the first connection line may fill the first opening and be in direct contact with each other, and the repair line and the second connection line may fill the second opening and be in direct contact with each other.

[0030] The light-emitting element may be electrically connected to the second thin-film transistor through the first connection line, the repair line, and the second connection line.

[0031] According to one or more embodiments, an electronic device includes a display device and a housing surrounding the display device, wherein the display device includes a substrate, a repair line disposed on the substrate, an insulating layer located on the repair line, a first thin film transistor disposed in the insulating layer, a first connection line disposed on the insulating layer and overlapping at least a portion of the repair line, and a light emitting element disposed on the first connection line and connected to the first connection line, wherein the insulating layer is thinner in a region above the repair line than in other regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a schematic perspective view of an electronic device according to an embodiment;

[0034] Figure 2 is a schematic perspective view of a display device according to an embodiment;

[0035] Figure 3 is a schematic plan view of a display device according to an embodiment;

[0036] Figure 4 is a schematic enlarged plan view of a portion of a display device according to an embodiment;

[0037] Figures 5A to 5C is where Figure 4 is an enlarged plan view of a region where a first connection line or a second connection line overlaps with a repair line;

[0038] Figure 6A is a cross-sectional view of a portion of a display device according to an embodiment;

[0039] Figure 6B is Figure 6A an enlarged cross-sectional view of a portion of the display device;

[0040] Figure 7A is a cross-sectional view of a portion of a display device according to another embodiment;

[0041] Figure 7B is Figure 7A an enlarged cross-sectional view of a portion of the display device;

[0042] Figure 8A is a cross-sectional view of a portion of a display device according to another embodiment;

[0043] Figure 8B is Figure 8A an enlarged cross-sectional view of a portion of the display device;

[0044] Figures 9A to 9Cis a schematic plan view showing operations in a process of manufacturing a display device according to an embodiment;

[0045] Figures 10A to 10C is a sectional view showing an operation of connecting a light-emitting diode to a second sub-pixel circuit in a specific case described with reference to Figure 3 and Figure 4 ;

[0046] Figure 11 is Figure 10C an enlarged sectional view of a part of; and

[0047] Figures 12A to 12C is a sectional view showing operations in a process of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0048] Now, embodiments will be described with reference to the accompanying drawings, in which examples of the embodiments are shown, and like reference numerals always indicate like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by referring to the drawings to explain aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items. Throughout the present disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0049] Since the present disclosure allows various changes and numerous embodiments, certain embodiments will be shown in the drawings and described in the written description. The effects and features of the present disclosure and the methods for achieving them will be clarified with reference to the embodiments described in detail below with reference to the drawings. However, the present disclosure is not limited to the following embodiments and may be embodied in various forms.

[0050] Hereinafter, embodiments will be described with reference to the drawings, in which like reference numerals always indicate like elements and repeated descriptions thereof are omitted.

[0051] Although terms such as "first" and "second" may be used to describe respective elements, such elements are not necessarily limited by the above terms. The above terms are used to distinguish one element from another.

[0052] Unless the context clearly indicates otherwise, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms.

[0053] It should be understood that as used herein, the terms "comprising", "comprises", "including" and / or "includes" specify the presence of the recited features or elements, but do not preclude the addition of one or more other features or elements.

[0054] It should also be understood that when a layer, region or element is referred to as being "on" another layer, region or element, it can be directly or indirectly on the other layer, region or element. That is, for example, there can be intervening layers, regions or elements. A first layer, region or element being "under" a second layer, region or element refers to an arrangement in which the second layer, region or element is "on" the first layer, region or element. Two layers, regions or elements "overlap" means that one of the two layers, regions or elements is on the other of the two layers, regions or elements, regardless of which one is on top.

[0055] For the sake of explanation, the sizes of the elements in the drawings can be exaggerated or reduced. For example, the size and thickness of each element shown in the drawings are arbitrarily represented for the convenience of description, and thus, the present disclosure is not necessarily limited to the relative dimensions depicted.

[0056] The x-axis, y-axis and z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0057] In cases where a certain embodiment can be implemented differently, the process steps can be performed in an order different from the described order. For example, two consecutively described processes can be performed simultaneously or in the reverse order.

[0058] The process of repairing a light-emitting element having a light-emitting defect can be as follows. First, the wiring connecting the light-emitting element to the corresponding sub-pixel circuit can be cut and disconnected. Then, a part of the wiring of the light-emitting element and a part of the repair line can be melted and cooled to be connected to each other. Similarly, a part of the wiring of the dummy sub-pixel circuit and a part of the repair line can be melted and cooled to be connected to each other. Accordingly, the light-emitting element can receive current from the dummy sub-pixel circuit and operate normally.

[0059] In this case, when connecting a part of the wiring of the light-emitting element to a part of the repair line, or connecting a part of the wiring of the dummy sub-pixel circuit to a part of the repair line, the connection may fail when the thickness of the insulating layer between the wirings is thick.

[0060] Aspects will be set forth in part in the following description and in part will be obvious from the description, or can be learned by practicing the presented embodiments of the present disclosure.

[0061] Figure 1It is a schematic perspective view of the electronic device 2 according to an embodiment. Figure 2 It is a schematic perspective view of the display device 1 according to an embodiment.

[0062] Referring to Figure 1 and Figure 2 , the display device 1 is a device configured to display moving or still images, and the electronic device 2 can be configured to display a screen or input or output data. Although the display device 1 is shown in Figure 1 as being used in a mobile phone, the present disclosure is not limited thereto, and the display device 1 can be used as a display screen for various electronic devices including televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile personal computers (UMPCs). In addition, the display device 1 according to an embodiment can be used in electronic devices such as wearable devices including smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). Further, in an embodiment, the display device 1 can be applied to display screens in various electronic devices, such as display screens in instrument panels for automobiles, center control panels for automobiles, or central information displays (CIDs) arranged on instrument panels, in-vehicle mirror displays replacing side mirrors of automobiles, and displays of entertainment systems arranged on the backs of front seats in automobiles for rear seat passengers.

[0063] In an embodiment, the display device 1 can be accommodated in the housing 3 of the electronic device 2. The housing 3 can be a cover configured to protect internal components such as the display device 1 and form the appearance of the electronic device 2. In addition, the display device 1 can be connected to an electronic module of the electronic device 2 and be driven on the electronic device 2. Hereinafter, the display device 1 will be mainly described.

[0064] As Figure 2 shown, the display device 1 can have a generally rectangular shape. For example, as Figure 2 shown, the display device 1 can have a general rectangular planar shape including a short side extending in a first direction (e.g., the ±x direction) and a long side extending in a second direction (e.g., the ±y direction). In an embodiment, a portion where the short side extending in the first direction intersects the long side extending in the second direction can form a corner (e.g., a right angle) shape or a rounded shape having a preset curvature. In addition, the planar shape of the display device 1 is not limited to a rectangular shape, but can have other polygonal shapes, circular shapes, or elliptical shapes.

[0065] The display device 1 may include a display area DA and a peripheral area PA. The display area DA may be configured to display an image. The first sub-pixels P1 may be arranged in the display area DA. Each of the first sub-pixels P1 may be configured to emit light by using a display element. In an embodiment, the first sub-pixels P1 may be configured to emit lights of different colors from each other. In an embodiment, each of the first sub-pixels P1 may be configured to emit red light, green light, or blue light. In an embodiment, each of the first sub-pixels P1 may be configured to emit red light, green light, blue light, or white light. The display device 1 may be configured to display an image by using the light emitted from the first sub-pixels P1.

[0066] The peripheral area PA may be a non-display area in which an image is not displayed. The peripheral area PA may surround at least a part of the display area DA. For example, the peripheral area PA may completely surround the display area DA. The second sub-pixels P2 may be arranged in the peripheral area PA. Each of the second sub-pixels P2 may include the same elements as the first sub-pixels P1 and may be dummy sub-pixels that do not include a display element and are configured not to emit light. For example, even when the display element included in the first sub-pixels P1 is connected to the second sub-pixels P2, the second sub-pixels P2 may be configured to emit light and display an image in the same manner. Hereinafter, although the second sub-pixels P2 are represented by'sub-pixels', it should be understood that the second sub-pixels P2 do not include a display element and do not emit light. A driver, a power line, etc. may be provided in the peripheral area PA, where the driver is configured to provide an electrical signal to the first sub-pixels P1 and the second sub-pixels P2, and the power line is configured to provide power. For example, a scan driver may be provided in the peripheral area PA, where the scan driver is configured to apply a scan signal to the first sub-pixels P1 and the second sub-pixels P2. In addition, a data driver may be arranged in the peripheral area PA, where the data driver is configured to apply a data signal to the first sub-pixels P1 and the second sub-pixels P2.

[0067] Figure 3 is a schematic plan view of a display device according to an embodiment.

[0068] Referring to Figure 3 , a plurality of scan lines SL (e.g., SL1 to SLm), a plurality of data lines DL (e.g., DLR and DL1 to DLm), a plurality of repair lines RL (e.g., RL1 to RLm), a plurality of first sub-pixels P1, and a plurality of second sub-pixels P2 may be provided on the substrate 100, where m is an integer greater than 1.

[0069] The first sub-pixel P1 may be disposed in the display area DA of the substrate 100, and the second sub-pixel P2 may be disposed in the peripheral area PA of the substrate 100. A plurality of scan lines SL, a plurality of data lines DL, and a plurality of repair lines RL may span the display area DA and the peripheral area PA.

[0070] Each of the plurality of scan lines SL may extend in a first direction (e.g., the ±x direction) and be spaced apart from each other in a second direction (e.g., the ±y direction). The extending direction and / or the separating direction of the plurality of scan lines SL are not limited thereto and may be changed differently. The plurality of scan lines SL may be respectively connected to thin film transistors of corresponding first sub-pixels P1 and second sub-pixels P2. As an example, the thin film transistors of the first sub-pixel P1 and the second sub-pixel P2 aligned in the first direction (e.g., the ±x direction) may be connected to the same scan line SL, e.g., the first scan line SL1. The light emitting element of the first sub-pixel P1 may be configured to emit light according to the signal of the scan line SL. Although Figure 3 shows that one first sub-pixel P1 or one second sub-pixel P2 is connected to one scan line SL, the present disclosure is not limited thereto. In another embodiment, the first sub-pixel P1 or the second sub-pixel P2 may be simultaneously connected to a plurality of scan lines SL.

[0071] The plurality of data lines DL may extend in a second direction (e.g., the ±y direction) and be spaced apart from each other in a first direction (e.g., the ±x direction). The extending direction and / or the separating direction of the plurality of data lines DL are not limited thereto and may be changed differently. Each of the plurality of data lines DL may be connected to a thin film transistor of a corresponding first sub-pixel P1 or second sub-pixel P2. For example, the thin film transistors of the first sub-pixel P1 aligned in the second direction (e.g., the ±y direction) may be connected to the same data line DL, e.g., the first data line DL1. Alternatively, the thin film transistors of the second sub-pixel P2 aligned in the second direction (e.g., the ±y direction) may be connected to the same data line DL, e.g., the repair data line DLR. The light emitting element of the first sub-pixel P1 may be configured to emit light according to the signal of the data line DL. Although Figure 3 shows that one first sub-pixel P1 or one second sub-pixel P2 is connected to one data line DL, the present disclosure is not limited thereto. In another embodiment, the first sub-pixel P1 or the second sub-pixel P2 may be simultaneously connected to a plurality of data lines DL. The plurality of scan lines SL and the plurality of data lines DL may cross each other and be insulated.

[0072] A plurality of repair lines RL may extend in a first direction (e.g., the ±x direction) and be spaced apart from each other in a second direction (e.g., the ±y direction). The extending direction and / or the separating direction of the plurality of repair lines RL are not limited thereto and may be changed differently. The plurality of repair lines RL and the plurality of data lines DL may cross each other and be insulated. The repair line RL may be arranged adjacent to at least one first sub-pixel P1 and at least one second sub-pixel P2. As an example, the first scan line SL1 and the first repair line RL1 may be arranged to face each other with a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2 aligned in the first direction (e.g., the ±x direction) therebetween. In a specific case, the repair line RL may be connected to a specific first sub-pixel P1 and an arbitrary second sub-pixel P2, which will be described below.

[0073] Figure 4 is a schematic enlarged plan view of a part of a display device according to an embodiment.

[0074] Referring to Figure 4 , there is shown a first sub-pixel P1, a second sub-pixel P2, a scan line SL, a repair line RL, a data line DL connected to the first sub-pixel P1, and a data line DL or a repair data line DLR connected to the second sub-pixel P2.

[0075] As referred to Figure 3 above, the scan line SL and the repair line RL may extend in a first direction (e.g., the ±x direction), and the data line DL may extend in a second direction (e.g., the ±y direction). The first sub-pixel P1 may include a first sub-pixel circuit PC1 including a thin film transistor and wirings. The second sub-pixel P2 may include a second sub-pixel circuit PC2 including a thin film transistor and wirings. Each of the first sub-pixel circuit PC1 and the second sub-pixel circuit PC2 may be connected to the scan line SL and the data line DL.

[0076] The first sub-pixel P1 may include a first connection line CL1 connected to the first sub-pixel circuit PC1 and extending in the second direction (e.g., the ±y direction). The first connection line CL1 may be connected to a light emitting diode LED as a display element. The first connection line CL1 may overlap with the repair line RL. As an example, in a plan view, the first connection line CL1 may cross and overlap with the repair line RL. Similarly, the second sub-pixel P2 may include a second connection line CL2 connected to the second sub-pixel circuit PC2 and extending in the second direction (e.g., the ±y direction). Different from the first connection line CL1, the second connection line CL2 may not be connected to a separate display element. The second connection line CL2 may overlap with the repair line RL. For example, in a plan view, the second connection line CL2 may cross and overlap with the repair line RL.

[0077] Under most conditions where the first sub-pixel circuit PC1 and the light-emitting diode LED operate normally, the first connection line CL1 is insulated from the repair line RL and the second connection line CL2 is insulated from the repair line RL. Accordingly, the light-emitting diode LED can be connected to the first sub-pixel circuit PC1 and can be not connected to the second sub-pixel circuit PC2. Sometimes, for example, if the first sub-pixel circuit PC1 does not operate as expected due to a defect, the light-emitting diode LED may not operate as expected. In an embodiment of the present disclosure, the first connection line CL1 and the second connection line CL2 can be connected to the repair line RL. In this case, the light-emitting diode LED can be connected to the second sub-pixel circuit PC2 and be turned on to operate as expected. A method of connecting the first connection line CL1 and the second connection line CL2 to the repair line RL in a specific case is described in detail below.

[0078] Figures 5A to 5C is a magnified plan view of a region where Figure 4 either the first connection line CL1 or the second connection line CL2 overlaps with the repair line RL.

[0079] Referring to Figure 5A 、 Figure 5B and Figure 5C , the first connection line CL1 or the second connection line CL2 can extend in a second direction (e.g., the ±y direction), and the repair line RL can extend in a first direction (e.g., the ±x direction). Hereinafter, for convenience, the description will focus on the relationship between the first connection line CL1 and the repair line RL; however, it should be understood that the same content also applies to the relationship between the second connection line CL2 and the repair line RL.

[0080] As Figure 5A and Figure 5B shown, the end of the first connection line CL1 can only overlap with a part of the repair line RL, or as Figure 5C shown, the end of the first connection line CL1 can completely overlap with the repair line RL to span the repair line RL in the second direction (e.g., the ±y direction). Although in Figures 5A to 5C it is shown that the end of the first connection line CL1 overlapping with the repair line RL has a greater width or length in the first direction (e.g., the ±x direction) than other parts of the first connection line CL1, the present disclosure is not limited thereto. In another embodiment, the first connection line CL1 can have a constant length in the first direction (e.g., the ±x direction) along the second direction (e.g., the ±y direction).

[0081] More specifically referring to Figure 5A and Figure 5B, a part of the repair line RL can extend toward the first connection line CL1 in a second direction (e.g., the ±y direction). As an example, the repair line RL can include a protrusion RL-1 that protrudes toward the +y direction and overlaps with the first connection line CL1. The protrusion RL-1 can completely overlap with the first connection line CL1. Although the shape of the protrusion RL-1 is shown as being generally quadrilateral in Figure 5A and Figure 5B , the present disclosure is not limited thereto, and the shape of the protrusion RL-1 can be differently modified into a triangle, a semi-circle, etc.

[0082] The insulating layer described below can be disposed between the repair line RL and the first connection line CL1. A first groove 105-1 can be provided in the insulating layer disposed between the protrusion RL-1 of the repair line RL and the first connection line CL1. A second groove 105-2 can be provided in the insulating layer disposed between another protrusion RL-1 of the repair line RL and the second connection line CL2. The first groove 105-1 and the second groove 105-2 can extend beyond a partial edge of the protrusion RL-1. As an example, the first groove 105-1 can extend beyond the edge of the protrusion RL-1 by a first interval S1, and the second groove 105-2 can extend beyond the edge of the protrusion RL-1 by a second interval S2. As shown in Figure 5A , the first groove 105-1 and the second groove 105-2 can extend beyond the edge of the protrusion RL-1 in the ±x direction. Alternatively, as shown in Figure 5B , the first groove 105-1 and the second groove 105-2 can extend beyond the edge of the protrusion RL-1 in the ±x direction and the +y direction. Alternatively, as shown in Figure 5C , the first groove 105-1 and the second groove 105-2 can extend beyond the edge of the repair line RL in the ±y direction.

[0083] Figure 6A is a cross-sectional view of a part of a display device according to an embodiment. Figure 6B is Figure 6A an enlarged cross-sectional view of a part of the display device.

[0084] Referring to Figure 6A , a first sub-pixel P1 and a second sub-pixel P2 are provided on a substrate 100. The first sub-pixel P1 can be arranged in a display area DA. The first sub-pixel P1 can include a first thin film transistor TFT1 and a light emitting diode LED provided on the substrate 100. The second sub-pixel P2 can be arranged in a peripheral area PA. The second sub-pixel P2 can include a second thin film transistor TFT2 provided on the substrate 100.

[0085] The substrate 100 may include glass or a polymer resin. The polymer resin includes polyethersulfone (PESU), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI) or polycarbonate (PC). The substrate 100 including the polymer resin may be flexible, rollable or bendable. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer.

[0086] The bottom metal layer BML may be disposed on the substrate 100 and may overlap with the first active layer ACT1 of the first thin film transistor TFT1 and the second active layer ACT2 of the second thin film transistor TFT2 described below. The bottom metal layer BML may be configured to block light from reaching the first thin film transistor TFT1 and the second thin film transistor TFT2, where the light is incident from below the substrate 100. The bottom metal layer BML may include a light shielding material. In an embodiment, the bottom metal layer BML may include a light shielding metal such as chromium (Cr) or molybdenum (Mo).

[0087] The repair line RL may be disposed at the same layer as the bottom metal layer BML. Accordingly, it is understood that the repair line RL is disposed at a layer located between the substrate 100 and the layer of the first active layer ACT1 of the first thin film transistor TFT1 and the second active layer ACT2 of the second thin film transistor TFT2 described below. In an embodiment, the repair line RL may include the same material as that of the bottom metal layer BML. In an embodiment, the repair line RL may be formed during the same process as the process of forming the bottom metal layer BML. In the following description, it is reasonably understood that the repair line RL present in each of the display area DA and the peripheral area PA is not a separate part but an integrated part. For example, because the portion of the repair line RL arranged in the display area DA overlaps with the first connection line CL1, the portion of the repair line RL may be a protrusion RL-1 of the repair line RL formed in the display area DA (see Figure 5A Similarly, since the portion of the repair line RL arranged in the peripheral area PA overlaps with the second connection line CL2, the portion of the repair line RL may be a protrusion RL-1 of the repair line RL formed in the peripheral area PA (see Figure 5A ).

[0088] The buffer layer 101 may be disposed on the substrate 100 and may cover the bottom metal layer BML and the repair line RL. The buffer layer 101 may be configured to prevent penetration of impurities and moisture. The buffer layer 101 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x) Silicon oxynitride (SiON), aluminum oxide (AlO x ) Aluminum nitride (AlN x ) Titanium oxide (TiO x ) Or titanium nitride (TiN x ).

[0089] The first thin film transistor TFT1 and the second thin film transistor TFT2 may be disposed on the buffer layer 101. The first thin film transistor TFT1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The second thin film transistor TFT2 may include a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0090] The first active layer ACT1 and the second active layer ACT2 may be disposed on the buffer layer 101. Each of the first active layer ACT1 and the second active layer ACT2 may overlap with a corresponding bottom metal layer BML. In an embodiment, the area of the bottom metal layer BML may be greater than the areas of the first active layer ACT1 and the second active layer ACT2. The first active layer ACT1 and the second active layer ACT2 may include polysilicon, amorphous silicon, or a semiconductor containing an oxide, and include an organic semiconductor. The first active layer ACT1 and the second active layer ACT2 may include a channel region, a drain region, and a source region, and the drain region and the source region are located on opposite sides of the channel region.

[0091] The gate insulating layer 103 may be disposed to cover each of the first active layer ACT1 and the second active layer ACT2. The gate insulating layer 103 may include an inorganic insulating material such as silicon oxide (SiO x ) Silicon nitride (SiN x ) Silicon oxynitride (SiON), aluminum oxide (AlO x ) Aluminum nitride (AlN x ) Titanium oxide (TiO x ) Or titanium nitride (TiN x ). The gate insulating layer 103 may separately cover each of the first active layer ACT1 and the second active layer ACT2, and different from Figure 6A , the gate insulating layer 103 may be disposed to completely cover the buffer layer 101.

[0092] The first gate electrode GE1 may be disposed on the gate insulating layer 103 and may overlap with the channel region of the first active layer ACT1. The second gate electrode GE2 may be disposed on the gate insulating layer 103 and may overlap with the channel region of the second active layer ACT2. The first gate electrode GE1 and the second gate electrode GE2 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and include a single-layer or multi-layer structure containing the above materials.

[0093] The interlayer insulating layer 105 may cover the first gate electrode GE1 and the second gate electrode GE2. In addition, the interlayer insulating layer 105 may be disposed to completely cover the gate insulating layer 103 and the buffer layer 101.

[0094] The interlayer insulating layer 105 may include contact holes that overlap with the source region and the drain region of the first active layer ACT1 and the source region and the drain region of the second active layer ACT2, respectively. The source electrodes and drain electrodes described below may be connected to the active layers through the contact holes, respectively.

[0095] The interlayer insulating layer 105 may include a first groove 105-1 that overlaps with the repair line RL. A part (but less than the entire first groove 105-1) of the first groove 105-1 may overlap with the repair line RL. Similarly, the interlayer insulating layer 105 may include a second groove 105-2 that overlaps with the repair line RL. A part (but less than the entire second groove 105-2) of the second groove 105-2 may overlap with the repair line RL. The first groove 105-1 and the second groove 105-2 are formed by making the interlayer insulating layer 105 thinner than in the surrounding regions.

[0096] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2, the first connection line CL1, and the second connection line CL2 may be disposed on the interlayer insulating layer 105. The first source electrode SE1 may overlap with the source region of the first active layer ACT1 and is connected to the first active layer ACT1 through a contact hole formed in the interlayer insulating layer 105 and the gate insulating layer 103. In an embodiment, the first source electrode SE1 may be integrally formed with other adjacent lines. The second source electrode SE2 may overlap with the source region of the second active layer ACT2 and is connected to the second active layer ACT2 through a contact hole formed in the interlayer insulating layer 105 and the gate insulating layer 103. In an embodiment, the second source electrode SE2 may be integrally formed with other adjacent lines.

[0097] The first drain electrode DE1 may overlap with the drain region of the first active layer ACT1 and be connected to the first active layer ACT1 through contact holes formed in the interlayer insulating layer 105 and the gate insulating layer 103. The first connection line CL1 may overlap with the first groove 105-1 and be partially disposed in the first groove 105-1. Accordingly, a part of the first connection line CL1 may overlap with the repair line RL. In an embodiment, the first connection line CL1 and the first drain electrode DE1 may be connected to each other. In an embodiment, the first connection line CL1 and the first drain electrode DE1 may be integrally formed. In other words, a part of the same line may be the first connection line CL1, and another part of the same line may be the first drain electrode DE1.

[0098] The second drain electrode DE2 may overlap with the drain region of the second active layer ACT2 and be connected to the second active layer ACT2 through contact holes formed in the interlayer insulating layer 105 and the gate insulating layer 103. The second connection line CL2 may overlap with the second groove 105-2 and be partially disposed in the second groove 105-2. Accordingly, a part of the second connection line CL2 may overlap with the repair line RL. In an embodiment, the second connection line CL2 and the second drain electrode DE2 may be connected to each other. In an embodiment, the second connection line CL2 and the second drain electrode DE2 may be integrally formed. In other words, a part of the same line may be the second connection line CL2, and another part of the same line may be the second drain electrode DE2.

[0099] The source electrode and the drain electrode have the same physical properties and may be interchangeable according to specific conditions such as the direction of the current. In other words, in another embodiment, the first connection line CL1 may be integrally formed with the first source electrode SE1, and the second connection line CL2 may be integrally formed with the second source electrode SE2.

[0100] The via layer 107 may be disposed on the interlayer insulating layer 105 to completely cover the first source electrode SE1 and the second source electrode SE2, the first drain electrode DE1 and the second drain electrode DE2, and the first connection line CL1 and the second connection line CL2. The via layer 107 may include an organic insulating material such as acrylic acid, benzocyclobutene (BCB), polyimide (PI), or hexamethyldisiloxane (HMDSO). The via layer 107 may include vias overlapping with the first connection line CL1. Although Figure 6A a single via layer 107 is shown, the present disclosure is not limited thereto. In another embodiment, the via layer may be provided as multiple, and connection metals may be disposed between the corresponding via layers to electrically connect the sub-pixel electrode 210 to the first connection line CL1.

[0101] The sub-pixel electrode 210 may be disposed on the via hole layer 107 in the display area DA. The sub-pixel electrode 210 may be connected to the first connection line CL1 through a via hole formed in the via hole layer 107. The sub-pixel electrode 210 may be formed as a (semi-)transparent electrode or a reflective electrode. When the sub-pixel electrode 210 is formed as a (semi-)transparent electrode, the sub-pixel electrode 210 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). When the sub-pixel electrode 210 is formed as a reflective electrode, the sub-pixel electrode 210 may include a reflective layer and a layer containing ITO, IZO, ZnO, or In2O3, wherein the reflective layer contains silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In an embodiment, the sub-pixel electrode 210 may have a structure in which an ITO layer, an Ag layer, and an ITO layer are sequentially stacked. However, the present disclosure is not limited thereto, and the sub-pixel electrode 210 may include various materials, and its structure may be a single layer or a multi-layer, and may be modified differently.

[0102] The bank layer 109 may be disposed on the via hole layer 107 to cover the edge region (or edge) of the sub-pixel electrode 210. In other words, the bank layer 109 may include an opening 109-1 that exposes the central portion of the sub-pixel electrode 210. The opening 109-1 of the bank layer 109 may define the emission region of the light-emitting diode LED. Accordingly, the size and shape of the emission region of the light-emitting diode LED may be determined by the opening 109-1 of the bank layer 109.

[0103] The intermediate layer 220 may be disposed on the sub-pixel electrode 210. The intermediate layer 220 may include a first common layer 221 and a second common layer 223 disposed on the bank layer 109, and an emission layer 222 disposed in the opening 109-1 of the bank layer 109. In an embodiment, the first common layer 221 may be disposed on the bank layer 109, the emission layer 222 may be disposed on the first common layer 221 in the opening 109-1 of the bank layer 109, and the second common layer 223 may be disposed on the first common layer 221 to cover the emission layer 222. In other words, the emission layer 222 may be disposed in the opening 109-1 of the bank layer 109 and between the first common layer 221 and the second common layer 223.

[0104] The emission layer 222 may include an organic emission layer containing a low molecular weight material or a polymeric material. The first common layer 221 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second common layer 223 may include a hole transport layer (HTL) and / or a hole injection layer (HIL). In an embodiment, the first common layer 221 or the second common layer 223 may be omitted. In an embodiment, the positions of the first common layer 221 and the second common layer 223 may be interchangeable.

[0105] The counter electrode 230 may be disposed on the intermediate layer 220. As an example, the counter electrode 230 may be disposed on the second common layer 223. The counter electrode 230 may be disposed to completely cover the intermediate layer 220. The counter electrode 230 may include a conductive material having a low work function. As an example, the counter electrode 230 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode 230 may further include a layer disposed on the (semi) transparent layer, the layer containing ITO, IZO, ZnO, or In2O3.

[0106] The encapsulation layer 300 may be disposed on the counter electrode 230. The encapsulation layer 300 may include at least one inorganic layer and at least one organic layer. In an embodiment, the encapsulation layer 300 may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material among silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO). The organic encapsulation layer 320 may include a polymer-based material. The polymer-based material may include a silicon-based resin, an acrylic-based resin, an epoxy-based resin, a polyimide, and polyethylene.

[0107] Hereinafter, the relationship between the repair line RL, the first connection line CL1, the second connection line CL2, the interlayer insulating layer 105, and the buffer layer 101 will be described in detail with reference to Figure 6B the detailed description.

[0108] As described above, the interlayer insulating layer 105 may include a first groove 105-1 overlapping with the repair line RL. The width of the first groove 105-1 may be equal to or greater than the width of the repair line RL. A part of the first connection line CL1 may be disposed in the first groove 105-1. Accordingly, the first connection line CL1, the first groove 105-1, and the repair line RL may at least partially overlap each other. As referred to Figures 5A to 5C above, a part of the first groove 105-1 may extend beyond the edge of the repair line RL. Accordingly, it can be understood that a part of the first connection line CL1 disposed inside the first groove 105-1 extends beyond the edge of the repair line RL. The length that the first groove 105-1 extends beyond the edge of the repair line RL may be defined as a first interval S1. In an embodiment, the first interval S1 may be about 1 μm or greater.

[0109] The depth of the first groove 105-1 may be defined as a first depth D1. In a region overlapping with the first groove 105-1, the distance between the upper surface of the repair line RL and the upper surface of the interlayer insulating layer 105 may be defined as a first-to-first thickness TH1-1. In addition, in a region not overlapping with the first groove 105-1, the distance between the upper surface of the repair line RL and the upper surface of the interlayer insulating layer 105 may be defined as a first-to-second thickness TH1-2. Accordingly, the first-to-second thickness TH1-2 may be understood as the sum of the first-to-first thickness TH1-1 and the first depth D1. In an embodiment, the first-to-first thickness TH1-1 may be about 20% to about 80% of the first-to-second thickness TH1-2. In an embodiment, the first depth D1 may be about 20% to about 80% of the first-to-second thickness TH1-2.

[0110] In addition, the interlayer insulating layer 105 may include a second groove 105-2 overlapping with the repair line RL. The width of the second groove 105-2 may be equal to or greater than the width of the repair line RL. A part of the second connection line CL2 may be disposed in the second groove 105-2. Accordingly, the second connection line CL2, the second groove 105-2, and the repair line RL may at least partially overlap each other. As referred to Figures 5A to 5C above, a part of the second groove 105-2 may extend beyond the edge of the repair line RL. Accordingly, it can be understood that a part of the second connection line CL2 disposed inside the second groove 105-2 extends beyond the edge of the repair line RL. The length that the second groove 105-2 extends beyond the edge of the repair line RL may be defined as a second interval S2. In an embodiment, the second interval S2 may be about 1 μm or greater.

[0111] The depth of the second groove 105-2 can be defined as the second depth D2. In the region overlapping with the second groove 105-2, the distance between the upper surface of the repair line RL and the upper surface of the interlayer insulating layer 105 can be defined as the 2-1 thickness TH2-1. In addition, in the region not overlapping with the second groove 105-2, the distance between the upper surface of the repair line RL and the upper surface of the interlayer insulating layer 105 can be defined as the 2-2 thickness TH2-2. Accordingly, the 2-2 thickness TH2-2 can be understood as the sum of the 2-1 thickness TH2-1 and the second depth D2. In an embodiment, the 2-1 thickness TH2-1 can be about 20% to about 80% of the 2-2 thickness TH2-2. In an embodiment, the second depth D2 can be about 20% to about 80% of the 2-2 thickness TH2-2.

[0112] In an embodiment, the configurations of the first connection line CL1, the second connection line CL2, the first groove 105-1, and the second groove 105-2 in the first sub-pixel P1 and the second sub-pixel P2 can be symmetric. As an example, in an embodiment, the first depth D1 can be substantially equal to the second depth D2. In an embodiment, the 1-1 thickness TH1-1 can be substantially equal to the 2-1 thickness TH2-1. In an embodiment, the 1-2 thickness TH1-2 can be substantially equal to the 2-2 thickness TH2-2.

[0113] Figure 7A is a cross-sectional view of a part of a display device according to another embodiment. Figure 7B is Figure 7A an enlarged cross-sectional view of a part of the display device.

[0114] Referring to Figure 7A and Figure 7B , the buffer layer 101 can include a first lower groove 101-1 and a second lower groove 101-2 overlapping with the repair line RL. A part of the interlayer insulating layer 105 can be disposed inside the first lower groove 101-1 and the second lower groove 101-2. In an embodiment, the interlayer insulating layer 105 may not be a planarization layer, and it can be understood that the first groove 105-1 and the second groove 105-2 are generated by the first lower groove 101-1 and the second lower groove 101-2 during the process of disposing the interlayer insulating layer 105 on the buffer layer 101.

[0115] In an embodiment, the depth of the first lower groove 101-1 can be equal to the first depth D1. In an embodiment, the depth of the second lower groove 101-2 can be equal to the second depth D2. In an embodiment, the depth of the first lower groove 101-1 and the depth of the second lower groove 101-2 can be equal to each other.

[0116] Although in Figure 7A and Figure 7BIt is shown that the interlayer insulating layer 105 is in direct contact with the repair line RL through the first lower groove 101-1 and the second lower groove 101-2, but the present disclosure is not limited thereto. In another embodiment, the first lower groove 101-1 and / or the second lower groove 101-2 may be formed such that a part of the buffer layer 101 remains on the upper surface of the repair line RL.

[0117] Figure 7B depicts an embodiment similar to Figure 6B except that the surface of the interlayer insulating layer 105 closest to the substrate 100 is not planar. In the region overlapping with the first groove 105-1, the distance between the upper surface of the repair line RL and the upper surface of the interlayer insulating layer 105 may be defined as the first-1 thickness TH1-1. In the region not overlapping with the first groove 105-1, the distance between the upper surface of the repair line RL and the upper surface of the interlayer insulating layer 105 may be defined as the first-2 thickness TH1-2. Similarly, in the region overlapping with the second groove 105-2, the distance between the upper surface of the repair line RL and the upper surface of the interlayer insulating layer 105 may be defined as the second-1 thickness TH2-1. In the region not overlapping with the second groove 105-2, the distance between the upper surface of the repair line RL and the upper surface of the interlayer insulating layer 105 may be defined as the second-2 thickness TH2-2. In Figure 7B the embodiment, the depth of the first lower groove 101-1 is part of the first-2 thickness TH1-2, and the depth of the second lower groove 101-2 is part of the second-2 thickness TH2-2.

[0118] Figure 8A is a cross-sectional view of a part of a display device according to another embodiment. Figure 8B is Figure 8A an enlarged cross-sectional view of a part of the display device of

[0119] Referring to Figure 8A , an adjacent line NL may be additionally provided between the buffer layer 101 and the interlayer insulating layer 105. The adjacent line NL may be provided only in the display area DA or only in the peripheral area PA. As Figure 8A shown in

[0120] Referring toFigure 8B The adjacent line NL and the repair line RL can be spaced apart from each other by a distance. The distance between an edge of the repair line RL located in the region overlapping with the first groove 105-1 and an edge of the adjacent line NL adjacent to the first groove 105-1 can be defined as the third interval S3. In an embodiment, the third interval S3 can be greater than the first interval S1. In an embodiment, the third interval S3 can be approximately twice or more the first interval S1. In an embodiment, the third interval S3 can be about 2 μm or more.

[0121] The distance between an edge of the repair line RL located in the region overlapping with the second groove 105-2 and an edge of the adjacent line NL adjacent to the second groove 105-2 can be defined as the fourth interval S4. In an embodiment, the fourth interval S4 can be greater than the second interval S2. In an embodiment, the fourth interval S4 can be approximately twice or more the second interval S2. In an embodiment, the fourth interval S4 can be about 2 μm or more.

[0122] Figures 9A to 9C is a schematic plan view showing operations in a process of manufacturing a display device according to an embodiment.

[0123] Figures 10A to 10C is shown in reference to Figure 3 and Figure 4 is a cross-sectional view showing an operation of connecting a light-emitting diode LED to a second sub-pixel circuit PC2 in a specific case described.

[0124] Figure 11 is Figure 10C an enlarged cross-sectional view of a part of

[0125] First, referring to Figure 9A , in a case where a defect occurs in the first sub-pixel circuit PC1 and the light-emitting diode LED cannot operate properly, a part of the first connection line CL1 connecting the light-emitting diode LED to the first sub-pixel circuit PC1 can be cut. As an example, the first connection line CL1 can be cut in a cutting region CTA located between the light-emitting diode LED and the first sub-pixel circuit PC1. The cutting process can be performed with a laser beam. Figure 9B shows a state in which a part of the first connection line CL1 is cut. In the state shown in Figure 9B , there can be no sub-pixel circuit connected to the light-emitting diode LED.

[0126] Then, referring to Figure 9C, the first connection line CL1 can be connected to the repair line RL, and the second connection line CL2 can be connected to the repair line RL. The connection process can be performed using a laser beam. The connection of the first connection line CL1 to the repair line RL and the connection of the second connection line CL2 to the repair line RL can be performed simultaneously, sequentially, or in any order. Accordingly, the light-emitting diode LED can be connected to the second sub-pixel circuit PC2 through the first connection line CL1, the repair line RL, and the second connection line CL2, and can be normally turned on. Through this process, the light-emitting defects of the sub-pixels caused by defects in the sub-pixel circuit during the process of manufacturing the display device can be reduced.

[0127] The following will be described with reference to Figures 10A to 11 in detail the connection of the first connection line CL1 to the repair line RL and the connection of the second connection line CL2 to the repair line RL described above.

[0128] First, with reference to Figure 10A , a part of the line can be cut in the cutting area CTA located between the first connection line CL1 and the first drain electrode DE1. Accordingly, the first connection line CL1 and the first drain electrode DE1 can be set to be spaced apart from each other. Although not shown in Figure 10A , during the process of cutting the line using a laser beam, openings can be formed in the interlayer insulating layer 105 and the buffer layer 101 below the cutting area CTA.

[0129] Then, with reference to Figure 10B , the laser beam LS can irradiate the pixel in the +z direction from the back surface of the substrate 100. For example, the laser beam LS can point from the back surface of the substrate 100 to the lower surface of the first connection line CL1. The laser beam LS can point to the end of the first groove 105-1 and beside the repair line RL such that the repair line RL is not in the path of the beam. In some embodiments, the laser beam LS can be adjacent to the repair line RL and irradiate the side surface of the repair line RL.

[0130] Similarly, another laser beam LS can point from the back surface of the substrate 100 to the lower surface of the second connection line CL2. The laser beam LS can point to the end of the second groove 105-2 and beside the repair line RL. In some embodiments, the laser beam LS can be adjacent to the repair line RL and irradiate the side surface of the repair line RL.

[0131] Each laser beam LS can pass through the buffer layer 101 and the interlayer insulating layer 105, and form openings in the buffer layer 101 and the interlayer insulating layer 105. At the same time, the laser beam LS can irradiate the side surface of the repair line RL, and heat and melt a part of the repair line RL. By heating the lower surfaces of the first connection line CL1 and the second connection line CL2, a part of the lower surface of the first connection line CL1 and a part of the lower surface of the second connection line CL2 can be melted.

[0132] Subsequently, referring together to Figure 10C and Figure 11 , the laser beam can be turned off or removed. A first opening OP1 can be formed in the buffer layer 101 and the interlayer insulating layer 105. A part of the first connection line CL1 and a part of the repair line RL melted by the laser beam can fill the first opening OP1, thereby connecting the first connection line CL1 to the repair line RL. As the laser beam is turned off, the first connection line CL1 and the repair line RL can be cured. Accordingly, the first connection line CL1 and the repair line RL can be electrically connected to each other. During this process, the boundary surface between the first connection line CL1 and the repair line RL can be located in the first opening OP1.

[0133] Similarly, a second opening OP2 can be formed in the buffer layer 101 and the interlayer insulating layer 105. A part of the second connection line CL2 and a part of the repair line RL melted by the laser beam can fill the second opening OP2, thereby connecting the second connection line CL2 to the repair line RL. As the laser beam is turned off, the second connection line CL2 and the repair line RL can be cured. Accordingly, the second connection line CL2 and the repair line RL can be electrically connected to each other. During this process, the boundary surface between the second connection line CL2 and the repair line RL can be located in the second opening OP2.

[0134] As a result, the first connection line CL1, the repair line RL, and the second connection line CL2 can be electrically connected to each other.

[0135] During this process, when the thickness of the insulating layer between the first connection line CL1 and the repair line RL or between the second connection line CL2 and the repair line RL is too thick, it may be difficult to connect these two lines using a laser. In contrast, since the display device according to the present disclosure includes the first groove 105-1 and the second groove 105-2 formed in the interlayer insulating layer 105, these difficulties can be alleviated. In other words, in the display device according to the present disclosure, since the first-1 thickness TH1-1 and the second-1 thickness TH2-1 are formed to be smaller than the first-2 thickness TH1-2 and the second-2 thickness TH2-2, the connection success rate between the first connection line CL1 and the repair line RL irradiated by the laser beam and / or the connection success rate between the second connection line CL2 and the repair line RL can be improved.

[0136] Figures 12A to 12C It is a cross-sectional view showing operations in a process of manufacturing a display device according to an embodiment.

[0137] Figures 12A to 12C It shows a process of forming a groove in the interlayer insulating layer 105 of a display device according to the present disclosure. Although it is described based on the interlayer insulating layer 105, a groove can also be formed in the buffer layer 101 in a similar manner. Figures 12A to 12C In, a photoresist PR can be provided on the interlayer insulating layer 105. The photoresist PR can include an opening overlapping the repair line RL.

[0138] Referring to Figure 12A , a photoresist PR can be used as a mask to etch a part of the interlayer insulating layer 105. Accordingly, a first groove 105-1 and a second groove 105-2 can be formed. The depth of the first groove 105-1 and the depth of the second groove 105-2 can be adjusted by the thickness of the photoresist PR. The present disclosure is not limited thereto, and the first groove 105-1 and the second groove 105-2 can be formed by providing a mask other than the photoresist PR.

[0139] Referring to Figure 12B , a first connection line CL1 and a second connection line CL2 can be provided on the interlayer insulating layer 105 to cover the first groove 105-1 and the second groove 105-2 respectively.

[0140] Then, referring to Figure 12C , a first connection line CL1 and a second connection line CL2 can be provided on the interlayer insulating layer 105 to cover the first groove 105-1 and the second groove 105-2 respectively.

[0141] According to an embodiment, a display device is provided that has a reduced interval between a repair line and a connection line and has an increased success rate when attempting to repair. However, the above effects are merely examples, and the present disclosure is not limited thereto.

[0142] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various changes in form and detail can be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, comprising: a substrate; a repair line disposed on the substrate; an insulating layer covering the repair line; a first thin film transistor disposed in the insulating layer; a first connection line disposed on the insulating layer and overlapping at least a part of the repair line; and a light emitting element disposed on the first connection line and connected to the first connection line, wherein the insulating layer includes a first groove on the repair line.

2. The display device according to claim 1, wherein, A portion of the first connection line on the repair line is disposed in the first groove.

3. The display device according to claim 1, wherein, The first thin film transistor includes an active layer containing a semiconductor, and the repair line is disposed at a layer located below the active layer.

4. The display device according to claim 1, wherein, The first connection line and the source electrode or drain electrode of the first thin film transistor are disposed in the same layer.

5. The display device according to any one of claims 1 to 4, wherein, A first distance between an upper surface of the repair line and an upper surface of the insulating layer in a region overlapping the first groove is 20% to 80% of a second distance between the upper surface of the repair line and the upper surface of the insulating layer in a region outside the first groove.

6. The display device according to any one of claims 1 to 4, wherein, A depth of the first groove is 20% to 80% of a thickness of the insulating layer.

7. The display device according to any one of claims 1 to 4, wherein, An edge of the repair line and an edge of the first groove are separated from each other by 1 μm or more in one of a first direction and a second direction.

8. The display device according to any one of claims 1 to 4, further comprising: an adjacent line disposed below the insulating layer and adjacent to the repair line, wherein a distance between the repair line and the adjacent line in one of a first direction and a second direction is 2 μm or more.

9. The display device according to any one of claims 1 to 4, wherein, In a plan view, the repair line extends in a first direction, and the first connection line extends in a second direction intersecting the first direction.

10. The display device according to claim 9, wherein, A portion of the repair line extends in the second direction and overlaps the first connection line.

11. The display device according to any one of claims 1 to 4, further comprising: a first opening extending through the insulating layer between the repair line and a portion of the first connection line disposed in the first groove.

12. The display device according to claim 11, wherein, The repair line and the first connection line fill the first opening in the insulating layer and are in direct contact with each other.

13. The display device according to claim 12, wherein, The first connection line is disconnected from the first thin film transistor.

14. The display device according to any one of claims 1 to 4, further comprising: a second thin film transistor spaced apart from the light emitting element and the first thin film transistor and disposed in the insulating layer; and a second connection line connected to the second thin film transistor, wherein the insulating layer further includes a second groove, and wherein the repair line, the second groove, and the second connection line overlap.

15. The display device according to claim 14, further comprising: a second opening extending through the insulating layer between the repair line and a portion of the second connection line disposed in the second groove, wherein the repair line and the second connection line fill the second opening in the insulating layer and are in direct contact with each other.

16. The display device according to claim 14, comprising: A display region, in which the light-emitting element, the first thin-film transistor, and the first connection line are arranged, and A peripheral region, in which the second thin-film transistor and the second connection line are arranged, wherein the peripheral region at least partially surrounds the display region.

17. A display device, comprising: A substrate including a display region and a peripheral region, in which a light-emitting element is arranged, and the peripheral region surrounds the display region; A first thin-film transistor disposed on the substrate in the display region; A first connection line disposed on the first thin-film transistor in the display region; A second thin-film transistor disposed on the substrate in the peripheral region; A second connection line disposed on the second thin-film transistor in the peripheral region; A repair line extending continuously across the display region and the peripheral region; And An insulating layer disposed between the repair line and the first connection line and the second connection line, wherein the repair line is disposed at a layer below the first thin-film transistor and the second thin-film transistor.

18. The display device according to claim 17, wherein, The repair line overlaps with a portion of the first connection line and a portion of the second connection line.

19. The display device according to claim 18, wherein, The insulating layer includes a first groove and a second groove, wherein the first groove overlaps with the repair line and the first connection line, and the second groove overlaps with the repair line and the second connection line.

20. The display device according to claim 19, wherein, At least one of the depth of the first groove and the depth of the second groove is 20% to 80% of the thickness of the insulating layer.

21. The display device according to any one of claims 17 to 19, wherein The first connection line and the source electrode or the drain electrode of the first thin-film transistor are disposed in the same layer.

22. The display device according to any one of claims 17 to 19, wherein, In a plan view, the repair line extends in a first direction, and at least one of the first connection line and the second connection line extends in a second direction intersecting the first direction.

23. The display device according to claim 22, wherein A portion of the repair line extends in the second direction and overlaps with at least one of the first connection line and the second connection line.

24. The display device according to any one of claims 17 to 19, further comprising: A first opening and a second opening extending through the insulating layer, wherein the first opening extends between the repair line and the first connection line, and the second opening extends between the repair line and the second connection line, wherein the repair line and the first connection line fill the first opening and are in direct contact with each other, and wherein the repair line and the second connection line fill the second opening and are in direct contact with each other.

25. The display device according to claim 24, wherein, The light-emitting element is electrically connected to the second thin-film transistor through the first connection line, the repair line, and the second connection line.

26. An electronic device, comprising: A display device; And A housing located around the display device, wherein the display device includes: A substrate; A repair line disposed on the substrate; An insulating layer disposed on the repair line; A first thin-film transistor disposed in the insulating layer; A first connection line disposed on the insulating layer and overlapping at least a portion of the repair line; and The light-emitting element is provided on and connected to the first connection line, wherein the insulating layer is thinner in the region above the repair line than in other regions.

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