Chip power consumption detection analysis method and system

Abstract

The invention discloses a chip power consumption detection analysis method and system, and relates to the technical field of chip power consumption detection. A chip power consumption detection and analysis system comprises a power consumption detection module, a power supply optimization module and a chip control module. Through the chip power consumption detection model, accurate denoising and key feature extraction can be realized, and a correlation model related to power consumption is established, so that the accuracy and reliability of power consumption detection are ensured; the chip power consumption detection circuit can perform dynamic adjustment according to current, voltage, temperature, working frequency and other data acquired in real time, and continuously optimize power consumption analysis and power supply strategies, thereby improving the energy efficiency and performance of the chip. Power consumption matching is carried out based on the power supply optimization model, and technologies of feature extraction, fractal prediction and the like are combined, so that accurate prediction of chip power consumption and optimization of a power control strategy are realized, the energy efficiency of the chip is further improved, and energy consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip power consumption detection, and particularly to a chip power consumption detection and analysis method and system. Background Art

[0002] With the rapid development of integrated circuit technology, the integration degree of chips has been continuously improved, and the power consumption problem has become increasingly prominent. High power consumption not only affects the stability and reliability of chips, but also increases the costs of heat dissipation and energy consumption. Traditional power consumption testing methods, such as measurements based on power analyzers or simulation modeling, have been difficult to meet the requirements of modern chips for high-precision, real-time and complex power consumption analysis. These methods usually have problems such as insufficient accuracy, slow response speed or poor compatibility, and cannot adapt to the increasingly complex design requirements.

[0003] To solve these problems, advanced data processing technologies need to be introduced in chip power consumption detection, which can monitor and accurately evaluate the energy consumption data of chips in different working states in real time. This not only ensures the measurement accuracy, but also effectively improves the test efficiency and reliability. By optimizing the power consumption measurement technology, accurate energy consumption information can be provided for designers, so as to help them discover power consumption bottlenecks, improve chip design, reduce energy consumption, and enhance the overall performance and stability of chips. Summary of the Invention

[0004] The present invention aims to provide a chip power consumption detection and analysis method and system to monitor and accurately evaluate the chip energy consumption data in real time.

[0005] A chip power consumption detection and analysis method includes the following steps: In the chip power consumption detection circuit, obtain the current chip power supply parameters, and obtain the chip current and chip voltage; at the same time, obtain compensation data, which includes the chip temperature and chip operating frequency; Perform power consumption detection based on the chip power consumption detection model to obtain the chip power consumption result; The chip power consumption detection model realizes data denoising, extracts key features, establishes a correlation model through power consumption compensation analysis, and predicts and analyzes the chip power consumption through pattern matching; Perform power consumption matching based on the chip power consumption result and the chip power supply optimization model to obtain the power supply optimization strategy; The chip power supply optimization model can predict the chip power consumption and optimize the control strategy according to the current chip power supply parameters through fractal prediction and power supply strategy optimization, improving the energy efficiency and performance of the chip; According to the power supply optimization strategy, perform real-time optimization on the chip power consumption detection circuit, change the current chip power supply parameters, and continuously perform the chip power consumption detection operation.

[0006] As a preferred technical solution of the present invention, denoising processing is performed on the chip current and chip voltage in the chip power consumption detection model to obtain the denoised chip current and the denoised chip voltage; a power supply - electrical variable - working correlation compensation model is established for analysis to obtain the chip power consumption result.

[0007] As a preferred technical solution of the present invention, the specific steps of the denoising processing include: Perform noise separation on the chip current to obtain the chip current noise I z ; Perform noise separation on the chip voltage to obtain the chip voltage noise V z ; Perform noise shaping on the chip current noise I z to obtain the noise - reduced chip current S(I); Perform noise shaping on the chip voltage noise V z to obtain the noise - reduced chip voltage S(V); Use the formula I q =W i *S(I)+(1 - W i )*I o to calculate and obtain the denoised chip current I q , where W i represents the weight coefficient corresponding to the noise - reduced chip current S(I); I o represents the chip current; Use the formula V q =W v *S(V)+(1 - W v )*V o to calculate and obtain the denoised chip voltage V q , where W v represents the weight coefficient corresponding to the noise - reduced chip voltage S(V); V o represents the chip voltage.

[0008] As a preferred technical solution of the present invention, the specific steps of establishing the power supply - electrical variable - working correlation compensation model include: Perform multi - scale differential extraction on the denoised chip current, denoised chip voltage, current chip power supply parameters, and compensation data to obtain current differential features, voltage differential features, power supply differential features, and compensation differential features; combine all differential features to obtain a power consumption compensation feature set; Based on the power consumption compensation feature set, establish a differential correlation matrix to obtain the power supply - electrical variable - working correlation compensation model; Extract the main variation direction from the power supply - electrical variable - working correlation compensation model to obtain the power consumption dominant variation source; Perform eigenvalue decomposition on the power supply - electrical variable - working correlation compensation model to obtain the power consumption correlation eigenvalues; Construct a power consumption anomaly trajectory by combining the power consumption-dominated variation sources and power consumption-related eigenvalue; Perform pattern matching on the power consumption anomaly trajectory to obtain the chip power consumption result.

[0009] As a preferred technical solution of the present invention, feature extraction is performed on the chip power consumption result in the chip power supply optimization model to obtain chip power consumption features; according to the chip power consumption features, fractal prediction is performed by using a convolutional feature processing unit, a feature recognition and division unit, and a fractal prediction unit to obtain a chip power consumption prediction value; based on the chip power consumption prediction value and the current chip power supply parameters, a power supply optimization control strategy is matched to obtain a power supply optimization strategy.

[0010] As a preferred technical solution of the present invention, in the convolutional feature processing unit, convolutional analysis is performed on the chip power consumption features to obtain chip power consumption convolutional features; In the feature recognition and division unit, construct K power consumption division individuals G k , k = 1, 2,..., K; where each power consumption division individual G k contains a set of scale values for dividing the chip power consumption convolutional features; combine the K power consumption division individuals G k to obtain a power consumption division iteration population; set the maximum number of iterations; Based on the power consumption division individual G k perform simulated division on the chip power consumption convolutional features to obtain a power consumption feature simulated division; calculate the standard deviation inside the power consumption feature simulated division to obtain a convolutional scale standard deviation; use the reciprocal of the convolutional scale standard deviation as the fitness A k of the power consumption division individual G k ; When the maximum number of iterations is reached, output the power consumption division individual corresponding to the maximum current fitness, which is the optimal power consumption division individual; divide the chip power consumption convolutional features according to the optimal power consumption division individual to obtain power consumption convolutional fractal features; where, is the total number of divisions of the chip power consumption convolutional features, is the optimal scale for dividing the chip power consumption convolutional features; In the fractal prediction unit, use the formula to calculate the fractal prediction judgment value D; α is the fractal prediction weight coefficient; If D > D0 or D = D0, then input the power consumption convolutional fractal features into the trained chaotic neural network for prediction to obtain the chip power consumption prediction value; if D < D0, then input the power consumption convolutional fractal features into the trained ARIMA time series for prediction to obtain the chip power consumption prediction value; D0 represents the power consumption prediction judgment threshold.

[0011] A chip power consumption detection and analysis system, comprising: The power consumption detection module includes a data acquisition unit and a power consumption detection unit; The data acquisition unit is used to obtain the current chip power supply parameters, the chip current, and the chip voltage in the chip power consumption detection circuit; at the same time, compensation data is obtained, and the compensation data includes the chip temperature and the chip operating frequency; The power consumption detection unit is used to perform power consumption detection based on the chip power consumption detection model to obtain the chip power consumption result; the chip power consumption detection model realizes data denoising, extracts key features, establishes a correlation model through power consumption compensation analysis, and predicts and analyzes the chip power consumption through pattern matching; The power supply optimization module includes a power control unit; The power control unit is used to perform power consumption matching based on the chip power consumption result and the chip power supply optimization model to obtain the power supply optimization strategy; the chip power supply optimization model can predict the chip power consumption and optimize the control strategy according to the current chip power supply parameters through fractal prediction and power supply strategy optimization, improving the energy efficiency and performance of the chip; The chip control module includes a chip micro-control unit; The chip micro-control unit is used to perform real-time optimization of the chip power consumption detection circuit according to the power supply optimization strategy, change the current chip power supply parameters, and continuously perform chip power consumption detection operations.

[0012] The present invention has the following advantages: 1. Through the chip power consumption detection model, the present invention can accurately denoise, extract key features, and establish a correlation model related to power consumption, ensuring the accuracy and reliability of power consumption detection; the chip power consumption detection circuit can perform dynamic adjustment according to the current obtained data such as current, voltage, temperature, and operating frequency, and continuously optimize the power consumption analysis and power supply strategy, thereby improving the energy efficiency and performance of the chip; through power consumption matching based on the chip power supply optimization model, combined with technologies such as feature extraction and fractal prediction, accurate prediction of chip power consumption and optimization of the power supply control strategy are realized, further improving the energy efficiency of the chip and reducing energy consumption.

[0013] 2. Through feature extraction, power consumption time series fractal prediction, and power supply strategy optimization, the chip power supply optimization model can accurately predict the chip power consumption and optimize the control strategy based on the current chip power supply parameters, enabling the chip to achieve optimal power consumption management under different working conditions and improving energy efficiency; the model can adjust the optimization strategy in real time according to the current power consumption analysis result and power supply status, thereby dynamically adapting to the changing needs of the chip in different working environments; by matching the predicted value of power consumption analysis and the power supply parameters, the control strategy is optimized, effectively reducing the energy consumption of the chip, avoiding excessive energy consumption while ensuring high performance, and improving the energy utilization efficiency. Description of the Drawings

[0014] Figure 1 This is a schematic structural diagram of a chip power consumption detection and analysis system adopted in an embodiment of the present invention. Specific Embodiments

[0015] In order to enable those skilled in the art of this technology to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention.

[0016] Embodiment 1, a chip power consumption detection and analysis method, includes the following steps: In the chip power consumption detection circuit, obtain the current chip power supply parameters, and obtain the chip current and chip voltage; at the same time, obtain compensation data, which includes chip temperature and chip operating frequency; The chip power consumption detection circuit can obtain the current and voltage of the chip in real time and calculate the power consumption, which helps engineers monitor the change of energy consumption of the chip during operation; through the analysis of parameters such as current and voltage, the circuit can help determine whether the energy consumption of the chip is normal, whether there is a situation of excessive power consumption, or whether it can achieve lower power consumption through optimization; among them, temperature and operating frequency have a significant impact on chip power consumption. By obtaining these parameters, the power consumption detection circuit can more accurately evaluate the actual power consumption status of the chip; the chip power consumption detection circuit is not only used for data acquisition, but also can provide data input for the chip power consumption detection model and adjust the chip power supply parameters according to the power consumption optimization strategy to achieve power consumption regulation; The current chip power supply parameters include the set values of the current chip current and the current chip voltage, which specifically represent the voltage and current parameters configured in real time in the chip power consumption detection circuit; the chip power supply parameters represent both the input data in chip power consumption detection and the optimization output target in chip power consumption detection and analysis; The obtained chip current and chip voltage are the actual current value and actual voltage value measured based on the setting of the current chip power supply parameters; Current is a basic parameter describing the electrical energy consumed by the chip during operation. By monitoring the current, the power of the chip can be directly calculated. The magnitude of the current is closely related to the working load and functional state of the chip. When the load is heavier, the current is larger and the power consumption is also higher; voltage is the driving force for providing energy when the chip is working. The change of the working voltage of the chip will directly affect the power consumption. In different working states, the voltage may be adjusted to ensure that the chip can work stably under different loads; Temperature is an important parameter for measuring the thermal state of a chip. The greater the chip power consumption, the more heat is usually generated, and the higher the temperature. High temperature will affect the performance stability of the chip, may cause the overheat protection mechanism to start, reduce the processing speed or even damage the chip. Therefore, real-time temperature monitoring is crucial for preventing chip overheating and ensuring its normal operation. The operating frequency of the chip is directly related to its processing speed and power consumption. The higher the frequency, the faster the chip's processing speed, but at the same time, the power consumption will also increase. Based on the chip power consumption detection model, power consumption detection is carried out to obtain the chip power consumption result. The chip power consumption detection model realizes data denoising, extracts key features, establishes a correlation model through power consumption compensation analysis, and predicts and analyzes the chip power consumption through pattern matching. In the chip power consumption detection model, denoising processing is performed on the chip current and chip voltage to obtain the denoised chip current and denoised chip voltage. A power-supply - electrical variable - operating correlation compensation model is established for analysis to obtain the chip power consumption result. Through multi-level data preprocessing, power consumption compensation analysis, and pattern matching, the chip power consumption detection model can accurately analyze the power consumption of the chip. Through denoising processing and feature extraction, the influence of external interference is reduced, thereby improving the accuracy of power consumption analysis. By denoising the chip current and voltage signals, unnecessary noise in the signals is eliminated, ensuring that the data for power consumption detection is more accurate and reliable. This helps to remove the interference caused by the external environment or sensor errors and improve the stability of power consumption prediction. According to the denoised data and other operating parameters of the chip (such as temperature, frequency, etc.), a power-supply - electrical variable - operating correlation compensation model is established. This model can consider the influence of various operating states on power consumption, provide more accurate power consumption analysis results, and further optimize the power supply strategy. From data acquisition to power consumption output, all are optimized for the key factors in chip power consumption analysis, improving the overall performance. The specific steps for denoising the chip current and chip voltage include: Perform noise separation on the chip current to obtain the chip current noise I z ; Perform noise separation on the chip voltage to obtain the chip voltage noise V z ; In the process of noise separation of the chip current and voltage, first, the chip current and chip voltage are respectively collected through the detection circuit, and then the signal is processed by filtering methods (such as low-pass, wavelet, or band-pass filtering) to filter out the high-frequency or non-operating frequency band noise in it and extract the denoised signal. By performing differential analysis on the original signal and the denoised signal, the chip current noise I z and the chip voltage noise V z are respectively obtained, realizing the effective separation of the noise components. The formula can be used Perform noise shaping on the chip current noise I z to obtain the noise-reduced chip current S(I); S(I) is the result of performing noise shaping on the chip current noise I z The calculation process involves using a specific formula to shape the current signal, thereby removing noise and enhancing the quality of the signal; Similarly, the formula can be used to perform noise shaping on the chip voltage noise V z to obtain the noise-reduced chip voltage S(V); S(V), as described for S(I), is the result of performing noise shaping on the chip voltage noise V z The result of performing noise shaping; where N represents the power of the numerator term, M represents the power of the denominator term, f s represents the chip current and voltage sampling frequency, f I represents the current noise frequency variable, f V represents the voltage noise frequency variable; The acquisition of the current noise frequency variable includes: using a spectrum analysis tool to perform frequency-domain analysis on the current signal, and obtaining the current noise frequency variable by analyzing the frequency components of the current noise; Similarly, using a spectrum analysis tool to perform frequency-domain analysis on the voltage signal, and similarly extracting the frequency components of the voltage noise to obtain the voltage noise frequency variable; The reason for setting 2N and 2M is to expand N and M and enhance the filtering effect. By doubling the powers of the sine and cosine functions, the control strength of the filter on the frequency components can be increased. In this way, the signals in the low-frequency part can be better retained, while the high-frequency noise part will be more effectively weakened; The sine and cosine functions have important periodic characteristics in the frequency domain; By performing this weighted shaping on the frequency components, the spectral characteristics of the signal can be changed, and the unwanted frequency components, especially the high-frequency noise part, can be weakened; The sine function is used to strengthen the low-frequency part of the signal, while the cosine function suppresses the high-frequency noise components; The values of N and M are integers. Usually, N and M will take some moderate integer values, such as 2, 3, 4, etc.; If the values are too large, it may cause signal distortion, and if the values are too small, the effective noise reduction effect may not be achieved; Therefore, the selection of the sizes of N and M needs to be adjusted according to the characteristics of the noise, the sampling rate, etc., and the specific values of N and M are set manually; Through frequency-domain filtering, especially through the weighting of the sine and cosine functions, the spectrum of the signal can be effectively changed, especially the suppression of high-frequency noise; By enhancing the low-frequency components and removing the high-frequency noise, the noise components in the final signal are significantly reduced; The chip current and voltage sampling frequency f s is a key factor affecting the noise frequency; In the noise shaping formula, the chip current and voltage sampling frequency f sAs the denominator of the current noise frequency variable or voltage noise frequency variable, the purpose is to standardize the noise at different frequencies; through this setting, it can be ensured that the noise shaping process matches the actual sampling rate. The standardization of the sampling frequency makes the noise processing more universal and can adapt to the noise characteristics at different sampling rates, which can effectively perform noise shaping in a variety of working environments; Using the formula I q =W i *S(I)+(1 - W i )*I o Calculate the denoised chip current I q , where W i represents the weight coefficient corresponding to the denoised chip current S(I); I o represents the chip current; W i is set manually by professional technicians. The weight coefficient corresponding to the denoised chip current S(I) is a value between 0 and 1, which determines the proportion of the denoised chip current S(I) and the chip current I o in the final result. For example: when the signal quality is good, if the current signal of the chip itself has little noise and the denoised chip current S(I) after noise reduction is already very close to the chip current I o , at this time the necessity of noise reduction processing is relatively low. In this case, W i can be set to be close to 0 because the contribution of the denoised chip current S(I) to the final result is small and more depends on the chip current I o ; when there is more noise in the signal, if the current signal of the chip is affected by greater noise and the denoised chip current S(I) after noise reduction can effectively remove the noise and is closer to the true signal, then the contribution of denoising will be more important. In this case, W i can be set close to 1, that is, mostly depends on the denoised chip current S(I) after noise reduction and reduces the dependence on the chip current I o ; in some cases, the signal contains both valid components and noise components, and the type and intensity of the noise are irregular; in this case, the denoising effect may not be perfect, and both the original signal and the denoised signal may contain some useful information. W i can be set to a medium value to represent the balanced contribution of the denoised signal and the original signal; in this case, both the denoised signal and the original signal can provide value to the final result, so a relatively balanced weight coefficient is adopted to balance the influence of both; in some advanced applications, the characteristics of the noise may change with time or the working state. For example, when the chip load changes, the level of the noise may also be different; in this case, a mechanism for dynamically adjusting the weight coefficient W i can be designed to flexibly control the proportion of denoised and original signals according to the real-time noise level, so as to optimize the denoising effect; Using the formula V q =W v *S(V)+(1 - W v )*V o the denoised chip voltage V is calculated, q where W v represents the weight coefficient corresponding to the noise reduction chip voltage S(V); V o represents the chip voltage; W v is set manually by professional technicians, and the setting is as described in W i : the greater the noise, the greater the weight of the noise reduction signal should be, and the smaller the weight of the original signal should be; when the signal quality is good, the original signal dominates and the weight coefficient can be smaller; in the case of continuously changing noise levels, dynamically adjusting the weight coefficient can obtain the best denoising effect; During the process of noise denoising, I q , I o , S(I) and similarly, V q , V o , S(V) are all used to describe the denoising process of the chip current and voltage signals. I o represents the original current signal collected when the chip is in normal working state, which is the current data without any processing or denoising and may contain noise components introduced by external interference, measurement errors, chip itself noise, etc.; S(I) is the current signal after noise shaping and denoising, and the noise shaping process is through specific filtering algorithms and mathematical processing; I q is the final denoised current signal, representing the result after integrating the noise reduction signal and the original signal on the basis of noise shaping and weighting; Similarly, V o is the original measured value of the chip voltage signal, which may be interfered by system noise, external interference and other influencing factors; S(V) is the voltage signal after noise shaping and filtering; the noise shaping technology is similar to the processing of the current signal; V q is the final denoised voltage signal, which is obtained by integrating the original signal and the denoised signal through weighting; By extracting and shaping the noise of the chip current and voltage signals, the noise interference brought by the sensor or the environment is effectively removed, ensuring that the data used for power consumption analysis is more accurate, which makes the subsequent power consumption analysis and prediction results more credible; by shaping the current and voltage noise data, while retaining the key features of the original signal, unnecessary noise components can be filtered out, thus improving the signal quality, which is crucial for the current and voltage data that need to be accurately calculated in chip power consumption detection; by introducing a noise reduction weight coefficient, the denoising effect can be adaptively adjusted according to the actual noise situation, making the denoising process more refined, avoiding problems such as over-filtering or under-filtering, and thus providing a more suitable denoising result; using the adaptive weight coefficients W i and W v , the denoising process can be dynamically adjusted according to the characteristics of the actual noise and current and voltage, so as to better cope with the noise effects in different working environments. This flexibility helps to adapt to various hardware conditions and usage scenarios; The specific steps to establish a power supply - electrical variable - working correlation compensation model include: Perform multi-scale differential extraction on the denoised chip current, denoised chip voltage, current chip power supply parameters, and compensation data to obtain current differential features, voltage differential features, power supply differential features, and compensation differential features; combine all differential features to obtain a power consumption compensation feature set; The meaning of multi-scale differential extraction is: extract information from different scales, such as time scale and frequency scale, to capture various dynamic change features in the signal; in practical applications, the signal may have multiple frequency components, such as high-frequency noise and low-frequency signal changes, so multi-scale extraction helps to reveal more complex signal features; The specific steps to perform multi-scale differential extraction on the denoised chip current, denoised chip voltage, current chip power supply parameters, and compensation data include: First, perform first-order and second-order differential processing on each signal to calculate the change rate of the signal at different time scales and identify the dynamic change trend of the signal; then, use methods such as sliding window or wavelet transform to perform multi-scale analysis on these signals within different time windows to extract fine-grained change features and capture the information of the signal at different frequency levels; finally, combine these differential features into a comprehensive feature set, including current differential features, voltage differential features, power supply differential features, and compensation differential features, providing rich dynamic information for the subsequent power consumption compensation model and analysis; Based on the power consumption compensation feature set, establish a differential correlation matrix to obtain a power supply - electrical variable - working correlation compensation model; The specific steps for establishing the differential correlation matrix include: calculating the correlation between each feature using these features in the power consumption compensation feature set. Usually, the Pearson correlation coefficient or covariance is used to quantify the linear dependence between features, and a differential correlation matrix is constructed. Each element of this matrix represents the correlation between features and is organized in the form of a symmetric matrix. Then, further analysis can be performed based on this differential correlation matrix to extract the main variation directions. Through the principal component analysis method or other dimensionality reduction methods, the features that can best explain the power consumption change are obtained, and finally, a power supply - electrical variable - working association compensation model is constructed, providing a data basis for subsequent power consumption prediction and optimization. Extract the main variation direction from the power supply - electrical variable - working association compensation model to obtain the power consumption dominant variation source. Perform eigenvalue decomposition on the power supply - electrical variable - working association compensation model to obtain the power consumption correlation eigenvalues. Combine the power consumption dominant variation source and the power consumption correlation eigenvalues to construct the power consumption abnormal trajectory. Perform pattern matching on the power consumption abnormal trajectory to obtain the chip power consumption result. Before performing pattern matching, it is first necessary to extract the power consumption abnormal trajectory from the power consumption compensation model. The abnormal trajectory is identified by analyzing data such as power supply, electronic variables, and working conditions, and is the part that is significantly different from the normal power consumption behavior. These abnormal trajectories may stem from the abnormal power consumption performance of the chip under different workloads, environmental changes, or faults. By calculating the change trend of power consumption and identifying these abnormal data, the abnormal trajectory of power consumption is formed. Once the abnormal trajectory is constructed, the next step is to extract the key features in the trajectory. These features may include the amplitude of power consumption fluctuations, change rate, periodicity, etc. The extracted features will be compared with the predefined known power consumption patterns, which are usually obtained through historical data, empirical rules, or simulations and represent the typical power consumption performance of the chip in different states. In the pattern matching process, a BP neural network model is used to find the matching degree between the abnormal trajectory and the known patterns. In this process, the power consumption abnormal trajectory is passed as input data to the input layer of the network. After multiple layers of neural network calculations, the output layer will give the predicted value of the power consumption pattern that matches the input data. The network identifies the most similar power consumption pattern by comparing the input trajectory with the corresponding patterns in the trained model. The BP neural network will output a matching power consumption result based on the input power consumption abnormal trajectory. The output result is usually the power consumption pattern that best matches the abnormal trajectory or the predicted power consumption value. Once the pattern matching is completed and accurate power consumption prediction results are obtained, the power consumption management strategy can be further optimized based on these results. For example, power supply optimization can be performed according to the power consumption pattern prediction, adjusting the working frequency or voltage of the chip to ensure that energy consumption is minimized while maintaining performance. In addition, by detecting the power consumption abnormal pattern, chip faults or abnormal working states can be timely discovered, providing fault warnings. Among them, the pattern matching operates based on a trained BP neural network model; by performing multi-scale differentiation extraction on the current, voltage, power supply parameters, and other working data of the denoising chip, the tiny changes and correlations of each variable can be captured, so as to analyze the power consumption more precisely. In a complex working environment, this meticulous analysis helps to compensate for the power consumption fluctuations caused by different factors; multi-scale differentiation extraction can extract the characteristics of chip current, voltage, operating frequency, etc. from different scales and angles, enhancing the depth and dimension of data processing, which helps to comprehensively understand the influencing factors of chip power consumption and enables the power consumption analysis model to better adapt to complex environmental changes; by constructing a power supply - electrical variable - working correlation compensation model, the data in multiple aspects such as current, voltage, and working parameters are correlated, and the source and its change trend of power consumption can be comprehensively analyzed. This multi-dimensional correlation modeling helps to improve the accuracy of power consumption compensation; through eigenvalue decomposition, the power consumption correlation eigenvalues are obtained, providing a scientific basis for the construction of the power consumption abnormal trajectory. Combining with the dominant variation source, the abnormal situation of chip power consumption can be monitored in real time, and effective support can be provided for abnormal prediction and fault prevention; combining multi-scale differentiation extraction, PCA dimensionality reduction, and the pattern matching of BP neural network can analyze the chip power consumption in real time and efficiently, and output accurate power consumption analysis results. The improvement of real-time performance helps the power consumption management system to make timely responses under dynamically changing working conditions, ensuring the performance and energy efficiency of the chip; The steps of training the pattern matching model include first collecting historical power consumption data and performing preprocessing such as denoising and normalization to ensure the quality and consistency of the data; extracting key features from the preprocessed data, including current, voltage, temperature, frequency, etc., to construct a training dataset and a test set; selecting a BP neural network to train the model using the training set and adjusting the parameters to minimize the prediction error; using the test set to verify the performance of the model, evaluate its accuracy, and improve its effect by optimizing the model parameters or increasing the data volume; applying the trained and optimized pattern matching model to real-time power consumption analysis to achieve power consumption anomaly detection and prediction; improving its effect specifically refers to improving the prediction accuracy and generalization ability of the model to ensure that the model can accurately detect and predict the power consumption anomalies of the chip in practical applications; for example, improving the data quality and diversity, enhancing the generalization ability and robustness of the model to improve the accuracy and reliability of the model in power consumption analysis, which includes reducing the prediction error, avoiding overfitting, ensuring the good performance of the model on unseen data, enhancing the generalization ability through regularization techniques and cross-validation, enhancing the diversity of the dataset to cope with various working conditions, and at the same time optimizing the network structure and training parameters to ensure that the model can accurately identify and predict power consumption anomalies and adapt to the changes in practical applications; based on the chip power consumption results and the chip power supply optimization model, perform power consumption matching to obtain the power supply optimization strategy; The chip power supply optimization model can predict the chip power consumption and optimize the control strategy according to the current chip power supply parameters through fractal prediction and power supply strategy optimization, improving the energy efficiency and performance of the chip; In the chip power supply optimization model, feature extraction is performed on the chip power consumption results to obtain chip power consumption features; based on the chip power consumption features, fractal prediction is carried out using a convolutional feature processing unit, a feature recognition and division unit, and a fractal prediction unit to obtain the chip power consumption prediction value; based on the chip power consumption prediction value and the current chip power supply parameters, a power supply optimization control strategy is matched to obtain a power supply optimization strategy; According to the power supply optimization strategy, the chip power consumption detection circuit is optimized in real time, the current chip power supply parameters are changed, and the chip power consumption detection operation is continuously carried out; The specific steps for training and matching the power supply optimization control strategy include: Collect several groups of power supply strategy output training samples; each group of power supply strategy output training samples contains a power consumption prediction value, the current power supply parameter value, and the predicted power supply parameter value; combine several groups of power supply strategy output training samples to obtain a power supply strategy output training set; Based on the power supply strategy output training set and the BP neural network model, training is carried out to obtain an initial matched power supply optimization control strategy model; the initial matched power supply optimization control strategy model is evaluated. If the initial matched power supply optimization control strategy model passes the model evaluation, the power supply optimization control strategy is matched using the initial matched power supply optimization control strategy model; otherwise, the power supply strategy output training set is used to continue model training; The specific steps for model evaluation include verifying the performance and accuracy of the initial matched power supply optimization control strategy model through a series of evaluation metrics; common methods include using a test set to verify the model, calculating prediction errors such as the mean squared error MSE, the mean absolute error MAE, etc., and evaluating the generalization ability of the model on unseen data; in addition, the cross-validation method can be used to evaluate the performance of the model on different data partitions through multiple trainings and tests; by comparing the predicted value and the true value, the accuracy, precision, and robustness of the model are calculated to ensure that it can effectively predict the power supply optimization control strategy and meet the application requirements; if the evaluation results show that the model performs well, the model can be used for power supply optimization control strategy matching; otherwise, training needs to be continued to optimize the model parameters; Through feature extraction, power consumption time-series fractal prediction, and power supply policy optimization, the chip power supply optimization model can accurately predict the chip's power consumption and optimize the control strategy based on real-time power supply parameters. This enables the chip to achieve optimal power management under different working conditions, improving energy efficiency. The close cooperation of multiple steps ensures that the model can adjust and optimize the strategy in real time according to the current power consumption analysis results and power supply status, thus dynamically adapting to the changing needs of the chip in different working environments. By matching the predicted power consumption analysis values with the power supply parameters and optimizing the control strategy, the energy consumption of the chip can be effectively reduced. While ensuring high performance, excessive energy consumption is avoided, and the energy utilization efficiency is improved. Through accurate power consumption prediction and real-time optimization control, the power supply strategy can effectively avoid problems such as overload and overheating, ensuring that the chip can still operate stably under high load. This not only improves the chip's performance but also extends its service life. Among them, the specific process of matching the predicted power consumption analysis values with the power supply parameters includes obtaining the power consumption demand of the current chip through the predicted power consumption analysis values and evaluating the current power supply status in combination with the power supply parameters. Then, based on this data, a power optimization control strategy model is used to calculate the optimal power supply strategy, which aims to meet the power consumption demand and optimize energy efficiency. By adjusting the power supply parameters, the matching and optimization control strategy are carried out in real time to ensure that the chip achieves optimal power management under different loads and working conditions, avoiding excessive energy consumption and overload, thereby improving the chip's performance and extending its service life. Through the model evaluation mechanism, the effectiveness of the initial matching power optimization control strategy model can be verified. If the model passes the evaluation, it can be used as part of the chip power supply optimization model to ensure that the power supply strategy used has been strictly verified and has high accuracy and stability. After multiple trainings and evaluations, the stability and efficiency of the chip power supply strategy can be guaranteed during long-term use, avoiding system overheating or reduced energy efficiency caused by improper power consumption, and supporting the stable operation of the chip under different loads. In the convolutional feature processing unit, convolutional analysis is performed on the chip power consumption characteristics to obtain the chip power consumption convolutional features. In the feature recognition and division unit, K power consumption division individuals G k are constructed, where k = 1, 2,..., K. Among them, each power consumption division individual G k contains a set of scale values for dividing the chip power consumption convolutional features. The K power consumption division individuals G k are combined to obtain the power consumption division iteration population. The maximum number of iterations is set by professional technical personnel according to the actual situation. Based on the power consumption division individual G kPerform simulation partitioning on the chip power consumption convolution features to obtain the simulated partitioning of power consumption features; calculate the standard deviation within the simulated partitioning of power consumption features to obtain the convolution scale standard deviation; use the reciprocal of the convolution scale standard deviation as the power consumption partitioning individual G k 's fitness A k ; The scale value represents the standard or boundary for partitioning power consumption features, usually obtained based on experience or data analysis. The scale value can be the size of the time window, the amplitude of power consumption changes, the frequency range, etc.; for each power consumption partitioning individual, it will contain one or more scale values, and each scale value corresponds to a partitioning method. These scale values can be selected according to the model requirements and the complexity of the data; The specific steps for performing simulation partitioning: Use the scale value in the power consumption partitioning individual G k to divide the chip's power consumption convolution features into several sub - parts, and each sub - part represents a specific power consumption pattern or change trend; for example, the power consumption convolution features can be divided into different segments according to the time or frequency range, respectively representing the power consumption behavior under different loads or states; the simulation partitioning method can be based on sliding windows, piece - wise functions, or other data segmentation techniques to divide the power consumption convolution features according to the selected scale value, thereby obtaining multiple sub - features; for each sub - part after partitioning, calculate its internal standard deviation. This step reflects the power consumption volatility of each partitioning segment. The smaller the standard deviation, the smoother the power consumption fluctuation within the segment, and the larger the standard deviation, the greater the fluctuation; through the calculation of the standard deviation, the degree of change in power consumption within different partitioning segments can be evaluated. The part with a smaller standard deviation may indicate that the system is operating stably, while the part with a larger standard deviation may reflect abnormal power consumption fluctuations or load changes; When the maximum number of iterations is reached, output the power consumption partitioning individual corresponding to the maximum current fitness, which is the optimal power consumption partitioning individual; according to the optimal power consumption partitioning individual, divide the chip power consumption convolution features to obtain the power consumption convolution fractal features; where, is the total number of partitions of the chip power consumption convolution features, is the optimal scale for partitioning the chip power consumption convolution features; In the fractal prediction unit, use the formula to calculate the fractal prediction judgment value D; α is the fractal prediction weight coefficient; When D > D0 or D = D0, the power consumption fractal feature is input into the trained chaotic neural network for prediction to obtain the chip power consumption prediction value; when D < D0, the power consumption fractal feature is input into the trained ARIMA time series for prediction to obtain the chip power consumption prediction value; D0 represents the power consumption prediction judgment threshold; the power consumption prediction judgment threshold is set by professional technicians according to the actual situation, and this threshold is used to judge whether to input the power consumption fractal feature into the chaotic neural network or the ARIMA time series model. Specifically, the following actual situations need to be considered when setting: determine the judgment threshold according to the periodicity, volatility and complexity of the power consumption signal; for example, a relatively stable and regular power consumption signal may require a higher threshold; adjust the threshold according to the training results of historical data and the performance requirements of the model to optimize the prediction effect; set an appropriate threshold according to the power consumption changes of the chip under different working loads, environmental temperatures, etc. to cope with different working states; set the threshold according to the statistical analysis of historical data so that the model can adapt to the actual distribution of the data and avoid over - or under - prediction. In the fractal prediction unit, α represents the weight coefficient of the fractal prediction, which is used to adjust the importance of the fractal feature in power consumption prediction; specifically, α controls the contribution degree of the fractal prediction result to the overall power consumption prediction. In practical applications, the setting of α depends on experiments and data analysis, aiming to balance the influence of different features on power consumption prediction; if the fractal feature has a greater impact on power consumption prediction, α can be set to a larger value; if the influence is smaller, it is set to a smaller value. Usually, professional technicians can set α through experimental optimization to optimize the performance of the model. The trained ARIMA time series and the trained chaotic neural network are obtained after being trained with historical data. By performing convolution analysis on the chip power consumption analysis features through a convolution feature processing unit, the key features of the current chip power consumption can be extracted, enhancing the feature expression ability and providing more accurate information for subsequent prediction; in the feature recognition and division unit, by constructing K power consumption analysis division individuals and performing simulation division, the power consumption analysis features can be optimized at multiple scales, effectively capturing different levels of laws and trends in the power consumption time series and enhancing the adaptability of the model; in the fractal prediction unit, based on the prediction judgment value D of the fractal feature, the most suitable prediction model, the chaotic neural network or the ARIMA time series, can be flexibly selected for power consumption analysis prediction; when the D value exceeds the threshold, the chaotic neural network is used for prediction, otherwise the ARIMA time series is used for prediction. This flexible prediction mechanism can adaptively select the most suitable model according to the different characteristics of the data, improving the accuracy and reliability of the prediction; by fusing the trained chaotic neural network and the ARIMA time series, the advantages of the two different models can be combined to make flexible predictions according to the characteristics of the historical data; the chaotic neural network is suitable for processing complex nonlinear relationships, while the ARIMA is good at processing time series data, thus enhancing the prediction ability of the system; through the extraction and optimization of the fractal feature, the change law of the power consumption time series can be better reflected, improving the accuracy of the power consumption prediction. The optimal division scale can accurately capture the details of the power consumption fluctuation, further improving the prediction effect; The training process of the trained ARIMA time series includes: first, collecting historical chip power consumption data and performing preprocessing, such as denoising and differencing, to make it stationary; then, according to the time series characteristics of the data, selecting the appropriate ARIMA model order (p, d, q); using the least squares method or the maximum likelihood estimation method to estimate the parameters and selecting the optimal model through the AIC / BIC criterion; finally, fitting with the training set and evaluating the prediction ability of the model. The training process of the trained chaotic neural network includes: first, generating the nonlinear features of the historical power consumption data and constructing the neural network model architecture; then, training the network through the backpropagation algorithm, adjusting the weights and biases to minimize the prediction error; evaluating the generalization ability of the model through cross-validation and continuously optimizing the network structure and hyperparameters until the model reaches the expected prediction accuracy; For example, in the actual use process, in an embedded chip system, the current, voltage and temperature data of the chip are collected in real time through a power consumption detection circuit; first, the current (I o = 2.5 A) and voltage (V o = 3.3 V) of the current chip are obtained, and the operating frequency (f = 1.5 GHz) and temperature (T = 75 °C) of the chip are recorded at the same time; then, it enters the chip power consumption detection model for processing; through multi-level data preprocessing, the current and voltage data are denoised to obtain the denoised current (I q= 2.4 A) and voltage (V q = 3.2 V); Next, based on the denoised data and other operating parameters, a power supply - electrical variable - operating association model is constructed to obtain the power consumption analysis result of the current chip (P = 8 W); Subsequently, through the chip power supply optimization model, the optimal power supply optimization strategy is calculated, and a suggestion to adjust the voltage to 3.0 V is proposed to improve energy efficiency and reduce the risk of overheating; Finally, this strategy is implemented, the power consumption change of the chip is monitored in real time, and the power supply parameters are continuously optimized to ensure the efficient and stable operation of the system.

[0017] Embodiment 2, a chip power consumption detection and analysis system, see Figure 1 as shown, including: A power consumption detection module, including a data acquisition unit and a power consumption detection unit; The data acquisition unit is used to obtain the current chip power supply parameters, the chip current, and the chip voltage in the chip power consumption detection circuit; At the same time, compensation data is obtained, and the compensation data includes the chip temperature and the chip operating frequency; The power consumption detection unit is used to perform power consumption detection based on the chip power consumption detection model to obtain the chip power consumption result; The chip power consumption detection model realizes data denoising, extracts key features, establishes an association model through power consumption compensation analysis, and predicts and analyzes the chip power consumption through pattern matching; A power supply optimization module, including a power supply control unit; The power supply control unit is used to perform power consumption matching based on the chip power consumption result and the chip power supply optimization model to obtain the power supply optimization strategy; The chip power supply optimization model can predict the chip power consumption and optimize the control strategy according to the current chip power supply parameters through fractal prediction and power supply strategy optimization, improving the energy efficiency and performance of the chip; A chip control module, including a chip micro - control unit; The chip micro - control unit is used to perform real - time optimization of the chip power consumption detection circuit according to the power supply optimization strategy, change the current chip power supply parameters, and continuously perform chip power consumption detection operations.

[0018] It should be understood that for those of ordinary skill in the art, improvements or transformations can be made according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention. The parts not described in detail in this specification belong to the prior art well - known to those of ordinary skill in the art.

Claims

1. A method for detecting and analyzing the power consumption of a chip, characterized in that, Including the following steps: In the chip power consumption detection circuit, obtain the current chip power supply parameters, and obtain the chip current and chip voltage; at the same time, obtain compensation data, which includes chip temperature and chip operating frequency; Based on the chip power consumption detection model, perform power consumption detection to obtain the chip power consumption result; The chip power consumption detection model realizes data denoising, extracts key features, establishes an association model through power consumption compensation analysis, and predicts and analyzes the chip power consumption through pattern matching; Based on the chip power consumption result and the chip power supply optimization model, perform power consumption matching to obtain the power supply optimization strategy; The chip power supply optimization model can predict the chip power consumption and optimize the control strategy according to the current chip power supply parameters through fractal prediction and power supply strategy optimization, improving the energy efficiency and performance of the chip; According to the power supply optimization strategy, perform real-time optimization on the chip power consumption detection circuit, change the current chip power supply parameters, and continuously perform chip power consumption detection operations.

2. The chip power consumption detection and analysis method according to claim 1, wherein In the chip power consumption detection model, perform denoising processing on the chip current and chip voltage to obtain the denoised chip current and denoised chip voltage; Establish a power supply - electrical variable - working association compensation model for analysis to obtain the chip power consumption result.

3. A method for detecting and analyzing the power consumption of a chip according to claim 2, characterized in that, The specific steps for performing denoising processing include: Perform noise separation on the chip current to obtain the chip current noise I z ; Perform noise separation on the chip voltage to obtain the chip voltage noise V z ; Perform noise shaping on the chip current noise I z to obtain the noise-reduced chip current S(I); Perform noise shaping on the chip voltage noise V z to obtain the noise-reduced chip voltage S(V); Using formula I q =W i *S(I)+(1 - W i )*I o Calculate the denoising chip current I q , where W i represents the weight coefficient corresponding to the denoising chip current S(I); I o represents the chip current; Using the formula V q =W v *S(V)+(1 - W v )*V o the voltage V of the denoising chip is calculated q , where W v represents the weight coefficient corresponding to the voltage S(V) of the noise reduction chip; V o represents the chip voltage.

4. A method for detecting and analyzing the power consumption of a chip according to claim 3, characterized in that, The specific steps for establishing a power supply - electrical variable - working association compensation model include: Perform multi-scale differential extraction on the denoised chip current, denoised chip voltage, current chip power supply parameters, and compensation data to obtain current differential features, voltage differential features, power supply differential features, and compensation differential features; combine all differential features to obtain the power consumption compensation feature set; Based on the power consumption compensation feature set, establish a differential association matrix to obtain the power supply - electrical variable - working association compensation model; Extract the main variation direction of the power supply - electrical variable - working association compensation model to obtain the power consumption dominant variation source; Perform eigenvalue decomposition on the power supply - electrical variable - working association compensation model to obtain the power consumption association eigenvalues; Combine the power consumption dominant variation source and the power consumption association eigenvalues to construct a power consumption abnormal trajectory; Perform pattern matching on the power consumption abnormal trajectory to obtain the chip power consumption result.

5. A method for detecting and analyzing the power consumption of a chip according to claim 4, characterized in that, In the chip power supply optimization model, perform feature extraction on the chip power consumption result to obtain chip power consumption features; according to the chip power consumption features, use the convolution feature processing unit, feature recognition division unit, and fractal prediction unit to perform fractal prediction to obtain the chip power consumption prediction value; based on the chip power consumption prediction value and the current chip power supply parameters, match the power supply optimization control strategy to obtain the power supply optimization strategy.

6. The method for detecting and analyzing the power consumption of a chip according to claim 5, wherein In the convolution feature processing unit, perform convolution analysis on the chip power consumption features to obtain chip power consumption convolution features; In the feature recognition and division unit, K power consumption division individuals G are constructed k , where k = 1, 2, …, K; among them, each power consumption division individual G k contains a set of scale values for dividing the convolutional features of the chip power consumption; combining the K power consumption division individuals G k to obtain a power consumption division iterative population; setting the maximum number of iterations; Dividing individual G based on power consumption k Performing simulation division on the convolution features of the chip power consumption to obtain the simulated division of power consumption features; calculating the standard deviation within the simulated division of power consumption features to obtain the convolution scale standard deviation; using the reciprocal of the convolution scale standard deviation as individual G for power consumption division k The fitness A k ; When the maximum number of iterations is reached, output the power consumption partitioning individual corresponding to the maximum current fitness, which is the optimal power consumption partitioning individual; partition the chip power consumption convolution features according to the optimal power consumption partitioning individual to obtain the power consumption convolution fractal features; where, is the total number of partitions of the chip power consumption convolution features, is the optimal scale for partitioning the chip power consumption convolution features; In the fractal prediction unit, the formula is used to calculate the fractal prediction judgment value D; α is the fractal prediction weight coefficient; If D > D0 or D = D0, then input the power consumption convolution fractal features into the trained chaotic neural network for prediction to obtain the chip power consumption prediction value; if D < D0, then input the power consumption convolution fractal features into the trained ARIMA time series for prediction to obtain the chip power consumption prediction value; D0 represents the power consumption prediction judgment threshold.

7. A chip power consumption detection and analysis system, characterized in that The system applies the chip power consumption detection and analysis method described in any one of claims 1 - 6 above, including: The power consumption detection module includes a data acquisition unit and a power consumption detection unit; The data acquisition unit is used to obtain the current chip power supply parameters, chip current and chip voltage in the chip power consumption detection circuit; meanwhile, compensation data is obtained, and the compensation data includes chip temperature and chip operating frequency. The power consumption detection unit is used to perform power consumption detection based on the chip power consumption detection model to obtain the chip power consumption result; the chip power consumption detection model realizes data denoising, extracts key features, establishes a correlation model through power consumption compensation analysis, and predicts and analyzes the chip power consumption through pattern matching. The power supply optimization module includes a power control unit. The power control unit is used to perform power consumption matching based on the chip power consumption result and the chip power supply optimization model to obtain the power supply optimization strategy; the chip power supply optimization model can predict the chip power consumption and optimize the control strategy according to the current chip power supply parameters through fractal prediction and power supply strategy optimization, improving the energy efficiency and performance of the chip. The chip control module includes a chip micro-control unit. The chip micro-control unit is used to perform real-time optimization of the chip power consumption detection circuit according to the power supply optimization strategy, change the current chip power supply parameters, and continuously perform chip power consumption detection operations.

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