Time constant calculation method and system based on overall control system

Abstract

The invention relates to a time constant calculation method and system based on an integral control system, and the method comprises the steps: obtaining PWM switching frequency, timer interruption code execution time, and a timing period set by a timer, and calculating the delay time of the analog quantity AD sampling hardware conditioning circuit, half of the retention time of the controlled value, the interval time from starting analog quantity AD sampling to entering a timer, and the interval time from entering the timer to adjusting the controlled object to the controlled value. According to the method, the initial time constant can be accurately calculated, automatic designers do not need to repeatedly try to debug PI parameters, proper parameter values can be quickly determined according to the calculation result provided by the invention, the debugging period is remarkably shortened, and the working efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of automated closed-loop control, and particularly to a method and system for calculating the time constant based on an overall control system. Background Art

[0002] The statements in this part merely provide background technical information related to the present invention and do not necessarily constitute prior art.

[0003] The overall control system refers to considering the controlled object and the actuator as a whole, avoiding separate consideration of the decentralized parts and the existence of cumulative errors. Currently, with the deepening of automation in various industries, various controllers play a crucial role in different industries, and traditional PID control technology is widely used. In this technology, the setting of the P proportional parameter and the I integral parameter often depends on the time constant of the system. The time constant generally refers to the duration from the start of signal acquisition to the final effect of closed-loop control.

[0004] However, in the prior art, affected by factors such as hardware signal sampling, signal processing, and processing mechanisms of the control system, digital control has delays and is not real-time control. This delay makes it necessary to consider the delay time when designing PI, but in actual operation, it is difficult to accurately quantify the time constant of the overall control system, resulting in the need to repeatedly debug the PI parameters. This increases the workload of automation designers and prolongs the design cycle on the one hand, and on the other hand, affects the stability of the control system, making it difficult to achieve the integrated collaborative work of the control system and the controlled object, and restricting the further improvement of the performance of the automated control system. Summary of the Invention

[0005] In order to solve the above problems, the present invention proposes a method and system for calculating the time constant based on an overall control system, aiming to solve the technical problems existing in the prior art pointed out in the background art.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a method for calculating the time constant based on an overall control system, including:

[0008] Obtain the PWM switching frequency, the execution time of the timer interrupt code, and the timing period set by the timer, and calculate the delay time of the analog-to-digital (AD) sampling hardware conditioning circuit;

[0009] Calculate the PWM switching period according to the PWM switching frequency, and obtain half of the holding time of the controlled value based on the PWM switching period and the timing period;

[0010] Determine the range of the interval time from the start of analog-to-digital (AD) sampling to entering the timer according to the analog AD sampling, the PWM switching period, and the execution time of the timer period interrupt signal obtained based on the timer period; obtain the interval time from entering the timer to the control object being adjusted to the controlled value according to the execution time of the timer interrupt code; calculate the equivalent value of the sum of the interval time from the start of analog AD sampling to entering the timer and the interval time from entering the timer to the control object being adjusted to the controlled value.

[0011] Add the equivalent value to half of the delay time of the analog AD sampling hardware conditioning circuit and the controlled value holding time to obtain the time constant.

[0012] In a further technical solution, the analog AD sampling hardware conditioning circuit includes a low-pass filter circuit, and the delay time of the analog AD sampling hardware conditioning circuit is calculated through the resistance and capacitance in the low-pass filter circuit. The specific calculation formula is: T h = RC, where T h represents the delay time of the analog AD sampling hardware conditioning circuit, R represents the resistance value, and C represents the capacitance value.

[0013] In a further technical solution, the formula for calculating the PWM switching period according to the PWM switching frequency is: where T PWM represents the PWM switching period, and f PWM represents the PWM switching frequency.

[0014] In a further technical solution, the method for obtaining the half-period delay time of the controlled value holding is as follows: when half of the PWM switching period is less than or equal to the timer period, the controlled value holding time is equal to the timer period; when half of the PWM switching period is greater than the timer period, the controlled value holding time is equal to half of the PWM switching period.

[0015] In a further technical solution, when the count inside the timer reaches the timer period, a timer period interrupt signal is generated.

[0016] In a further technical solution, the maximum interval of the interval time from the start of analog AD sampling to entering the timer is one PWM switching period. According to the range of the interval time from the start of analog AD sampling to entering the timer and in combination with the execution time of the timer interrupt code, calculate the sum of the interval time from the start of analog AD sampling to entering the timer and the interval time from entering the timer to the control object being adjusted to the controlled value.

[0017] In a further technical solution, calculate the equivalent value of the sum of the interval time from the start of analog AD sampling to entering the timer and the interval time from entering the timer to the control object being adjusted to the controlled value according to the weighted percentage.

[0018] In a second aspect, the present invention provides a time constant calculation system based on an overall control system, including:

[0019] A parameter acquisition module, configured to: acquire the PWM switching frequency, the execution time of the timer interrupt code, and the timing period set by the timer, and calculate the delay time of the analog-to-digital (AD) sampling hardware conditioning circuit;

[0020] A parameter processing module, configured to: calculate the PWM switching period according to the PWM switching frequency, and obtain half of the controlled value holding time according to the PWM switching period and the timing period; determine the range of the interval time from the start of analog AD sampling to entering the timer according to the analog AD sampling, the PWM switching period, and the execution time of the timing period interrupt signal obtained according to the timing period; obtain the interval time from entering the timer until the controlled object is adjusted to the controlled value according to the execution time of the timer interrupt code; calculate the equivalent value of the sum of the interval time from the start of analog AD sampling to entering the timer and the interval time from entering the timer until the controlled object is adjusted to the controlled value;

[0021] A calculation module, configured to: add the equivalent value to the delay time of the analog AD sampling hardware conditioning circuit and half of the controlled value holding time to obtain the time constant.

[0022] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0023] By acquiring the PWM switching frequency, the execution time of the timer interrupt code, and the timing period set by the timer, and through calculation and processing, the present invention obtains the equivalent value of the sum of the interval time from the start of analog AD sampling to entering the timer and the interval time from entering the timer until the controlled object is adjusted to the controlled value, the delay time of the analog AD sampling hardware conditioning circuit, and the half-period delay time of the controlled value holding. It can accurately calculate the initial time constant, enabling automation designers to quickly determine appropriate parameter values based on the calculation results provided by the present invention without repeatedly trying to debug the PI parameters, significantly shortening the debugging period and improving work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings forming a part of this specification are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute a limitation to the present invention.

[0025] Figure 1 is the first control loop dynamic structure diagram of Embodiment 1 of the present invention;

[0026] Figure 2 is the control loop delay time schematic diagram of Embodiment 1 of the present invention;

[0027] Figure 3 It is the dynamic structure diagram of the control loop after given filtering in the first embodiment of the present invention;

[0028] Figure 4 It is the dynamic structure diagram of the second control loop in the first embodiment of the present invention;

[0029] Figure 5 It is the analog - to - digital (AD) sampling hardware conditioning circuit in the first embodiment of the present invention;

[0030] Figure 6 It is the schematic diagram of the current - loop delay time under different T1 conditions in the first embodiment of the present invention;

[0031] Figure 7 It is the schematic diagram of the control - loop delay time under different T1 conditions in the first embodiment of the present invention;

[0032] Figure 8 It is the schematic diagram of the control - loop delay time under different T1 conditions in the first embodiment of the present invention; Detailed implementation manners

[0033] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0034] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0035] Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0036] Embodiment 1

[0037] Currently, the control operation chip is implemented using a DSP. Its timer period is determined by the MTU, and the analog - to - digital (AD) sampling of the controlled object is started by hardware at the beginning of each timing period, and the sampling value is obtained through an AD interrupt. When the controlled value is obtained in the timing - period interrupt, it is always sent (Loading) by hardware at the end of the nearest timing period; the timing period is determined by the timer CMT. When the count inside the timer reaches the timing period, a timing - period interrupt signal is generated, and the execution time of the timing - period interrupt signal (TB interrupt - signal execution time) can be obtained. Therefore, the generation mechanism of the timing - period interrupt is independent of the generation mechanism of the analog - to - digital (AD) sampling; the PWM period can be arbitrarily changed within a certain range, and the timing - interrupt period is assumed to be fixed at 250 μs.

[0038] This embodiment proposes a time - constant calculation method based on the overall control system, specifically including the following technical solutions:

[0039] To obtain the PWM switching frequency, the timer interrupt code execution time, and the timer setting period, first, Figure 1 As shown in the figure, assuming that the PWM switching frequency is 10KHz and the code execution time of the timer interrupt is 170Us, the specific analysis of the control loop delay time is as follows:

[0040] First of all, it should be noted that Figure 2 Sampling is the sampling point, Loading Update is the action update, and Loading Hold is the action hold. Figure 1 Middle T h It represents the delay time of the analog AD sampling hardware conditioning circuit; T1 represents the interval time from starting analog AD sampling to entering the timer. Since the generation mechanism of analog AD sampling is independent of the generation mechanism of timer interrupt, the size of T1 is random; T2 represents the interval time from entering the timer when the controlled object is adjusted to the controlled value; T3 represents half of the controlled value holding time. Since each controlled value must be maintained for a certain time until the next controlled value is updated, this time is related to the PWM switching period and the timing period. It can be considered that the delay time of this process is equal to half of the controlled value holding time.

[0041] For balance Figure 1 The delay of the PI feedback channel in Figure 3 As shown in the figure, a similar filtering link is added at the given end, and Figure 3 After appropriate merging, we can get Figure 4 The second control loop dynamic structure diagram is shown in FIG, where T f =T h +T1+T2+T3 represents the total delay time of the control loop, that is, the time constant. The following will analyze each part in detail.

[0042] T h :

[0043] like Figure 5 The figure shows an analog AD sampling hardware conditioning circuit on the DSP control board. The R423 and C211 parts are low-pass filter circuits. The delay time of the analog AD sampling hardware conditioning circuit is the filter time constant, which is calculated by the resistance and capacitance in the low-pass filter circuit. The specific calculation formula is: T h =RC, where T h represents the delay time of the analog AD sampling hardware conditioning circuit, R represents the resistance value, and C represents the capacitance value; in this embodiment, for example, T h =RC=10×10 3 ×0.01×10 -6 =100Us.

[0044] T3:

[0045] As described above, T3 is equal to half of the controlled value holding time, and the controlled value holding time is related to the PWM switching period T PWM and the timing period TB. Among them, T PWM represents the PWM switching period, and f PWM represents the PWM switching frequency.

[0046] The method to obtain the half-cycle delay time of the controlled value holding is as follows: when , the controlled value holding time is equal to the timing period, and when , the controlled value holding time is equal to When the TB period is fixed at 300 μs, so when the PWM switching frequency is greater than 1 kHz, the duty value holding time is equal to the TB period. Only when the PWM switching frequency is equal to 1 kHz, the controlled value holding time is equal to (600 μs).

[0047] T1 + T2:

[0048] Because the generation mechanism of the analog AD sampling is independent of the generation mechanism of the TB interrupt, the magnitude of T1 is random. Figure 6 That is, it is a schematic diagram of the control loop delay time under different T1 conditions. Among them, the sampling signal is obtained by AD sampling after a delay time T h . And because the analog AD sampling is started by a hardware cycle, it can be considered that the maximum interval from starting the analog AD sampling to entering the timer is 1 PWM cycle (100 μs); the TB (timing period interrupt) interrupt always acts at the moment of the nearest PWM cycle underflow after obtaining the controlled value, and this time interval is T2; the controlled value is updated again after a holding time of 2T3, and the equivalent delay time of this holding link is T3.

[0049] Since it always acts at the moment of the nearest PWM cycle underflow after obtaining the controlled value, when T1 varies within a certain range, the value of T1 + T2 remains unchanged. From Figure 6 it can be easily known that according to different magnitudes of T1, there are the following situations for T1 + T2:

[0050] (1) 0 μs < T1 < 30 μs, T1 + T2 = 200 μs

[0051] (2) 30 μs < T1 < 80 μs, T1 + T2 = 250 μs

[0052] (3) 80 μs < T1 < 100 μs, T1 + T2 = 300 μs

[0053] Through weighted averaging, T1 + T2 can be equivalent to

[0054]

[0055] where 20, 50, and 30 are weighted percentages and can be adjusted according to system characteristics.

[0056] T f :

[0057] The total delay time of the control loop, i.e., the time constant is: T f = T h +(T1 + T2)+T3 = 40 + 245 + 125 = 410 Us.

[0058] The above derivation process and method are applicable to different PWM switching frequencies and TB interrupt signal execution times. Now assume that the PWM switching frequency is 7 KHz and the TB interrupt signal execution time is 100 Us, as Figure 7 shown:

[0059] The specific analysis process is the same as the foregoing. From Figure 7 it can be known that according to the different magnitudes of T1, T1 + T2 has the following several cases.

[0060] (1) 0 Us < T1 < 44.5 Us, T1 + T2 = 214.5 Us

[0061] (2) 44.5 Us < T1 < 116 Us, T1 + T2 = 286 Us

[0062] (3) 116 Us < T1 < 143 Us, T1 + T2 = 357.5 Us

[0063] Through weighted averaging, T1 + T2 can be equivalent to

[0064]

[0065] where 44.5, 71.5, and 27 are weighted percentages and can be adjusted according to system characteristics.

[0066] Therefore, the total delay time of the control loop is:

[0067] T f = T h +(T1 + T2)+T3 = 40 + 277.25 + 125 = 442 Us.

[0068] If it is assumed that the PWM switching frequency is 5 KHz and the TB interrupt signal execution time is 120 Us, as Figure 8 shown:

[0069] The specific analysis process is the same as described above. Starting from Figure 8 it can be seen that according to the different magnitudes of T1, there are the following situations for T1 + T2:

[0070] (1) 0Us < T1 < 20Us, T1 + T2 = 150Us

[0071] (2) 20Us < T1 < 70Us, T1 + T2 = 200Us

[0072] (3) 70Us < T1 < 100Us, T1 + T2 = 250Us

[0073] Through weighted averaging, T1 + T2 can be equivalent to

[0074]

[0075] Among them, 20, 50, and 30 are weighted percentages, which can be adjusted according to the system characteristics.

[0076] Therefore, the total delay time of the control loop is:

[0077] T f = T h +(T1 + T2)+T3 = 40 + 205 + 125 = 370Us.

[0078] In summary, for different switching frequencies f PWM and the execution time T of the TB interrupt signal code , the statistical delay time T f is as shown in the following table:

[0079]

[0080] Embodiment 2

[0081] This embodiment provides a time constant calculation system based on an overall control system, which specifically includes the following modules:

[0082] A parameter acquisition module, configured to: acquire the PWM switching frequency, the execution time of the timer interrupt code, and the timing period set by the timer, and calculate the delay time of the analog-to-digital (AD) sampling hardware conditioning circuit;

[0083] A parameter processing module, configured to: calculate a PWM switching period according to a PWM switching frequency, and obtain a half-cycle delay time for maintaining a controlled value according to the PWM switching period and the timing period; determine a range of an interval time from starting analog-to-digital (AD) sampling of an analog quantity to entering a timer according to the analog quantity AD sampling, the PWM switching period, and an execution time of a timing period interruption signal obtained according to the timing period; obtain an interval time from entering the timer to adjusting a controlled object to a controlled value according to an execution time of a timer interruption code; calculate an equivalent value of the interval time from starting analog quantity AD sampling to entering the timer plus the interval time from entering the timer to adjusting the controlled object to the controlled value.

[0084] A calculation module, configured to: add the equivalent value to a delay time of an analog quantity AD sampling hardware conditioning circuit and a half-cycle delay time for maintaining a controlled value to obtain a time constant.

[0085] For the implementation of specific modules in this embodiment, refer to the steps of a method for calculating a time constant based on an overall control system described in Embodiment 1, and no specific description will be given here.

[0086] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but should not be construed as a limitation on the scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A method for calculating the time constant based on an overall control system, characterized in that, Including: Obtain the PWM switching frequency, the execution time of the timer interrupt code, and the timing period set by the timer, and calculate the delay time of the analog-to-digital (AD) sampling hardware conditioning circuit; Calculate the PWM switching period based on the PWM switching frequency, and obtain the half-cycle delay time for maintaining the controlled value according to the PWM switching period and the timing period; Determine the range of the interval time from the start of analog AD sampling to entering the timer according to the analog AD sampling, the PWM switching period, and the timing period interrupt signal obtained according to the timing period; Obtain the interval time from the start of the controlled object adjustment to the controlled value after entering the timer according to the execution time of the timer interrupt code; Calculate the equivalent value of the interval time from the start of analog AD sampling to entering the timer plus the interval time from the start of the controlled object adjustment to the controlled value after entering the timer; Add the equivalent value to the delay time of the analog AD sampling hardware conditioning circuit and the half-cycle delay time for maintaining the controlled value, which is the time constant.

2. The time constant calculation method based on the overall control system according to claim 1, wherein, The analog AD sampling hardware conditioning circuit includes a low-pass filter circuit. The delay time of the analog AD sampling hardware conditioning circuit is calculated through the resistors and capacitors in the low-pass filter circuit. The specific calculation formula is: T h = RC, where T h represents the delay time of the analog AD sampling hardware conditioning circuit, R represents the resistance value, and C represents the capacitance value.

3. The time constant calculation method based on the overall control system according to claim 1, characterized in that The formula for calculating the PWM switching period based on the PWM switching frequency is as follows: where T PWM represents the PWM switching period, and f PWM represents the PWM switching frequency.

4. A method for calculating the time constant based on the overall control system according to claim 1, characterized in that, The method for obtaining the half-cycle delay time of the controlled value is as follows: when the PWM switching period is less than the timing period, the half-cycle delay time of the controlled value is half of the timing period; when the PWM switching period is greater than the timing period, the half-cycle delay time of the controlled value is half of 5. A time constant calculation method based on an overall control system according to claim 1, characterized in that, When the count inside the timer reaches the timing period, a timing period interrupt signal is generated.

6. A time constant calculation method based on an overall control system according to claim 1, characterized in that, The maximum interval of the interval time from the start of analog AD sampling to entering the timer is one PWM switching period. Calculate the interval time from the start of analog AD sampling to entering the timer plus the interval time from the start of the controlled object adjustment to the controlled value after entering the timer according to the range of the interval time from the start of analog AD sampling to entering the timer and in combination with the execution time of the timer interrupt code.

7. A method for calculating the time constant based on the overall control system according to claim 1, characterized in that, Calculate the equivalent value of the interval time from the start of analog AD sampling to entering the timer plus the interval time from the start of the controlled object adjustment to the controlled value after entering the timer according to the weighted percentage.

8. A time constant calculation system based on an overall control system, characterized in that, Including: A parameter acquisition module, configured to: obtain the PWM switching frequency, the execution time of the timer interrupt code, and the timing period set by the timer, and calculate the delay time of the analog AD sampling hardware conditioning circuit; A parameter processing module, configured to: calculate the PWM switching period based on the PWM switching frequency, and obtain the half-cycle delay time for maintaining the controlled value according to the PWM switching period and the timing period; Determine the range of the interval time from the start of analog AD sampling to entering the timer according to the analog AD sampling, the PWM switching period, and the execution time of the timing period interrupt signal obtained according to the timing period; Obtain the interval time from the start of the controlled object adjustment to the controlled value after entering the timer according to the execution time of the timer interrupt code; Calculate the equivalent value of the interval time from the start of analog AD sampling to entering the timer plus the interval time from the start of the controlled object adjustment to the controlled value after entering the timer; A calculation module, configured to: add the equivalent value to the delay time of the analog AD sampling hardware conditioning circuit and the half-cycle delay time for maintaining the controlled value, which is the time constant.

9. A computer-readable storage medium having a program stored thereon, characterized in that, When the program is executed by a processor, it implements the steps in a method for calculating a time constant based on an overall control system as described in any one of claims 1-7.

10. An electronic device, comprising a memory, a processor, and a program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in a method for calculating a time constant based on an overall control system as described in any one of claims 1-7.

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