Method, device, medium and product for data processing

Abstract

The invention discloses a data processing method and device, a medium and a product, and relates to the technical field of data storage, and the method comprises the steps: distributing a same input / output queue to a plurality of controllers, enabling each controller to independently control the distributed queue item, and enabling the plurality of controllers to jointly distribute the same input / output queue, thereby remarkably reducing the hardware overhead, and improving the data processing efficiency. Moreover, dynamic allocation of input and output queues among a plurality of controllers is supported, system requirements of different scales can be met, in addition, the fairness of each controller can be ensured and the real-time performance of a high-priority task can be considered through combination of polling scheduling and weight priority, and therefore, the method and the device have the advantages of being high in practicability and the like. The technical problems of high time delay, resource waste and the like under the condition that an arbitration mechanism processes large-scale queues can be solved, and the technical effects of reducing hardware overhead, reducing time delay and improving the resource utilization rate are achieved.

Description

Technical Field

[0001] This application relates to the technical field of data storage, and in particular to methods, devices, media, and products for data processing. Background Art

[0002] Non-Volatile Memory Express (NVMe) is a high-performance and low-latency storage protocol designed for flash-based storage devices. For example, NVMe can be applied to Solid State Disks (SSDs). In the NVMe protocol, command submission and return of completion status are achieved through Queue Pairs. The NVMe protocol supports multiple Queue Pairs, and each Queue Pair can independently process input / output requests, thus achieving parallel processing and high throughput.

[0003] In the arbitration mechanism in the related art, problems such as high latency and resource waste exist when dealing with a large number of queues. Summary of the Invention

[0004] This application provides methods, devices, media, and products for data processing to at least solve the problems of high latency and resource waste in the related art when dealing with a large number of queues.

[0005] This application provides a method for data processing, including: creating an input / output queue, where the attributes of the input / output queue include a first attribute, and based on the first attribute, it represents the controller to which each queue entry in the input / output queue belongs, or the queue entry is not assigned to a controller; traversing the input / output queue based on the instruction for configuring the queue entries of each controller to determine the queue entries assigned to each controller; if there are requests from multiple controllers, determine the target controller corresponding to the next request to be processed through round-robin scheduling, and among the multiple queue entries of the target controller, determine the queue entry to be processed based on the weight priority of each queue entry, and perform data processing based on the attributes of the queue entry to be processed.

[0006] This application also provides a computer device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above methods for data processing when executing the computer program.

[0007] This application also provides a computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the steps of any of the above methods for data processing.

[0008] The present application also provides a computer program product, including a computer program which, when executed by a processor, implements the steps of any one of the above methods for data processing.

[0009] Through the present application, by allocating the same input / output queue to multiple controllers, each controller exclusively controls the queue items allocated to it. By jointly allocating the same input / output queue by multiple controllers, the hardware overhead can be significantly reduced. Moreover, it supports the dynamic allocation of the input / output queue among multiple controllers, and can adapt to the system requirements of different scales. In addition, the combination of polling scheduling and weight priority can not only ensure the fairness of each controller, but also take into account the real-time performance of high-priority tasks. Therefore, it can solve the technical problems such as high latency and resource waste existing in the arbitration mechanism when dealing with large-scale queues, and achieve the technical effects of reducing hardware overhead, reducing latency, and improving resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 Shows the structural schematic diagram of the read-commit queue command in the related art; Figure 2 Shows the structural schematic diagram of the write-complete queue command in the related art; Figure 3 Shows the flow schematic diagram of the method for data processing provided by the present application; Figure 4 Shows the structural schematic diagram of the controller description table of multiple controllers provided by the present application; Figure 5 Shows the application scenario schematic diagram of the fetch-commit queue command provided by the present application; Figure 6 Shows the application scenario schematic diagram of the write-complete queue completion command provided by the present application; Figure 7 Shows the structural schematic diagram of the device for data processing provided by the present application; Figure 8 Shows the structural schematic diagram of the electronic device provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0013] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0014] In order to enable those skilled in the art of this technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0015] The queue pairs in the NVMe protocol include a submission queue and a completion queue. The submission queue (abbreviated as SQ), is used for the host to submit input / output (abbreviated as I / O) commands to the SSD controller, and the I / O commands can be read commands or write commands. The host is a computing device that runs an operating system and application programs, such as a server or a personal computer (abbreviated as PC). The completion queue (abbreviated as CQ) is used for the SSD controller to return the execution result of the command to the host.

[0016] In the design of an SSD main control chip using the Peripheral Component Interconnect express (abbreviated as PCIe) interface, the Physical Function (abbreviated as PF) controller or the Virtual Function (abbreviated as VF) controller usually manages their respective submission queues or completion queues independently, resulting in low utilization of hardware resources and poor scheduling efficiency. As the scale of the SSD main control chip expands, the number of submission queues and completion queues increases, and the hardware overhead and scheduling complexity increase significantly. Especially in a multi-controller environment, the scheduling and processing efficiency of commands directly affect the performance and response speed of the SSD.

[0017] In the related art, each controller exclusively occupies fixed queue resources, such as the submission queue or the completion queue in the I / O queue, and each controller has an independent module for obtaining and processing commands. Figure 1 shows a schematic structural diagram of a read submission queue command in the related art. As Figure 1 shown, the queue resources owned by the first controller 10 include the submission queue request acquisition sequence 101 of the first controller. The queue resources owned by the second controller 11 include the submission queue request acquisition sequence 111 of the second controller. The queue resources owned by the third controller 12 include the submission queue request acquisition sequence 121 of the third controller.

[0018] The first polling scheduling module 13 is configured to obtain and perform polling scheduling based on the submission queue request acquisition sequence 101 of the first controller, the submission queue request acquisition sequence 111 of the second controller, and the submission queue request acquisition sequence 121 of the third controller.

[0019] The command prompt first-in-first-out module 14 is configured to receive the I / O commands obtained from the submission queue by the submission queue request acquisition sequence, and send the submission queue request to each weighted polling scheduling module. Specifically, the submission queue request of the first controller is sent to the first weighted polling scheduling module 15; the first weighted polling scheduling module 15 sends the submission queue request of the first controller to the processing module 151 of the first controller for processing. The submission queue request of the second controller is sent to the second weighted polling scheduling module 16; the second weighted polling scheduling module 16 sends the submission queue request of the second controller to the processing module 161 of the second controller for processing. The submission queue request of the third controller is sent to the third weighted polling scheduling module 17; the third weighted polling scheduling module 17 sends the submission queue request of the third controller to the processing module 171 of the third controller for processing.

[0020] Figure 2 shows a schematic structural diagram of a write completion queue command in the related art. As Figure 2 shown, the command prompt completion module 20 obtains the first hardware completion queue 21, the first firmware completion queue 22, and the first direct memory access completion queue 23, and sends each completion queue to the first first-in-first-out module 24, the second first-in-first-out module 25, or the third first-in-first-out module 26 indicated by the controller identification information in each completion queue according to the indication of the controller identification information.

[0021] The queue resources owned by the first controller 10 also include the completion queue processing resources of the first controller. Based on the first first-in, first-out module 24, the completion queue 241 of the target first controller is determined. The queue resources owned by the second controller 11 also include the completion queue processing resources of the second controller. Based on the second first-in, first-out module 25, the completion queue 251 of the target second controller is determined. The queue resources owned by the third controller 12 also include the completion queue processing resources of the third controller. Based on the third first-in, first-out module 26, the completion queue 261 of the target third controller is determined.

[0022] The completion queue write arbiter 27 determines the write signal 271 among the completion queue 241 of the target first controller, the completion queue 251 of the target second controller, and the completion queue 261 of the target third controller. The completion queue read arbiter 28 determines the read signal 281 among the completion queue 241 of the target first controller, the completion queue 251 of the target second controller, and the completion queue 261 of the target third controller.

[0023] The specific implementation is as follows: Each controller has an independent I / O submission queue (SQ) and I / O completion queue (CQ), and the queue resources are not shared. The controller includes register resources such as a doorbell register, the base address of the CQ / SQ, and whether the CQ / SQ is continuous. Among them, the doorbell register is used for the Host to notify the controller that a new command has been submitted to the SQ or the completion status needs to be read from the CQ. Each controller is also equipped with an independent command acquisition module and a command processing module. The command acquisition module interacts with the Host through the doorbell register and reads commands from the SQ. The command processing module performs preliminary analysis and verification on the read commands. Through the analysis and verification, it judges whether the commands conform to the format specified by the protocol. If the commands do not conform to the format specified by the protocol, the read commands will be put into the hardware completion queue. If the commands conform to the format specified by the protocol, the read commands will be delivered to the software for processing.

[0024] The technical solutions in the related art have the following problems: First, each controller monopolizes fixed queue resources, which leads to low resource utilization. For example, the queue resources of some controllers may not be fully utilized, while the queue resources of other controllers may be insufficient. Due to the inability to share resources, the hardware overhead is large. Especially in a multi-controller environment, the redundant design of queue resources increases the chip area and power consumption.

[0025] Second, a certain controller may be unable to process new commands due to insufficient queue resources, while the queue resources of other controllers may be idle. Due to the lack of a resource sharing mechanism, the overall system scheduling efficiency is low, and the hardware resources cannot be fully utilized.

[0026] Thirdly, queue resources are statically allocated during initialization and cannot be dynamically adjusted according to actual requirements. For example, when the load of a certain controller increases, more queue resources cannot be dynamically allocated. Due to the lack of a dynamic resource allocation mechanism, the system cannot adapt to I / O requests of different scales and has poor flexibility.

[0027] Combined with a specific application environment architecture or a specific hardware architecture on which the execution of the method for data processing depends, the specific application environment architecture or the specific hardware architecture is described herein.

[0028] The method for data processing provided by the embodiments of the present application depends on the co - design of a multi - controller parallel architecture, a two - layer arbitration hardware, and a shared input - output queue, accelerates scheduling decisions through a hardware - level arbiter, and realizes efficient allocation by using hardware encoding of queue attributes. It can be applied to scenarios that require multi - controller concurrent processing and have clear requirements for scheduling fairness and priority, such as high - end storage systems, multi - core computing platforms, or high - speed network devices.

[0029] The embodiments of the present application provide a method for data processing. Figure 3 The flowchart of the method for data processing provided by the present application is shown, as Figure 3 shown, the method for data processing includes: Step S301: Create an input - output queue. Among them, the attributes of the input - output queue include a first attribute. Based on the first attribute, it characterizes the controller to which each queue item in the input - output queue belongs, or the queue item is not allocated to a controller.

[0030] In this step, the I / O queues of multiple controllers are merged, so that multiple controllers share the created input - output queue. Based on the created input - output queue, it characterizes a shared resource pool. The attributes of the input - output queue include queue item identification information, and different queue items can be distinguished by numbering the input - output queue.

[0031] Specifically, the input / output queue includes multiple queue items such as a first queue item, a second queue item, ..., an Nth queue item, etc. Among them, the first queue item can be a submission queue, and the second queue item can be a completion queue. The submission queue in the input / output queue can be represented based on local_sqn, and the completion queue in the input / output queue can be represented based on local_cqn. n can represent a number, such as 0, 1, or 2, etc. The input / output queue can also include a first queue pair, a second queue pair, ..., an Mth queue pair, etc. Among them, the first queue pair includes a first queue item and a second queue item. The first queue item can be a submission queue, and the second queue item can be a completion queue. The Submission Queue Number (abbreviated as sqn) is used to identify a specific submission queue. The Completion Queue Number (abbreviated as cqn) is used to identify a specific completion queue.

[0032] The attributes of the input / output queue, in addition to the first attribute, also include a doorbell register, a submission queue base address, a completion queue base address, whether the submission queue is continuous, and whether the completion queue is continuous, etc. If the value of the first attribute of a certain queue item is empty or NULL, it indicates that the queue item has not been allocated to the controller; if the value of the first attribute of a certain queue item is the controller identification information, such as the controller identifier (controller_id), it indicates that the queue item has been allocated to the controller represented by the controller identifier.

[0033] Step S302: Based on the instruction for configuring the queue items of each controller, traverse the input / output queue to determine the queue items allocated to each controller.

[0034] In this step, when the controller receives the Set Feature command, traverse the first attribute of the input / output queue. The Set Feature management command can be FID 07h in the NVMe protocol. If the first controller receives the Set Feature management command, the first controller traverses the first attribute of the input / output queue. If the first attribute of the first queue item in the input / output queue indicates that the first queue item has not been allocated, the identification information of the first queue item can be written into the controller description table of the first controller until the number of queues specified by the Set Feature management command is obtained, or all the queue items in the input / output queue have been traversed. Send the allocation situation of the input / output queue to the Host. Among them, the Set Feature command is used to configure the queue quantity, functions, or attributes, etc. of the NVMe device.

[0035] Step S303: If there are requests from multiple controllers, determine the target controller corresponding to the next request to be processed through round-robin scheduling. Among the multiple queue entries of the target controller, determine the queue entry to be processed based on the weight priority of each queue entry, and perform data processing based on the attributes of the processed queue entry.

[0036] In this step, if there are requests from multiple controllers, the round-robin scheduling algorithm (Round-Robin, abbreviated as RR) can be used to select the target controller for request processing. Then, for the multiple submit queue requests inside the target controller, arbitration is performed based on the weighted round-robin scheduling (Weighted Round-Robin, abbreviated as WRR) algorithm. Through the weighted round-robin scheduling result, determine the target submit queue request for the read command operation, and perform the corresponding data processing operation based on the target submit queue request.

[0037] In this way, the same input / output queue is allocated to multiple controllers, and each controller exclusively controls the queue entries assigned to it. By jointly allocating the same input / output queue by multiple controllers, the hardware overhead can be significantly reduced; by determining the target controller through round-robin scheduling and then processing the queue entries based on the weight priority, the complex judgment of cross-queue scheduling in the solutions of the related art is avoided, and the resource utilization rate can be improved; when multiple controllers request simultaneously, the round-robin mechanism allocates the processing right in order, and the weight priority ensures that high-priority tasks are executed first, and resource optimization can be achieved.

[0038] In some alternative embodiments, based on the instruction for configuring the queue entries of each controller, traverse the input / output queue to determine the queue entries allocated to each controller, including: after obtaining the instruction for configuring the queue entries of the target controller, traverse the first attribute of the input / output queue; if the first attribute indicates that the queue entry is in a state of not being allocated to a controller, write the identification information of the target controller into the first attribute of the queue entry; if the first attribute indicates that the queue entry has been allocated to other controllers, traverse the next queue entry based on the order of the queue entries in the input / output queue until the specified number of queue entries in the instruction is obtained or the input / output queue traversal is completed.

[0039] In this embodiment, when the host initializes the controller, the input / output queue resources are allocated to the controller by sending a set feature instruction through the management (admin) queue. It can be judged whether each queue entry in the input / output queue is allocated by traversing the value of the first attribute in the input / output queue. If the first attribute indicates that the queue entry is not allocated, the identification information of the queue entry can be written into the controller description table of the controller to be initialized, and the mapping relationship between the queue entries in the input / output queue and the controller is established until the number of management queue requests is reached or the input / output queue traversal is completed.

[0040] In the case of adding a new controller, only idle queue items need to be allocated from the input / output queue, without modifying the hardware architecture, which supports seamless expansion.

[0041] In this way, only operating on unallocated queue items can avoid repeated allocation or invalid traversal; at the same time, unallocated queue items can be dynamically allocated to any controller, which can solve the problem of idle dedicated input / output queues in related technologies; in addition, supporting the modification of the allocation policy at runtime can improve the flexibility and scalability of the system.

[0042] In some alternative embodiments, the foregoing method for data processing further includes creating a controller description table: after determining the queue items allocated to each controller, establishing the correspondence between the identified information of the allocated queue items, the identified information of the allocated controllers, and the identified information of the controller request queues; based on the correspondence, representing the controller description table.

[0043] In this embodiment, a corresponding controller description table (QueueMap) and an allocated queue item quantity register can be created for each controller. Based on the allocated queue item quantity register, the identified information and the total number of queue items allocated to the controller are recorded. The controller description table can store the identified information of the queue items or the identified information of the queue pairs.

[0044] Figure 4 The structural schematic diagram of the controller description table of multiple controllers provided by this application is shown. Figure 4 In, the method for data processing in this application is described by taking ten queue items and three controllers as examples. As Figure 4 shown, the input / output queue 400 includes a first queue item (local_sq0) 4001, a second queue item (local_sq1) 4002, a third queue item (local_sq2) 4003, a fourth queue item (local_sq3) 4004, a fifth queue item (local_sq4) 4005, a sixth queue item (local_sq5) 4006, a seventh queue item (local_sq6) 4007, an eighth queue item (local_sq7) 4008, a ninth queue item (local_sq8) 4009, and a tenth queue item (local_sq9) 4010. The system includes a first controller, a second controller, and a third controller. The first controller can be controller0, the second controller can be controller1, and the third controller can be controller3.

[0045] The queue items assigned to the first controller include the first queue item 4001, the fourth queue item 4004, the fifth queue item 4005, the sixth queue item 4006, and the seventh queue item 4007. The queue items assigned to the second controller include the second queue item 4002 and the third queue item 4003.

[0046] In response to the setting characteristic management command for the third controller issued by the host, the third controller traverses the first attribute of the input / output queue 400. The first attributes of the first queue item 4001 to the seventh queue item 4007 all indicate that the queue items have been assigned to the controller. The first attribute of the eighth queue item 4008 indicates that the eighth queue item 4008 has not been assigned, and the eighth queue item 4008 can be assigned to the third controller. Similarly, for the first attributes of the ninth queue item 4009 and the tenth queue item 4010, which indicate that the ninth queue item 4009 and the tenth queue item 4010 have not been assigned, the ninth queue item 4009 and the tenth queue item 4010 can be assigned to the third controller.

[0047] The first controller includes the first controller's first request (sq1) 4021, the first controller's second request (sq2) 4022, the first controller's third request (sq3) 4023, the first controller's fourth request (sq4) 4024, and the first controller's fifth request (sq5) 4025. The second controller includes the second controller's first request 4031 and the second controller's second request 4032. The third controller includes the third controller's first request 4041, the third controller's second request 4042, and the third controller's third request 4043.

[0048] The controller description table 402 of the first controller includes the correspondence between the first queue item 4001 and the first request 4021 of the first controller; the correspondence between the fourth queue item 4004 and the second request 4022 of the first controller. The controller description tables 403 of the second controller and 404 of the third controller are as Figure 4 shown and will not be elaborated here one by one. The input / output queue 400 can be a submission queue or a completion queue. For both the submission queue and the completion queue, the controller description table can be established according to the above method.

[0049] In this way, through the controller description table, bidirectional queries of controller identifier → queue item identifier or queue item identifier → controller identifier are supported, which can avoid repeated traversal of the global queue and significantly reduce the scheduling delay; at the same time, it is convenient to monitor the load conditions of each controller in real time and provide data support for dynamic load balancing; in addition, by uniformly managing the allocation relationship through the description table, there is no need to independently maintain the queue item allocation information in each controller, which can reduce the memory occupancy and data synchronization overhead, and further reduce the hardware overhead.

[0050] In some alternative embodiments, the attributes of the queue entries in the input / output queue further include the doorbell register address, and the foregoing method for data processing further includes: determining the address offset of the doorbell register based on the difference between the base address of the doorbell register and the doorbell register address; determining the queue entry index offset corresponding to the address offset based on the address offset; determining the queue entry index based on the queue entry index offset; and establishing a mapping relationship between the doorbell register address and the queue entry identification information based on the controller descriptor table and the queue entry index.

[0051] In this embodiment, the mapping relationship between the doorbell register address (address) and the identification of each queue entry in the input / output queue can be characterized in the following manner; Map[(address - base address of the doorbell register) / 8 - 1] Among them, the doorbell register address (address) can be allocated based on the NVMe protocol; the base address of the doorbell register can be determined separately based on different types of doorbell registers, for example, it can be 0x1000 or 0x1004. Dividing the address offset by 8 indicates that each doorbell register occupies an eight-byte address space. Subtracting one can convert the queue entry index to start from 0.

[0052] The correspondence between the sequence number and the number in the submission queue in the input / output queue of each controller on the host side is: Map[sqn - 1]. The correspondence between the sequence number and the number in the completion queue is: Map[cqn - 1]. Map is used to represent the controller descriptor table.

[0053] In the case of executing a submission queue request or a completion queue request, when a submission queue index or a completion queue index needs to be submitted, the identification information of the queue entry in the input / output queue can be obtained through the above mapping relationship, and then the configuration information of the queue entry can be obtained, so as to complete the corresponding submission queue request or completion queue request.

[0054] In this way, resources can be directly located through simple mathematical calculations without traversing and searching; at the same time, queue information can be obtained through one address calculation, which can avoid multi-level pointer references; in addition, the linear address mapping highly matches the NVMe controller hardware implementation, which can accelerate command processing.

[0055] In some alternative embodiments, the foregoing method for data processing further includes determining whether there is a request from the controller: if the positions pointed to by the head pointer and the tail pointer of the queue entry are different, and the first attribute of the queue entry indicates that the queue entry has been allocated to the target controller, it is determined that there is a request from the target controller.

[0056] In this embodiment, it is possible to determine whether there is a command read request for the controller corresponding to the queue entry based on the head and tail pointers of the queue entries in the controller descriptor and the value of the first attribute. For example, if the attributes of the head and tail pointers of the queue entry numbered local_sq1 are not equal, and the value of the first attribute of this queue entry is 1, it indicates that this queue entry has been allocated to the first controller, and the current first controller has a read command request.

[0057] Specifically, a read request signal for the controller can be generated through the controller descriptor and the head and tail pointers of the queue entries. For example, when the head and tail pointers of the second queue entry 4002 corresponding to the 0th position of the controller descriptor of the second controller (controller1) are not equal, it indicates that there is a read request for the second controller's second controller first request 4031. According to the above rules, if each controller can have a maximum of ten request signals, there are a total of 3 * 10 request signals at most.

[0058] In this way, through the double verification of the pointer status and the attribute mark, misjudgment of the controller request can be avoided; at the same time, each controller only checks the requests allocated to itself and will not interfere with other controllers. When a certain controller fails, it will not affect the system's processing of requests from other controllers.

[0059] In some alternative embodiments, if there are requests from multiple controllers, the target controller corresponding to the next request to be processed is determined through round-robin scheduling. Among the multiple queue entries of the target controller, based on the weight priorities of the queue entries, the queue entry to be processed is determined as follows: after determining the target controller, based on the number of queue entries allocated to the target controller, the weight priorities of the queue entries in the target controller, and the requests in the queue entries, the queue entry to be processed is determined.

[0060] In this embodiment, in the case where there are controller requests from multiple controllers, based on the round-robin scheduling algorithm (RR), the round-robin scheduling result can be obtained to determine the target controller for which the command is to be read. The number of queue entries allocated to the target controller, the weight priorities of the queue entries in the target controller, and the requests in the queue entries can be passed to the weighted round-robin scheduling arbitration module. The weighted round-robin scheduling arbitration module is set up to perform arbitration based on the NVMe protocol requirements and the weight priorities of the queue entries, and then determine the request for performing the read command operation and the number of read commands.

[0061] To achieve the maximum number of arbitration requests, the weighted round-robin scheduling arbitration module should be able to handle the maximum number of arbitration requests. In the case of using sequential logic arbitration, the methods in the related art need to consume the number of clock cycles of the maximum queue to traverse all requests. Since the number of queues of each controller is dynamically changing, for example, the first controller may have 250 requests, while the second controller only has 6 requests, the methods in the related art will result in a large number of meaningless traversals.

[0062] In this way, according to the round-robin scheduling result obtained by RR, the number of queue items assigned to the target controller is transmitted to the weighted round-robin scheduling arbitration module. If the number of requests to be traversed by the weighted round-robin scheduling arbitration module reaches the number of queue items assigned to the target controller, the requests are traversed again from the low serial number, reducing the time for meaningless request traversal and thus reducing the arbitration delay.

[0063] In some alternative embodiments, after determining the target controller, based on the number of queue items assigned to the target controller, the weight priorities of the queue items in the target controller, and the requests in the queue items, determining the queue items to be processed includes: based on the number of queue items, traversing the queue items of the target controller to determine whether there are requests in the queue items of the target controller; among the queue items with requests, based on the maximum request acquisition number of the target controller, the free space amount of the first first-in-first-out cache, and the number of commands to be processed in the queue item, determining the queue items to be processed.

[0064] In this embodiment, Figure 5 shows a schematic diagram of the application scenario of fetching the commit queue command provided by the present application, as Figure 5 shown, when the controller has a commit queue read request, for example, in the case where there are a first controller commit queue request 5011, a second controller commit queue request 5012, and a third controller commit queue request 5013, first, through the round-robin scheduling module 501, it is determined which controller's request signal to process.

[0065] After determining the selected target controller, among the multiple controller information, the target controller information 5017 is obtained, that is, the number of queue items assigned to the target controller, the weight priorities of the queue items in the target controller, and the requests in the queue items. Each controller information includes the number of queue items assigned, the weight priorities of the queue items in the target controller, and the requests in the queue items. The multiple controller information includes a first controller information 5014, a second controller information 5015, and a third controller information 5016.

[0066] Transmit the information of the obtained target controller to the weighted round-robin scheduling module 502. The weighted round-robin scheduling module 502 traverses each submission queue of the target controller based on the number of queue items assigned to the target controller, determines whether there is a read request signal, and performs weighted round-robin scheduling arbitration. At the same time, based on the maximum request acquisition quantity (arbitration burst, abbreviated as ab) of the target controller, the free space amount of the first first-in-first-out cache 503, and the number of commands to be processed in the queue items, determine the weighted round-robin scheduling result 5021, that is, the number of commands that should be read in this weighted round-robin scheduling arbitration.

[0067] Then, store the identification information of the target controller, the request (sqn) in the target controller, the queue items (local_sqn) assigned to the target controller, and the number of commands that should be read in this weighted round-robin scheduling arbitration into the first first-in-first-out cache 503. Update the weight consumption situation of each queue item in the target controller to the weighted round-robin scheduling weight register of the target controller. At the same time, update the pseudo-head pointer 504, which can prevent the value of the head pointer that has participated in arbitration from being reused. The pseudo-head pointer is used to represent the head pointer when the actual command has not been read from the host memory. It should be noted that only when there is free space in the first first-in-first-out cache 503, that is, when the first first-in-first-out cache 503 is not full, can round-robin scheduling be performed so that the round-robin scheduling arbitration result can be saved.

[0068] In this way, by first judging whether there is a request in the queue item and skipping the processing of the empty queue, invalid processing can be avoided; at the same time, the processing amount is dynamically adjusted based on the cache free space to prevent request loss caused by cache overflow and ensure the reliability of data processing.

[0069] In some alternative embodiments, data processing based on the attributes of the processed queue items includes: obtaining the attribute information of the queue item based on the queue item identification information in the processed queue item; reading the command information from the host memory based on the attribute information; and storing the command information, the identification information of the target controller, and the identification information of the processed queue item into the second first-in-first-out cache.

[0070] In this embodiment, as Figure 5As shown, the command acquisition module 507 is used to read the command information in the host memory. Based on the value of the processed queue item (local_sqn) obtained from the first first-in-first-out cache 503, the command acquisition module 507 determines the attribute information of the processed queue item (local_sqn), that is, among the first queue item attribute information 505, the second queue item attribute information... the tenth queue item attribute information 506, it determines the target queue item attribute information 5031. Based on the target queue item attribute information 5031, it obtains information such as the base address, size, continuity, head pointer, and tail pointer of the corresponding submission queue (SQ). Then, the command acquisition module 507 reads the command information from the specified location in the host memory according to this information. After the command information is read, the head pointer 512 is updated. The update of the head pointer indicates that the command has been read from the host, and the read command information, the identification information of the target controller, and the identification information of the processed queue item are stored in the second first-in-first-out cache 508.

[0071] When the number of the read command information reaches the quantity indicated by the first first-in-first-out cache 503, the output value of the first first-in-first-out cache 503 is updated to read the command of the next submission queue (SQ).

[0072] The processor module 509 reads the commands in the second first-in-first-out cache 508 and performs operations such as checking the command format. According to the command type, the commands are stored in the firmware read queue 510, or the command processing results are put into the hardware completion queue 511. Among them, the firmware read queue (Firmware Read Queue, abbreviated as FWRQ) 510 is used to store the commands for the firmware reading operation. The firmware refers to the software running in the solid-state drive controller, which is responsible for managing the hardware resources and executing the commands submitted by the host.

[0073] In this way, by obtaining the attribute information based on the queue item identification information and using the unique identifier, the direct positioning of the queue item attributes can be realized, avoiding traversing all the data, which can reduce the retrieval time overhead; at the same time, by directly reading the command information in the host memory based on the attribute information, the invalid memory addressing can be avoided.

[0074] In some alternative embodiments, the foregoing method for data processing further includes: if there are hardware completion queue requests, firmware completion queue requests, and direct memory access requests, perform round-robin scheduling based on the hardware completion queue requests, the controller request queue identification information corresponding to the hardware completion queue requests, the firmware completion queue requests, the controller request queue identification information corresponding to the firmware completion queue requests, the direct memory access requests, and the controller request queue identification information corresponding to the direct memory access requests to determine a target controller; determine target queue item identification information based on the target controller and the controller description table of the target controller; and based on the target queue item identification information, obtain the attribute information corresponding to the target queue item identification information and perform data writing processing.

[0075] In this embodiment, Figure 6 FIG. shows a schematic diagram of an application scenario of the write completion queue completion command provided by the present application. As Figure 6 shown, when executing the write completion queue completion command, the instruction completion module 601 performs preprocessing based on the information in the obtained hardware completion queue 511, firmware completion queue 603, and direct storage access completion queue 604, and according to the indication of the controller identification information in each of the hardware completion queue 511, firmware completion queue 603, and direct storage access completion queue 604, sends each completion queue to the third first-in-first-out buffer 605, fourth first-in-first-out buffer 606, or fifth first-in-first-out buffer 607 indicated by the controller identification information.

[0076] The round-robin scheduling arbiter 608 performs round-robin scheduling arbitration based on the contents in the third first-in-first-out buffer 605, fourth first-in-first-out buffer 606, and fifth first-in-first-out buffer 607 to determine the target controller 609 for performing the send operation. The completion command sending module 610 is configured to put the completion command into the completion queue specified by the host.

[0077] The mapping module 611, based on the identification information of the target controller 609, the completion queue identification (cqn), and the controller description table of the target controller, obtains the value of the target queue item (local_cqn), i.e., the target queue item attribute information 5031, from the first queue item attribute information 505, second queue item attribute information... tenth queue item attribute information 506. Furthermore, attribute information such as the base address, size, continuity, head pointer, and tail pointer of the completion queue to be written is obtained. The completion command sending module 610 writes the foregoing obtained attribute information into the completion queue (CQ) based on the write enable module 613 or read enable module 614.

[0078] In this way, by integrating hardware to complete queue requests, firmware complete queue requests, and direct memory access requests, and adopting a polling scheduling algorithm to determine the target controller, it is possible to avoid a single queue occupying resources for a long time and achieve fair scheduling of different types of requests. At the same time, by storing the completion queue commands and requests of different controllers in separate first-in-first-out (FIFO) caches (such as the third to fifth FIFO caches), it is possible to avoid request interference between controllers. In addition, the independent FIFO cache design provides natural fault isolation capabilities. If an exception occurs in a certain controller, it only affects its corresponding cache and does not affect other controllers.

[0079] In some alternative embodiments, the foregoing method for data processing further includes configuring a controller weight information register and recording the arbitration weight information of the controller based on the controller weight information register.

[0080] In this embodiment, since only one weighted round-robin scheduling arbiter (WRR arbiter) is set in this solution and the arbitration configurations and consumption situations of each controller are different, weight information registers can be established for each controller to record the arbitration weight consumption situations of each controller. After obtaining the previous RR arbitration result, the weight consumption situation of the WRR arbiter is dynamically configured to ensure the correct WRR arbitration weight of each controller. And after one arbitration is completed, the weight information register is updated to prevent the loss of weight information.

[0081] In this way, the weights are dynamically updated based on the real-time arbitration consumption situation of the controller to achieve adaptive scheduling. At the same time, a single WRR arbiter combined with the weight information register improves efficiency while ensuring scheduling fairness. Compared with static polling, weighted round-robin can allocate time slices according to the actual processing capabilities of the controllers. In addition, the independent configuration of the weight information register ensures that the exception of a single controller does not affect other controllers.

[0082] In some alternative embodiments, the foregoing method for data processing further includes: after polling scheduling, writing the identification information of the target controller, the queue items allocated to the target controller, the request queue of the target controller, and the number of commands into the first FIFO cache; and updating the head pointer of the processed queue items.

[0083] In this embodiment, after polling scheduling determines the target controller, the identification information of the target controller, the queue items allocated to the target controller, the request queue of the target controller, and the number of commands are extracted and written into the first FIFO cache. Then, the head pointer is updated, that is, the pseudo-head pointer 504 is updated, which can prevent the values of the head pointers that have participated in arbitration from being reused. The pseudo-head pointer is used to represent the head pointer when the actual command has not been read from the host memory.

[0084] In this way, the first FIFO cache serves as an intermediate buffer between the scheduling module and the execution module, decoupling the polling scheduling from the actual processing logic. For example, the scheduling module can continue with the next round of scheduling without waiting for the current command processing to complete. The execution module can continuously process commands in the cache order, reducing the time overhead of waiting for scheduling. This mode improves the system's concurrent processing ability, especially in high-load scenarios.

[0085] In some alternative embodiments, the aforementioned method for data processing further includes, after determining the queue item to be processed, storing the attributes of the processed queue item based on a second first-in-first-out cache.

[0086] In this embodiment, the target controller sends a host read request through the command acquisition module 507 according to the arbitration result, and stores the read command information, the identification information of the target controller, and the identification information of the processed queue item into the second first-in-first-out cache 508. Since there is a delay in reading commands, this delay may be greater than the arbitration speed. If arbitration is performed after data reading is completed, there will be a phenomenon of waiting for the arbitration result. Therefore, a second first-in-first-out module 508 is added between the arbitration and the command acquisition module to cache the arbitration result, which can reduce the latency.

[0087] The method for data processing provided by this application can be applied to a data transmission system that complies with the NVMe protocol based on the Peripheral Component Interconnect Express (PCIe) interface.

[0088] The method for data processing provided by this application addresses the situation where queue resources cannot be shared among multiple controllers and there is redundancy in logical functions. A queue resource pool (input / output queue) is established, and through a controller description table, a mapping between physical queue resources and the controller's logical queues is achieved. Furthermore, the queue sharing function of the controller is realized. At the same time, according to the characteristics of the change in the number of controller queues, the arbitration method is optimized, the arbitration cycle is shortened, and the arbitration efficiency is improved. And a FIFO mechanism is introduced to improve the arbitration efficiency and thereby reduce the latency of command acquisition.

[0089] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation.

[0090] The embodiments of this application also provide a device for data processing. Figure 7 The structural schematic diagram of the device for data processing provided by this application is shown as Figure 7As shown, the apparatus for data processing includes: A shared module 701, configured to create an input / output queue, where the attributes of the input / output queue include a first attribute, and based on the first attribute, it represents the controller to which each queue entry in the input / output queue belongs, or the queue entry is not assigned to a controller.

[0091] A configuration module 702, configured to traverse the input / output queue based on an instruction for configuring queue entries of each controller, and determine the queue entries assigned to each controller.

[0092] A processing module 703, configured to, if there are requests from multiple controllers, determine the target controller corresponding to the next request to be processed through round-robin scheduling, and among multiple queue entries of the target controller, determine the queue entry to be processed based on the weight priority of each queue entry, and perform data processing based on the attributes of the queue entry to be processed.

[0093] In some alternative embodiments, the configuration module 702 includes: A first unit of the configuration module, configured to, after obtaining an instruction for configuring queue entries of a target controller, traverse the first attribute of the input / output queue; if the first attribute represents that the queue entry is in a state of not being assigned to a controller, write the identification information of the target controller into the first attribute of the queue entry; if the first attribute represents that the queue entry has been assigned to another controller, traverse the next queue entry based on the order of queue entries in the input / output queue until the specified number of queue entries in the instruction is obtained or the input / output queue is traversed completely.

[0094] In some alternative embodiments, the foregoing apparatus for data processing further includes: A first module, configured to create a controller description table, and after determining the queue entries assigned to each controller, establish a correspondence relationship between the identification information of the assigned queue entries, the identification information of the controller to which they are assigned, and the identification information of the controller request queue; based on the correspondence relationship, represent the controller description table.

[0095] In some alternative embodiments, the foregoing apparatus for data processing further includes: A second module, configured to determine the address offset of the doorbell register based on the difference between the base address of the doorbell register and the doorbell register address; determine the queue entry index offset corresponding to the address offset based on the address offset; determine the queue entry index based on the queue entry index offset; and establish a mapping relationship between the doorbell register address and the queue entry identification information based on the controller description table and the queue entry index.

[0096] In some alternative embodiments, the foregoing apparatus for data processing further includes: The third module is used to determine whether there is a request from the controller: If the positions pointed to by the head pointer and the tail pointer of the queue item are different, and the first attribute of the queue item indicates that the queue item has been allocated to the target controller, it is determined that there is a request from the target controller.

[0097] In some alternative embodiments, the processing module 703 includes: The first unit of the processing module is used to, after determining the target controller, determine the queue item to be processed based on the number of queue items allocated to the target controller, the weight priorities of the queue items in the target controller, and the requests in each queue item.

[0098] In some alternative embodiments, the first unit of the processing module includes: The first sub-unit of the processing module is used to traverse the queue items of the target controller based on the number of queue items, and determine whether there is a request in the queue items of the target controller; among the queue items with requests, determine the queue item to be processed based on the maximum request acquisition quantity of the target controller, the free space quantity of the first first-in-first-out cache, and the number of commands to be processed in the queue item.

[0099] In some alternative embodiments, the processing module 703 further includes: The second unit of the processing module is used to obtain the attribute information of the queue item based on the queue item identification information in the queue item to be processed; based on the attribute information, read the command information from the host memory; store the command information, the identification information of the target controller, and the identification information of the queue item to be processed into the second first-in-first-out cache.

[0100] In some alternative embodiments, the aforementioned apparatus for data processing further includes: The fourth module is used to, if there are a hardware completion queue request, a firmware completion queue request, and a direct memory access request, perform round-robin scheduling based on the hardware completion queue request, the controller request queue identification information corresponding to the hardware completion queue request, the firmware completion queue request, the controller request queue identification information corresponding to the firmware completion queue request, the direct memory access request, and the controller request queue identification information corresponding to the direct memory access request to determine the target controller; determine the target queue item identification information based on the target controller and the controller description table of the target controller; obtain the attribute information corresponding to the target queue item identification information based on the target queue item identification information, and perform data writing processing.

[0101] In some alternative embodiments, the aforementioned apparatus for data processing further includes: The fifth module is used to configure the controller weight information register, and record the arbitration weight information of the controller based on the controller weight information register.

[0102] In some alternative embodiments, the aforementioned apparatus for data processing further includes: A sixth module, configured to, after polling scheduling, write the identification information of the target controller, the queue entries allocated by the target controller, the request queue of the target controller, and the number of commands into a first first-in-first-out buffer; and update the head pointer of the queue entries being processed.

[0103] In some alternative embodiments, the aforementioned apparatus for data processing further includes: A seventh module, configured to, after determining the queue entries being processed, store the attributes of the queue entries being processed based on a second first-in-first-out buffer.

[0104] For the descriptions of the features in the embodiments corresponding to the apparatus for data processing, reference may be made to the relevant descriptions in the embodiments corresponding to the method for data processing, which will not be elaborated herein one by one.

[0105] An embodiment of the present application further provides an electronic device. Figure 8 The structural schematic diagram of the electronic device provided by the present application is shown. As Figure 8 shown, it includes a processor 81 and a memory 82. A computer program is stored in the memory 82, and the processor 81 is configured to run the computer program to execute the steps in any of the above method embodiments for data processing.

[0106] The electronic device further includes an input device 83 and an output device 84. The processor 81, the memory 82, the input device 83, and the output device 84 may be connected through a bus or other means. Figure 8 Taking connection through a bus as an example.

[0107] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above method embodiments for data processing when running.

[0108] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0109] An embodiment of the present application further provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above method embodiments for data processing.

[0110] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the steps in any of the above-described method embodiments for data processing.

[0111] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0112] The above has introduced in detail a method, device, medium, and product for data processing provided by the present application. Specific examples are used herein to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for data processing, characterized in that, Including: Create an input / output queue, where the attributes of the input / output queue include a first attribute. Based on the first attribute, it represents the controller to which each queue item in the input / output queue belongs, or the queue item is not assigned to a controller. Based on the instruction to configure the queue items of each controller, traverse the input / output queue to determine the queue items assigned to each controller. If there are requests from multiple controllers, determine the target controller corresponding to the next request to be processed through round-robin scheduling. Among the multiple queue items of the target controller, based on the weight priorities of each queue item, determine the queue item to be processed, and perform data processing based on the attributes of the processed queue item.

2. The method for data processing according to claim 1, characterized in that, The step of traversing the input / output queue based on the instruction to configure the queue items of each controller to determine the queue items assigned to each controller includes: After obtaining the instruction to configure the queue items of the target controller, traverse the first attribute of the input / output queue. If the first attribute represents that the queue item is in a state of not being assigned to a controller, write the identification information of the target controller into the first attribute of the queue item. If the first attribute represents that the queue item has been assigned to another controller, traverse the next queue item based on the order of the queue items in the input / output queue until the specified number of queue items in the instruction is obtained or the input / output queue is traversed completely.

3. The method for data processing according to claim 1 or 2, characterized in that, The method further includes creating a controller description table: After determining the queue items assigned to each controller, establish the correspondence between the identification information of the assigned queue items, the identification information of the assigned controllers, and the identification information of the controller request queues. Based on the correspondence, represent the controller description table.

4. The method for data processing according to claim 3, characterized in that, The attributes of the queue items in the input / output queue further include the doorbell register address, and the method further includes: Based on the difference between the base address of the doorbell register and the doorbell register address, determine the address offset of the doorbell register. Based on the address offset, determine the queue item index offset corresponding to the address offset. Based on the queue item index offset, determine the queue item index. Based on the controller description table and the queue item index, establish the mapping relationship between the doorbell register address and the queue item identification information.

5. The method for data processing according to claim 1, characterized in that The method further includes determining whether there is a request for the controller: If the positions pointed to by the head pointer and the tail pointer of the queue item are different, and the first attribute of the queue item represents that the queue item has been assigned to the target controller, it is determined that there is a request for the target controller.

6. The method for data processing according to claim 1, characterized in that, The step of, if there are requests from multiple controllers, determining the target controller corresponding to the next request to be processed through round-robin scheduling and determining the queue item to be processed based on the weight priorities of each queue item among the multiple queue items of the target controller includes: After determining the target controller, based on the number of queue items assigned to the target controller, the weight priorities of each queue item in the target controller, and the requests in each queue item, determine the queue item to be processed.

7. The method for data processing according to claim 6, characterized in that, After determining the target controller, based on the number of queued items assigned to the target controller, the weight priorities of the queued items in the target controller, and the requests in each of the queued items, determining the queued items to be processed includes: Based on the number of queued items, traverse the queued items of the target controller to determine whether there is a request in the queued items of the target controller; Among the queued items with the request, based on the maximum request acquisition quantity of the target controller, the free space quantity of the first-in-first-out buffer, and the number of commands to be processed in the queued item, determine the queued items to be processed.

8. The method for data processing according to claim 1, wherein, The data processing based on the attributes of the queued items to be processed includes: Based on the queued item identification information in the queued items to be processed, obtain the attribute information of the queued items; Based on the attribute information, read the command information from the host memory; Store the command information, the identification information of the target controller, and the identification information of the queued items to be processed into a second first-in-first-out buffer.

9. The method for data processing according to claim 1, characterized in that It further includes: If there are hardware completion queue requests, firmware completion queue requests, and direct memory access requests, based on the hardware completion queue requests, the controller request queue identification information corresponding to the hardware completion queue requests, the firmware completion queue requests, the controller request queue identification information corresponding to the firmware completion queue requests, the direct memory access requests, and the controller request queue identification information corresponding to the direct memory access requests, perform the polling scheduling to determine the target controller; Based on the target controller and the controller description table of the target controller, determine the target queued item identification information; Based on the target queued item identification information, obtain the attribute information corresponding to the target queued item identification information, and perform data writing processing.

10. The method for data processing according to claim 1, characterized in that, The method further includes configuring a controller weight information register, and based on the controller weight information register, recording the arbitration weight information of the controller.

11. The method for data processing according to claim 1, characterized in that, The method further includes: After the polling scheduling, write the identification information of the target controller, the queued items assigned to the target controller, the request queue of the target controller, and the number of commands into a first-in-first-out buffer; Update the head pointer of the queued items to be processed.

12. The method for data processing according to claim 1, wherein The method further includes: after determining the queued items to be processed, based on a second first-in-first-out buffer, store the attributes of the queued items to be processed.

13. A computer device, characterized in that, It includes: A memory for storing a computer program; A processor for implementing the steps of the method for data processing according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the method for data processing according to any one of claims 1 to 12 when executed by a processor.

15. A computer program product, comprising a computer program, characterized in that, The computer program implements the steps of the method for data processing according to any one of claims 1 to 12 when executed by a processor.

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