Display module and display device

Abstract

The invention discloses a display module and a display device. The display module comprises a display substrate which comprises a plurality of first bonding pads arranged in the first direction, and the display substrate comprises a first edge and a second edge which are opposite to each other in the first direction; the first circuit board comprises a plurality of first connecting lines, a plurality of second bonding pads arranged in the first direction and a plurality of third bonding pads arranged in the first direction, the second bonding pads are electrically connected with the first bonding pads, one ends of the first connecting lines are connected with the second bonding pads, and the other ends of the first connecting lines are connected with the third bonding pads; the driving chip comprises a plurality of pins arranged in the first direction, and the pins are electrically connected with the third bonding pad; wherein in the direction from the first edge to the second edge, signals transmitted by the ith second bonding pad and the ith third bonding pad are different, i is larger than or equal to 1, and i is an integer. The embodiment of the invention is beneficial to reducing the manufacturing cost of the display module.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display module and a display device. Background Art

[0002] A display module generally includes a display substrate and a driving chip, and the driving chip provides signals to the display substrate.

[0003] With the continuous development of science and technology, large-sized display modules have emerged as the times require. A large-sized display substrate requires a large number of signals, and often one driving chip cannot meet the requirements, and two or more driving chips are needed.

[0004] Moreover, the arrangement orders of the signal pads on both sides of the display substrate are often different, and chips with various pin arrangement orders are required, so that molds of various driving chips need to be opened, resulting in an increase in the manufacturing cost of the display module. Summary of the Invention

[0005] Embodiments of this application provide a display module and a display device, which are beneficial to reducing the manufacturing cost of the display module.

[0006] In a first aspect, an embodiment of this application provides a display module, including: a display substrate including a plurality of first pads arranged along a first direction, the display substrate including a first edge and a second edge opposite to each other in the first direction; a first circuit board including a plurality of first connection lines, a plurality of second pads arranged along the first direction, and a plurality of third pads arranged along the first direction, the second pads being electrically connected to the first pads, one end of the first connection line being connected to the second pad, and the other end of the first connection line being connected to the third pad; a driving chip including a plurality of pins arranged along the first direction, the pins being electrically connected to the third pads; wherein, in a direction from the first edge to the second edge, the signals transmitted by the i-th second pad and the i-th third pad are different, i≥1, and i is an integer.

[0007] In a second aspect, an embodiment of this application provides a display device including the display module as described in the embodiment of the first aspect.

[0008] According to the display module and display device provided by the embodiments of the present application, the second pad of the first circuit board is electrically connected to the first pad of the display substrate, the third pad of the first circuit board is electrically connected to the pin of the driving chip, the second pad and the third pad are electrically connected by a first connection line, and in the direction from the first edge to the second edge, the signals transmitted by the i-th second pad and the i-th third pad are different; the third pad of the first circuit board accesses the signal provided by the pin of the driving chip, and the second pad of the first circuit board outputs the signal to the first pad of the display substrate; since there is at least one group of second pads and third pads in the first circuit board that have the same arrangement order but transmit different signals, in this way, the driving chip can re-arrange the output signals through the first circuit board, so that in the case of requiring multiple driving chips, it is convenient to use multiple driving chips with the same arrangement order of output signals, which is beneficial to reducing the manufacturing cost of the display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] By reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, other features, objects, and advantages of the present application will become more apparent, wherein the same or similar reference numerals represent the same or similar features, and the drawings are not drawn to actual scale.

[0010] Figure 1 Showing a schematic side structure diagram of the display module provided by the embodiments of the present application;

[0011] Figure 2 Showing a schematic diagram of pad arrangement of the display substrate provided by the embodiments of the present application;

[0012] Figure 3 Showing a schematic connection diagram of the display module provided by the embodiments of the present application;

[0013] Figure 4 Showing a schematic structure diagram of the first circuit board provided by the embodiments of the present application;

[0014] Figure 5 Showing another schematic structure diagram of the first circuit board provided by the embodiments of the present application;

[0015] Figure 6 Showing a schematic backlight surface structure diagram of the display module provided by the embodiments of the present application;

[0016] Figure 7 Showing another schematic connection diagram of the display module provided by the embodiments of the present application;

[0017] Figure 8 Showing Figure 7 A corresponding schematic signal diagram;

[0018] Figure 9Schematic diagram of another backlight surface structure of the display module provided by the embodiment of the present application;

[0019] Figure 10 Schematic diagram of another connection of the display module provided by the embodiment of the present application;

[0020] Figure 11 Shows Figure 10 Corresponding signal schematic diagram;

[0021] Figure 12 Schematic diagram of another side structure of the display module provided by the embodiment of the present application;

[0022] Figure 13 Schematic diagram of another backlight surface structure of the display module provided by the embodiment of the present application;

[0023] Figure 14 Schematic diagram of another backlight surface structure of the display module provided by the embodiment of the present application;

[0024] Figure 15 Schematic diagram of a top view structure of the display substrate provided by the embodiment of the present application;

[0025] Figure 16 Schematic diagram of another top view structure of the display substrate provided by the embodiment of the present application;

[0026] Figure 17 Schematic diagram of another top view structure of the display substrate provided by the embodiment of the present application;

[0027] Figure 18 Schematic diagram of another top view structure of the display substrate provided by the embodiment of the present application;

[0028] Figure 19 Schematic diagram of another top view structure of the display substrate provided by the embodiment of the present application;

[0029] Figure 20 Schematic diagram of a structure of the driving chip provided by the embodiment of the present application;

[0030] Figure 21 Schematic diagram of a three-dimensional structure of the display substrate provided by the embodiment of the present application;

[0031] Figure 22 Schematic diagram of a film layer structure of the display substrate provided by the embodiment of the present application;

[0032] Figure 23 Schematic diagram of a structure of the display device provided by the embodiment of the present application;

[0033] Figure 24Another structural schematic diagram of the display device provided by the embodiments of the present application is shown. Detailed implementation manners

[0034] The features of various aspects of the present application and exemplary embodiments will be described in detail below. To make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only provided to provide a better understanding of the present application by showing examples of the present application.

[0035] It should be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0036] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or this region will be "below" or "beneath" the other layer or another region.

[0037] It should be understood that the term "and / or" used herein is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally represents an "or" relationship between the associated objects before and after.

[0038] In the embodiments of the present application, the term "electrically connected" may refer to direct electrical connection between two components, or may refer to electrical connection between two components via one or more other components.

[0039] The term "connection" may refer to "electrical connection" or "electrical connection without an intermediate transistor". The term "insulation" may refer to "electrical insulation" or "electrical isolation". The term "drive" may refer to "control" or "operation". The display module may be a display device or a module / part of a display device.

[0040] Without departing from the spirit or scope of the present application, various modifications and variations can be made in the present application, which will be obvious to those skilled in the art. Therefore, the present application is intended to cover modifications and variations of the present application that fall within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0041] Embodiments of the present application provide a display module and a display device. The following will describe the embodiments of the display module and the display device with reference to the accompanying drawings.

[0042] Please refer to Figure 1 、 Figure 2 and Figure 3 , the display module 100 provided by the embodiments of the present application includes a display substrate 1, a first circuit board 2, and a driving chip 3.

[0043] The display substrate 1 includes a plurality of first pads P1 arranged along a first direction X. The display substrate 1 includes a first edge s1 and a second edge s2 opposite to each other in the first direction X. The first edge s1 and the second edge s2 extend along a second direction Y, and the first direction X and the second direction Y intersect. For example, the first direction X is the row direction, and the second direction Y is the column direction.

[0044] Exemplarily, the display substrate 1 includes a pixel circuit (not shown in the figure). At least some of the first pads P1 are electrically connected to the pixel circuit and the driving chip 3. The first pads P1 are used to transmit signals from the driving chip 3 to the pixel circuit. The display substrate 1 further includes a light-emitting element L. The light-emitting element L is electrically connected to the pixel circuit. The pixel circuit is used to drive the light-emitting element L to emit light. The light-emitting element L includes, but is not limited to, an inorganic light-emitting element (such as a Micro LED or a Mini LED, etc.) or an organic light-emitting element (such as an OLED, etc.). The first pads electrically connected to the pixel circuit are used to transmit data signals or power signals.

[0045] Exemplarily, when the display substrate 1 includes a scan driving circuit (not shown in the figure), at least part of the first pads P1 are electrically connected to the scan driving circuit and the driving chip 3. The first pads P1 are used to transmit signals from the driving chip 3 to the scan driving circuit, and the scan driving circuit is also electrically connected to the pixel circuit. The scan driving circuit is used to drive the pixel circuit. The first pads electrically connected to the scan driving circuit are used to transmit scan driving signals to drive the scan driving circuit to operate.

[0046] Exemplarily, the light-emitting element L is located on the light-emitting side of the display substrate 1, and the first circuit board 2 and the driving chip 3 are located on the backlight side of the display substrate 1. It should be noted that Figure 1 in order to clearly show the first circuit board 2 and the driving chip 3, it is schematically shown that the first circuit board 2 and the driving chip 3 are not attached to the backlight surface of the display substrate 1, which is not used to limit this application. For example, the first circuit board 2 and the driving chip 3 can be attached to the backlight surface of the display substrate 1.

[0047] The first circuit board 2 includes a plurality of first connection lines 21, a plurality of second pads P2 arranged along the first direction X, and a plurality of third pads P3 arranged along the first direction X. The second pads P2 are electrically connected to the first pads P1. One end of the first connection line 21 is connected to the second pad P2, and the other end of the first connection line 21 is connected to the third pad P3.

[0048] Exemplarily, the first circuit board 2 includes a flexible printed circuit board (FPC). Of course, in other examples, the first circuit board 2 can also be a non-flexible circuit board.

[0049] The driving chip 3 includes a plurality of pins 31 arranged along the first direction X, and the pins 31 are electrically connected to the third pads P3.

[0050] The signals output by the pins 31 of the driving chip 3 are sequentially transmitted to the first pads P1 through the third pads P3, the first connection lines 21, and the second pads P2. Then, the first pads P1 transmit the signals provided by the driving chip 3 to the pixel circuit, and the pixel circuit drives the light-emitting element L to emit light based on the signals provided by the driving chip 3.

[0051] In the direction from the first edge s1 to the second edge s2, the first second pad P2, the second second pad P2, the third second pad P2, and so on are arranged in sequence; in the direction from the first edge s1 to the second edge s2, the first third pad P3, the second third pad P3, the third third pad P3, and so on are arranged in sequence. It can be understood that among the multiple second pads P2, the first second pad P2 is closest to the first edge s1, and the last second pad P2 is closest to the second edge s2. Among the multiple third pads P3, the first third pad P3 is closest to the first edge s1, and the last third pad P3 is closest to the second edge s2.

[0052] In the direction from the first edge s1 to the second edge s2, the signals transmitted by the i-th second pad P2 and the i-th third pad P3 are different, where i≥1 and i is an integer. There are i - 1 second pads P2 between the i-th second pad P2 and the first edge s1, and there are i - 1 third pads P3 between the i-th third pad P3 and the first edge s1. The direction from the first edge s1 to the second edge s2 is parallel to the first direction X. In the drawings of this application, the direction from the first edge s1 to the second edge s2 is taken as the direction from left to right as an example.

[0053] It can be understood that among the multiple second pads P2 and the multiple third pads P3, the second pad P2 and the third pad P3 that are electrically connected to each other are the same group of pads, and there is at least one group of second pads P2 and third pads P3 with the same arrangement order but different transmitted signals.

[0054] For example, when i = 1, the first second pad P2 transmits a ground voltage signal COM, and the first third pad P3 transmits a second power supply signal PVEE.

[0055] For another example, when i = 2, the second second pad P2 transmits a scan trigger signal STV, and the second third pad P3 transmits a second power supply signal PVEE.

[0056] For another example, when i = 8, the eighth second pad P2 transmits a data signal data, and the eighth third pad P3 transmits a first power supply signal PVDD; and so on.

[0057] Among them, the voltage of the first power supply signal PVDD is greater than the voltage of the second power supply signal PVEE. For example, the first power supply signal PVDD is a positive voltage, and the second power supply signal PVEE is a negative voltage.

[0058] The second pad P2 and the third pad P3 are electrically connected through a first connection line 21. The first circuit board 2 includes multiple first connection lines 21, and at least two first connection lines 21 have overlapping portions, so that there is at least one group of second pads P2 and third pads P3 with the same arrangement order but different transmitted signals. Here, "overlapping" means that at least two first connection lines 21 overlap in the thickness direction of the first circuit board 2.

[0059] According to the display module provided by the embodiment of the present application, the second pad of the first circuit board is electrically connected to the first pad of the display substrate, the third pad of the first circuit board is electrically connected to the pin of the driving chip, the second pad and the third pad are electrically connected through a first connection line, and in the direction from the first edge to the second edge, the signals transmitted by the i-th second pad and the i-th third pad are different; the third pad of the first circuit board receives the signal provided by the pin of the driving chip, and the second pad of the first circuit board outputs the signal to the first pad of the display substrate; since there is at least one group of second pads and third pads in the first circuit board with the same arrangement order but different transmitted signals, in this way, the driving chip can re-arrange the output signals through the first circuit board, so that when multiple driving chips are required, it is convenient to use multiple driving chips with the same arrangement order of output signals, which is beneficial to reducing the manufacturing cost of the display module.

[0060] In some embodiments, in the direction from the first edge s1 to the second edge s2, the signals transmitted by the i-th first pad P1 and the i-th second pad P2 are the same, and the signals transmitted by the i-th third pad P3 and the i-th pin 31 are the same.

[0061] The i-th first pad P1 and the i-th second pad P2 are electrically connected, and the i-th third pad P3 and the i-th pin 31 are electrically connected.

[0062] Exemplarily, multiple first pads P1 and multiple second pads P2 are electrically connected in one-to-one correspondence. Specifically, the first first pad P1 and the first second pad P2 are electrically connected, the second first pad P1 and the second second pad P2 are electrically connected, the third first pad P1 and the second second pad P2 are electrically connected, and so on.

[0063] Multiple third pads P3 and multiple pins 31 are electrically connected in one-to-one correspondence. Specifically, the first third pad P3 and the first pin 31 are electrically connected, the second third pad P3 and the third pin 31 are electrically connected, the third third pad P3 and the third pin 31 are electrically connected, and so on.

[0064] Exemplarily, such as Figure 3As shown, multiple first pads P1 and multiple second pads P2 can be connected in a one-to-one correspondence, and multiple third pads P3 and multiple pins 31 can be connected in a one-to-one correspondence. For example, the third pad P3 and the pin 31 can be press-fitted. Specifically, the third pad P3 and the pin 31 can be press-fitted through anisotropic conductive film (ACF). It should be noted that Figure 3 In order to clearly illustrate the one-to-one correspondence between multiple third pads P3 and multiple pins 31, a trace is connected between the third pad P3 and the pin 31 for illustration, which is not used to limit this application.

[0065] In this example, the signals transmitted by the i-th first pad P1 and the i-th second pad P2 are the same, and the signals transmitted by the i-th third pad P3 and the i-th pin 31 are the same, which facilitates the press-fitting connection between the third pad P3 and the pin 31.

[0066] In some embodiments, in the direction from the first edge s1 to the second edge s2, the sorting of multiple second pads P2 and multiple pins 31 is the same and the transmitted signals are different.

[0067] For example, taking Figure 3 as an example, the pads and pins connected together by traces represent the pads and pins with the same transmitted signals, and the pads and pins not connected together represent the pads and pins with different transmitted signals.

[0068] For example, the first second pad P2 transmits a ground voltage signal COM, and the first third pad P3 transmits a second power supply signal PVEE; and, the second second pad P2 transmits a scan trigger signal STV, and the second third pad P3 transmits a second power supply signal PVEE; and, the eighth second pad P2 transmits a data signal data, and the eighth third pad P3 transmits a first power supply signal PVDD; and so on.

[0069] Still taking the second pads P2 and third pads P3 in which the mutually electrically connected second pads P2 and third pads P3 are in the same group of pads as an example, in this embodiment, there are multiple groups of second pads P2 and third pads P3 with the same arrangement order but different transmitted signals. In this way, it can be more convenient for the driving chip 3 to re-arrange the signals output to the display substrate through the first circuit board 2.

[0070] In some embodiments, in the direction from the first edge s1 to the second edge s2, the signals transmitted by the j-th second pad P2 and the j-th pin 31 are the same, i≠j, j≥1, and j is an integer.

[0071] Exemplarily, the j-th second pad P2 and the j-th pin 31 can be electrically connected, and the j-th second pad P2 and the j-th first pad P1 can be electrically connected.

[0072] Exemplarily, in the direction from the first edge s1 to the second edge s2, the sorting of the plurality of second pads P2 and the plurality of pins 31 is the same, but the signals transmitted are different; additionally, the sorting of the plurality of second pads P2 and the plurality of pins 31 is the same and the signals transmitted are the same.

[0073] In this embodiment, when the first circuit board 2 transmits the signal from the j-th pin 31 of the driving chip 3 to the display substrate 1, it is not necessary to rearrange the signal of the j-th pin 31; that is to say, when the first circuit board 2 transmits the signal of the driving chip 3 to the display substrate 1, the signals of some pins 31 can be rearranged, while the signals of some other pins 31 are not rearranged, thereby simplifying the complexity of signal rearrangement.

[0074] In some embodiments, the first circuit board 2 includes a plurality of metal layers disposed insulatingly, and the intersecting portions of different first connection lines 21 are disposed in different metal layers.

[0075] For the same first connection line 21, if a part of the line segment of the first connection line 21 is located in the first metal layer and another part of the line segment is located in the second metal layer, the line segments of the first connection line 21 located in different metal layers can be connected through vias.

[0076] As an example, please refer to Figure 4 , the first connection line 21 includes a first sub-connection line 211 and a second sub-connection line 212 that intersect each other. The first sub-connection line 211 includes a first segment 211a and a second segment 211b that are electrically connected to each other. The second segment 211b and the second sub-connection line 212 overlap in the thickness direction Z of the first circuit board. The first segment 211a and the second sub-connection line 212 can be located in one of the metal layers of the first circuit board, and the second segment 211b can be located in another metal layer of the first circuit board. An insulating layer is provided between different metal layers of the first circuit board.

[0077] In this embodiment, when signal rearrangement can be achieved on the first circuit board 2, crosstalk between signals of different first connection lines 21 can be avoided to ensure the accuracy of signal transmission.

[0078] In some embodiments, as Figure 1 shown, the driving chip 3 includes a display driving chip DDIC and a film 30. The display driving chip DDIC is electrically connected to the film 30, and the film 30 includes a plurality of metal layers.

[0079] Exemplarily, the driving chip 3 may adopt the Chip On Flex (COF) technology, which refers to the technology of fixing an integrated circuit (IC) on a flexible printed circuit board. The display driving integrated circuit (DDIC) is fixed on the film 30. The film 30 includes a plurality of pins 31. The display driving integrated circuit (DDIC) is used to provide data signals, and the data signals provided by the display driving integrated circuit (DDIC) are transmitted to the pins 31 through the traces in the film 30.

[0080] Exemplarily, the film 30 includes a plurality of metal layers, which facilitates the traces in the film 30 to cross lines if necessary.

[0081] In some embodiments, as Figure 5 shown, the second pad P2 is located on the first side C1 of the first circuit board 2, and the third pad P3 is located on the second side C2 of the first circuit board 2. The first side C1 and the second side C2 are opposite to each other in the thickness direction Z of the first circuit board 2.

[0082] In this example, the first circuit board 2 adopts a double-layer structure, which facilitates the traces of the first connection line 21 in the first circuit board 2 to cross lines.

[0083] In some embodiments, as Figure 6 shown, the first circuit board 2 is electrically connected to a plurality of driving chips 3. Figure 6 In the figure, the number of the driving chips 3 is two for illustration, which does not limit the present application. For example, in other examples, the number of the driving chips 3 may be 3, 4 or more.

[0084] Taking Figure 7 as an example, for any one of the driving chips 3, in the direction from the first edge s1 to the second edge s2, the first pin 31, the second pin 31, the third pin 31... are arranged in sequence. It can be understood that for any one of the driving chips 3, among the plurality of pins 31, the first pin 31 is closest to the first edge s1, and the last pin 31 is closest to the second edge s2. In the direction from the first edge s1 to the second edge s2, the signals transmitted by the k-th pins 31 in different driving chips 3 are the same, k≥1, and k is an integer. The k-th pin 31 is any one of the pins in the driving chip 3.

[0085] For example, when k = 1, the first pins 31 of different driving chips 3 all transmit the second power supply signal PVEE.

[0086] For another example, when k = 2, the second pins 31 of different driving chips 3 all transmit the second power supply signal PVEE.

[0087] For another example, when k = 8, the 8th pin 31 of different driving chips 3 all transmits the first power signal PVDD; and so on.

[0088] It can be understood that the signals transmitted by the third pads P3 respectively electrically connected to the kth pins 31 in different driving chips 3 are the same.

[0089] Exemplarily, multiple pins 31 of multiple driving chips 3 are electrically connected to multiple third pads P3 in a one-to-one correspondence. The number of pins 31 of different driving chips 3 is the same.

[0090] In some embodiments, in the direction from the first edge s1 to the second edge s2, the arrangement order of multiple pins 31 in multiple driving chips 3 is the same and the transmitted signals are the same.

[0091] For example, in each driving chip 3, the pin 31 closest to the first edge s1 is the 1st pin, the pin 31 closest to the second edge s2 is the last pin, the signals transmitted by the 1st pins 31 in different driving chips 3 are the same, the signals transmitted by the 2nd pins 31 in different driving chips 3 are the same, the signals transmitted by the 3rd pins 31 in different driving chips 3 are the same, and so on, and the signals transmitted by the last pins 31 in different driving chips 3 are the same.

[0092] As an example, as Figure 8 shown, the display module includes multiple driving chips 3 (for example, 2), and the arrangement order of multiple pins 31 in different driving chips 3 is the same and the transmitted signals are the same. In the drawings of the present application, PVDD and PVEE represent different power signals, STV1~STV3, Scan1~Scan3, and Emit1~Emit3 represent different scan driving signals, R1~Rn represent data signals for driving red light-emitting elements, G1~Gn represent data signals for driving green light-emitting elements, and B1~Bn represent data signals for driving blue light-emitting elements.

[0093] It should be noted that the specific signals transmitted by the pins 31 in each sorting of the driving chip 3 can be determined according to actual needs, and the present application does not limit this.

[0094] In this embodiment, the arrangement order of multiple pins 31 in multiple driving chips 3 is the same and the transmitted signals are the same. In this way, multiple driving chips 3 with the same structure can be directly used, without preparing driving chips with multiple signal pin arrangement orders, thereby reducing the manufacturing cost of the display module.

[0095] In some embodiments, please refer to Figure 9 and Figure 10, the display module includes a plurality of first circuit boards 2, and different first circuit boards 2 are electrically connected to different first pads P1. In the direction from the first edge s1 to the second edge s2, among different first circuit boards 2, the signals transmitted by the s-th second pad P2 are different, where s≥1 and s is an integer.

[0096] Figure 9 In the figure, the number of the first circuit boards 2 is shown as two for illustration, which is not used to limit this application. For example, in other examples, the number of the first circuit boards 2 can be 3, 4, or more.

[0097] Take Figure 10 as an example. For any one of the first circuit boards 2, in the direction from the first edge s1 to the second edge s2, the 1st second pad P2, the 2nd second pad P2, the 3rd second pad P2,... are arranged in sequence. It can be understood that for any one of the first circuit boards 2, among the multiple second pads P2, the 1st second pad P2 is closest to the first edge s1, and the last second pad P2 is closest to the second edge s2. The s-th second pad P2 is any one of the second pads in the first circuit board 2.

[0098] As an example, as Figure 11 shown, Figure 11 The same parts as Figure 8 will not be elaborated again. The differences include: Figure 11 In Figure 11 , the display module includes a plurality of first circuit boards 2 (such as 2) and a plurality of driving chips 3 (such as 2). Among different first circuit boards 2, the signals transmitted by the s-th second pad P2 are different. In addition,

[0099] Exemplarily, Figure 11 in

[0100] For a large-sized display module, more signals are required, and the number of first pads on the display substrate is relatively large. In this embodiment, the number of first circuit boards 2 is set to be multiple. In this way, for a single first circuit board 2, the width in the first direction X can be reduced. Compared with manufacturing a circuit board with a larger width, the manufacturing difficulty of a small-sized circuit board will be reduced. In addition, the signals transmitted by the s-th second pad P2 in different circuit boards are different. In this way, it is convenient for the driving chip to transmit different signals to the display substrate through multiple first circuit boards. In addition, when the size of the display substrate is fixed, setting multiple first circuit boards 2 rather than only one first circuit board 2 allows the number of second pads P2 on each first circuit board 2 to be smaller, and thus the wiring difficulty of the first circuit board 2 will also be smaller.

[0101] Exemplarily, the multiple second pads P2 and the multiple first pads P1 in the multiple first circuit boards 2 are electrically connected in one-to-one correspondence. The number of second pads P2 in different first circuit boards 2 is the same. The number of third pads P3 in different first circuit boards 2 is the same.

[0102] In some embodiments, the number of first circuit boards 2 is the same as the number of driving chips 3. For example, both the number of first circuit boards 2 and the number of driving chips 3 are 2. Or, both the number of first circuit boards 2 and the number of driving chips 3 are 3; and so on. The specific numbers of the first circuit boards 2 and the driving chips 3 can be designed according to actual requirements, and this application does not limit this.

[0103] In this embodiment, the number of first circuit boards 2 is the same as the number of driving chips 3, and the first circuit boards 2 and the driving chips 3 can be electrically connected in one-to-one correspondence, which is convenient for realizing the connection between the first circuit boards 2 and the driving chips 3.

[0104] In some embodiments, as Figures 12 to 14 shown, the display module further includes a second circuit board 4, and the second circuit board 4 is electrically connected to the driving chip 3.

[0105] Exemplarily, the second circuit board 4 includes, but is not limited to, an FPC.

[0106] Exemplarily, the driving chip 3 adopts COF technology. The driving chip 3 includes a display driving chip DDIC and a film 30. The display driving chip DDIC and the second circuit board 4 are electrically connected to different pins of the film. The display driving chip DDIC is used to provide data signals. The second circuit board 4 is used to electrically connect a timing driver and / or a power chip (not shown in the figure). The timing driver is used to provide a scan driving signal. For example, the display driving chip DDIC is used to provide Figure 6 or Figure 9 shown data signals R1~Rn, G1~Gn, B1~Bn; the timing driver is used to provide Figure 6 orFigure 9 The scanning drive signals STV1 to STV3, Scan1 to Scan3, and Emit1 to Emit3 as shown; the power supply chip is used to provide Figure 6 or Figure 9 the power supply signals PVDD and PVEE as shown.

[0107] When the thin film 30 is a flexible thin film, its texture is relatively soft and it cannot be directly connected to the timing driver and / or the power supply chip. In this embodiment, a second circuit board 4 is further provided to connect the thin film 30 to the timing driver and / or the power supply chip, which can improve the reliability of the display module.

[0108] In some embodiments, as Figure 15 shown, the first pad includes a first data pad p11, a first scan pad p12, and a first power supply pad p13. The first data pad p11 transmits data signals, the first scan pad p12 transmits scanning drive signals, and the first power supply pad p13 transmits power supply signals.

[0109] The display substrate 1 includes a bonding area BA. The bonding area BA includes a first area BA1 and a second area BA2. The first area BA1 includes the first data pad p11 and the first scan pad p12, and the second area BA2 includes the first data pad p11 and the first power supply pad p13.

[0110] Exemplarily, multiple first data pads p11 are respectively used to transmit data signals R1 to Rn, G1 to Gn, and B1 to Bn, and multiple first scan pads p12 are respectively used to transmit STV1 to STV3, Scan1 to Scan3, and Emit1 to Emit3.

[0111] Exemplarily, the display substrate includes multiple pixel circuit columns. Each pixel circuit column includes multiple pixel circuits arranged along the second direction. In a large-sized display panel, the number of pixel circuit columns is relatively large, and the number of required first data pads is also relatively large. Compared with multiple first data pads being concentrated in one area, in this embodiment, the bonding area of the display substrate includes a first area and a second area. The first data pad p11 and the first scan pad p12 are arranged in the first area BA1, and the first data pad p11 and the first power supply pad p13 are arranged in the second area BA2; in this way, both areas include the first data pad p11. Overall, the connection line between the first data pad p11 and the pixel circuit column will not be too long, which is beneficial to the design of a narrow border. In addition, if multiple first data pads P1 are concentratedly arranged and then connected to the pixel circuit column through connection lines, the lengths of the respective connection lines will vary greatly, resulting in signal unevenness and ultimately uneven brightness in the panel. In this embodiment, it is equivalent to dispersedly arranging multiple first data pads P1, which can improve the problem of uneven brightness.

[0112] As an example, it is shown that a scan driving circuit is provided on the substrate 1. The scan driving circuit is used to drive the pixel circuit, and the scan driving signal is the signal for driving the scan driving circuit. The scan driving signal includes, but is not limited to, a trigger signal STV, a clock signal CK, a high-level signal VGH, a low-level signal VGL, etc.

[0113] As another example, it is shown that no scan driving circuit is provided on the substrate 1, and the scan driving signal is the signal for directly driving the pixel circuit.

[0114] In some embodiments, in the first direction X, the first regions BA1 are provided on both sides of the second region BA2. The second region BA2 can be understood as the central pad region, and the first region BA1 can be understood as the edge pad region. The first region BA1 includes a first scan pad p12, which facilitates bilateral driving of the pixel circuits in the same row in the first direction X to improve display unevenness caused by signal delay or voltage drop.

[0115] Some examples regarding the first scan pad and the first data pad are introduced below by way of example.

[0116] In some embodiments, as Figure 15 shown, the display substrate 1 includes a scan driving circuit 5, and the scan driving circuit 5 is electrically connected to the first scan pad p12. In the second direction Y, the scan driving circuit 5 at least partially overlaps with the first region BA1, the scan driving circuit 5 does not overlap with the second region BA2, and the first direction X and the second direction Y intersect.

[0117] The first scan pad p12 is provided in the first region BA1. If the scan driving circuit 5 at least partially overlaps with the first region BA1 in the second direction Y, the first scan pad p12 can be connected to the scan driving circuit 5 in the vicinity to shorten the length of the connection trace between the first scan pad and the scan driving circuit, thereby reducing the voltage drop of the connection trace.

[0118] In some embodiments, as Figure 16 the display substrate 1 includes a first center line 11 and a second center line 12. The first center line 11 and the second center line 12 extend along the second direction Y. The width of the display substrate 1 in the first direction X is D. The distance d1 between the first center line 11 and the first edge s1 in the first direction X, and the distance d2 between the second center line 12 and the first center line 11 in the first direction X, where d1 = D / 2 and d2 = D / 4. The scan driving circuit 5 is adjacent to the second center line 12. In the second direction Y, the first region BA1 overlaps with the second center line 12, and the second region BA2 overlaps with the first center line 11.

[0119] It should be noted that the first center line 11 and the second center line 12 are located in the display area, and the first center line 11, the second center line 12 are parallel or substantially parallel to the first edge s1. The first center line 11 and the second center line 12 do not represent the actual traces on the display substrate, and can be understood as the position center lines of the virtual defined display substrate, that is, the first center line 11 and the second center line 12 are used to represent positions. The two or more parameters "equal", "equals", "=" defined in this article are not absolutely equal, and a certain error is allowed. It should be noted that the equal distances mentioned in this disclosure refer to the equal distance values within the allowable range of the error (±5%).

[0120] The display substrate 1 includes two second center lines 12, and a scanning drive circuit 5 is arranged beside each of the two second center lines 12. In the second direction Y, the first area BA1 overlaps with the second center line 12; the scanning drive circuit 5 arranged beside the second center line 12 can be connected to the first scanning pad p12 in the first area BA1 nearby.

[0121] In some embodiments, please refer to Figure 8 or Figure 11 , the first pad P1 for transmitting the data signals R1~Rn, G1~Gn, B1~Bn is the first data pad, the first pad P1 for transmitting the scanning drive signals STV1~STV3, Scan1~Scan3, Emit1~Emit3 is the first scanning pad, and the first pad P1 for transmitting the power supply signals PVDD, PVEE is the first power supply pad.

[0122] The first area BA1 includes a plurality of first data pads and a plurality of first scanning pads. In the first direction X, the plurality of first data pads and the plurality of first scanning pads in the first area BA1 are arranged crosswise.

[0123] In the first direction X, the plurality of first data pads and the plurality of first scanning pads in the first area BA1 are arranged crosswise, including but not limited to the following examples:

[0124] For example, in the first direction X, the first pads in the first area BA1 are arranged in the pattern of the first scanning pad, the first data pad, the first scanning pad, and the first data pad, that is, in the first direction X, there is a first scanning pad between every two adjacent first data pads in the first area BA1, and there is a first data pad between every two adjacent first scanning pads.

[0125] Another example is that in the first direction X, there are a plurality of first scanning pads between every two adjacent first data pads in the first area BA1, and / or there are a plurality of first data pads between every two adjacent first scanning pads.

[0126] It is understandable that there is at least one first scan pad between two adjacent first data pads in the first region BA1, and there is at least one first data pad between two adjacent first scan pads. That is to say, multiple first data pads and multiple first scan pads in the first region BA1 are arranged in a cross pattern in the first direction X.

[0127] In a large-size display panel, the number of pixel circuit columns is relatively large, and multiple pixel circuit columns are usually arranged evenly in the first direction. In this embodiment, multiple first data pads and multiple first scan pads in the first region BA1 are arranged in a cross pattern. In this way, multiple first data pads in multiple first regions can be distributed approximately evenly, and the first data pads can be connected to the pixel circuit columns nearby to shorten the length of the connection traces between the first data pads and the pixel circuit columns, thereby reducing the voltage drop of the connection traces.

[0128] In some embodiments, in the first direction, the first scan pads on the first side of the first data pads in the first region transmit the first scan driving signal, and the first scan pads on the second side of the first data pads in the first region transmit the second scan driving signal.

[0129] For example, please refer to Figure 8 or Figure 11 , the display substrate includes two first regions BA1. The first first region BA1 is located between the first edge s1 and the second region BA2. The first pads P1 that transmit data signals R1, R2..., G1, G2..., B1, B2... in the first first region BA1 are first data pads, and the first pads P1 that transmit scan driving signals STV1~STV3, Scan1~Scan3, Emit1~Emit3 in the first first region BA1 are first scan pads. For example, the scan driving signals STV1~STV3, Scan1~Scan3 are the first scan driving signals, the scan driving signals Emit1~Emit3 are the second scan driving signals. The first scan pads on the first side of the first data pads that transmit the data signals R1, R2, G1, G2, B1, B2 transmit the first scan driving signal, and the first scan pads on the first side of the first data pads that transmit the data signals R1, R2, G1, G2, B1, B2 transmit the second scan driving signal.

[0130] The second first area BA1 is located between the second edge s2 and the second area BA2. The first pads P1 in the second first area BA1 that transmit data signals Rn, Rn-1, ..., Gn, Gn-1, ..., Bn, Bn-1, ... are first data pads. The first pads P1 in the second first area BA1 that transmit scan drive signals STV1-STV3, Scan1-Scan3, and Emit1-Emit3 are first scan pads. For example, the scan drive signals STV1-STV3 and Scan1-Scan3 are first scan drive signals, the scan drive signals Emit1-Emit3 are second scan drive signals, the first scan pads on the first side of the first data pads that transmit data signals Rn, Rn-1, Gn, Gn-1, Bn, and Bn-1 transmit the first scan drive signal, and the first scan pads on the first side of the first data pads that transmit data signals Rn, Rn-1, Gn, Gn-1, Bn, and Bn-1 transmit the second scan drive signal.

[0131] In this embodiment, in the first direction, the first scan pads on both sides of the first data pad in the first area are respectively used to transmit different scan drive signals. In this way, the first scan pads for different scan drive signals required by the scan drive circuit can be separated by the first data pads to reduce mutual interference between different scan drive signals.

[0132] Exemplarily, the first scan driving signal and the second scan driving signal may be used to drive different scan driving circuits.

[0133] In some embodiments, at least one first scan pad p12 is electrically connected to different scan driving circuits 5. In other words, at least one first scan pad p12 can provide signals to multiple scan driving circuits 5. For example, the first scan pad p12 that transmits the high-level signal VGH is electrically connected to different scan driving circuits 5. For another example, the first scan pad p12 that transmits the low-level signal VGL is electrically connected to different scan driving circuits 5.

[0134] In this embodiment, at least one first scanning pad p12 is electrically connected to different scanning driving circuits 5 , and multiple scanning driving circuits 5 can share at least one first scanning pad, which can reduce the number of first scanning pads and thus simplify the structure.

[0135] In some embodiments, as Figure 17 As shown, the display substrate 1 includes a plurality of pixel circuit columns 101 arranged along a first direction X. The pixel circuit columns 101 include a plurality of pixel circuits 10 arranged along a second direction Y. The number of pixel circuit columns 101 spaced between different scan driving circuits 5 is different, and the number of first data pads p11 spaced between different first scan pads p12 is different.

[0136] Exemplarily, there may be a one-to-one electrical connection between the multiple pixel circuit columns 101 and the multiple first data pads p11.

[0137] As an example, in the case where the number of pixel circuit columns 101 between two scanning driving circuits 5 is larger, the number of first data pads p11 between the first scanning pads p12 to which these two scanning driving circuits 5 are electrically connected is larger.

[0138] In this embodiment, the number of pixel circuit columns 101 between different scanning driving circuits 5 is different, and the number of first data pads p11 between different first scanning pads p12 is also different. The arrangement rule of the multiple first scanning pads p12 and the multiple first data pads p11 in the first area can follow the arrangement rule of the multiple scanning driving circuits 5 and the multiple pixel circuit columns 101 electrically connected to the first pads in the first area. In this way, it is convenient to connect the multiple first scanning pads p12 and the multiple first scanning pads p12 respectively in the vicinity, and it is convenient to connect the multiple first data pads p11 and the multiple pixel circuit columns 101 respectively in the vicinity.

[0139] In some embodiments, as Figure 17 shown, the scanning driving circuit 5 includes a first scanning driving circuit 51 and a second scanning driving circuit 52. The first scanning pad p12 includes a first sub-scanning driving pad p121 and a second sub-scanning driving pad p122. The first scanning driving circuit 51 is electrically connected to the first sub-scanning driving pad p121, and the second scanning driving circuit 52 is electrically connected to the second sub-scanning driving pad p122.

[0140] The number of pixel circuit columns 101 between the first scanning driving circuit 51 and the second scanning driving circuit 52 is the same as the number of first data pads p11 between the first sub-scanning driving pad p121 and the second sub-scanning driving pad p122.

[0141] The first scanning driving circuit 51 and the second scanning driving circuit 52 are used to provide different scanning signals to the pixel circuit 10. For example, the pixel circuit includes a data writing transistor and a light emitting control transistor. The output end of the first scanning driving circuit 51 is electrically connected to the gate of the data writing transistor, and the output end of the second scanning driving circuit 52 is electrically connected to the gate of the light emitting control transistor.

[0142] Again, for example, at least one of the first scanning driving circuit 51 and the second scanning driving circuit 52 is used to provide a sweep signal SWEEP to the pixel circuit 10.

[0143] In other embodiments, as Figure 18As shown, in the first direction X, the display substrate 1 includes a central region Q11 and a peripheral region Q12. The pixel circuit 10 is located in the central region Q11, and the scan driving circuit 5 is located in the peripheral region Q12. Light-emitting elements L are provided in both the central region Q11 and the peripheral region Q12. The light-emitting elements L at least partially overlap with the pixel circuit 10, and the pixel circuit 10 at least partially overlaps with the scan driving circuit 5. It should be noted that Figure 18 Taking the example that scan driving circuits 5 are provided on both sides of the central region Q11, in other examples, the scan driving circuit 5 may also be provided only on one side of the central region Q11.

[0144] Some examples regarding the first scan pad and the first data pad are introduced above by way of example.

[0145] Some examples regarding the first pad in the second region are introduced below.

[0146] In some embodiments, as Figure 15 or Figure 16 shown, in the first direction X, a plurality of first power pads p13 in the second region BA2 are interspersed between a plurality of first data pads p11.

[0147] As an example, as Figure 8 or Figure 11 shown, the first pads for transmitting power signals PVDD and PVEE are the first power pads p13. The second region BA2 includes a plurality of first power pads p13 and a plurality of first data pads p11. In the first direction X, the plurality of first power pads p13 in the second region BA2 are interspersed between the plurality of first data pads p11, including but not limited to the following examples:

[0148] For example, in the first direction X, the first pads in at least a part of the second region BA2 are arranged in the pattern of first data pad, first power pad, first data pad, first power pad, that is, in the first direction X, there is a first power pad between every two adjacent first data pads in at least a part of the second region BA2, and there is a first data pad between every two adjacent first voltage pads.

[0149] For another example, in the first direction X, there is at least one first power pad between at least two adjacent first data pads in the second region BA2, and / or there are a plurality of first data pads between at least two adjacent first power pads.

[0150] It can be understood that if there is a first power pad between at least two adjacent first data pads in the second region BA2, it can be regarded as the plurality of first power pads p13 in the second region BA2 being interspersed between the plurality of first data pads p11.

[0151] In a large-sized display panel, the number of pixel circuit columns is relatively large, and multiple pixel circuit columns are usually evenly arranged in the first direction. In this embodiment, multiple first power pads p13 in the second region BA2 are interspersed between multiple first data pads p11. The multiple first power pads p13 can provide power signals to multiple pixel circuit columns at multiple positions, which is beneficial to uniformly providing power signals to the pixel circuits in the entire display region, so as to improve display uniformity.

[0152] Exemplarily, as Figure 8 or Figure 11 shown, in the first direction X, multiple first power pads p13 can be located in the central region of the second region BA2.

[0153] In some other embodiments, as Figure 19 shown, the first region BA1 may further include a first power pad p13. In this way, the first power pad p13 in the first region BA1 can also provide a power signal to the pixel circuit, so as to further improve display uniformity.

[0154] In some embodiments, as Figure 19 shown, the first power pad p13 includes a first sub-power pad p131 and a second sub-power pad p132, and the voltage transmitted by the first sub-power pad p131 is greater than the voltage transmitted by the second sub-power pad p132. For example, the first sub-power pad p131 transmits a power signal PVDD, and the second sub-power pad p132 transmits a power signal PVEE.

[0155] The number of first sub-power pads p131 in the first region BA1 is less than the number of first sub-power pads p131 in the second region BA2, and / or the number of second sub-power pads p132 in the first region BA1 is less than the number of second sub-power pads p132 in the second region BA2.

[0156] Since a first scan pad p12 also needs to be provided in the first region BA1, the number of first sub-power pads p131 in the first region BA1 is set to be less, and / or the number of second sub-power pads p132 in the first region BA1 is set to be less, so as to ensure that there is enough space to accommodate the first scan pad p12.

[0157] Some examples of the first pads in the second region are introduced above.

[0158] Some examples of the driving chip are introduced below.

[0159] In some embodiments, as Figure 20As shown, the pins of the driving chip 3 include data pins 311, scan pins 312, and power pins 313. The data pins 311 transmit data signals, the scan pins 312 transmit scan driving signals, and the power pins 313 transmit power signals. The data signals, scan driving signals, and power signals are different types of signals.

[0160] The driving chip 3 includes a third region Q3, a fourth region Q4, and a fifth region Q5. The third region Q3 includes the data pins 311, the fourth region Q4 includes the scan pins 312, and the fifth region Q5 includes the power pins 313.

[0161] Exemplarily, the third region Q3 includes a plurality of data pins 311, and the plurality of data pins 311 are respectively used to transmit data signals required by light-emitting elements of different light-emitting colors and located in different columns. The fourth region Q4 includes a plurality of scan pins 312, and the plurality of scan pins 312 are respectively used to transmit different scan driving signals. The fifth region Q5 includes a plurality of power pins 313, and the power pins 313 include pins for transmitting power signals PVDD and PVEE respectively. There may be a plurality of power pins 313 for transmitting the power signal PVDD, and / or there may be a plurality of power pins 313 for transmitting the power signal PVEE.

[0162] In this embodiment, the pins for transmitting different types of signals are respectively arranged in different regions of the driving chip, which can reduce the interference between different types of signals.

[0163] For example, please refer to Figure 20 and Figure 8 or Figure 11 , the pins 3 for transmitting data signals R1~Rn, G1~Gn, B1~Bn are data pins, the pins 3 for transmitting scan driving signals STV1~STV3, Scan1~Scan3, Emit1~Emit3 are scan pins, and the pins 3 for transmitting power signals PVDD and PVEE are power pins.

[0164] Among them, the first pad P1, the second pad P2, the third pad P3, and the pin 3 for transmitting the same signal are electrically connected to each other. Specifically, the first pad P1, the second pad P2, the third pad P3, and the pin 3 for transmitting the data signal R1 are electrically connected to each other, the first pad P1, the second pad P2, the third pad P3, and the pin 3 for transmitting the data signal R2 are electrically connected to each other, and so on, the first pad P1, the second pad P2, the third pad P3, and the pin 3 for transmitting the data signal Rn are electrically connected to each other. Similarly, the first pad P1, the second pad P2, the third pad P3, and the pin 3 for transmitting the data signal G1 are electrically connected to each other, the first pad P1, the second pad P2, the third pad P3, and the pin 3 for transmitting the data signal B1 are electrically connected to each other, the first pad P1, the second pad P2, the third pad P3, and the pin 3 for transmitting the scan driving signal STV1 are electrically connected to each other, the first pad P1, the second pad P2, the third pad P3, and the pin 3 for transmitting the power signal PVDD are electrically connected to each other; and so on.

[0165] In some embodiments, in the first direction X, the fourth region Q4 is located between the third region Q3 and the fifth region Q5.

[0166] In some embodiments, in the first direction X, the fourth region Q4 is disposed on both sides of the third region Q3, and the fifth region Q5 is disposed on both sides of the third region Q3.

[0167] Some examples of the driving chip are introduced above.

[0168] Some examples of the display substrate are introduced below.

[0169] In some embodiments, as Figure 21 shown, the display substrate 1 further includes a fourth pad P4 and a second connection line 13. The first pad P1 and the fourth pad P4 are located on opposite sides of the display substrate 1, and the second connection line 13 electrically connects the first pad P1 and the fourth pad P4.

[0170] The display substrate 1 includes a light-emitting surface b1 and a backlight surface b2, and the light-emitting surface b1 and the backlight surface b2 are opposite to each other. The light-emitting surface b1 of the display substrate 1 is its light-emitting side, and the backlight surface b2 of the display substrate 1 is its backlight side. One of the first pad P1 and the fourth pad P4 is located on the light-emitting side, and the other is located on the backlight side. The light-emitting surface b1 and the backlight surface b2 are two surfaces opposite to each other along the thickness direction of the display substrate 1, and the light-emitting surface b1 and the backlight surface b2 are connected through the side surface.

[0171] As an example, as Figure 21 shown, the first pad P1 is located on the light-emitting side of the display substrate 1, and the fourth pad P4 is located on the backlight side of the display substrate 1.

[0172] Please refer to Figure 1 andFigure 21 The first circuit board 2 and the driving chip 3 are located on the backlight side of the display substrate 1, and the second pad P2 and the fourth pad P4 on the first circuit board 2 can be press-connected. The signal provided by the driving chip 3 is transmitted to the first pad P1 through the pin 3, the third pad P3, the second pad P2, and the fourth pad P4 in sequence.

[0173] In large-sized display products, multiple display modules need to be spliced together. By adopting the design of the second connecting line, the splicing gap can be reduced, and even seamless splicing can be achieved.

[0174] Exemplarily, the connection between the light-emitting surface b1 and the side surface b3 can be chamfered to form a first transition surface b31, and the connection between the backlight surface b2 and the side surface b3 can be chamfered to form a second transition surface b32. By chamfering to form a transition surface, the second connecting line 13 will not be bent at a right angle, making the second connecting line 13 not easily fall off and improving the reliability.

[0175] In some embodiments, as Figure 22 shown, the backlight side of the display substrate includes a metal layer BM, and the fourth pad P4 is located on the metal layer BM on the backlight side of the display substrate 1.

[0176] Exemplarily, the display substrate includes a substrate Glass (the substrate includes but is not limited to a glass substrate), a buffer layer Barrier, a semiconductor layer (the material of the semiconductor layer includes but is not limited to polysilicon poly), a first metal layer M1, a capacitive metal layer Mc, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, a metal layer BM, and a gate insulating layer GI, a capacitive insulating layer IMD, an interlayer dielectric layer ILD, an insulating layer PV1, a first planarization layer PLN1, and a second planarization layer PLN2. For the stacking relationship of each film layer, refer to Figure 19 , which will not be elaborated here.

[0177] The metal layer BM is located on the side of the substrate Glass facing away from the semiconductor layer poly. Since different metal layers need to be insulated by an insulating layer, when there is only one metal layer BM on the backlight side of the display substrate, there is no need to prepare an insulating layer on the side of the substrate Glass facing away from the semiconductor layer poly; compared with the backlight side of the display panel including multiple metal layers, this embodiment can reduce the number of film layers of the display substrate, thereby simplifying the manufacturing process of the display substrate. In addition, it is precisely because there is only one metal layer on the backlight side of the display substrate that signal rearrangement cannot be directly achieved through the single metal layer on the backlight side, so a first circuit board is provided for signal rearrangement.

[0178] Exemplarily, as Figure 22 shown, the second pad P2 on the first circuit board 2 is connected to the fourth pad P4.

[0179] In some embodiments, as Figure 21 shown, multiple fourth pads P4 are arranged in the first direction X. In the direction from the first edge s1 to the second edge s2, the i-th first pad P1 is electrically connected to the i-th fourth pad P4.

[0180] For example, in the direction from the first edge s1 to the second edge s2, the 1st first pad P1, the 2nd first pad P1, the 3rd first pad P1,... are arranged in sequence. In the direction from the first edge s1 to the second edge s2, the 1st fourth pad P4, the 2nd fourth pad P4, the 3rd fourth pad P4,... are arranged in sequence. The i-th first pad P1 is any one of the first pads in the display substrate, the i-th fourth pad P4 is any one of the fourth pads in the display substrate, and the i-th first pad P1 and the i-th fourth pad P4 have the same sorting order.

[0181] Exemplarily, the number of the first pads P1 is the same as the number of the fourth pads P4. Multiple first pads P1 and multiple fourth pads P4 are electrically connected to each other one-to-one through multiple second connection lines 13. In this way, the situation where the second connection lines 13 cross can be avoided, and the manufacturing difficulty of the second connection lines 13 is reduced.

[0182] In some embodiments, multiple first pads P1 and fourth pads P4 with the same arrangement order are electrically connected to each other.

[0183] Specifically, in the direction from the first edge s1 to the second edge s2, the 1st first pad P1 and the 1st fourth pad P4 are electrically connected through the first second connection line 13, and the signals transmitted by the 1st first pad P1 and the 1st fourth pad P4 are the same; the 2nd first pad P1 and the 2nd fourth pad P4 are electrically connected through the second second connection line 13, and the signals transmitted by the 2nd first pad P1 and the 2nd fourth pad P4 are the same; the 3rd first pad P1 and the 3rd fourth pad P4 are electrically connected through the third second connection line 13, and the signals transmitted by the 3rd first pad P1 and the 3rd fourth pad P4 are the same; and so on. The last first pad P1 and the last fourth pad P4 are electrically connected through the last second connection line 13, and the signals transmitted by the last first pad P1 and the last fourth pad P4 are the same.

[0184] In this embodiment, multiple first pads P1 and fourth pads P4 with the same arrangement order are electrically connected to each other, and the signals transmitted by multiple first pads P1 and fourth pads P4 with the same arrangement order are the same. There is no need to rearrange the signals, so that multiple second connection lines 13 can occupy one metal layer.

[0185] Based on the same technical concept, the embodiment of the present application also provides a display device. As Figure 23As shown, the display device 1000 includes the display module 100 described in any of the above embodiments. The display device 1000 includes at least one display module 100.

[0186] The display device provided by the embodiments of the present application can be a mobile phone, a computer, a television, a vehicle-mounted display device, or other display devices with a display function. The present application does not make specific limitations thereto. The display device provided by the embodiments of the present application has the beneficial effects of the display module provided by the embodiments of the present application. For specific descriptions of the display module, reference can be made to the above embodiments, and details thereof will not be repeated herein.

[0187] In some embodiments, as Figure 24 shown, the display device 1000 includes a plurality of display modules 100, and at least two display modules 100 are spliced and arranged. In this embodiment, large-size display, seamless splicing, and narrow-bezel display of the display device can be achieved.

[0188] According to the embodiments of the present application as described above, these embodiments do not describe all details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display module, characterized in that, Including: A display substrate including a plurality of first pads arranged in a first direction, the display substrate including a first edge and a second edge opposite to each other in the first direction; A first circuit board including a plurality of first connection lines, a plurality of second pads arranged in the first direction, and a plurality of third pads arranged in the first direction, the second pads being electrically connected to the first pads, one end of the first connection line being connected to the second pad, and the other end of the first connection line being connected to the third pad; A driving chip including a plurality of pins arranged in the first direction, the pins being electrically connected to the third pads; Wherein, in the direction from the first edge to the second edge, the signals transmitted by the i-th second pad and the i-th third pad are different, i≥1, and i is an integer.

2. The display module according to claim 1, wherein In the direction from the first edge to the second edge, the signals transmitted by the i-th first pad and the i-th second pad are the same, and the signals transmitted by the i-th third pad and the i-th pin are the same.

3. The display module according to claim 1, wherein In the direction from the first edge to the second edge, the sorting of the plurality of second pads and the plurality of pins is the same and the signals transmitted are different.

4. The display module according to claim 1, wherein In the direction from the first edge to the second edge, the signals transmitted by the j-th second pad and the j-th pin are the same, i≠j, j≥1, and j is an integer.

5. The display module according to claim 1, wherein The first circuit board includes a plurality of metal layers provided in an insulating manner, and the intersecting portions of different first connection lines are provided in different metal layers.

6. The display module according to claim 1, wherein The second pads are located on a first side of the first circuit board, the third pads are located on a second side of the first circuit board, and the first side and the second side are opposite to each other in the thickness direction of the first circuit board.

7. The display module according to claim 1, wherein The first circuit board is electrically connected to a plurality of the driving chips, and in the direction from the first edge to the second edge, the signals transmitted by the k-th pins in different driving chips are the same, k≥1, and k is an integer.

8. The display module according to claim 7, wherein In the direction from the first edge to the second edge, among the plurality of driving chips, the arrangement order of the plurality of pins is the same and the signals transmitted are the same.

9. The display module according to claim 7, wherein, The display module includes a plurality of the first circuit boards, and different first circuit boards are electrically connected to different first pads; in the direction from the first edge to the second edge, among different first circuit boards, the signals transmitted by the s-th second pads are different, s≥1, and s is an integer.

10. The display module according to claim 9, wherein, The number of the first circuit boards is the same as the number of the driving chips.

11. The display module according to claim 1, characterized in that, The display module further includes a second circuit board, and the second circuit board is electrically connected to the driving chips.

12. The display module according to claim 1, wherein The first pads include first data pads, first scan pads, and first power pads, the first data pads transmit data signals, the first scan pads transmit scan driving signals, and the first power pads transmit power signals; The display substrate includes a bonding area, the bonding area includes a first area and a second area, the first area includes the first data pad and the first scan pad, and the second area includes the first data pad and the first power pad.

13. The display module according to claim 12, characterized in that, In the first direction, the first area is disposed on both sides of the second area.

14. The display module according to claim 12, wherein, The display substrate includes a scan driving circuit, the scan driving circuit is electrically connected to the first scan pad; in the second direction, the scan driving circuit at least partially overlaps with the first area, and the scan driving circuit does not overlap with the second area, and the first direction and the second direction intersect.

15. The display module according to claim 14, wherein The display substrate includes a first center line and a second center line, the first center line and the second center line extend along the second direction, the width of the display substrate in the first direction is D, the distance between the first center line and the first edge in the first direction is D / 2, the distance between the second center line and the first center line in the first direction is D / 4, and the scan driving circuit is adjacent to the second center line; In the second direction, the first area overlaps with the second center line, and the second area overlaps with the first center line.

16. The display module according to claim 15, wherein In the first direction, the plurality of first data pads and the plurality of first scan pads in the first area are arranged in a cross pattern.

17. The display module according to claim 16, wherein In the first direction, the first scan pad on the first side of the first data pad in the first area transmits a first scan driving signal, and the first scan pad on the second side of the first data pad in the first area transmits a second scan driving signal.

18. The display module according to claim 17, wherein At least one of the first scan pads is electrically connected to different scan driving circuits.

19. The display module according to claim 15, wherein The display substrate includes a plurality of pixel circuit columns arranged in the first direction, the number of pixel circuit columns spaced between different scan driving circuits is different, and the number of first data pads spaced between different first scan pads is different.

20. The display module according to claim 19, wherein, The scan driving circuit includes a first scan driving circuit and a second scan driving circuit, the first scan pad includes a first sub-scan driving pad and a second sub-scan driving pad, the first scan driving circuit is electrically connected to the first sub-scan driving pad, and the second scan driving circuit is electrically connected to the second sub-scan driving pad; The number of pixel circuit columns spaced between the first scan driving circuit and the second scan driving circuit is the same as the number of first data pads spaced between the first sub-scan driving pad and the second sub-scan driving pad.

21. The display module according to claim 12, wherein In the first direction, the plurality of first power pads in the second area are interspersed between the plurality of first data pads.

22. The display module according to claim 12, wherein The first area further includes the first power pad.

23. The display module according to claim 22, wherein The first power pad includes a first sub-power pad and a second sub-power pad, and the voltage transmitted by the first sub-power pad is greater than the voltage transmitted by the second sub-power pad; The number of the first sub-power pads in the first area is less than that in the second area, and / or, the number of the second sub-power pads in the first area is less than that in the second area.

24. The display module according to claim 1, wherein, The pins include data pins, scan pins and power pins. The data pins transmit data signals, the scan pins transmit scan driving signals, and the power pins transmit power signals. The driving chip includes a third area, a fourth area and a fifth area. The third area includes the data pins, the fourth area includes the scan pins, and the fifth area includes the power pins.

25. The display module according to claim 24, wherein, In the first direction, the fourth area is located between the third area and the fifth area.

26. The display module according to claim 25, wherein In the first direction, the fourth area is disposed on both sides of the third area, and the fifth area is disposed on both sides of the third area.

27. The display module according to claim 1, wherein The display substrate further includes a fourth pad and a second connection line. The first pad and the fourth pad are located on opposite sides of the display substrate, and the second connection line electrically connects the first pad and the fourth pad.

28. The display module according to claim 27, wherein, The first pad is located on the light-emitting side of the display substrate, and the fourth pad is located on the backlight side of the display substrate.

29. The display module according to claim 28, wherein The backlight side of the display substrate includes a metal layer, and the fourth pad is located on the metal layer.

30. The display module according to claim 27, wherein A plurality of the fourth pads are arranged in the first direction. In the direction from the first edge to the second edge, the i-th first pad is electrically connected to the i-th fourth pad.

31. The display module according to claim 30, wherein A plurality of the first pads and the fourth pads with the same arrangement order are electrically connected to each other.

32. A display device, characterized in that, It includes the display module according to any one of claims 1-30.

33. The display device according to claim 32, characterized in that, It includes a plurality of the display modules, and at least two of the display modules are spliced and arranged.

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