Gate driving circuit and touch sensing display device including the same

Abstract

A gate driving circuit includes: a plurality of first odd-numbered main stages configured to drive first odd-numbered gate lines of a first display block in a first display period; a plurality of second odd-numbered main stages configured to drive second odd-numbered gate lines of a second display block adjacent to the first display block in a second display period; an odd reset dummy stage configured to reset, in the first display period, a Q node included in a first lower priority operation stage that is relatively later in operation order among the plurality of first odd master stages; and an odd setting dummy stage configured to set, in the second display period, a Q node included in a first higher priority operation stage that is relatively front in an operation order among the plurality of second odd primary stages.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0013179, filed on January 29, 2024, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a gate driving circuit and a touch-sensing display device including the gate driving circuit. Background Art

[0004] The touch-sensing display device may recognize a user's touch input applied to a display panel and may execute various application functions based thereon.

[0005] The touch sensing display device time-divisionally allocates a display period for display driving and a touch period for touch sensing driving, and alternately performs the display driving and the touch sensing driving.

[0006] In this case, the touch period is arranged between adjacent display periods. The gate drive circuit only outputs scan signals during the display period and stops outputting scan signals during the touch period. Therefore, during the touch period, Q-node retention stress is applied to some stages of the gate drive circuit. In some stages, when the Q-node remains charged for a long time without being discharged due to the touch period, the Q-node retention stress applied to the pull-up element increases. This disadvantage is further exacerbated when the pull-up element is implemented as an oxide transistor. Summary of the Invention

[0007] In order to overcome the above-mentioned problems of the prior art, the present disclosure may provide a gate driving circuit and a touch sensing display device including the gate driving circuit, which can minimize or at least reduce the Q-node holding stress applied to at least some stages when performing time-sharing driving of the display period and the touch period.

[0008] In one embodiment, a gate driving circuit includes: a plurality of first odd masters configured to drive first odd gate lines of a first display block during a first display period, the plurality of first odd masters including a first plurality of first odd masters and a second plurality of first odd masters; a plurality of second odd masters configured to drive second odd gate lines of a second display block arranged after the first display block during a second display period after the first display period, the plurality of second odd masters including a first plurality of second odd masters and a second plurality of second odd masters; an odd reset dummy stage configured to reset a Q node included in each of the second plurality of first odd masters operating after the first plurality of first odd masters to a reset level during the first display period; and an odd set dummy stage configured to set a Q node included in each of the first plurality of second odd masters operating before the second plurality of second odd masters during the second display period, wherein all Q nodes of the plurality of first odd masters and all Q nodes of the plurality of second odd masters maintain the reset level during a touch period arranged between the first display period and the second display period.

[0009] In one embodiment, a touch-sensing display device includes a display panel that is divided into a first display block and a second display block, the second display block being arranged after the first display block in the display panel. The first display block includes first odd sub-pixels connected to first odd gate lines included in the display panel and first even sub-pixels connected to first even gate lines included in the display panel, and the second display block includes second odd sub-pixels connected to second odd gate lines included in the display panel and second even sub-pixels connected to second even gate lines included in the display panel; and a gate driving circuit configured to drive the first odd gate lines and the first even gate lines of the first display block and the second odd gate lines and the second even gate lines of the second display block. The gate driving circuit includes: a plurality of first odd master stages configured to drive the first odd gate lines of the first display block during a first display period, the plurality of first odd master stages including a first plurality of first odd master stages and a second plurality of first odd master stages; a plurality of second odd master stages configured to drive the second odd gate lines of the second display block during a second display period, the plurality of second odd master stages including a first plurality of second odd master stages and a second plurality of second odd master stages; an odd reset dummy stage configured to reset a Q node included in each of the second plurality of first odd master stages that operate after the first plurality of first odd master stages to a reset level during the first display period; and an odd set dummy stage configured to set a Q node included in each of the first plurality of second odd master stages that operate before the second plurality of second odd master stages during the second display period. All Q nodes of the plurality of first odd master stages and all Q nodes of the plurality of second odd master stages maintain a reset level during a touch period arranged between the first display period and the second display period, and touch of the display panel is sensed during the touch period.

[0010] In one embodiment, a touch display device includes: a display panel divided into a plurality of display blocks including a first display block, the first display block including a first sub-pixel connected to a first gate line included in the display panel and a second sub-pixel connected to a second gate line included in the display panel; and a gate driving circuit configured to drive the first gate line and the second gate line of the first display block, the gate driving circuit including: a plurality of first main stages configured to drive one gate line but not the second gate line during a first display period when an image is displayed on the display panel, the plurality of first main stages including a first plurality of first main stages and a second plurality of first main stages; and a first reset dummy stage configured to reset a Q node included in each of the second plurality of first main stages that operate after the first plurality of first main stages to a reset level during the first display period, and not to reset the Q nodes included in the first plurality of first main stages during the first display period, wherein all Q nodes of the first plurality of first main stages and all Q nodes of the second plurality of first main stages included in the plurality of first main stages have a reset level during a touch period, and touch of the display panel is sensed during the touch period, the touch period being after the first display period.

[0011] To achieve these and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a gate driving circuit includes: a plurality of first odd main stages configured to drive a first odd gate line of a first display block during a first display period; a plurality of second odd main stages configured to drive a second odd gate line of a second display block adjacent to the first display block during a second display period; an odd reset dummy stage configured to reset a Q node included in a first lower priority operation stage that is relatively late in the operation order among the plurality of first odd main stages during the first display period; and an odd set dummy stage configured to set a Q node included in a first higher priority operation stage that is relatively early in the operation order among the plurality of second odd main stages during the second display period, wherein all Q nodes of the plurality of first odd main stages and all Q nodes of the plurality of second odd main stages maintain a reset level during a touch period arranged between the first display period and the second display period. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0013] Figure 1 and Figure 2is a diagram schematically showing a touch sensing display device according to the present embodiment;

[0014] Figure 3 is a diagram showing an example of time-division driving of one frame according to the present embodiment during a display period and a touch period;

[0015] Figure 4 is a diagram showing an example of split driving a display panel as a plurality of display blocks according to the present embodiment;

[0016] Figure 5 is a diagram showing an example of performing display scanning on a display block during a display period and stopping the display scanning of the display block during a touch period;

[0017] Figure 6 is a diagram showing a configuration of a gate driving circuit for split driving a plurality of display blocks according to the present embodiment;

[0018] Figure 7 is a detailed illustration corresponding to Figure 6 a diagram of the configuration of the first gate driver for the region AR1. Figure 8 is a diagram showing corresponding to Figure 6 a diagram of the operation timing of the first gate driver for the region AR1.

[0019] Figure 9 is a detailed illustration corresponding to Figure 6 a diagram of the configuration of the second gate driver for the region AR2. Figure 10 is a diagram showing corresponding to Figure 6 a diagram of the operation timing of the second gate driver for the region AR2.

[0020] Figure 11 is a diagram showing the Q-node holding stress that causes problems in the prior art; and

[0021] Figure 12 is a diagram showing a configuration of a main stage or a dummy stage included in a gate driving circuit according to the present embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0023] The advantages, features, and methods for implementing the present disclosure will be elucidated by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is only defined by the scope of the claims.

[0024] The shapes, sizes, ratios, angles, quantities, etc. of the various embodiments disclosed in the drawings for describing the present disclosure are merely exemplary, and the present disclosure is not limited thereto. The same reference numerals always denote the same elements. Throughout the specification, the same elements are denoted by the same reference numerals. As used herein, terms such as "comprising," "having," "including," etc. indicate that other parts may be added, unless the term "only" is used. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0025] Elements in the various embodiments of the present disclosure will be construed to include a margin of error even if not explicitly stated.

[0026] When describing positional relationships, for example, when the positional relationship between two parts is described as "on," "above," "below," and "next to," one or more other parts may be provided between the two parts, unless "exactly" or "directly" is used.

[0027] It should be understood that although terms such as "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0028] In the following description, when a detailed description of related known functions or configurations is determined to unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 and Figure 2 is a diagram schematically showing a touch sensing display device 100 according to the present embodiment.

[0030] Reference Figure 1 and Figure 2, according to the touch sensing display device 100 of the present embodiment, a display function for reproducing an input image on its screen and a touch sensing function for sensing a touch input of a user can be provided.

[0031] The touch sensing display device 100 may include a display panel 110 provided with a plurality of data lines DL and a plurality of gate lines GL, a display driving circuit for driving the display panel 110, and a timing controller 140.

[0032] In terms of functions, the display driving circuit may be divided into a gate driving circuit 120 for driving the gate lines GL and a data driving circuit 130 for driving the data lines DL. The display driving circuit may be implemented as one or more integrated circuits (ICs).

[0033] The display panel 110 may include an active area AA provided with a plurality of sub-pixels SP and a non-active area NA provided outside the active area AA. Each of the plurality of touch electrodes TE may be provided in an area corresponding to the plurality of sub-pixels SP. The touch electrode TE may be referred to as a touch node.

[0034] The plurality of data lines DL and the plurality of gate lines GL may be provided in the display panel 110, and the sub-pixels SP may be provided in an area defined by intersections between the data lines DL and the gate lines GL. A plurality of touch lines TL electrically connected to the plurality of touch electrodes TE may be provided in the display panel 110.

[0035] First, the elements for display driving in the touch sensing display device 100 will be described below.

[0036] The gate driving circuit 120 may be controlled by the timing controller 140, and may sequentially output scan signals to the plurality of gate lines GL provided in the display panel 110 to control the driving timing of each of the plurality of sub-pixels SP.

[0037] The gate driving circuit 120 may include one or more gate driver integrated circuits (GDICs), and based on the driving type, the GDICs may be provided only on one side of the display panel 110 or on both sides of the display panel 110.

[0038] Each of the GDICs may be connected to bonding pads of the display panel 110 in a tape automated bonding (TAB) type or a chip on glass (COG) type. Alternatively, each GDIC may be implemented as a gate in panel (GIP) type in the panel and may be directly disposed in the display panel 110. Alternatively, each GDIC may be integrated and disposed in the display panel 110. Alternatively, each GDIC may be implemented as a chip on film (COF) type mounted on a film connected to the display panel 110.

[0039] The data driving circuit 130 may receive image data from the timing controller 140 and may convert the image data into an analog data voltage. The data driving circuit 130 may output the data voltage to the data lines DL in synchronization with the timing at which a scan signal is applied through the gate lines GL, and thus may allow the sub-pixels SP to implement brightness based on the image data.

[0040] The data driving circuit 130 may include one or more source driver integrated circuits (SDICs). Each of the SDICs may include a shift register, a latch circuit, a digital-to-analog converter (DAC), and an output buffer.

[0041] Each SDIC may be connected to bonding pads of the display panel 110 in a TAB type or a COG type. Alternatively, each SDIC may be directly disposed in the display panel 110. Alternatively, each SDIC may be integrated and disposed in the display panel 110. Alternatively, each SDIC may be implemented as a COF type. In this case, each SDIC may be mounted on a film connected to the display panel 110 and may be electrically connected to the display panel 110 through wirings of the film.

[0042] The timing controller 140 may provide various control signals to the gate driving circuit 120 and the data driving circuit 130 and may control the operation timing of the gate driving circuit 120 and the data driving circuit 130.

[0043] The timing controller 140 may be mounted on a printed circuit board (PCB) or a flexible PCB (FPCB) and may be electrically connected to the gate driving circuit 120 and the data driving circuit 130 through the PCB or the FPCB.

[0044] The timing controller 140 may allow the gate driving circuit 120 to output a scan signal based on the timing set in each frame and may allow the data driving circuit 130 to convert image data into a data voltage and output the data voltage in synchronization with the scan signal.

[0045] The timing controller 140 may receive various timing signals including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal CLK, as well as image data, from an external source (e.g., a host system).

[0046] The timing controller 140 may generate a gate control signal GCS and a data control signal DCS by using the various timing signals received from the external source, may output the gate control signal GCS to the gate driver circuit 120, and may output the data control signal DCS to the data driver circuit 130.

[0047] The gate control signal GCS may include a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE. The gate start pulse GSP may control the operation start timing of each of one or more GDICs configuring the gate driver circuit 120. The gate shift clock GSC may be a clock signal commonly input to one or more GDICs and may control the shift timing of the scan signal. The gate output enable signal GOE may control the output timing of each of one or more GDICs.

[0048] The data control signal DCS may include a source start pulse SSP, a source sampling clock SSC, and a source output enable signal SOE. The source start pulse SSP may control the data sampling start timing of each of one or more SDICs configuring the data driver circuit 130. The source sampling clock SSC may be a clock signal controlling the sampling timing of data in each SDIC. The source output enable signal SOE may control the output timing of the data driver circuit 130.

[0049] The touch sensing display device 100 may further include a power management IC that supplies various voltages or currents to the display panel 110, the gate driver circuit 120, and the data driver circuit 130, or controls the various voltages or currents to be supplied.

[0050] Elements for touch sensing driving in the touch sensing display device 100 will be described.

[0051] The touch sensing display device 100 may include a touch screen panel in which a plurality of touch electrodes TE are provided for touch sensing, and a touch circuit 200 that drives and senses the touch screen panel.

[0052] The touch screen panel may be an external type, in which the touch screen panel is manufactured independently of the display panel 110 and bonded to the display panel 110, or may be an internal type, in which the touch screen panel is manufactured together during the manufacturing process of the display panel 110 and disposed in the display panel 110. In the touch sensing display device 100 according to the present embodiment, the touch screen panel may be an independent panel including a touch sensing function, or may represent the display panel 110 having all touch sensing functions and display functions. Hereinafter, as an example, the internal type in which the touch screen panel is in the display panel 110 will be described.

[0053] The touch circuit 200 may drive and sense a plurality of touch electrodes TE disposed in the display panel 100. The touch circuit 200 may provide a touch driving signal to the touch electrodes TE, may receive and accumulate touch sensing signals from the touch electrodes TE, and may detect touch coordinates and the presence or absence of a touch based on the touch sensing accumulated signal. The touch circuit 200 may be implemented as one element or two or more elements (e.g., an IC), and may be implemented independently of the display driving circuit. In addition, all or part of the touch circuit 200 may be integrated and implemented in the display driving circuit or may be an internal circuit of the display driving circuit. For example, a part of the touch circuit 200 may be implemented as an IC together with the data driving circuit 130.

[0054] The touch electrode TE may be an electrode provided by dividing a common electrode for display driving. In this case, the touch electrode TE may perform the function of an electrode for touch sensing and the function of an electrode for display sensing.

[0055] The touch circuit 200 may provide a touch driving signal to the touch electrodes TE in a touch period that is temporally different from the display driving period to perform touch sensing.

[0056] Figure 3 is a diagram showing an example of time-division driving of one frame according to the present embodiment in the display period and the touch period.

[0057] Reference Figure 3 , in the touch sensing display device according to the present embodiment, one frame period may include a plurality of display periods D and a plurality of touch periods T. The display period D may correspond to the high period H of the touch synchronization signal SYNC, and the touch period T may correspond to the low period L of the touch synchronization signal SYNC. In response to the touch synchronization signal SYNC in which the high period H and the low period L alternate, the display period D and the touch period T may be alternately arranged in one frame.

[0058] The display driving ① can be executed during the display period D, and the touch sensing driving ② can be executed during the touch period T. In one frame, the start timing of the touch sensing driving ② can be ΔT later than the start timing of the display driving ①.

[0059] Some of the multiple horizontal blanking periods can be used as the touch period T. During the horizontal blanking period, the display scanning operation and the writing operation of the image data based thereon can be not executed and stopped. During the horizontal blanking period, the data enable signal can not swing between the high level and the low level and can be maintained at the low level.

[0060] The touch sensing display device according to the present embodiment can sense a touch input based on a user's finger or stylus during the touch period T. As described above, the touch sensing display device according to the present embodiment can sense a user's touch input through the touch period T that is temporally distinguished from the display period D in one frame period. Therefore, the touch sensing driving can be executed in the middle of the display image.

[0061] Figure 4 FIG. is an example showing the split driving of the display panel according to the present embodiment as a plurality of display blocks. Figure 5 FIG. is an example showing the execution of display scanning for the display block during the display period and the stop of the display scanning of the display block during the touch period.

[0062] Reference Figure 4 , the display panel 110 according to the present embodiment can be split-driven as a plurality of display blocks LHB1 to LBHj. For the plurality of display blocks LHB1 to LBHj, the display driving ① can be executed, and then the touch sensing driving ② can be executed. Regarding the plurality of display blocks LHB1 to LBHj, the display driving ① and the touch sensing driving ② can be alternated with a time difference equal to ΔT.

[0063] The touch sensing driving ② can be executed for LHB1 while the display driving ① is executed for LHB2, the touch sensing driving ② can be executed for LHB2 while the display driving ① is executed for LHB3, and the touch sensing driving ② can be executed for LHBj-1 while the display driving ① is executed for LHBj.

[0064] The display scanning operation (GIP operation) can be executed during the display period X as Figure 5 shown, and can not be executed during the touch period Y. That is, the display scanning operation can be stopped during the touch period Y (GIP hold).

[0065] The display scanning operation can be performed by Figure 1The gate driving circuit 120 performs. The gate driving circuit 120 can output a scan signal to the gate lines during the display period X. In addition, the gate driving circuit 120 can stop outputting the scan signal to the gate lines during the touch period Y. Therefore, the gate driving circuit 120 does not output a scan signal to the gate lines during the touch period Y.

[0066] Since the output of the scan signal to the gate lines is stopped during the touch period Y, Q-node holding stress is applied to some stages of the gate driving circuit 120 during the touch period Y.

[0067] Embodiments of the present disclosure described below can provide a method for minimizing or at least reducing Q-node holding stress applied to at least some stages of the gate driving circuit 120 when performing time-division driving of the display period X and the touch period Y.

[0068] Figure 6 is a diagram showing a configuration of a gate driving circuit for driving a plurality of display blocks LHB1 to LHB8 in a divided manner according to the present embodiment.

[0069] Reference Figure 6 , the gate driving circuit 120 according to the present embodiment may include a first gate driver 120A provided on the left side (e.g., the first side) of the display blocks LHB1 to LHB8 and a second gate driver 120B provided on the right side (e.g., the second side) of the display blocks LHB1 to LHB8.

[0070] The first gate driver 120A and the second gate driver 120B may drive the display blocks LHB1 to LHB8 in an interleaved manner.

[0071] Regarding the eight display blocks LHB1 to LHB8, eight display periods and eight touch periods may be allocated. In this case, the display periods and the touch periods may be alternately arranged one by one.

[0072] The first gate driver 120A may include eight odd main blocks LBK1 to LBK8 and eight odd dummy blocks LDM1 to LDM8 to drive the odd gate lines OL included in the eight display blocks LHB1 to LHB8.

[0073] The eight odd main blocks LBK1 to LBK8 and the eight odd dummy blocks LDM1 to LDM8 may be provided in the left GIP region of the display blocks LHB1 to LHB8. In the left GIP region, one of the eight odd main blocks LBK1 to LBK8 and one of the eight odd dummy blocks LDM1 to LDM8 may be alternately arranged. Therefore, at least one odd dummy block LDM is between a pair of odd main blocks LBK in the first gate driver 120A.

[0074] The eight odd main blocks LBK1 to LBK8 may include operation levels equal in number to the number of odd gate lines OL included in the eight display blocks LHB1 to LHB8.

[0075] One or more odd reset dummy levels and one or more odd set dummy levels may be included in each of the eight odd dummy blocks LDM1 to LDM8.

[0076] The odd reset dummy levels included in the eight odd dummy blocks LDM1 to LDM8 may allow all Q nodes of the eight odd main blocks LBK1 to LBK8 to be maintained at a reset level during a touch period. Accordingly, the odd reset dummy levels reset or change the voltage of the Q nodes to the reset level during the touch period.

[0077] To this end, the output of the odd reset dummy level of the odd dummy block LDM1 may reset the Q nodes included in the lower-priority operation levels included in the odd main block LBK1, the output of the odd reset dummy level of the odd dummy block LDM2 may reset the Q nodes included in the lower-priority operation levels included in the odd main block LBK2, and the output of the odd reset dummy level of the odd dummy block LDM3 may reset the Q nodes included in the lower-priority operation levels included in the odd main block LBK3. Similarly, the output of the odd reset dummy level of the odd dummy block LDM8 may reset the Q nodes included in the lower-priority operation levels included in the odd main block LBK8. In one embodiment, "priority" refers to the arrangement of operation levels. For example, the "low-priority" operation level in the odd main block LBK refers to the low-priority operation level being arranged after other operation levels in the odd main block LBK. Due to such an arrangement, the lower-priority operation levels operate (e.g., output their respective scan signals) after the higher-priority operation levels operate.

[0078] The Q nodes of the odd reset dummy levels may be reset by one of the external odd reset signals RST1(L) to RST8(L).

[0079] In addition, the outputs of the odd-set dummy levels of the odd dummy blocks LDM1 can set the Q nodes included in the higher-priority operation levels included in the odd main block LBK2 to a predetermined voltage, the outputs of the odd-set dummy levels of the odd dummy blocks LDM2 can set the Q nodes included in the higher-priority operation levels included in the odd main block LBK3 to a predetermined voltage, and the outputs of the odd-set dummy levels of the odd dummy blocks LDM3 can set the Q nodes included in the higher-priority operation levels included in the odd main block LBK4 to a predetermined voltage. Similarly, the outputs of the odd-set dummy levels of the odd dummy blocks LDM7 can set the Q nodes included in the higher-priority operation levels included in the odd main block LBK8 to a predetermined voltage. In one embodiment, the "higher-priority" operation level refers to, for example, arranging the operation levels before the lower-priority operation levels within the odd main block LBK. Due to this arrangement, the higher-priority operation levels operate (e.g., output their respective scan signals) before the lower-priority operation levels operate.

[0080] The Q nodes of the odd-set dummy levels can be set by one of the external odd-set signals VST1(L)-VST8(L).

[0081] In addition, the second gate driver 120B can include eight even main blocks RBK1 to RBK8 and eight even dummy blocks RDM1 to RDM8 to drive the even gate lines EL included in the eight display blocks LHB1 to LHB8.

[0082] The eight even main blocks RBK1 to RBK8 and the eight even dummy blocks RDM1 to RDM8 can be provided in the right GIP region of the display blocks LHB1 to LHB8. In the right GIP region, one of the eight even main blocks RBK1 to RBK8 and one of the eight even dummy blocks RDM1 to RDM8 can be alternately arranged. Therefore, at least one even dummy block RDM is between a pair of even main blocks RBK in the second gate driver 120B.

[0083] The eight even main blocks RBK1 to RBK8 can include the same number of operation levels as the number of even gate lines EL included in the eight display blocks LHB1 to LHB8.

[0084] One or more even reset dummy levels and one or more even set dummy levels can be included in each of the eight even dummy blocks RDM1 to RDM8.

[0085] The even reset dummy levels included in the eight even dummy blocks RDM1 to RDM8 can allow all the Q nodes of the eight even main blocks RBK1 to RBK8 to be maintained at the reset level during the touch period. Therefore, the even reset dummy levels reset or change the voltage of the Q nodes to the reset level during the touch period.

[0086] Accordingly, the output of the even reset dummy stage of the even dummy block RDM1 can reset the Q nodes included in the lower priority operation stage included in the even main block RBK1, the output of the even reset dummy stage of the even dummy block RDM2 can reset the Q nodes included in the lower priority operation stage included in the even main block RBK2, and the output of the even reset dummy stage of the even dummy block RDM3 can reset the Q nodes included in the lower priority operation stage included in the even main block RBK3. Similarly, the output of the even reset dummy stage of the even dummy block RDM8 can reset the Q nodes included in the lower priority operation stage included in the even main block RBK8. As described above, "priority" refers to the arrangement of operation stages. For example, the "low priority" operation stage refers to the arrangement of the operation stages with lower priority among the operation stages included in the even main block RBK.

[0087] The Q nodes of the even reset dummy stage can be reset by one of the external even reset signals RST1(R) to RST8(R).

[0088] In addition, the output of the even setting dummy stage of the even dummy block RDM1 can set the Q nodes included in the higher priority operation stage included in the even main block RBK2 to a predetermined voltage, the output of the even setting dummy stage of the even dummy block RDM2 can set the Q nodes included in the higher priority operation stage included in the even main block RBK3 to a predetermined voltage, and the output of the even setting dummy stage of the even dummy block RDM3 can set the Q nodes included in the higher priority operation stage included in the even main block RBK4 to a predetermined voltage. Similarly, the output of the even setting dummy stage of the even dummy block RDM7 can set the Q nodes included in the higher priority operation stage included in the even main block RBK8 to a predetermined voltage. In one embodiment, the "higher priority" operation stage means that in the even virtual block RDK, the higher priority operation stage is arranged before other operation stages.

[0089] The Q nodes of the even setting dummy stage can be set by one of the external even setting signals VST1(R)-VST8(R).

[0090] Figure 7 is a diagram showing in detail the configuration of the first gate driver 120A corresponding to Figure 6 the region AR1 according to one embodiment. Figure 8 is a diagram showing the operation timing of the first gate driver 120A corresponding to Figure 6 the region AR1 according to one embodiment.

[0091] Refer to Figure 6 、 Figure 7 and Figure 8, the first gate driver 120A according to the present embodiment may include a plurality of first odd main stages LBK1 for driving the first odd gate lines OL of the first display block LHB1 during a first display period, a plurality of second odd main stages LBK2 for driving the second odd gate lines OL of the second display block LHB2 adjacent to the first display block LHB1 during a second display period, odd reset dummy stages RST-DMY1 and RST-DMY3 for resetting the Q nodes included in the lower-priority operation levels MGIP 147 and MGIP 149 of the first odd main stage LBK1 during the first display period without resetting the Q nodes included in the high-priority operation levels, and odd set dummy stages ST-DMY1 and ST-DMY3 for setting the Q nodes included in the higher-priority operation level MGIP 151 of the second odd main stage LBK2 during the second display period without setting the Q nodes included in the lower-priority operation levels.

[0092] In one embodiment, each main stage includes a first plurality of main stages and a second plurality of main stages. The second plurality of main stages operate (e.g., output their respective scan signals) after the first plurality of main stages operate. In one embodiment, the second plurality of main stages are arranged after the first plurality of main stages. For example, in Figure 7 , the operation levels MGIP 147 and MGIP 149 are the last operation levels in the first odd main stage LBK1 and are regarded as lower-priority operation levels, while the operation levels arranged before the operation levels MGIP 147 and MGIP 149 in the first odd main stage LBK1 are regarded as higher-priority operation levels because these operation levels operate before the operation levels MGIP 147 and MGIP 149.

[0093] All the odd reset dummy stages RST-DMY1 and RST-DMY3 and the odd set dummy stages ST-DMY1 and ST-DMY3 may not be connected to the first odd gate lines OL of the first display block LHB1 and the second odd gate lines OL of the second display block LHB2.

[0094] Based on the output RST-CRY1 of the odd reset dummy stage RST-DMY1, the voltage of the Q node included in the lower-priority operation level MGIP 147 of the first odd main stage LBK1 may be reset to the low-level voltage VSS at the first timing T1 during the first display period.

[0095] Based on the output RST-CRY3 of the odd reset dummy stage RST-DMY3, the voltage of the Q node included in the lower-priority operation level MGIP 149 of the first odd main stage LBK1 may be reset to the low-level voltage VSS at the second timing T2 during the first display period.

[0096] Therefore, during the touch period, all Q-nodes of the first odd master stage LBK1 and all Q-nodes of the second odd master stage LBK2 can be maintained at the reset level of the low-level voltage VSS. Therefore, the Q-node holding stress that causes the problems of the prior art can be minimized.

[0097] Figure 11 The Q-node holding stress that causes the problems of the prior art is shown. Refer to Figure 11 , in the Q-nodes Q147, Q149, and Q151 of some stages of the gate driving circuit, since the Q-nodes are not reset and are maintained in the set state during the touch period, the output characteristics may change due to the deterioration deviation between the pull-up elements connected to the Q-nodes.

[0098] According to the present embodiment, during the first display period before the touch period, all Q-nodes of the first odd master stage LBK1 and all Q-nodes of the second odd master stage LBK2 can be reset. Therefore, the problems of the prior art can be solved.

[0099] Based on the external odd reset signal RST1(L), the voltage of the Q-nodes included in each of the odd reset dummy stages RST-DMY1 and RST-DMY3 can be reset to the low-level voltage VSS at the third timing T3 of the first display period. At this time, the external odd reset signal RST1(L) can be synchronized with the start timing of the touch period.

[0100] Based on the external odd set signal VST2(L), the voltage of the Q-nodes included in each of the odd set dummy stages ST-DMY1 and ST-DMY3 can be reset to the high-level voltage VDD at the fourth timing T4 of the touch period. At this time, the external odd set signal VST2(L) can be synchronized with the end timing of the touch period.

[0101] Based on the outputs ST-CRY1 and ST-CRY3 of the odd set dummy stages ST-DMY1 and ST-DMY2, the voltage of the Q-nodes included in the higher-priority operation stage MGIP 151 of the second odd master stage LBK2 can be set to the high-level voltage VDD at the fifth timing T5 of the second display period.

[0102] In Figure 8 , GOUT147 represents the output of the operation stage MGIP 147, GOUT149 represents the output of the operation stage MGIP 149, GOUT151 represents the output of the operation stage MGIP 151, and GOUT153 represents the output of the operation stage MGIP 153.

[0103] Figure 9 is a detailed illustration corresponding to one embodiment Figure 6A diagram of the configuration of the second gate driver 120B for the region AR2. Figure 10 is a diagram showing the operation timing of the second gate driver 120B corresponding to Figure 6 the region AR2 according to one embodiment.

[0104] Refer to Figure 6 、 Figure 9 and Figure 10 , the second gate driver 120B according to the present embodiment may include a plurality of first even master stages RBK1 for driving the first even gate lines EL of the first display block LHB1 in the first display period, a plurality of second even master stages RBK2 for driving the second even gate lines EL of the second display block LHB2 adjacent to the first display block LHB1 in the second display period, an even reset dummy stage RST-DMY2 and RST-DMY4 included in the lower priority operation stages MGIP 148 and MGIP 150 for resetting the Q nodes included in the first even master stage RBK1 in the first display period, and an even set dummy stage ST-DMY2 and ST-DMY4 included in the higher priority operation stage MGIP 152 for setting the Q nodes included in the second even master stage RBK2 in the second display period.

[0105] All the even reset dummy stages RST-DMY2 and RST-DMY4 and the even set dummy stages ST-DMY2 and ST-DMY4 may not be connected to the first even gate lines EL of the first display block LHB1 and the second even gate lines EL of the second display block LHB2.

[0106] Based on the output RST-CRY2 of the even reset dummy stage RST-DMY2, the voltage of the Q node included in the lower priority operation stage MGIP 148 of the first even master stage RBK1 may be reset to the low level voltage VSS at the first timing T1' in the first display period.

[0107] Based on the output RST-CRY4 of the even reset dummy stage RST-DMY4, the voltage of the Q node included in the lower priority operation stage MGIP 150 of the first even master stage RBK1 may be reset to the low level voltage VSS at the second timing T2' in the first display period.

[0108] Therefore, during the touch period, all the Q nodes of the first even master stage RBK1 and all the Q nodes of the second even master stage RBK2 may be maintained at the reset level with the low level voltage VSS, and thus, the Q node holding stress causing the problems of the prior art may be minimized.

[0109] Based on an external even reset signal RST1(R), the voltages of the Q nodes included in each of the even reset dummy levels RST-DMY2 and RST-DMY2 can be reset to a low-level voltage VSS at the third timing T3' of the first display period. At this time, the external even reset signal RST1(R) can be synchronized with the start timing of the touch period.

[0110] Based on an external even setting signal VST2(R), the voltages of the Q nodes included in each of the even setting dummy levels ST-DMY2 and ST-DMY4 can be reset to a high-level voltage VDD at the fourth timing T4' of the touch period. At this time, the external even setting signal VST2(R) can be synchronized with the end timing of the touch period.

[0111] Based on the outputs ST-CRY2 and ST-CRY4 of the even setting dummy levels ST-DMY2 and ST-DMY4, the voltage of the Q node included in the higher priority operation level MGIP 152 of the second even main level RBK2 can be set to the high-level voltage VDD at the fifth timing T5' of the second display period.

[0112] In Figure 10 GOUT148 represents the output of the operation level MGIP 148, GOUT150 represents the output of the operation level MGIP 150, GOUT152 represents the output of the operation level MGIP 152, and GOUT154 represents the output of the operation level MGIP 154.

[0113] Figure 12 is a diagram showing the configuration of the main level (or dummy level) included in the gate driving circuit according to the present embodiment. The above main level and dummy level can be designed to be equivalent to Figure 12 .

[0114] Refer to Figure 12 , the main level included in the gate driving circuit according to the present embodiment may include a plurality of transistors and at least one capacitor. Each transistor is shown as a single transistor type in which one transistor is provided, and according to circumstances, may be configured as a dual transistor type in which two or more transistors are connected to each other. Each transistor can be implemented using an oxide semiconductor.

[0115] The main level may include a pull-up transistor T6 and a pull-down transistor T7 that control the output of a scan signal GOUT(N) synchronized with the current stage clock signal CLK(N). The main level may include a pull-up transistor T6c and a pull-down transistor T7c that control the output of the current stage carry signal CRY(N) synchronized with the current stage clock signal CLK(N).

[0116] The master stage may include a capacitor CB connected between the Q node and the scan output node.

[0117] The master stage may include a transistor T1 that turns on based on a previous stage carry signal CRY(N - 2) output from the previous stage and sets the voltage of the Q node.

[0118] The master stage may include a transistor T3 that turns on based on the voltage of the QB node and resets the voltage of the Q node.

[0119] The master stage may include a transistor T4 that applies a high-level voltage VDD to the QB node.

[0120] The master stage may include a transistor T5c that turns on based on the previous stage carry signal CRY(N - 2) and applies a low-level voltage VSS to the QB node.

[0121] The master stage may include a transistor T5q that turns on based on the voltage of the Q node and applies a low-level voltage VSS to the QB node.

[0122] The master stage may include a transistor T3n that turns on based on a subsequent stage carry signal CRY(N + 4) output from the subsequent stage and resets the voltage of the Q node.

[0123] The master stage may include a transistor T3no that turns on based on the subsequent stage carry signal CRY CRY(N + 4) and applies a low-level voltage VGL to the scan output node.

[0124] The present embodiment can achieve the following effects.

[0125] When performing time-division driving of the display period and the touch period, the present embodiment can minimize the Q node holding stress applied to at least some stages, thereby reducing the output deviation between the stages.

[0126] The effects according to the present disclosure are not limited to the above examples, and various other effects may be included in this specification.

[0127] Although the present disclosure has been specifically shown and described with reference to exemplary embodiments of the present disclosure, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure defined by the appended claims.

Claims

1. A gate driving circuit, comprising: A plurality of first odd masters configured to drive first odd gate lines of a first display block during a first display period, the plurality of first odd masters including a first plurality of first odd masters and a second plurality of first odd masters; A plurality of second odd masters configured to drive second odd gate lines of a second display block arranged after the first display block during a second display period after the first display period, the plurality of second odd masters including a first plurality of second odd masters and a second plurality of second odd masters; An odd reset dummy stage configured to reset a Q node included in each of the second plurality of first odd masters operating after the first plurality of first odd masters to a reset level during the first display period; And An odd set dummy stage configured to set a Q node included in each of the first plurality of second odd masters operating before the second plurality of second odd masters during the second display period, Wherein all Q nodes of the plurality of first odd masters and all Q nodes of the plurality of second odd masters maintain the reset level during a touch period arranged between the first display period and the second display period.

2. The gate driving circuit according to claim 1, wherein the odd reset dummy stage and the odd set dummy stage are not connected to the first odd gate lines and the second odd gate lines.

3. The gate driving circuit according to claim 1, wherein Q nodes included in the odd reset dummy stage are reset based on an external odd reset signal, and Q nodes included in the odd set dummy stage are set based on an external odd set signal, and Wherein the external odd reset signal is synchronized with a start timing of the touch period, and the external odd set signal is synchronized with an end timing of the touch period.

4. The gate driving circuit according to claim 1, further comprising: A plurality of first even masters configured to drive first even gate lines of the first display block during the first display period, the plurality of first even masters including a first plurality of first even masters and a second plurality of first even masters; A plurality of second even masters configured to drive second even gate lines of the second display block during the second display period, the plurality of second even masters including a first plurality of second even masters and a second plurality of second even masters; An even reset dummy stage configured to reset a Q node included in each of the second plurality of first even masters operating after the first plurality of first even masters to the reset level during the first display period; And An even-setting dummy stage configured to set Q nodes included in each of the first plurality of second even main stages that operate before the second plurality of second even main stages during the second display period. All Q nodes of the plurality of first even main stages and all Q nodes of the plurality of second even main stages maintain the reset level during the touch period arranged between the first display period and the second display period.

5. The gate driving circuit according to claim 4, wherein the even-reset dummy stage and the even-setting dummy stage are not connected to the first even gate line and the second even gate line.

6. The gate driving circuit according to claim 4, wherein Q nodes included in the even-reset dummy stage are reset based on an external even-reset signal, and Q nodes included in the even-setting dummy stage are set based on an external even-setting signal, and wherein the external even-reset signal is synchronized with the start timing of the touch period, and the external even-setting signal is synchronized with the end timing of the touch period.

7. A touch-sensing display device, comprising: A display panel divided into a first display block and a second display block, the second display block being arranged after the first display block in the display panel, the first display block including first odd sub-pixels connected to first odd gate lines included in the display panel and first even sub-pixels connected to first even gate lines included in the display panel, and the second display block including second odd sub-pixels connected to second odd gate lines included in the display panel and second even sub-pixels connected to second even gate lines included in the display panel; And A gate driving circuit configured to drive the first odd gate lines and first even gate lines of the first display block and the second odd gate lines and the second even gate lines of the second display block, wherein the gate driving circuit includes: A plurality of first odd main stages configured to drive the first odd gate lines of the first display block during a first display period, the plurality of first odd main stages including a first plurality of first odd main stages and a second plurality of first odd main stages; A plurality of second odd main stages configured to drive the second odd gate lines of the second display block during a second display period, the plurality of second odd main stages including a first plurality of second odd main stages and a second plurality of second odd main stages; An odd-reset dummy stage configured to reset Q nodes included in each of the second plurality of first odd main stages that operate after the first plurality of first odd main stages to a reset level during the first display period; and an odd-numbered setup dummy stage configured to, during the second display period, set a Q node included in each of the first plurality of second odd-numbered main stages that operates before the second plurality of second odd-numbered main stages, and a Q node included in a first higher priority operation stage that is relatively earlier in the operation order among the plurality of second odd-numbered main stages, All Q nodes of the plurality of first odd-numbered main stages and all Q nodes of the plurality of second odd-numbered main stages maintain the reset level during a touch period arranged between the first display period and the second display period, during which a touch of the display panel is sensed. 8 . The touch-sensing display device of claim 7 , wherein the odd-numbered reset dummy stages and the odd-numbered set dummy stages are not connected to the first odd-numbered gate lines and the second odd-numbered gate lines.

9. The touch-sensing display device according to claim 7 , wherein the Q node included in the odd-numbered reset dummy stage is reset based on an external odd-numbered reset signal, and the Q node included in the odd-numbered set dummy stage is set based on an external odd-numbered set signal, and The external odd reset signal is synchronized with a start timing of the touch period, and the external odd set signal is synchronized with an end timing of the touch period.

10. The touch-sensing display device according to claim 7, wherein the gate driving circuit further comprises: a plurality of first even main stages configured to drive the first even gate lines of the first display block during the first display period, the plurality of first even main stages comprising a first plurality of first even main stages and a second plurality of first even main stages; a plurality of second even main stages configured to drive second even gate lines of the second display block during the second display period, the plurality of second even main stages including a first plurality of second even main stages and a second plurality of second even main stages; an even reset dummy stage configured to reset a Q node included in each of the second plurality of first even main stages operated after the first plurality of first even main stages to the reset level during the first display period; as well as an even setting dummy stage configured to set a Q node included in each of the first plurality of second even main stages operated before the second plurality of second even main stages during the second display period, All the Q nodes of the plurality of first even-numbered main stages and all the Q nodes of the plurality of second even-numbered main stages maintain the reset level during the touch period arranged between the first display period and the second display period. 11 . The touch-sensing display device according to claim 10 , wherein all of the even-numbered reset dummy stages and the even-numbered set dummy stages are not connected to the first even-numbered gate line and the second even-numbered gate line.

12. The touch sensing display device according to claim 10, wherein, Reset the Q nodes included in the even reset dummy stage based on an external even reset signal, and set the Q nodes included in the even set dummy stage based on an external even set signal, and wherein the external even reset signal is synchronized with the start timing of the touch period, and the external even set signal is synchronized with the end timing of the touch period.

13. A touch display device, comprising: A display panel divided into a plurality of display blocks including a first display block, the first display block including a first sub-pixel connected to a first gate line included in the display panel and a second sub-pixel connected to a second gate line included in the display panel; And A gate driving circuit configured to drive the first gate line and the second gate line of the first display block, the gate driving circuit including: A plurality of first main stages configured to drive the first gate line but not the second gate line during a first display period when an image is displayed on the display panel, the plurality of first main stages including a first plurality of first main stages and a second plurality of first main stages; And A first reset dummy stage configured to reset the Q nodes included in each of the second plurality of first main stages that operate after the first plurality of first main stages to a reset level during the first display period, and not to reset the Q nodes included in the first plurality of first main stages during the first display period, wherein all the Q nodes of the first plurality of first main stages and all the Q nodes of the second plurality of first main stages included in the plurality of first main stages have the reset level during a touch period, and touch of the display panel is sensed during the touch period, and the touch period is after the first display period.

14. The touch display device according to claim 10, wherein the display panel further includes a second display block disposed after the first display block in the display panel, the second display block including a third sub-pixel connected to a third gate line included in the display panel and a fourth sub-pixel connected to a fourth gate line included in the display panel, and the gate driving circuit further includes: A plurality of second main stages configured to drive the third gate line of the second display block but not the fourth gate line during a second display period after the first display period, the plurality of second main stages including a first plurality of second main stages and a second plurality of second main stages; And A first set dummy stage configured to set the Q nodes included in each of the first plurality of second main stages that operate before the second plurality of second main stages to a set level greater than the reset level during the second display period.

15. The touch display device according to claim 14, wherein the first reset dummy stage and the first set dummy stage are not connected to the first gate line and the third gate line.

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