Gate driver, display device, and electronic device

Abstract

The invention relates to a gate driver, a display device and an electronic device. The gate driver includes a plurality of stages. Each of the plurality of stages includes: a control circuit configured to control a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; and a gate output circuit configured to output a gate signal in response to the voltage of the first node and the voltage of the second node. The control circuit includes a first control switching element configured to selectively connect the first node and the gate output path in response to an enable signal.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gate driver, a display device including the gate driver, and an electronic device including the display device. More specifically, the present invention relates to a gate driver for reducing power consumption, a display device including the gate driver, and an electronic device including the display device. Background Art

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines, emission lines, and pixels. The display panel driver includes a gate driver for providing a gate signal to the gate lines, a data driver for providing a data voltage to the data lines, an emission driver for providing an emission signal to the emission lines, and a driving controller for controlling the gate driver, the data driver, and the emission driver.

[0003] Recently, there has been a demand for reducing the power consumption of display devices, and in particular, there has been a demand for reducing the power consumption of display devices in mobile devices such as smart phones and tablet computers. To reduce the power consumption of a display device, a low-frequency driving technique has been developed to drive or refresh the display panel at a lower frequency than the conventional driving frequency.

[0004] Meanwhile, in a conventional display device applying the low-frequency driving technique, when a still image is not displayed in the entire area of the display panel, that is, when the still image is only displayed in a part of the display panel, the entire area of the display panel is driven at the conventional driving frequency. Therefore, in this case, low-frequency driving is not performed and the power consumption is not reduced. Summary of the Invention

[0005] Embodiments of the present invention provide a gate driver for supporting driving frequency multi-division to reduce the power consumption of a display device.

[0006] Embodiments of the present invention provide a display device including a gate driver.

[0007] Embodiments of the present invention provide an electronic device including a display device.

[0008] In an embodiment of a gate driver according to the present invention, the gate driver includes a plurality of stages. Each of the plurality of stages includes: a control circuit configured to control voltages of a first node and a second node in response to an input signal, a first clock signal, and a second clock signal; and a gate output circuit configured to output a gate signal in response to the voltage of the first node and the voltage of the second node. The control circuit includes a first control switch element configured to selectively connect the first node and the gate output circuit in response to an enable signal.

[0009] In an embodiment, the gate output circuit may be configured to selectively output the gate signal in response to the enable signal.

[0010] In an embodiment, when the enable signal has an inactive level that turns off the first control switch element before the input signal has a high level, the gate signal having a low level may be output, and when the enable signal has the inactive level after the input signal has the high level, the gate signal having a high level may be output.

[0011] In an embodiment, when the enable signal has an inactive level that turns off the first control switch element before the input signal has a low level, the gate signal having a high level may be output, and when the enable signal has the inactive level after the input signal has the low level, the gate signal having a low level may be output.

[0012] In an embodiment, the gate signal may be at least one of a data write gate signal, a compensation gate signal, and a data initialization gate signal applied to a pixel, and in response to the data write gate signal, a data voltage may be applied to the pixel, in response to the compensation gate signal, a threshold voltage of a driving transistor included in the pixel may be compensated, and in response to the data initialization gate signal, the driving transistor may be initialized.

[0013] In an embodiment, the pixel may include: a first transistor, which is the driving transistor, and the first transistor includes a gate electrode connected to a first pixel node, a first electrode connected to a second pixel node, and a second electrode connected to a third pixel node; a second transistor, including a gate electrode to which the data write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second pixel node; a third transistor, including a gate electrode to which the compensation gate signal is applied, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node; a fourth transistor, including a gate electrode to which the data initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the first pixel node; a fifth transistor, including a gate electrode to which the emission signal is applied, a first electrode to which the first driving voltage is applied, and a second electrode connected to the second pixel node; a seventh transistor, including a gate electrode to which the light-emitting element initialization gate signal is applied, a first electrode to which the light-emitting element initialization voltage is applied, and a second electrode connected to the anode electrode of the light-emitting element; and the light-emitting element, including the anode electrode and a cathode electrode to which the second driving voltage is applied.

[0014] In an embodiment, the first control switch element may include a gate electrode configured to receive the enable signal, a first electrode connected to a third node, and a second electrode connected to a fifth node, and the control circuit may further include: a first switch element, including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the third node; a second switch element, including a gate electrode connected to the first node, a first electrode configured to receive the second clock signal, and a second electrode connected to a fourth node; a ninth switch element, including a gate electrode configured to receive a gate low voltage, a first electrode connected to the fifth node, and a second electrode connected to the first node; and a third capacitor, including a first electrode connected to the fourth node and a second electrode connected to the first node.

[0015] In an embodiment, the control circuit may further include: a third switching element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the low gate voltage, and a second electrode connected to a sixth node; a fourth switching element including a gate electrode configured to receive the low gate voltage, a first electrode connected to the sixth node, and a second electrode connected to a seventh node; a fifth switching element including a gate electrode connected to the first node, a first electrode configured to receive the first clock signal, and a second electrode connected to the sixth node; a sixth switching element including a gate electrode connected to the seventh node, a first electrode configured to receive the second clock signal, and a second electrode connected to an eighth node; a seventh switching element including a gate electrode configured to receive the second clock signal, a first electrode connected to the eighth node, and a second electrode connected to the second node; an eighth switching element including a gate electrode connected to the first node, a first electrode configured to receive the first clock signal, and a second electrode connected to the second node; a first capacitor including a first electrode configured to receive the first clock signal and a second electrode connected to the second node; and a second capacitor including a first electrode connected to the seventh node and a second electrode connected to the eighth node.

[0016] In an embodiment, the gate output circuit may include: a tenth switching element including a gate electrode connected to the second node, a first electrode configured to receive the first clock signal, and a second electrode connected to a gate output node; and an eleventh switching element including a gate electrode connected to the first node, a first electrode configured to receive the low gate voltage, and a second electrode connected to the gate output node.

[0017] In an embodiment, the control circuit may further include: a first switching element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to a third node, and the gate output circuit may include: a seventh switching element including a gate electrode connected to the second node, a first electrode configured to receive a high gate voltage, and a second electrode connected to a gate output node; and an eighth switching element including a gate electrode connected to the first node, a first electrode configured to receive the second clock signal, and a second electrode connected to the gate output node.

[0018] In an embodiment, the first control switching element may include a gate electrode configured to receive the enable signal, a first electrode connected to a fifth node, and a second electrode connected to the first node.

[0019] In an embodiment, the control circuit may further include: a sixth switching element including a gate electrode configured to receive a low gate voltage, a first electrode connected to the third node, and a second electrode connected to the fifth node.

[0020] In an embodiment, the control circuit may further include: a second switching element including a gate electrode connected to the second node, a first electrode configured to receive the high gate voltage, and a second electrode connected to the fourth node; a third switching element including a gate electrode configured to receive the second clock signal, a first electrode connected to the fourth node, and a second electrode connected to the third node; a fourth switching element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the low gate voltage, and a second electrode connected to the second node; and a fifth switching element including a gate electrode connected to the third node, a first electrode configured to receive the first clock signal, and a second electrode connected to the second node, and the gate output circuit may further include: a first capacitor including a first electrode connected to the first node and a second electrode connected to the gate output node; and a second capacitor including a first electrode configured to receive the high gate voltage and a second electrode connected to the second node.

[0021] In an embodiment, the first control switching element may have a dual-transistor structure including two transistors.

[0022] In an embodiment, the first control switching element may be an N-type transistor.

[0023] In an embodiment, the control circuit may further include a second control switching element configured to selectively connect the second node and the gate output circuit in response to the enable signal.

[0024] In an embodiment, the control circuit may further include: a first switching element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the third node, and the gate output circuit may include: a seventh switching element including a gate electrode connected to the second node, a first electrode configured to receive the high gate voltage, and a second electrode connected to the gate output node; and an eighth switching element including a gate electrode connected to the first node, a first electrode configured to receive the second clock signal, and a second electrode connected to the gate output node.

[0025] In an embodiment, the first control switch element may include a gate electrode configured to receive the enable signal, a first electrode connected to the fifth node, and a second electrode connected to the first node.

[0026] In an embodiment, the second control switch element may include a gate electrode configured to receive the enable signal, a first electrode connected to the sixth node, and a second electrode connected to the second node.

[0027] In an embodiment, the control circuit may further include: a sixth switch element including a gate electrode configured to receive a low gate voltage, a first electrode connected to the third node, and a second electrode connected to the fifth node.

[0028] In an embodiment, the control circuit may further include: a second switch element including a gate electrode connected to the sixth node, a first electrode configured to receive the high gate voltage, and a second electrode connected to the fourth node; a third switch element including a gate electrode configured to receive the second clock signal, a first electrode connected to the fourth node, and a second electrode connected to the third node; a fourth switch element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the low gate voltage, and a second electrode connected to the sixth node; and a fifth switch element including a gate electrode connected to the third node, a first electrode configured to receive the first clock signal, and a second electrode connected to the sixth node, and the gate output circuit may further include: a first capacitor including a first electrode connected to the first node and a second electrode connected to the gate output node; and a second capacitor including a first electrode configured to receive the high gate voltage and a second electrode connected to the second node.

[0029] In an embodiment, the control circuit may further include: a first switch element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the third node, and the gate output circuit may include: a ninth switch element including a gate electrode connected to the second node, a first electrode configured to receive the high gate voltage, and a second electrode connected to the gate output node; and a tenth switch element including a gate electrode connected to the first node, a first electrode configured to receive the low gate voltage, and a second electrode connected to the gate output node.

[0030] In an embodiment, the first control switch element may include a gate electrode configured to receive the enable signal, a first electrode connected to the third node, and a second electrode connected to the first node.

[0031] In an embodiment, the second control switch element may include a gate electrode configured to receive the enable signal, a first electrode connected to the seventh node, and a second electrode connected to the second node.

[0032] In an embodiment, the control circuit may further include: a second switch element including a gate electrode connected to the fifth node, a first electrode configured to receive the gate high voltage, and a second electrode connected to the fourth node; a third switch element including a gate electrode configured to receive the second clock signal, a first electrode connected to the fourth node, and a second electrode connected to the third node; a fourth switch element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the gate low voltage, and a second electrode connected to the fifth node; a fifth switch element including a gate electrode configured to receive the second clock signal, a first electrode connected to the sixth node, and a second electrode connected to the seventh node; a sixth switch element including a gate electrode connected to the fifth node, a first electrode configured to receive the second clock signal, and a second electrode connected to the sixth node; a seventh switch element including a gate electrode connected to the third node, a first electrode configured to receive the gate high voltage, and a second electrode connected to the second node; an eighth switch element including a gate electrode connected to the third node, a first electrode configured to receive the first clock signal, and a second electrode connected to the fifth node; a first capacitor including a first electrode configured to receive the second clock signal and a second electrode connected to the third node; a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the sixth node; and a third capacitor including a first electrode configured to receive the gate high voltage and a second electrode connected to the seventh node.

[0033] In an embodiment of a display device according to the present invention, the display device includes: a display panel including a plurality of pixels; a gate driver configured to apply a gate signal to the display panel; and a data driver configured to apply a data voltage to the display panel. The gate driver includes a plurality of stages, and each of the plurality of stages includes: a control circuit configured to control voltages of a first node and a second node in response to an input signal, a first clock signal, and a second clock signal; and a gate output circuit configured to output the gate signal in response to the voltage of the first node and the voltage of the second node. The control circuit includes a first control switch element configured to selectively connect the first node and the gate output circuit in response to an enable signal.

[0034] In an embodiment, the gate output circuit may be configured to selectively output the gate signal in response to the enable signal.

[0035] In an embodiment, when the enable signal has an inactive level that turns off the first control switch element before the input signal has a high level, the gate signal having a low level may be output, and when the enable signal has the inactive level after the input signal has the high level, the gate signal having a high level may be output.

[0036] In an embodiment, when the enable signal has an inactive level that turns off the first control switch element before the input signal has a low level, the gate signal having a high level may be output, and when the enable signal has the inactive level after the input signal has the low level, the gate signal having a low level may be output.

[0037] In an embodiment of an electronic device according to the present invention, the electronic device includes: a display panel including a plurality of pixels; a gate driver configured to apply a gate signal to the display panel; a data driver configured to apply a data voltage to the display panel; a driving controller configured to control the gate driver and the data driver; and a processor configured to apply input image data to the driving controller. The gate driver includes a plurality of stages, and each of the plurality of stages includes: a control circuit configured to control voltages of a first node and a second node in response to an input signal, a first clock signal, and a second clock signal; and a gate output circuit configured to output the gate signal in response to the voltages of the first node and the second node. The control circuit includes a first control switch element configured to selectively connect the first node and the gate output circuit in response to an enable signal.

[0038] According to the gate driver, the display device, and the electronic device, the gate driver and the display device may include a control circuit and a gate output circuit, and the control circuit may include a first control switch element configured to selectively connect a first node and the gate output circuit in response to an enable signal, so that driving frequency multiple division can be supported. Through driving frequency multiple division, power consumption of the display device can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] By describing embodiments of the present invention in detail with reference to the accompanying drawings, the above and other features of the embodiments of the present invention will become more apparent, in the drawings:

[0040] Figure 1is a block diagram showing a display device according to an embodiment of the present invention;

[0041] Figure 2 is a description of Figure 1 a conceptual diagram of the driving frequency of the display panel;

[0042] Figure 3 is a circuit diagram showing an example of a pixel of Figure 1 the display panel;

[0043] Figure 4 is a timing diagram showing the driving signal of a pixel in Figure 3 variable-frequency driving;

[0044] Figure 5 is a conceptual diagram showing Figure 1 the gate driver;

[0045] Figure 6 is a conceptual diagram showing the driving frequency of each area of Figure 1 the display panel in multi-frequency driving;

[0046] Figure 7 is a conceptual diagram showing each stage included in Figure 5 the gate driver;

[0047] Figure 8 is a circuit diagram showing an example of Figure 7 each stage;

[0048] Figure 9 is a timing diagram showing the input signal, first clock signal, second clock signal, node signal, enable signal, and output signal of each stage when the enable signal has an effective level; Figure 8

[0049] Figure 10 is a circuit diagram showing the operation of each stage of Figure 8 in Figure 9 the first time period;

[0050] Figure 11 is a circuit diagram showing the operation of each stage of Figure 8 in Figure 9 the second time period;

[0051] Figure 12 is a circuit diagram showing the operation of each stage of Figure 8 in Figure 9 the third time period;

[0052] Figure 13 is a circuit diagram showing the operation of each stage of Figure 8 in Figure 9 the fourth time period;​

[0053] Figure 14 is a circuit diagram showing the operations of each stage of Figure 8 in the fifth time period of Figure 9 ;

[0054] Figure 15 is a circuit diagram showing the operations of each stage of Figure 8 in the sixth time period of Figure 9 ;

[0055] Figure 16 is a circuit diagram showing the operations of each stage of Figure 8 in the seventh time period of Figure 9 ;

[0056] Figure 17 is a circuit diagram showing the operations of each stage of Figure 8 in the eighth time period of Figure 9 ;

[0057] Figure 18 is a timing diagram showing the input signal, first clock signal, second clock signal, node signal, and output signal of each stage of Figure 8 when the enable signal has an inactive level;

[0058] Figure 19 is a circuit diagram showing the operations of each stage of Figure 8 in the first time period of Figure 18 ;

[0059] Figure 20 is a circuit diagram showing the operations of each stage of Figure 8 in the second time period of Figure 18 ;

[0060] Figure 21 is a circuit diagram showing the operations of each stage of Figure 8 in the third time period of Figure 18 ;

[0061] Figure 22 is a circuit diagram showing the operations of each stage of Figure 8 in the fourth time period of Figure 18 ;

[0062] Figure 23 is a circuit diagram showing the operations of each stage of Figure 8 in the fifth time period of Figure 18 ;

[0063] Figure 24 is a circuit diagram showing another example of each stage of Figure 7 ;

[0064] Figure 25 is a timing diagram showing the input signal, first clock signal, second clock signal, node signal, and output signal of each stage of Figure 24 ;

[0065] Figure 26 is a circuit diagram showing the operation of each stage of Figure 24 in the first time period of Figure 25 ;

[0066] Figure 27 is a circuit diagram showing the operation of each stage of Figure 24 in the second time period of Figure 25 ;

[0067] Figure 28 is a circuit diagram showing the operation of each stage of Figure 24 in the third time period of Figure 25 ;

[0068] Figure 29 is a circuit diagram showing the operation of each stage of Figure 24 in the fourth time period of Figure 25 ;

[0069] Figure 30 is a circuit diagram showing the operation of each stage of Figure 24 in the fifth time period of Figure 25 ;

[0070] Figure 31 is a circuit diagram showing the operation of each stage of Figure 24 when the enable signal has an inactive level;

[0071] Figure 32 is a circuit diagram showing another example of each stage of Figure 7 ;

[0072] Figure 33 is a circuit diagram showing yet another example of each stage of Figure 7 ;

[0073] Figure 34 is a circuit diagram showing another example of each stage of Figure 7 ;

[0074] Figure 35 is a circuit diagram showing yet another example of each stage of Figure 7 ;

[0075] Figure 36 is a timing diagram showing the input signal, first clock signal, second clock signal, node signal, and output signal of each stage of Figure 35 ;

[0076] Figure 37is a circuit diagram showing the operation of each stage of Figure 35 in the first time period of Figure 36 ;

[0077] Figure 38 is a circuit diagram showing the operation of each stage of Figure 35 in the second time period of Figure 36 ;

[0078] Figure 39 is a circuit diagram showing the operation of each stage of Figure 35 in the third time period of Figure 36 ;

[0079] Figure 40 is a circuit diagram showing the operation of each stage of Figure 35 when the enable signal has an inactive level;

[0080] Figure 41 is a block diagram showing an electronic device; and

[0081] Figure 42 is a diagram showing an embodiment in which the Figure 41 electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0082] The terms used herein are for the purpose of describing particular embodiments only and are not limiting. As used herein, unless the context clearly dictates otherwise, "a", "an", "the", and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural. For example, "an element" has the same meaning as "at least one element" unless the context clearly dictates otherwise. "At least one" should not be construed as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises" and / or "comprising", or "has" and / or "having", specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0083] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, without departing from the teachings herein, the "first element", "first component", "first region", "first layer", or "first section" discussed below may be named the "second element", "second component", "second region", "second layer", or "second section". Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

[0084] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0085] Referring Figure 1 , the display device may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 500, a data driver 600, and an emission driver 700.

[0086] The display panel 100 may include a display area for displaying an image and a peripheral area disposed adjacent to the display area.

[0087] The display panel 100 may include gate lines GWL, GCL, GIL, and GBL, data lines DL, emission lines EML, and pixels electrically connected to the gate lines GWL, GCL, GIL, and GBL, the data lines DL, and the emission lines EML, respectively. The gate lines GWL, GCL, GIL, and GBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 intersecting the first direction D1, and the emission lines EML may extend in the first direction D1.

[0088] The driving controller 200 may receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signals CONT may include a main clock signal and a data enable signal. The input control signals CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0089] The driving controller 200 may generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0090] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0091] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 600 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 600. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0092] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 600.

[0093] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 500 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 500.

[0094] The driving controller 200 may generate a fourth control signal CONT4 for controlling the operation of the emission driver 700 based on the input control signal CONT, and output the fourth control signal CONT4 to the emission driver 700.

[0095] The gate driver 300 may generate gate signals for driving the gate lines GWL, GCL, GIL, and GBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signals to the gate lines GWL, GCL, GIL, and GBL.

[0096] The gamma reference voltage generator 500 may generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 500 may provide the gamma reference voltage VGREF to the data driver 600. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

[0097] For example, the gamma reference voltage generator 500 may be provided in the driving controller 200, or may be provided in the data driver 600.

[0098] The data driver 600 may receive a second control signal CONT2 and a data signal DATA from the driving controller 200, and receive a gamma reference voltage VGREF from the gamma reference voltage generator 500. The data driver 600 may convert the data signal DATA into a data voltage of an analog type using the gamma reference voltage VGREF. The data driver 600 may output the data voltage to the data line DL.

[0099] The emission driver 700 may generate an emission signal for driving the emission line EML in response to a fourth control signal CONT4 received from the driving controller 200. The emission driver 700 may output the emission signal to the emission line EML.

[0100] In Figure 1 for ease of explanation, the gate driver 300 may be provided on the first side of the display panel 100, and the emission driver 700 may be provided on the second side of the display panel 100. Although shown, the present invention is not limited thereto. For another example, both the gate driver 300 and the emission driver 700 may be provided on the first side of the display panel 100. For example, both the gate driver 300 and the emission driver 700 may be provided on opposite sides of the display panel 100. For example, the gate driver 300 and the emission driver 700 may be integrally formed.

[0101] Figure 2 is a conceptual diagram Figure 1 describing the driving frequency of the display panel 100.

[0102] Referring to Figure 1 and Figure 2 , the display panel 100 may be driven at a variable frequency. A first frame FR1 having a first frequency may include a first active period AC1 and a first blanking period BL1. A second frame FR2 having a second frequency different from the first frequency may include a second active period AC2 and a second blanking period BL2. A third frame FR3 having a third frequency different from the first frequency and the second frequency may include a third active period AC3 and a third blanking period BL3.

[0103] The first active period AC1 may have the same length as the second active period AC2, and the first blanking period BL1 may have a different length from the second blanking period BL2. The second active period AC2 may have the same length as the third active period AC3, and the second blanking period BL2 may have a different length from the third blanking period BL3.

[0104] A display device supporting variable frequencies may include a data writing period in which a data voltage is written into a pixel and a self-scanning period in which no data voltage is written into the pixel and only light emission occurs. The data writing period may be arranged within active periods AC1, AC2, and AC3. The self-scanning period may be arranged within blanking periods BL1, BL2, and BL3.

[0105] Figure 3 is a circuit diagram showing Figure 1 an example of a pixel of the display panel 100.

[0106] Referring Figures 1 to 3 , the display panel 100 includes pixels, and each of the pixels includes a light-emitting element EE.

[0107] The pixel may receive a data writing gate signal GW[n], a compensation gate signal GC[n], a data initialization gate signal GI[n], a light-emitting element initialization gate signal GB[n], a data voltage VDATA, and an emission signal EM[n], and may display an image by causing the light-emitting element EE to emit light according to the level of the data voltage VDATA. Here, n is a positive integer.

[0108] In an embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor. For example, the first type of switching element may be a polysilicon thin-film transistor. For example, the first type of switching element may be a low-temperature polysilicon (“LTPS”) thin-film transistor. For example, the second type of switching element may be an oxide thin-film transistor. At least one of the pixels may include a first transistor PT1 to a seventh transistor PT7 and a light-emitting element EE.

[0109] The first transistor PT1 (i.e., the driving transistor) may include a gate electrode connected to a first pixel node PN1, a first electrode connected to a second pixel node PN2, and a second electrode connected to a third pixel node PN3.

[0110] The second transistor PT2 may include a gate electrode to which the data writing gate signal GW[n] is applied, a first electrode to which the data voltage VDATA is applied, and a second electrode connected to the second pixel node PN2. The data voltage VDATA may be applied to the pixel in response to the data writing gate signal GW[n].

[0111] The third transistor PT3 may include a gate electrode to which a compensation gate signal GC[n] is applied, a first electrode connected to the first pixel node PN1, and a second electrode connected to the third pixel node PN3. The threshold voltage of the first transistor PT1 may be compensated in response to the compensation gate signal GC[n].

[0112] The fourth transistor PT4 may include a gate electrode to which a data initialization gate signal GI[n] is applied, a first electrode to which an initialization voltage VINIT is applied, and a second electrode connected to the first pixel node PN1. The gate electrode of the first transistor PT1 may be initialized to the initialization voltage VINIT in response to the data initialization gate signal GI[n].

[0113] The fifth transistor PT5 may include a gate electrode to which an emission signal EM[n] is applied, a first electrode to which a first driving voltage ELVDD is applied, and a second electrode connected to the second pixel node PN2.

[0114] The sixth transistor PT6 may include a gate electrode to which an emission signal EM[n] is applied, a first electrode connected to the third pixel node PN3, and a second electrode connected to the anode electrode of the light-emitting element EE.

[0115] The seventh transistor PT7 may include a gate electrode to which a light-emitting element initialization gate signal GB[n] is applied, a first electrode to which a light-emitting element initialization voltage VAINIT is applied, and a second electrode connected to the anode electrode of the light-emitting element EE.

[0116] The light-emitting element EE may include an anode electrode and a cathode electrode to which a second driving voltage ELVSS is applied.

[0117] The pixel may further include a storage capacitor CST, and the storage capacitor CST includes a first electrode to which a first driving voltage ELVDD is applied and a second electrode connected to the first pixel node PN1.

[0118] The signal output from the gate output circuit of the gate driver 300 may be a data write gate signal GW[n], a compensation gate signal GC[n], a data initialization gate signal GI[n], or a light-emitting element initialization gate signal GB[n].

[0119] The driving current of the pixel may flow in the order of the fifth transistor PT5, the first transistor PT1, and the sixth transistor PT6 to drive the light-emitting element EE. The intensity of the driving current may be determined by the level of the data voltage VDATA. The brightness of the light-emitting element EE may be determined by the intensity of the driving current.

[0120] Leakage current may be generated more in P-type transistors than in N-type transistors. Therefore, some of the transistors included in the pixel may be N-type transistors. In an embodiment, the third transistor PT3 and the fourth transistor PT4 may be N-type transistors. The first transistor PT1, the second transistor PT2, the fifth transistor PT5, the sixth transistor PT6, and the seventh transistor PT7 may be P-type transistors.

[0121] In the present embodiment, it is illustrated that some of the switching elements of the pixel are N-type transistors and some of the switching elements are P-type transistors, but the present invention is not limited thereto. In another embodiment, the present invention may be applied to pixels including only P-type transistors. Additionally, in still another embodiment, the present invention may be applied to pixels including only N-type transistors.

[0122] When the signal applied to the gate electrode of the switching element has an effective level, the switching element may turn on. When the signal applied to the gate electrode of the switching element has a non-effective level, the switching element may turn off. The effective level means the level that turns on the switching element, and the non-effective level means the level that turns off the switching element. When the switching element is a P-type transistor, the effective level may be a low level, and the non-effective level may be a high level. When the switching element is an N-type transistor, the effective level may be a high level, and the non-effective level may be a low level.

[0123] Figure 4 is a timing diagram showing the Figure 3 driving signal of the pixel in variable frequency driving.

[0124] Referring to Figures 1 to 4 , the display panel 100 can be driven at a variable frequency. For example, the display panel 100 can be driven at a maximum of 120 Hz. When the display panel 100 is driven at 120 Hz, in the first period P1, the third period P3, the fifth period P5, and the seventh period P7, the data write gate signal GW[n] may have an effective pulse, and a data write operation can be performed. When the display panel 100 is driven at 60 Hz, in the first period P1 and the fifth period P5, the data write gate signal GW[n] may have an effective pulse, and a data write operation can be performed.

[0125] When the display panel 100 is driven at 120 Hz, in the first period P1, the third period P3, the fifth period P5, and the seventh period P7, the emission signal EM[n] may have an effective pulse, and a light emission operation can be performed. When the display panel 100 is driven at 60 Hz, in the first period P1, the third period P3, the fifth period P5, and the seventh period P7, the emission signal EM[n] may have an effective pulse, and a light emission operation can be performed.

[0126] When the display panel 100 is driven at 120 Hz, in the first period P1, the third period P3, the fifth period P5, and the seventh period P7, the light-emitting element initialization gate signal GB[n] may have an effective pulse, and a bias operation may be performed. When the display panel 100 is driven at 60 Hz, in the first period P1, the third period P3, the fifth period P5, and the seventh period P7, the light-emitting element initialization gate signal GB[n] may have an effective pulse, and a bias operation may be performed.

[0127] As Figure 4 shown, only the emission signal EM[n], the light-emitting element initialization gate signal GB[n], and the data write gate signal GW[n] are shown, but the compensation gate signal GC[n] and the data initialization gate signal GI[n] may also be applied to the pixels in the same manner as the data write gate signal GW[n]. When the display panel 100 is driven at 120 Hz, in the first period P1, the third period P3, the fifth period P5, and the seventh period P7, the compensation gate signal GC[n] and the data initialization gate signal GI[n] may have effective pulses, and when the display panel 100 is driven at 60 Hz, in the first period P1 and the fifth period P5, the compensation gate signal GC[n] and the data initialization gate signal GI[n] may have effective pulses.

[0128] Figure 5 is a conceptual diagram showing Figure 1 the gate driver 300. Figure 6 is a conceptual diagram showing Figure 1 the driving frequency of each region of the display panel 100 in multi-frequency driving. Figure 7 is a conceptual diagram showing Figure 5 each stage 400 included in

[0129] Referring Figures 1 to 7 to, the gate driver 300 may include a plurality of stages ST1, ST2, ST3, ST4, ST5, ST6,.... Each stage 400 may be any one of the plurality of stages ST1, ST2, ST3, ST4, ST5, ST6,....

[0130] The stages ST1, ST2, ST3, ST4, ST5, ST6,... may receive a gate start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and an enable signal EN. The first clock signal CLK1 and the second clock signal CLK2 may have different phases.

[0131] Levels ST1, ST2, ST3, ST4, ST5, ST6, … can sequentially output gate signals GS1, GS2, GS3, GS4, GS5, GS6, …. Each of the gate signals GS1, GS2, GS3, GS4, GS5, GS6, … can be provided as carry signals CR1, CR2, CR3, CR4, CR5, CR6, … to the subsequent level. In an embodiment, odd levels ST1, ST3, ST5, … can receive an input signal (e.g., a gate start signal FLM or previous carry signals CR2, CR4, …) in response to a first clock signal CLK1, and can start output of the gate signals GS1, GS3, GS5, … in response to a second clock signal CLK2. In an embodiment, even levels ST2, ST4, ST6, … can receive an input signal (e.g., previous carry signals CR1, CR3, CR5, …) in response to the second clock signal CLK2, and can start output of the gate signals GS2, GS4, GS6, … in response to the first clock signal CLK1. In an embodiment, each of the gate signals GS1, GS2, GS3, GS4, GS5, GS6, … can be at least one of a data write gate signal GW[n], a compensation gate signal GC[n], and a data initialization gate signal GI[n].

[0132] For example, as Figure 5 shown, the first level ST1 can receive the gate start signal FLM in response to the first clock signal CLK1, and output a first gate signal GS1 in response to the second clock signal CLK2. The second level ST2 can receive the first gate signal GS1 as a first carry signal CR1 in response to the second clock signal CLK2, and output a second gate signal GS2 in response to the first clock signal CLK1. The third level ST3 can receive the second gate signal GS2 as a second carry signal CR2 in response to the first clock signal CLK1, and output a third gate signal GS3 in response to the second clock signal CLK2. The fourth level ST4 can receive the third gate signal GS3 as a third carry signal CR3 in response to the second clock signal CLK2, and output a fourth gate signal GS4 in response to the first clock signal CLK1. The fifth level ST5 can receive the fourth gate signal GS4 as a fourth carry signal CR4 in response to the first clock signal CLK1, and output a fifth gate signal GS5 in response to the second clock signal CLK2. The sixth level ST6 can receive the fifth gate signal GS5 as a fifth carry signal CR5 in response to the second clock signal CLK2, and output a sixth gate signal GS6 in response to the first clock signal CLK1.

[0133] The display panel 100 may perform multi-frequency driving ("MFD") according to the driving frequency for each region. Stages ST1, ST2, ST3, ST4, ST5, ST6, … may selectively output gate signals GS1, GS2, GS3, GS4, GS5, GS6, … according to the level of the enable signal EN. Specifically, when the enable signal EN has an inactive level before the input signal FLM / PCR has a high level, a gate signal having a low level may be output, and when the enable signal EN has an inactive level after the input signal FLM / PCR has a high level, a gate signal having a high level may be output. Here, the reference numeral PCR represents previous carry signals CR1, CR2, CR3, CR4, CR5, CR6, …, and the reference numeral FLM / PCR represents that the input signal may be a gate start signal FLM or carry signals CR1, CR2, CR3, CR4, CR5, CR6, ….

[0134] For example, the switching element that receives the enable signal EN may be a P-type transistor. In this case, the inactive level of the enable signal EN may be a high level, and the active level of the enable signal EN may be a low level. When the enable signal EN has a high level, the switching element that receives the enable signal EN may be turned off.

[0135] Figure 6 The case where the switching element that receives the enable signal EN is a P-type transistor is illustrated, but the present invention is not limited thereto.

[0136] For example, the switching element that receives the enable signal EN may be an N-type transistor. In this case, the inactive level of the enable signal EN may be a low level, and the active level of the enable signal EN may be a high level. When the enable signal EN has a low level, the switching element that receives the enable signal EN may be turned off.

[0137] As Figure 6 shown, in the first period P1', the enable signal EN may have a low level, and in the first period P1', gate signals GS1, GS2, GS3, GS4, GS5, GS6, … having a high level may be sequentially output. In the second period P2', the enable signal EN may have a high level, and in the second period P2', a first gate signal GS1, a second gate signal GS2, a third gate signal GS3, and a fourth gate signal GS4 having a high level may be output, and subsequent gate signals GS5, GS6, … having a low level may be output.

[0138] Figure 6Illustrates the case where the gate signals GS1, GS2, GS3, GS4, GS5, GS6,... have a high level when the input signal FLM / PCR has a high level and the enable signal EN has an active level, but the present invention is not limited thereto.

[0139] When the enable signal EN has an inactive level before the input signal FLM / PCR has a low level, a gate signal having a high level can be output, and when the enable signal EN has an inactive level after the input signal FLM / PCR has a low level, a gate signal having a low level can be output.

[0140] In an embodiment, the stages ST1, ST2, ST3, ST4, ST5, ST6,... may further receive a third clock signal (not shown) and a fourth clock signal (not shown). The first clock signal CLK1, the second clock signal CLK2, the third clock signal, and the fourth clock signal may have different phases. In this case, the first stage ST1 may receive the first clock signal CLK1 and the second clock signal CLK2, the second stage ST2 may receive the second clock signal CLK2 and the third clock signal, the third stage ST3 may receive the third clock signal and the fourth clock signal, the fourth stage ST4 may receive the fourth clock signal and the first clock signal CLK1, the fifth stage ST5 may receive the first clock signal CLK1 and the second clock signal CLK2, and the sixth stage ST6 may receive the second clock signal CLK2 and the third clock signal.

[0141] As Figure 7 shown, each stage 400 may include a control circuit 410 and a gate output circuit 420. The control circuit 410 may control the voltage V_Q of the first node and the voltage V_QB of the second node in response to the input signal FLM / PCR, the first clock signal CLK1, and the second clock signal CLK2. The control circuit 410 may include a first control switch element TC1, and the first control switch element TC1 selectively connects the first node and the gate output circuit 420 in response to the enable signal EN. In an embodiment, the control circuit 410 may further include a second control switch element TC2, and the second control switch element TC2 selectively connects the second node and the gate output circuit 420 in response to the enable signal EN. In an embodiment, the first control switch element TC1 may include a first sub-switch element TS1 and a second sub-switch element TS2. That is, the first control switch element TC1 may have a dual-transistor structure including two transistors. In an embodiment, the second control switch element TC2 may include a third sub-switch element TS3 and a fourth sub-switch element TS4. That is, the second control switch element TC2 may have a dual-transistor structure including two transistors.

[0142] The gate output circuit 420 can output a gate signal GS(n) in response to the voltage V_Q of the first node and the voltage V_QB of the second node.

[0143] Figure 8 is a circuit diagram showing Figure 7 an example of each stage 400.

[0144] Referring Figure 8 , each stage 400 may include a control circuit 410 and a gate output circuit 420. The control circuit 410 can control the voltage V_Q of the first node Q and the voltage V_QB of the second node QB in response to an input signal FLM / PCR, a first clock signal CLK1, and a second clock signal CLK2. The control circuit 410 may include a first control switch element TC1 that selectively connects the first node Q and the gate output circuit 420 in response to an enable signal EN. Additionally, the gate output circuit 420 can output a gate signal GS(n) in response to the voltage V_Q of the first node Q and the voltage V_QB of the second node QB. In an embodiment, the gate signal GS(n) may be one of a compensation gate signal GC[n] and a data initialization gate signal GI[n] applied to a pixel. The control circuit 410 may include a first switch element T1, a second switch element T2, a ninth switch element T9, a first control switch element TC1, and a third capacitor C3. The control circuit 410 may further include a third switch element T3, a fourth switch element T4, a fifth switch element T5, a sixth switch element T6, a seventh switch element T7, an eighth switch element T8, a first capacitor C1, and a second capacitor C2.

[0145] The first switch element T1 may include a gate electrode that receives the first clock signal CLK1, a first electrode that receives the input signal FLM / PCR, and a second electrode that is connected to the third node N3.

[0146] The second switch element T2 may include a gate electrode that is connected to the first node Q, a first electrode that receives the second clock signal CLK2, and a second electrode that is connected to the fourth node N4.

[0147] The third switch element T3 may include a gate electrode that receives the first clock signal CLK1, a first electrode that receives the gate low voltage VGL, and a second electrode that is connected to the sixth node N6.

[0148] The fourth switch element T4 may include a gate electrode that receives the gate low voltage VGL, a first electrode that is connected to the sixth node N6, and a second electrode that is connected to the seventh node N7.

[0149] The fifth switching element T5 may include a gate electrode connected to the first node Q, a first electrode receiving the first clock signal CLK1, and a second electrode connected to the sixth node N6.

[0150] The sixth switching element T6 may include a gate electrode connected to the seventh node N7, a first electrode receiving the second clock signal CLK2, and a second electrode connected to the eighth node N8.

[0151] The seventh switching element T7 may include a gate electrode receiving the second clock signal CLK2, a first electrode connected to the eighth node N8, and a second electrode connected to the second node QB.

[0152] The eighth switching element T8 may include a gate electrode connected to the first node Q, a first electrode receiving the first clock signal CLK1, and a second electrode connected to the second node QB.

[0153] The first control switching element TC1 may include a gate electrode receiving the enable signal EN, a first electrode connected to the third node N3, and a second electrode connected to the fifth node N5. In an embodiment, the first control switching element TC1 may include a first sub-switching element TS1 and a second sub-switching element TS2. That is, the first control switching element TC1 may have a dual-transistor structure including two transistors.

[0154] The ninth switching element T9 may include a gate electrode receiving the gate low voltage VGL, a first electrode connected to the fifth node N5, and a second electrode connected to the first node Q.

[0155] The first capacitor C1 may include a first electrode receiving the first clock signal CLK1 and a second electrode connected to the second node QB.

[0156] The second capacitor C2 may include a first electrode connected to the seventh node N7 and a second electrode connected to the eighth node N8.

[0157] The third capacitor C3 may include a first electrode connected to the fourth node N4 and a second electrode connected to the first node Q.

[0158] The gate output circuit 420 may include a tenth switching element T10 and an eleventh switching element T11.

[0159] The tenth switching element T10 may include a gate electrode connected to the second node QB, a first electrode receiving the first clock signal CLK1, and a second electrode connected to the gate output node GS_ON.

[0160] The eleventh switching element T11 may include a gate electrode connected to the first node Q, a first electrode receiving a gate low voltage VGL, and a second electrode connected to the gate output node GS_ON.

[0161] In this embodiment, each stage 400 including only P-type transistors is illustrated, but the present invention is not limited thereto. Leakage current may be generated more in P-type transistors than in N-type transistors. Therefore, in another embodiment, some of the switching elements included in each stage 400 may be N-type transistors. For example, the first control switching element TC1 may be an N-type transistor, and the first switching element T1 to the eleventh switching element T11 may be P-type transistors.

[0162] Figure 9 is a timing diagram of the input signal FLM / PCR, the first clock signal CLK1, the second clock signal CLK2, the node signals (i.e., the voltage V_Q of the first node Q and the voltage V_QB of the second node QB), the enable signal EN, and the output signal (i.e., the gate signal GS(n)) of each stage 400 when the enable signal EN has an active level Figure 8 Figure 10 is a circuit diagram showing Figure 8 the operation of each stage 400 in Figure 9 the first time period TP1. Figure 11 is a circuit diagram showing Figure 8 the operation of each stage 400 in Figure 9 the second time period TP2. Figure 12 is a circuit diagram showing Figure 8 the operation of each stage 400 in Figure 9 the third time period TP3. Figure 13 is a circuit diagram showing Figure 8 the operation of each stage 400 in Figure 9 the fourth time period TP4. Figure 14 is a circuit diagram showing Figure 8 the operation of each stage 400 in Figure 9 the fifth time period TP5. Figure 15 is a circuit diagram showing Figure 8 the operation of each stage 400 in Figure 9 the sixth time period TP6. Figure 16 is a circuit diagram showing Figure 8 the operation of each stage 400 in Figure 9 the seventh time period TP7. Figure 17 is a circuit diagram showing Figure 8 the operation of each stage 400 in Figure 9 the eighth time period TP8.

[0163] Refer to​Figures 8 to 17 This can illustrate the operation of each stage 400 when the first control switch element TC1 remains in the conducting state in response to an enable signal EN having an effective level. The effective level can be the level that turns on the switch element. For example, the effective level of an N-type transistor can be a high level VH, and the effective levels of a P-type transistor can be a first low level VL1, a low level VL, and a second low level VL2. The first low level VL1 can be higher than the low level VL, and the second low level VL2 can be lower than the low level VL. The 1 horizontal time 1H can be the time assigned to each pixel row of the display panel 100.

[0164] The non-effective level can be the level that turns off the switch element. For example, the non-effective levels of an N-type transistor can be a first low level VL1, a low level VL, and a second low level VL2, and the non-effective level of a P-type transistor can be a high level VH.

[0165] As Figure 10 shown, in the first time period TP1, the input signal FLM / PCR can have a low level VL, the first clock signal CLK1 can have a low level VL, and the second clock signal CLK2 can have a high level VH.

[0166] The first switch element T1 can turn on in response to the first clock signal CLK1 having a low level VL. The ninth switch element T9 can turn on in response to a gate low voltage VGL. The level of the gate low voltage VGL can be the low level VL. The first switch element T1 can apply the input signal FLM / PCR having a low level VL to the third node N3 and the first node Q. Due to the characteristics of the P-type transistor, even if the input signal FLM / PCR has a low level VL, the first node Q can have a first low level VL1 that is reduced from the low level VL by the threshold voltage of the first switch element T1, the threshold voltage of the first control switch element TC1, or the threshold voltage of the ninth switch element T9.

[0167] The eighth switch element T8 can turn on in response to the voltage V_Q of the first node Q having a first low level VL1, and can apply the first clock signal CLK1 having a low level VL to the second node QB. However, since the first low level VL1 is higher than the low level VL, the eighth switch element T8 may not turn on completely. Therefore, the voltage V_QB of the second node QB can have a first low level VL1 that is higher than the low level VL.

[0168] The tenth switching element T10 can be turned on in response to the voltage V_QB of the second node QB having a first low level VL1, and can apply the first clock signal CLK1 having a low level VL to the gate output node GS_ON. The eleventh switching element T11 can be turned on in response to the voltage V_Q of the first node Q having a first low level VL1, and can apply the gate low voltage VGL to the gate output node GS_ON. Therefore, a gate signal GS(n) having a low level VL can be output from the gate output node GS_ON.

[0169] As Figure 11 shown, in the second time period TP2, the input signal FLM / PCR can have a high level VH, the first clock signal CLK1 can have a low level VL, and the second clock signal CLK2 can have a high level VH.

[0170] Since the first clock signal CLK1 remains at the low level VL, the first switching element T1 can remain in the on state and apply the input signal FLM / PCR having a high level VH to the third node N3 and the first node Q. Therefore, the voltage V_Q of the first node Q can have a high level VH. Accordingly, the second capacitor C2 can be charged with a voltage corresponding to the difference between the voltage of the seventh node N7 having a low level VL and the voltage of the eighth node N8 having a high level VH.

[0171] The third switching element T3 can be turned on in response to the first clock signal CLK1 having a low level VL, and the fourth switching element T4 can be turned on in response to the gate low voltage VGL. Therefore, the voltage of the seventh node N7 can have a low level VL, and the sixth switching element T6 can be turned on in response to the voltage of the seventh node N7 having a low level VL. The seventh switching element T7 can be turned off in response to the second clock signal CLK2 having a high level VH, and the voltage of the eighth node N8 can have a high level VH.

[0172] The fifth switching element T5 and the eighth switching element T8 can be turned off in response to the voltage V_Q of the first node Q having a high level VH, and the voltage V_QB of the second node QB can be maintained as the first low level VL1 of the previous level of the voltage V_QB of the second node QB through the first capacitor C1.

[0173] The tenth switching element T10 can be turned on in response to the voltage V_QB of the second node QB having a first low level VL1. Therefore, the tenth switching element T10 can apply the first clock signal CLK1 having a low level VL to the gate output node GS_ON. Therefore, a gate signal GS(n) having a low level VL can be output from the gate output node GS_ON.

[0174] As Figure 12 shown, in the third time period TP3, the input signal FLM / PCR may have a high level VH, the first clock signal CLK1 may have a low level VL, and the second clock signal CLK2 may have a low level VL.

[0175] The seventh switching element T7 may turn on in response to the second clock signal CLK2 having a low level VL, the third switching element T3 may turn on in response to the first clock signal CLK1 having a low level VL, and the fourth switching element T4 may turn on in response to the gate low voltage VGL. Accordingly, the voltage of the seventh node N7 may have a low level VL, and the sixth switching element T6 may turn on in response to the voltage of the seventh node N7 having a low level VL and apply the second clock signal CLK2 having a low level VL to the eighth node N8 and the second node QB. The voltage V_QB of the second node QB may have a first low level VL1, and the tenth switching element T10 may turn on in response to the voltage V_QB of the second node QB having the first low level VL1. Accordingly, the tenth switching element T10 may apply the first clock signal CLK1 having a low level VL to the gate output node GS_ON. Accordingly, a gate signal GS(n) having a low level VL may be output from the gate output node GS_ON.

[0176] As Figure 13 shown, in the fourth time period TP4, the input signal FLM / PCR may maintain a high level VH and then change from the high level VH to a low level VL, the first clock signal CLK1 may have a high level VH, and the second clock signal CLK2 may maintain a low level VL and then change from the low level VL to a high level VH.

[0177] The seventh switching element T7 may turn on in response to the second clock signal CLK2 having a low level VL, and the sixth switching element T6 may turn on in response to the voltage of the seventh node N7 having a low level VL held by the second capacitor C2 and apply the second clock signal CLK2 having a low level VL to the second node QB. Accordingly, the first capacitor C1 may be charged with a voltage corresponding to the difference between the high level VH of the first clock signal CLK1 and the first low level VL1 of the voltage V_QB of the second node QB.

[0178] The voltage V_QB of the second node QB may have a first low level VL1, and the tenth switching element T10 may turn on in response to the voltage V_QB of the second node QB having the first low level VL1. Therefore, the tenth switching element T10 may apply the first clock signal CLK1 having a high level VH to the gate output node GS_ON. Accordingly, a gate signal GS(n) having a high level VH may be output from the gate output node GS_ON.

[0179] As Figure 14 shown, in the fifth time period TP5, the input signal FLM / PCR may have a low level VL, the first clock signal CLK1 may have a low level VL, and the second clock signal CLK2 may have a high level VH.

[0180] The first switching element T1 may turn on in response to the first clock signal CLK1 having a low level VL. The ninth switching element T9 may turn on in response to the gate low voltage VGL. The first switching element T1 may apply the input signal FLM / PCR having a low level VL to the third node N3 and the first node Q. The first node Q may have the first low level VL1 similarly in the first time period TP1.

[0181] Since the seventh switching element T7 turns off in response to the second clock signal CLK2 having a high level VH, the first capacitor C1 may be floated, and when the fourth time period TP4 changes to the fifth time period TP5, the first clock signal CLK1 may change from a high level VH to a low level VL. Accordingly, the voltage V_QB of the second node QB may be boosted while maintaining the difference between the high level VH and the low level VL that is charged to the opposite electrode of the first capacitor C1. That is, the voltage V_QB of the second node QB may reduce the difference between the high level VH and the low level VL and change from the first low level VL1 to the second low level VL2.

[0182] The tenth switching element T10 may turn on in response to the voltage V_QB of the second node QB having the second low level VL2, and may apply the first clock signal CLK1 having a low level VL to the gate output node GS_ON. The eleventh switching element T11 may turn on in response to the voltage V_Q of the first node Q having the first low level VL1, and may apply the gate low voltage VGL to the gate output node GS_ON. Accordingly, a gate signal GS(n) having a low level VL may be output from the gate output node GS_ON.

[0183] In this way, the gate output circuit 420 may output a gate signal GS(n) having a high level VH in the fourth time period TP4.

[0184] AsFigure 15 As shown, in the sixth time period TP6, the input signal FLM / PCR may have a low level VL, the first clock signal CLK1 may have a low level VL, and the second clock signal CLK2 may have a low level VL.

[0185] Since the first clock signal CLK1 remains at the low level VL, the first switching element T1 may remain conducting, and the input signal FLM / PCR having the low level VL is applied to the third node N3 and the first node Q.

[0186] When the fifth time period TP5 changes to the sixth time period TP6, the second clock signal CLK2 may change from the high level VH to the low level VL. Therefore, the voltage V_Q of the first node Q can be boosted while maintaining the voltage charged to the opposite electrode of the third capacitor C3. That is, the voltage V_Q of the first node Q can reduce the difference between the high level VH and the low level VL, and change from the first low level VL1 to the second low level VL2.

[0187] In the first time period TP1, the second switching element T2 may conduct in response to the voltage V_Q of the first node Q having the first low level VL1, and the second clock signal CLK2 having the high level VH may be applied to the fourth node N4. Therefore, the third capacitor C3 can be charged with a voltage corresponding to the difference between the voltage V_Q of the first node Q having the first low level VL1 and the second clock signal CLK2 having the high level VH. When the fifth time period TP5 changes to the sixth time period TP6, the second clock signal CLK2 may change from the high level VH to the low level VL. Therefore, the voltage V_Q of the first node Q can be boosted while maintaining the difference between the high level VH and the low level VL that is charged to the opposite electrode of the third capacitor C3. That is, the voltage V_Q of the first node Q can reduce the difference between the high level VH and the low level VL, and change from the first low level VL1 to the second low level VL2.

[0188] Since the second low level VGL2 is lower than the low level VL, the eighth switching element T8 can be fully conducting, and the first clock signal CLK1 having the low level VL can be applied to the second node QB. Therefore, the voltage V_QB of the second node QB can have the low level VL.

[0189] The tenth switching element T10 can be turned on in response to the voltage V_QB of the second node QB having a low level VL, and can apply the first clock signal CLK1 having a low level VL to the gate output node GS_ON. The eleventh switching element T11 can be turned on in response to the voltage V_Q of the first node Q having a second low level VL2, and can apply the gate low voltage VGL to the gate output node GS_ON. Accordingly, a gate signal GS(n) having a low level VL can be output from the gate output node GS_ON.

[0190] As Figure 16 shown, in the seventh time period TP7, the input signal FLM / PCR can have a low level VL, the first clock signal CLK1 can have a high level VH, and the second clock signal CLK2 can have a low level VL.

[0191] The voltage V_Q of the first node Q can maintain the second low level VL2. In response to the voltage V_Q of the first node Q having the second low level VL2, the eighth switching element T8 can be turned on, and the eighth switching element T8 can apply the first clock signal CLK1 having a high level VH to the second node QB. The fifth switching element T5 can be turned on in response to the voltage V_Q of the first node Q having the second low level VL2, and the fifth switching element T5 and the fourth switching element T4 can apply the first clock signal CLK1 having a high level VH to the seventh node N7. The sixth switching element T6 can be turned off in response to the voltage of the seventh node N7 having a high level VH, and the voltage of the eighth node N8 can have a high level VH through the second capacitor C2. The seventh switching element T7 can be turned on in response to the second clock signal CLK2 having a low level VL, and can apply the voltage of the eighth node N8 having a high level VH to the second node QB.

[0192] The eleventh switching element T11 can be turned on in response to the voltage V_Q of the first node Q having the second low level VL2, and can apply the gate low voltage VGL to the gate output node GS_ON. Accordingly, a gate signal GS(n) having a low level VL can be output from the gate output node GS_ON.

[0193] As Figure 17 shown, in the eighth time period TP8, the input signal FLM / PCR can have a low level VL, the first clock signal CLK1 can have a high level VH, and the second clock signal CLK2 can have a high level VH.

[0194] The voltage V_Q of the first node Q can have a first low level VL1, and the voltage V_QB of the second node QB can have a high level VH.

[0195] The eleventh switching element T11 can be turned on in response to the voltage V_Q of the first node Q having a first low level VL1, and can apply a gate low voltage VGL to the gate output node GS_ON. Accordingly, a gate signal GS(n) having a low level VL can be output from the gate output node GS_ON.

[0196] Figure 18 is a timing chart showing the input signal FLM / PCR, the first clock signal CLK1, the second clock signal CLK2, the node signals (i.e., the voltage V_Q of the first node Q and the voltage V_QB of the second node QB), and the output signal (i.e., the gate signal GS(n)) of each stage 400 when the enable signal EN has an inactive level Figure 8 Figure 19 is a circuit diagram showing Figure 8 the operation of each stage 400 Figure 18 in a first time period t1 Figure 20 is a circuit diagram showing Figure 8 the operation of each stage 400 Figure 18 in a second time period t2 Figure 21 is a circuit diagram showing Figure 8 the operation of each stage 400 Figure 18 in a third time period t3 Figure 22 is a circuit diagram showing Figure 8 the operation of each stage 400 Figure 18 in a fourth time period t4 Figure 23 is a circuit diagram showing Figure 8 the operation of each stage 400 Figure 18 in a fifth time period t5

[0197] Referring to Figure 8 and Figures 18 to 23 the operation of each stage 400 when the first control switching element TC1 is turned off in response to the enable signal EN having an inactive level can be described. One horizontal time 1H can be the time allotted to each pixel row of the display panel 100.

[0198] The control circuit 410 can include a first control switching element TC1 that selectively controls the voltage V_Q of the first node Q in response to the enable signal EN. The gate output circuit 420 can selectively output the gate signal GS(n) according to the enable signal EN.

[0199] When the enable signal EN has an active level, the first control switching element TC1 can transfer the voltage of the third node N3 to the fifth node N5 and the first node Q, and the voltage V_Q of the first node Q can be changed according to the input signal FLM / PCR.

[0200] ​On the other hand, when the enable signal EN has a non-effective level, the first control switch element TC1 may not transfer the voltage of the third node N3 to the fifth node N5 and the first node Q, and the voltage V_Q of the first node Q may be maintained below a specific level.

[0201] As Figure 19 shown, in the first time period t1, the input signal FLM / PCR may have a low level VL, the first clock signal CLK1 may have a low level VL, the second clock signal CLK2 may have a high level VH, and the enable signal EN may have a low level VL.

[0202] The first switch element T1 may be turned on in response to the first clock signal CLK1 having a low level VL. The first control switch element TC1 may be turned on in response to the enable signal EN having a low level VL. The ninth switch element T9 may be turned on in response to the gate low voltage VGL. The first switch element T1 may apply the input signal FLM / PCR having a low level VL to the third node N3 and the first node Q. Due to the characteristics of the P-type transistor, even if the input signal FLM / PCR has a low level VL, the first node Q may have a first low level VL1 which is the low level VL reduced by the threshold voltage of the first switch element T1, the threshold voltage of the first control switch element TC1, or the threshold voltage of the ninth switch element T9.

[0203] The eighth switch element T8 may be turned on in response to the voltage V_Q of the first node Q having the first low level VL1, and may apply the first clock signal CLK1 having a low level VL to the second node QB. However, since the first low level VL1 is higher than the low level VL, the eighth switch element T8 may not be fully turned on. Therefore, the voltage V_QB of the second node QB may have a first low level VL1 higher than the low level VL.

[0204] The tenth switch element T10 may be turned on in response to the voltage V_QB of the second node QB being the first low level VL1, and may apply the first clock signal CLK1 having a low level VL to the gate output node GS_ON. The eleventh switch element T11 may be turned on in response to the voltage V_Q of the first node Q having the first low level VL1, and may apply the gate low voltage VGL to the gate output node GS_ON. Therefore, a gate signal GS(n) having a low level VL may be output from the gate output node GS_ON.

[0205] As Figure 20As shown, in the second time period t2, the input signal FLM / PCR may remain at the low level VL and then change from the low level VL to the high level VH. The first clock signal CLK1 may have the low level VL, the second clock signal CLK2 may have the high level VH, and the enable signal EN may have the high level VH.

[0206] The first control switch element TC1 may turn off in response to the enable signal EN having the high level VH. Therefore, the first control switch element TC1 may not transfer the voltage of the third node N3 to the fifth node N5 and the first node Q.

[0207] The voltage V_Q of the first node Q may be held as a first low level VL1, which is the previous level of the voltage V_Q of the first node Q, through the third capacitor C3.

[0208] The voltage V_QB of the second node QB may have the first low level VL1 as in the first time period t1.

[0209] The tenth switch element T10 may turn on in response to the voltage V_QB of the second node QB having the first low level VL1 and may apply the first clock signal CLK1 having the low level VL to the gate output node GS_ON. The eleventh switch element T11 may turn on in response to the voltage V_Q of the first node Q having the first low level VL1 and may apply the gate low voltage VGL to the gate output node GS_ON. Therefore, a gate signal GS(n) having the low level VL may be output from the gate output node GS_ON.

[0210] As Figure 21 As shown, in the third time period t3, the input signal FLM / PCR may have the high level VH, the first clock signal CLK1 may have the low level VL, the second clock signal CLK2 may have the low level, and the enable signal EN may have the high level VH.

[0211] The first control switch element TC1 may turn off in response to the enable signal EN having the high level VH. Therefore, the first control switch element TC1 may not transfer the voltage of the third node N3 to the fifth node N5 and the first node Q.

[0212] When the second time period t2 changes to the third time period t3, the second clock signal CLK2 may change from the high level VH to the low level VL. Therefore, the voltage V_Q of the first node Q may be boosted by the difference between the high level VH and the low level VL through the third capacitor C3. That is, the voltage V_Q of the first node Q may be boosted from the first low level VL1 to a second low level VL2 through the third capacitor C3.

[0213] Since the second low level VL2 is lower than the low level VL, the eighth switching element T8 can be fully turned on and can apply the first clock signal CLK1 having the low level VL to the second node QB. Therefore, the voltage V_QB of the second node QB can have the low level VL.

[0214] The tenth switching element T10 can be turned on in response to the voltage V_QB of the second node QB having the low level VL, and can apply the first clock signal CLK1 having the low level VL to the gate output node GS_ON. The eleventh switching element T11 can be turned on in response to the voltage V_Q of the first node Q having the second low level VL2, and can apply the gate low voltage VGL to the gate output node GS_ON. Therefore, the gate signal GS(n) having the low level VL can be output at the gate output node GS_ON.

[0215] As Figure 22 shown, in the fourth time period t4, the input signal FLM / PCR can have the high level VH, the first clock signal CLK1 can have the high level VH, the second clock signal CLK2 can have the low level VL, and the enable signal EN can have the high level VH.

[0216] The first control switching element TC1 can be turned off in response to the enable signal EN having the high level VH. Therefore, the first control switching element TC1 can not transfer the voltage of the third node N3 to the fifth node N5 and the first node Q.

[0217] The voltage V_Q of the first node Q can be held as the second low level VL2 of the previous level of the voltage V_Q of the first node Q through the third capacitor C3. The eighth switching element T8 can be turned on in response to the voltage V_Q of the first node Q having the second low level VL2, and the eighth switching element T8 can apply the first clock signal CLK1 having the high level VH to the second node QB.

[0218] The eleventh switching element T11 can be turned on in response to the voltage V_Q of the first node Q having the second low level VL2, and can apply the gate low voltage VGL to the gate output node GS_ON. Therefore, the gate signal GS(n) having the low level VL can be output from the gate output node GS_ON.

[0219] As Figure 23As shown, in the fifth time period t5, the input signal FLM / PCR may remain at the high level VH and then change from the high level VH to the low level VL. The first clock signal CLK1 may have the high level VH, the second clock signal CLK2 may remain at the low level VL and then change from the low level VL to the high level VH, and the enable signal EN may have the low level VL. Since the first switching element T1 may be turned off in response to the first clock signal CLK1 having the high level VH, the voltage V_Q of the first node Q may maintain the previous level of the voltage V_Q of the first node Q through the third capacitor C3. When the second clock signal CLK2 changes from the low level VL to the high level VH, the voltage V_Q of the first node Q may be boosted through the third capacitor C3. That is, the voltage V_Q of the first node Q may change from the second low level VL2 to the first low level VL1.

[0220] The eighth switching element T8 may be turned on in response to the voltage V_Q of the first node Q having the first low level VL1, and the eighth switching element T8 may apply the first clock signal CLK1 having the high level VH to the second node QB.

[0221] The eleventh switching element T11 may be turned on in response to the voltage V_Q of the first node Q having the second low level VL2 or the first low level VL1, and may apply the gate low voltage VGL to the gate output node GS_ON. Thus, the gate signal GS(n) having the low level VL may be output from the gate output node GS_ON.

[0222] In this way, the gate driver 300 (see Figure 5 ) and the display device may include the control circuit 410 and the gate output circuit 420, and the control circuit 410 may include the first control switching element TC1. The first control switching element TC1 selectively connects the first node Q and the gate output circuit 420 in response to the enable signal EN, so that the driving frequency multiple division can be supported. Through the driving frequency multiple division, the power consumption of the display device can be effectively reduced.

[0223] Figure 24 is a circuit diagram showing another example (hereinafter, each stage 400a) of each stage 400 Figure 7 .

[0224] Referring to Figure 24 , each stage 400a may include a control circuit 410a and a gate output circuit 420a. The control circuit 410a may control the voltage V_Q' of the first node Q' (see Figure 25 ) and the voltage V_QB' of the second node QB' (seeFigure 25 )。The control circuit 410a may include a first control switch element TC1' that selectively connects the first node Q' and the gate output circuit 420a in response to an enable signal EN'. The gate output circuit 420a may output a gate signal GS(n)' in response to the voltage V_Q' of the first node Q' and the voltage V_QB' of the second node QB'. In an embodiment, the gate signal GS(n)' may be a data write gate signal GW[n] applied to the pixel (see Figure 3 ).

[0225] The control circuit 410a may include a first switch element T1'. The control circuit 410a may further include a first control switch element TC1'. The control circuit 410a may further include a sixth switch element T6'. The control circuit 410a may further include a second switch element T2', a third switch element T3', a fourth switch element T4', and a fifth switch element T5'.

[0226] The first switch element T1' may include a gate electrode that receives a first clock signal CLK1', a first electrode that receives an input signal FLM / PCR', and a second electrode that is connected to a third node N3'.

[0227] The second switch element T2' may include a gate electrode that is connected to the second node QB', a first electrode that receives a gate high voltage VGH, and a second electrode that is connected to a fourth node N4'.

[0228] The third switch element T3' may include a gate electrode that receives a second clock signal CLK2', a first electrode that is connected to the fourth node N4', and a second electrode that is connected to the third node N3'.

[0229] The fourth switch element T4' may include a gate electrode that receives a first clock signal CLK1', a first electrode that receives a gate low voltage VGL, and a second electrode that is connected to the second node QB'.

[0230] The first control switch element TC1' may include a gate electrode that receives an enable signal EN', a first electrode that is connected to a fifth node N5', and a second electrode that is connected to the first node Q'. In an embodiment, the first control switch element TC1' may include a first sub-switch element (not shown) and a second sub-switch element (not shown). That is, the first control switch element TC1' may have a dual-transistor structure including two transistors.

[0231] The fifth switch element T5' may include a gate electrode that is connected to the third node N3', a first electrode that receives a first clock signal CLK1', and a second electrode that is connected to the second node QB'.

[0232] The sixth switching element T6' may include a gate electrode receiving a gate low voltage VGL, a first electrode connected to the third node N3', and a second electrode connected to the fifth node N5'.

[0233] The gate output circuit 420a may include a seventh switching element T7' and an eighth switching element T8'. The gate output circuit 420a may further include a first capacitor C1' and a second capacitor C2'.

[0234] The seventh switching element T7' may include a gate electrode connected to the second node QB', a first electrode receiving a gate high voltage VGH, and a second electrode connected to the gate output node GS_ON'.

[0235] The eighth switching element T8' may include a gate electrode connected to the first node Q', a first electrode receiving a second clock signal CLK2', and a second electrode connected to the gate output node GS_ON'.

[0236] The first capacitor C1' may include a first electrode connected to the first node Q' and a second electrode connected to the gate output node GS_ON'. The first capacitor C1' may store the voltage difference between the voltage of the gate output node GS_ON' and the voltage V_Q' of the first node Q'.

[0237] The second capacitor C2' may include a first electrode receiving a gate high voltage VGH and a second electrode connected to the second node QB'. The second capacitor C2' may store the voltage difference between the gate high voltage VGH and the voltage V_QB' of the second node QB'.

[0238] Leakage current may be generated more in P-type transistors than in N-type transistors. Therefore, some of the switching elements included in each stage 400a may be N-type transistors. For example, the first control switching element TC1' may be an N-type transistor, and the first switching element T1' to the eighth switching element T8' may be P-type transistors.

[0239] In this embodiment, some of the switching elements of each stage 400a are N-type transistors, and the others of the switching elements are P-type transistors. However, the present invention is not limited thereto. In another embodiment, the present invention may also be applied to each stage including only P-type transistors.

[0240] Figure 25 is a timing diagram showing Figure 24 the input signal FLM / PCR', the first clock signal CLK1', the second clock signal CLK2', the node signals (i.e., the voltage V_Q' of the first node Q' and the voltage V_QB' of the second node QB'), and the output signal (i.e., the gate signal GS(n)') of each stage 400a.

[0241] Figure 26 shows the Figure 24 operation of each stage 400a during Figure 25 the first time period TP1' of Figure 27 shows the Figure 24 operation of each stage 400a during Figure 25 the second time period TP2' of Figure 28 shows the Figure 24 operation of each stage 400a during Figure 25 the third time period TP3' of Figure 29 shows the Figure 24 operation of each stage 400a during Figure 25 the fourth time period TP4' of Figure 30 shows the Figure 24 operation of each stage 400a during Figure 25 the fifth time period TP5' of

[0242] Refer to Figures 24 to 30 to describe the operation of each stage 400a when the first control switch element TC1' remains in the conducting state in response to an enable signal EN' having an active level. The 1 horizontal time 1H can be the time assigned to each pixel row of the display panel 100.

[0243] As Figure 26 shown, during the first time period TP1', the input signal FLM / PCR' can have a low level VL', the first clock signal CLK1' can have a low level VL', and the second clock signal CLK2' can have a high level VH'.

[0244] The first switch element T1' can conduct in response to the first clock signal CLK1' having a low level VL'. The sixth switch element T6' can conduct in response to the gate low voltage VGL. The first switch element T1' can apply the input signal FLM / PCR' to the third node N3' and the first node Q'. Thus, the first node Q' can have a low level VL' corresponding to the input signal FLM / PCR', and the first capacitor C1' can be charged.

[0245] The fourth switch element T4' can conduct in response to the first clock signal CLK1' having a low level VL'. The fourth switch element T4' can apply the gate low voltage VGL to the second node QB'. Thus, the second node QB' can have a low level VL' corresponding to the gate low voltage VGL, and the second capacitor C2' can be charged.

[0246] The eighth switching element T8' can be turned on in response to the voltage V_Q' of the first node Q' having a low level VL', and can apply the second clock signal CLK2' having a high level VH' to the gate output node GS_ON'. Accordingly, a gate signal GS(n)' having a high level VH' can be output from the gate output node GS_ON'.

[0247] The seventh switching element T7' can be turned on in response to the voltage V_QB' of the second node QB' being a low level VL', and can apply the gate high voltage VGH to the gate output node GS_ON'. Accordingly, a gate signal GS(n)' having a high level VH' can be output from the gate output node GS_ON'.

[0248] As Figure 27 shown, in the second time period TP2', the input signal FLM / PCR' can have a high level VH', the first clock signal CLK1' can have a high level VH', and the second clock signal CLK2' can have a high level VH'. The voltage of the third node N3' can be equal to the voltage V_Q' of the first node Q' having a low level VL'.

[0249] The fifth switching element T5' can be turned on in response to the voltage of the third node N3' having a low level VL', and can apply the first clock signal CLK1' having a high level VH' to the second node QB'. Accordingly, the second node QB' can have a high level VH' in response to the first clock signal CLK1' having a high level VH', and the second capacitor C2' can be discharged.

[0250] As Figure 28 shown, in the third time period TP3', the input signal FLM / PCR' can have a high level VH', the first clock signal CLK1' can have a high level VH', and the second clock signal CLK2' can have a low level VL'.

[0251] The first switching element T1' can be turned off in response to the first clock signal CLK1' having a high level VH'. When the second time period TP2' changes to the third time period TP3', the voltage V_Q' of the first node Q' can change from a low level VL' to a second low level VL2' through the first capacitor C1'. The second low level VL2' can be lower than the low level VL'. Since the fifth switching element T5' continuously applies the first clock signal CLK1' having a high level VH' to the second node QB', the voltage V_QB' of the second node QB' can remain at the high level VH'. Therefore, the eighth switching element T8' can remain in the on state in response to the voltage V_Q' of the first node Q' having the second low level VL2', and can apply the second clock signal CLK2' having a low level VL' to the gate output node GS_ON'. Therefore, a gate signal GS(n)' having a low level VL' can be output from the gate output node GS_ON'.

[0252] As Figure 29 shown, in the fourth time period TP4', the input signal FLM / PCR' can have a high level VH', the first clock signal CLK1' can have a high level VH', the second clock signal CLK2' can have a low level VL', and the voltage V_Q' of the first node Q' can have a low level VL'. The eighth switching element T8' can remain in the on state in response to the voltage V_Q' of the first node Q' having a low level VL', and can apply the second clock signal CLK2' having a high level VH' to the gate output node GS_ON'. Therefore, a gate signal GS(n)' having a high level VH' can be output from the gate output node GS_ON'.

[0253] In this way, the gate output circuit 420a can output the gate signal GS(n)' in the second time period TP2' to the fourth time period TP4'.

[0254] As Figure 30 shown, in the fifth time period TP5', the input signal FLM / PCR' can have a high level VH', the first clock signal CLK1' can have a low level VL', and the second clock signal CLK2' can have a high level VH'.

[0255] When the first clock signal CLK1' has a low level VL', the first switching element T1' can be turned on in response to the first clock signal CLK1'. The sixth switching element T6' can be turned on in response to the gate low voltage VGL, and the first control switching element TC1' can be turned on in response to the enable signal EN' having an effective level.

[0256] The first switching element T1' can apply the input signal FLM / PCR' to the third node N3' and the first node Q'. Accordingly, the third node N3' and the first node Q' can have a high level VH' corresponding to the input signal FLM / PCR'.

[0257] The eighth switching element T8' can be turned off in response to the voltage V_Q' of the first node Q'.

[0258] The first capacitor C1' can store the voltage difference between the voltage of the gate output node GS_ON' and the voltage V_Q' of the first node Q'.

[0259] The fourth switching element T4' can be turned on in response to the first clock signal CLK1' having a low level VL'. The fourth switching element T4' can apply the gate low voltage VGL to the second node QB'. Accordingly, the second node QB' can have a low level VL' in response to the gate low voltage VGL.

[0260] The seventh switching element T7' can be turned on in response to the voltage V_QB' of the second node QB', and can apply the gate high voltage VGH to the gate output node GS_ON'. Accordingly, a gate signal GS(n)' having a high level VH' can be output from the gate output node GS_ON'.

[0261] The second capacitor C2' can store the voltage difference between the gate high voltage VGH and the voltage V_QB' of the second node QB'.

[0262] Figure 31 is a circuit diagram showing Figure 24 the operation of each stage 400a when the enable signal EN' has an inactive level.

[0263] Refer to Figures 24 to 31 , the control circuit 410a can include a first control switching element TC1' that selectively controls the voltage V_Q' of the first node Q' in response to the enable signal EN'. The gate output circuit 420a can selectively output the gate signal GS(n)' according to the enable signal EN'.

[0264] When the enable signal EN' has an active level, the first control switching element TC1' can transfer the voltage of the third node N3' to the fifth node N5' and the first node Q', and the voltage V_Q' of the first node Q' can be changed according to the input signal FLM / PCR'.

[0265] On the other hand, when the enable signal EN' has a non-effective level, the first control switch element TC1' may not transfer the voltage of the third node N3' to the fifth node N5' and the first node Q'. The voltage stored in the first capacitor C1' may not be lost. Therefore, the voltage V_Q' of the first node Q' may remain at the high level VH' stored by the first capacitor C1'. The voltage V_QB' of the second node QB' may remain at the low level VL'.

[0266] The seventh switch element T7' may be turned on in response to the voltage V_QB' of the second node QB' having the low level VL', and may apply the gate high voltage VGH to the gate output node GS_ON'. Therefore, a gate signal GS(n)' having the high level VH' may be output from the gate output node GS_ON'.

[0267] In this way, the gate driver 300 (see Figure 5 ) and the display device may include a control circuit 410a and a gate output circuit 420a, and the control circuit 410a may include a first control switch element TC1', and the first control switch element TC1' selectively controls the voltage V_Q' of the first node Q' in response to the enable signal EN' such that the driving frequency multiple division is supported. By the driving frequency multiple division, the power consumption of the display device can be effectively reduced.

[0268] Figure 32 is a circuit diagram showing Figure 7 yet another example (hereinafter, each stage 400b) of each stage 400.

[0269] Referring to Figure 24 and Figure 32 , each stage 400b may include a control circuit 410b and a gate output circuit 420b. The control circuit 410b may control the voltage V_Q' of the first node Q' (see Figure 25 ) and the voltage V_QB' of the second node QB' (see Figure 25 ) in response to the input signal FLM / PCR', the first clock signal CLK1' and the second clock signal CLK2'. The control circuit 410b may include a first control switch element TC1' that selectively connects the first node Q' and the gate output circuit 420b in response to the enable signal EN' and a second control switch element TC2' that selectively connects the second node QB' and the gate output circuit 420b in response to the enable signal EN'. The gate output circuit 420b may output a gate signal GS(n)' in response to the voltage V_Q' of the first node Q' and the voltage V_QB' of the second node QB'. In an embodiment, the gate signal GS(n)' may be a data write gate signal GW[n] applied to a pixel (see Figure 3 ).

[0270] Except that a second control switch element TC2' is added, each stage 400b described with reference to Figure 32 can be substantially equivalent to or similar to each stage 400a described with reference to Figure 24 Thus, the description of repetitive components is omitted.

[0271] The control circuit 410b may include a first switch element T1'. The control circuit 410b may also include a first control switch element TC1'. The control circuit 410b may also include a sixth switch element T6'. The control circuit 410b may also include a second control switch element TC2'. The control circuit 410b may also include a second switch element T2', a third switch element T3', a fourth switch element T4', and a fifth switch element T5'.

[0272] The first switch element T1' may include a gate electrode that receives a first clock signal CLK1', a first electrode that receives an input signal FLM / PCR', and a second electrode that is connected to a third node N3'.

[0273] The second switch element T2' may include a gate electrode that is connected to a sixth node N6', a first electrode that receives a gate high voltage VGH, and a second electrode that is connected to a fourth node N4'.

[0274] The third switch element T3' may include a gate electrode that receives a second clock signal CLK2', a first electrode that is connected to the fourth node N4', and a second electrode that is connected to the third node N3'.

[0275] The fourth switch element T4' may include a gate electrode that receives the first clock signal CLK1', a first electrode that receives a gate low voltage VGL, and a second electrode that is connected to the sixth node N6'.

[0276] The first control switch element TC1' may include a gate electrode that receives an enable signal EN', a first electrode that is connected to a fifth node N5', and a second electrode that is connected to a first node Q'. In an embodiment, the first control switch element TC1' may include a first sub-switch element (not shown) and a second sub-switch element (not shown). That is, the first control switch element TC1' may have a dual-transistor structure including two transistors.

[0277] The second control switch element TC2' may include a gate electrode receiving an enable signal EN', a first electrode connected to the sixth node N6', and a second electrode connected to the second node QB'. In an embodiment, the second control switch element TC2' may include a third sub-switch element (not shown) and a fourth sub-switch element (not shown). That is, the second control switch element TC2' may have a dual-transistor structure including two transistors.

[0278] The fifth switch element T5' may include a gate electrode connected to the third node N3', a first electrode receiving the first clock signal CLK1', and a second electrode connected to the sixth node N6'.

[0279] The sixth switch element T6' may include a gate electrode receiving a gate low voltage VGL, a first electrode connected to the third node N3', and a second electrode connected to the fifth node N5'.

[0280] The gate output circuit 420b may include a seventh switch element T7' and an eighth switch element T8'. The gate output circuit 420b may further include a first capacitor C1' and a second capacitor C2'.

[0281] The seventh switch element T7' may include a gate electrode connected to the second node QB', a first electrode receiving a gate high voltage VGH, and a second electrode connected to the gate output node GS_ON'.

[0282] The eighth switch element T8' may include a gate electrode connected to the first node Q', a first electrode receiving the second clock signal CLK2', and a second electrode connected to the gate output node GS_ON'.

[0283] The first capacitor C1' may include a first electrode connected to the first node Q' and a second electrode connected to the gate output node GS_ON'. The first capacitor C1' may store the voltage difference between the voltage of the gate output node GS_ON' and the voltage V_Q' of the first node Q'.

[0284] The second capacitor C2' may include a first electrode receiving the gate high voltage VGH and a second electrode connected to the second node QB'. The second capacitor C2' may store the voltage difference between the gate high voltage VGH and the voltage V_QB' of the second node QB'.

[0285] Leakage current may be generated more in P-type transistors than in N-type transistors. Therefore, some of the switch elements included in each stage 400b may be N-type transistors. For example, the first control switch element TC1' and the second control switch element TC2' may be N-type transistors, and the first switch element T1' to the eighth switch element T8' may be P-type transistors.

[0286] In this embodiment, some of the switching elements in each stage 400b are illustrated as N-type transistors and some of the other switching elements are P-type transistors, but the present invention is not limited thereto. In another embodiment, the present invention can also be applied to each stage including only P-type transistors.

[0287] Figure 33 is a diagram showing Figure 7 another example of each stage 400 (hereinafter, each stage 400c).

[0288] Referring to Figure 24 and Figure 33 , each stage 400c may include a control circuit 410c and a gate output circuit 420c. The control circuit 410c may control the voltage V_Q' of the first node Q' (see Figure 25 ) and the voltage V_QB' of the second node QB' (see Figure 25 ) in response to the input signal FLM / PCR', the first clock signal CLK1', and the second clock signal CLK2'. The control circuit 410c may include a first control switching element TC1' that selectively connects the first node Q' and the gate output circuit 420c in response to the enable signal EN'. The gate output circuit 420c may output a gate signal GS(n)' in response to the voltage V_Q' of the first node Q' and the voltage V_QB' of the second node QB'. In an embodiment, the gate signal GS(n)' may be a data write gate signal GW[n] applied to the pixel (see Figure 3 ).

[0289] Except for the position of the first control switching element TC1', each stage 400c described with reference to Figure 33 may be substantially equivalent to or similar to each stage 400a described with reference to Figure 24 . Therefore, the description of the repeated components is omitted.

[0290] The control circuit 410c may include a first switching element T1'. The control circuit 410c may further include a first control switching element TC1'. The control circuit 410c may further include a sixth switching element T6'. The control circuit 410c may further include a second switching element T2', a third switching element T3', a fourth switching element T4', and a fifth switching element T5'.

[0291] The first switching element T1' may include a gate electrode receiving the first clock signal CLK1', a first electrode receiving the input signal FLM / PCR', and a second electrode connected to the third node N3'.

[0292] The second switching element T2' may include a gate electrode connected to the second node QB', a first electrode receiving a gate high voltage VGH, and a second electrode connected to the fourth node N4'.

[0293] The third switching element T3' may include a gate electrode receiving the second clock signal CLK2', a first electrode connected to the fourth node N4', and a second electrode connected to the third node N3'.

[0294] The fourth switching element T4' may include a gate electrode receiving the first clock signal CLK1', a first electrode receiving a gate low voltage VGL, and a second electrode connected to the second node QB'.

[0295] The first control switching element TC1' may include a gate electrode receiving an enable signal EN', a first electrode connected to the third node N3', and a second electrode connected to the fifth node N5'. In an embodiment, the first control switching element TC1' may include a first sub-switching element (not shown) and a second sub-switching element (not shown). That is, the first control switching element TC1' may have a dual-transistor structure including two transistors.

[0296] The fifth switching element T5' may include a gate electrode connected to the third node N3', a first electrode receiving the first clock signal CLK1', and a second electrode connected to the second node QB'.

[0297] The sixth switching element T6' may include a gate electrode receiving a gate low voltage VGL, a first electrode connected to the fifth node N5', and a second electrode connected to the first node Q'.

[0298] The gate output circuit 420c may include a seventh switching element T7' and an eighth switching element T8'. The gate output circuit 420c may further include a first capacitor C1' and a second capacitor C2'.

[0299] The seventh switching element T7' may include a gate electrode connected to the second node QB', a first electrode receiving a gate high voltage VGH, and a second electrode connected to the gate output node GS_ON'.

[0300] The eighth switching element T8' may include a gate electrode connected to the first node Q', a first electrode receiving the second clock signal CLK2', and a second electrode connected to the gate output node GS_ON'.

[0301] The first capacitor C1' may include a first electrode connected to the first node Q' and a second electrode connected to the gate output node GS_ON'. The first capacitor C1' may store the voltage difference between the voltage of the gate output node GS_ON' and the voltage V_Q' of the first node Q'.

[0302] The second capacitor C2' may include a first electrode receiving the gate high voltage VGH and a second electrode connected to the second node QB'. The second capacitor C2' may store the voltage difference between the gate high voltage VGH and the voltage V_QB' of the second node QB'.

[0303] Leakage current may be generated more in P-type transistors than in N-type transistors. Therefore, some of the switching elements included in each stage 400c may be N-type transistors. For example, the first control switching element TC1' may be an N-type transistor, and the first switching element T1' to the eighth switching element T8' may be P-type transistors.

[0304] In the present embodiment, some of the switching elements of each stage 400c are illustrated as N-type transistors and some of the other switching elements are P-type transistors, but the present invention is not limited thereto. In another embodiment, the present invention may also be applied to each stage including only P-type transistors.

[0305] Figure 34 is a circuit diagram showing Figure 7 yet another example of each stage 400 (hereinafter, each stage 400d).

[0306] Referring to Figure 24 and Figure 34 , each stage 400d may include a control circuit 410d and a gate output circuit 420d. The control circuit 410d may control the voltage V_Q' of the first node Q' (see Figure 25 ) and the voltage V_QB' of the second node QB' (see Figure 25 ) in response to the input signal FLM / PCR', the first clock signal CLK1', and the second clock signal CLK2'. The control circuit 410d may include a first control switching element TC1' that selectively connects the first node Q' and the gate output circuit 420d in response to the enable signal EN' and a second control switching element TC2' that selectively connects the second node QB' and the gate output circuit 420d in response to the enable signal EN'. The gate output circuit 420d may output a gate signal GS(n)' in response to the voltage V_Q' of the first node Q' and the voltage V_QB' of the second node QB'. In an embodiment, the gate signal GS(n)' may be a data write gate signal GW[n] applied to the pixel (see Figure 3 ).

[0307] Except for the position of the first control switch element TC1' and the additional second control switch element TC2', each stage 400d described with reference to Figure 34 can be substantially equivalent to or similar to each stage 400a described with reference to Figure 24 . Therefore, the description of the repetitive components is omitted.

[0308] The control circuit 410d can include a first switch element T1'. The control circuit 410d can also include a first control switch element TC1'. The control circuit 410d can also include a sixth switch element T6'. The control circuit 410d can also include a second control switch element TC2'. The control circuit 410d can also include a second switch element T2', a third switch element T3', a fourth switch element T4', and a fifth switch element T5'.

[0309] The first switch element T1' can include a gate electrode receiving a first clock signal CLK1', a first electrode receiving an input signal FLM / PCR', and a second electrode connected to a third node N3'.

[0310] The second switch element T2' can include a gate electrode connected to a sixth node N6', a first electrode receiving a gate high voltage VGH, and a second electrode connected to a fourth node N4'.

[0311] The third switch element T3' can include a gate electrode receiving a second clock signal CLK2', a first electrode connected to the fourth node N4', and a second electrode connected to the third node N3'.

[0312] The fourth switch element T4' can include a gate electrode receiving the first clock signal CLK1', a first electrode receiving a gate low voltage VGL, and a second electrode connected to the sixth node N6'.

[0313] The first control switch element TC1' can include a gate electrode receiving an enable signal EN', a first electrode connected to the third node N3', and a second electrode connected to a fifth node N5'. In an embodiment, the first control switch element TC1' can include a first sub-switch element (not shown) and a second sub-switch element (not shown). That is, the first control switch element TC1' can have a dual-transistor structure including two transistors.

[0314] The second control switch element TC2' may include a gate electrode that receives an enable signal EN', a first electrode connected to the sixth node N6', and a second electrode connected to the second node QB'. In an embodiment, the second control switch element TC2' may include a third sub-switch element (not shown) and a fourth sub-switch element (not shown). That is, the second control switch element TC2' may have a dual-transistor structure including two transistors.

[0315] The fifth switch element T5' may include a gate electrode connected to the third node N3', a first electrode that receives the first clock signal CLK1', and a second electrode connected to the sixth node N6'.

[0316] The sixth switch element T6' may include a gate electrode that receives a gate low voltage VGL, a first electrode connected to the fifth node N5', and a second electrode connected to the first node Q'.

[0317] The gate output circuit 420d may include a seventh switch element T7' and an eighth switch element T8'. The gate output circuit 420d may further include a first capacitor C1' and a second capacitor C2'.

[0318] The seventh switch element T7' may include a gate electrode connected to the second node QB', a first electrode that receives a gate high voltage VGH, and a second electrode connected to the gate output node GS_ON'.

[0319] The eighth switch element T8' may include a gate electrode connected to the first node Q', a first electrode that receives a second clock signal CLK2', and a second electrode connected to the gate output node GS_ON'.

[0320] The first capacitor C1' may include a first electrode connected to the first node Q' and a second electrode connected to the gate output node GS_ON'. The first capacitor C1' may store the voltage difference between the voltage of the gate output node GS_ON' and the voltage V_Q' of the first node Q'.

[0321] The second capacitor C2' may include a first electrode that receives a gate high voltage VGH and a second electrode connected to the second node QB'. The second capacitor C2' may store the voltage difference between the gate high voltage VGH and the voltage V_QB' of the second node QB'.

[0322] Leakage current may be generated more in P-type transistors than in N-type transistors. Therefore, some of the switch elements included in each stage 400d may be N-type transistors. For example, the first control switch element TC1' and the second control switch element TC2' may be N-type transistors, and the first switch element T1' to the eighth switch element T8' may be P-type transistors.

[0323] In this embodiment, some of the switching elements in each stage 400d are illustrated as N-type transistors and some of the other switching elements are P-type transistors, but the present invention is not limited thereto. In another embodiment, the present invention can also be applied to each stage including only P-type transistors.

[0324] Figure 35 is a circuit diagram showing Figure 7 another example of each stage 400 (hereinafter, each stage 400e).

[0325] Referring to Figure 35 , each stage 400e may include a control circuit 410e and a gate output circuit 420e. The control circuit 410e may control the voltage V_Q” of the first node Q” (see Figure 36 ) and the voltage V_QB” of the second node QB” (see Figure 36 ) in response to the input signal “FLM / PCR”, the first clock signal CLK1” and the second clock signal CLK2”. The control circuit 410e may include a first control switch element TC1” that selectively connects the first node Q” and the gate output circuit 420e in response to the enable signal EN” and a second control switch element TC2” that selectively connects the second node QB” and the gate output circuit 420e in response to the enable signal EN”. The gate output circuit 420e may output a gate signal GS(n)” in response to the voltage V_Q” of the first node Q” and the voltage V_Q” of the second node QB”. In an embodiment, the gate signal GS(n)” may be one of a compensation gate signal GC[n] applied to the pixel (see Figure 3 ) and a data initialization gate signal GI[n] (see Figure 3 ).

[0326] The control circuit 410e may include a first switching element T1”. The control circuit 410e may further include a first control switch element TC1”. The control circuit 410e may further include a second control switch element TC2”. The control circuit 410e may further include a second switching element T2”, a third switching element T3”, a fourth switching element T4”, a fifth switching element T5”, a sixth switching element T6”, a seventh switching element T7”, an eighth switching element T8”, a first capacitor C1”, a second capacitor C2” and a third capacitor C3”.

[0327] The first switching element T1” may include a gate electrode receiving the first clock signal CLK1”, a first electrode receiving the input signal “FLM / PCR”, and a second electrode connected to the third node N3”.

[0328] The second switching element T2” may include a gate electrode connected to the fifth node N5”, a first electrode receiving a gate high voltage VGH, and a second electrode connected to the fourth node N4”.

[0329] The third switching element T3” may include a gate electrode receiving the second clock signal CLK2”, a first electrode connected to the fourth node N4”, and a second electrode connected to the third node N3”.

[0330] The fourth switching element T4” may include a gate electrode receiving the first clock signal CLK1”, a first electrode receiving a gate low voltage VGL, and a second electrode connected to the fifth node N5”.

[0331] The fifth switching element T5” may include a gate electrode receiving the second clock signal CLK2”, a first electrode connected to the sixth node N6”, and a second electrode connected to the seventh node N7”.

[0332] The sixth switching element T6” may include a gate electrode connected to the fifth node N5”, a first electrode receiving the second clock signal CLK2”, and a second electrode connected to the sixth node N6”.

[0333] The seventh switching element T7” may include a gate electrode connected to the third node N3”, a first electrode receiving a gate high voltage VGH, and a second electrode connected to the second node QB”.

[0334] The first control switching element TC1” may include a gate electrode receiving an enable signal EN”, a first electrode connected to the third node N3”, and a second electrode connected to the first node Q”.

[0335] The second control switching element TC2” may include a gate electrode receiving an enable signal EN”, a first electrode connected to the seventh node N7”, and a second electrode connected to the second node QB”.

[0336] The eighth switching element T8” may include a gate electrode connected to the third node N3”, a first electrode receiving the first clock signal CLK1”, and a second electrode connected to the fifth node N5”.

[0337] The first capacitor C1” may include a first electrode receiving the second clock signal CLK2” and a second electrode connected to the third node N3”. The first capacitor C1” may store a voltage difference between the voltage of the gate output node GS_ON” and the voltage of the third node N3”.

[0338] The second capacitor C2” may include a first electrode connected to the fifth node N5” and a second electrode connected to the sixth node N6”. The second capacitor C2” may store a voltage difference between the voltage of the fifth node N5” and the voltage of the sixth node N6”.

[0339] The third capacitor C3” may include a first electrode receiving the gate high voltage VGH and a second electrode connected to the seventh node N7”. The third capacitor C3” may store a voltage difference between the gate high voltage VGH and the voltage of the seventh node N7”.

[0340] The gate output circuit 420e may include a ninth switching element T9” and a tenth switching element T10”.

[0341] The ninth switching element T9” may include a gate electrode connected to the second node QB”, a first electrode receiving the gate high voltage VGH, and a second electrode connected to the gate output node GS_ON”.

[0342] The tenth switching element T10” may include a gate electrode connected to the first node Q”, a first electrode receiving the gate low voltage VGL, and a second electrode connected to the gate output node GS_ON”.

[0343] Leakage current may be generated more in P-type transistors than in N-type transistors. Therefore, some of the switching elements included in each stage 400e may be N-type transistors. For example, the first control switching element TC1” and the second control switching element TC2” may be N-type transistors, and the first switching element T1” to the tenth switching element T10” may be P-type transistors.

[0344] In the present embodiment, it is illustrated that some of the switching elements of each stage 400e are N-type transistors and some of the other switching elements are P-type transistors, but the present invention is not limited thereto. In another embodiment, the present invention may also be applied to each stage including only P-type transistors.

[0345] Figure 36 is a timing diagram showing Figure 35 the input signal FLM / PCR”, the first clock signal CLK1”, the second clock signal CLK2”, the node signals (i.e., the voltage V_Q of the first node Q” and the voltage V_QB of the second node QB”), and the output signal (i.e., the gate signal GS(n)”) of each stage 400e. Figure 37 is a timing diagram showing Figure 35 the operation of each stage 400e during Figure 36 the first time period TP1”. Figure 38 is a circuit diagram showing Figure 35 the operation of each stage 400e during Figure 36The circuit diagram of the operation in the second time period TP2”. Figure 39 shows Figure 35 the operation of each stage 400e in Figure 36 the third time period TP3” of

[0346] Refer to Figures 35 to 39 , and describe the operation of each stage 400e when the first control switch element TC1” and the second control switch element TC2” remain conducting in response to an enable signal EN” having an active level. The 1 horizontal time 1H can be the time assigned to each pixel row of the display panel 100.

[0347] As Figure 37 shown, in the first time period TP1”, the input signal FLM / PCR” can have a high level VH”, the first clock signal CLK1” can remain at a low level VL”, and then change from the low level VL” to the high level VH”, and the second clock signal CLK2” can have a high level VH”.

[0348] The first switch element T1” can conduct in response to the first clock signal CLK1” having a low level VL”. The first switch element T1” can apply the input signal FLM / PCR” having a high level VH” to the third node N3” and the first node Q”, and the first capacitor C1” can be charged.

[0349] The fourth switch element T4” can conduct in response to the first clock signal CLK1” having a low level VL”. The fourth switch element T4” can apply the gate low voltage VGL to the fifth node N5”.

[0350] The sixth switch element T6” can conduct in response to the voltage of the fifth node N5” having the gate low voltage VGL. The sixth switch element T6” can apply the second clock signal CLK2” having a high level VH” to the sixth node N6”, and the second capacitor C2” can be charged.

[0351] As Figure 38 shown, in the second time period TP2”, the input signal FLM / PCR” can have a high level VH”, the first clock signal CLK1” can alternately have a high level VH” and a low level VL”, and the second clock signal CLK2” can alternately have a high level VH” and a low level VL”.

[0352] The third switching element T3” can be turned on in response to a second clock signal CLK2” having a low level VL”. The second switching element T2” can remain turned on in response to the voltage of a fifth node N5” having a low level VL”. The gate high voltage VGH can be applied to a third node N3” and a first node N1” through the second switching element T2” and the third switching element T3”.

[0353] The fifth switching element T5” can be turned on in response to a second clock signal CLK2” having a low level VL”. The sixth switching element T6” can remain turned on in response to the voltage of a fifth node N5” having a low level VL”. The second clock signal CLK2” having a low level VL” can be applied to a seventh node N7” and a second node QB” through the sixth switching element T6” and the fifth switching element T5”, and a third capacitor C3” can be charged. Accordingly, a ninth switching element T9” can be turned on in response to the voltage V_QB” of the second node QB” having a low level VL”, and the gate high voltage VGH can be applied to a gate output node GS_ON”. Accordingly, a gate signal GS(n)” having a high level VH” can be output from the gate output node GS_ON”.

[0354] As Figure 39 shown, in a third time period TP3”, an input signal FLM / PCR” can have a low level VL”, a first clock signal CLK1” can remain at the low level VL” and then change to a high level VH”, and a second clock signal CLK2” can have a high level VH”.

[0355] The first switching element T1” can be turned on in response to a first clock signal CLK1” having a low level VL”. The first switching element T1” can apply the input signal FLM / PCR” having a low level VL” to a third node N3” and a first node Q”, and a first capacitor C1” can be charged. A tenth switching element T10” can be turned on in response to the voltage V_Q” of the first node Q” having a low level VL”, and the gate low voltage VGL can be applied to a gate output node GS_ON”. Accordingly, a gate signal GS(n)” having a low level VL” can be output from the gate output node GS_ON”.

[0356] The fourth switching element T4” can be turned on in response to a first clock signal CLK1” having a low level VL”. The fourth switching element T4” can apply the gate low voltage VGL to a fifth node N5”.

[0357] The sixth switching element T6” can be turned on in response to the voltage of the fifth node N5” having a low gate voltage VGL. The sixth switching element T6” can apply the second clock signal CLK2” having a high level VH” to the sixth node N6”, and the second capacitor C2” can be charged.

[0358] In this way, the gate output circuit 420e can output the gate signal GS(n)” in the second time period TP2”.

[0359] Figure 40 is a circuit diagram showing Figure 35 the operation of each stage 400e when the enable signal EN” has an inactive level.

[0360] Reference Figures 35 to 40 , the control circuit 410e can include a first control switching element TC1” that selectively controls the voltage V_Q” of the first node Q” in response to the enable signal EN” and a second control switching element TC2” that selectively controls the voltage V_QB” of the second node QB”. The gate output circuit 420e can selectively output the gate signal GS(n)” according to the enable signal EN”.

[0361] When the enable signal EN” has an active level, the first control switching element TC1” can transfer the voltage of the third node N3” to the first node Q”, and the voltage V_Q” of the first node Q” can change according to the input signal FLM / PCR”.

[0362] On the other hand, when the enable signal EN” has an inactive level, the first control switching element TC1” can not transfer the voltage of the third node N3” to the fifth node N5” and the first node Q”.

[0363] Since the first control switching element TC1” can be turned off in response to the enable signal EN” having a low level VL”, the input signal FLM / PCR” can not be applied to the first node Q”. Therefore, the voltage V_Q” of the first node Q” can maintain the low level VL” stored by the first capacitor C1”. The voltage V_QB” of the second node QB” can maintain a high level VH”.

[0364] The tenth switching element T10” can be turned on in response to the voltage V_Q” of the first node Q” having a low level VL”, and can apply the gate low voltage VGL to the gate output node GS_ON”. Therefore, a gate signal GS(n)” having a low level VL” can be output from the gate output node GS_ON”.

[0365] In this way, the gate driver 300 (see Figure 5) and the display device may include a control circuit 410e and a gate output circuit 420e, and the control circuit 410e may include a first control switch element TC1”. The first control switch element TC1” selectively controls the voltage V_Q” of the first node Q” in response to an enable signal EN” so as to support driving frequency multiple division. Through driving frequency multiple division, the power consumption of the display device can be effectively reduced.

[0366] Figure 41 is a block diagram showing the electronic device 1000. Figure 42 is showing Figure 41 a diagram of an embodiment in which the electronic device 1000 is implemented as a smart phone.

[0367] Referring to Figure 41 and Figure 42 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (“I / O”) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 a display device. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (“USB”) device, and / or other electronic devices, etc.

[0368] In an embodiment, as shown in Figure 42 , the electronic device 1000 may be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For another example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (“PC”), a car navigation system, a computer monitor, a laptop computer, and / or a head-mounted display (“HMD”) device, etc.

[0369] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (“CPU”), and / or an application processor (“AP”), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, and / or a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0370] The memory device 1020 may store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, and / or a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, and / or a mobile (“DRAM”) device, etc.).

[0371] The storage device 1030 may include a solid state drive (“SSD”) device, a hard disk drive (“HDD”) device, and / or a read-only compact disc memory (“CD-ROM”) device, etc.

[0372] The I / O device 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touchpad, and / or a touch screen, etc., and output devices such as a printer and / or a speaker, etc. In some embodiments, the I / O device 1040 may include the display device 1060.

[0373] The power supply 1050 may provide power for the operation of the electronic device 1000.

[0374] The display device 1060 may be connected to other components via a bus or other communication link.

[0375] The present invention may be applied to any display device and any electronic device including a touch panel. For example, the present invention may be applied to mobile phones, smart phones, tablet computers, digital televisions (“TVs”), three-dimensional (“3D”) TVs, personal computers, household appliances, laptop computers, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, and / or navigation devices, etc.

[0376] The foregoing is a description of the invention and is not to be construed as limiting thereof. Although some embodiments of the invention have been described, it will be readily understood by those skilled in the art that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the invention. Accordingly, all such modifications are intended to be included within the scope of the invention as defined in the claims. In the claims, the apparatus-plus-function clauses are intended to cover the structures that perform the recited function herein, and not only structural equivalents but also equivalent structures. Thus, it will be understood that the foregoing is a description of the invention and is not to be construed as limited to the particular embodiments disclosed, and that modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the appended claims and equivalents of the claims included therein.

Claims

1. A gate driver, the gate driver comprising a plurality of stages, wherein, Each of the plurality of stages includes: a control circuit configured to control the voltage of a first node and the voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; and a gate output circuit configured to output a gate signal in response to the voltage of the first node and the voltage of the second node, wherein the control circuit includes a first control switch element configured to selectively connect the first node and the gate output circuit in response to an enable signal.

2. The gate driver according to claim 1, wherein The gate output circuit is configured to selectively output the gate signal in response to the enable signal.

3. The gate driver according to claim 2, wherein, When the enable signal has an inactive level that turns off the first control switch element before the input signal has a high level, the gate signal having a low level is output, and wherein when the enable signal has the inactive level after the input signal has the high level, the gate signal having a high level is output.

4. The gate driver according to claim 2, wherein When the enable signal has an inactive level that turns off the first control switch element before the input signal has a low level, the gate signal having a high level is output, and wherein when the enable signal has the inactive level after the input signal has the low level, the gate signal having a low level is output.

5. The gate driver according to claim 2, wherein, The gate signal is at least one of a data write gate signal, a compensation gate signal, and a data initialization gate signal applied to a pixel, and wherein in response to the data write gate signal, a data voltage is applied to the pixel, in response to the compensation gate signal, the threshold voltage of a driving transistor included in the pixel is compensated, and in response to the data initialization gate signal, the driving transistor is initialized.

6. The gate driver according to claim 5, wherein, The pixel includes: a first transistor, which is the driving transistor, and includes a gate electrode connected to a first pixel node, a first electrode connected to a second pixel node, and a second electrode connected to a third pixel node; a second transistor, including a gate electrode to which the data write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second pixel node; a third transistor, including a gate electrode to which the compensation gate signal is applied, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node; a fourth transistor, including a gate electrode to which the data initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the first pixel node; a fifth transistor, including a gate electrode to which an emission signal is applied, a first electrode to which a first driving voltage is applied, and a second electrode connected to the second pixel node; and a seventh transistor, including a gate electrode to which a light-emitting element initialization gate signal is applied, a first electrode to which a light-emitting element initialization voltage is applied, and a second electrode connected to an anode electrode of the light-emitting element; and The light-emitting element includes the anode electrode and the cathode electrode to which the second driving voltage is applied.

7. The gate driver according to claim 1, wherein, The first control switch element includes a gate electrode configured to receive the enable signal, a first electrode connected to the third node, and a second electrode connected to the fifth node, and wherein the control circuit further includes: A first switch element, including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the third node; A second switch element, including a gate electrode connected to the first node, a first electrode configured to receive the second clock signal, and a second electrode connected to the fourth node; A ninth switch element, including a gate electrode configured to receive a low gate voltage, a first electrode connected to the fifth node, and a second electrode connected to the first node; and A third capacitor, including a first electrode connected to the fourth node and a second electrode connected to the first node.

8. The gate driver according to claim 7, wherein, The control circuit further includes: A third switch element, including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the low gate voltage, and a second electrode connected to the sixth node; A fourth switch element, including a gate electrode configured to receive the low gate voltage, a first electrode connected to the sixth node, and a second electrode connected to the seventh node; A fifth switch element, including a gate electrode connected to the first node, a first electrode configured to receive the first clock signal, and a second electrode connected to the sixth node; A sixth switch element, including a gate electrode connected to the seventh node, a first electrode configured to receive the second clock signal, and a second electrode connected to the eighth node; A seventh switch element, including a gate electrode configured to receive the second clock signal, a first electrode connected to the eighth node, and a second electrode connected to the second node; An eighth switch element, including a gate electrode connected to the first node, a first electrode configured to receive the first clock signal, and a second electrode connected to the second node; A first capacitor, including a first electrode configured to receive the first clock signal and a second electrode connected to the second node; and A second capacitor, including a first electrode connected to the seventh node and a second electrode connected to the eighth node.

9. The gate driver according to claim 8, wherein, The gate output circuit includes: A tenth switch element, including a gate electrode connected to the second node, a first electrode configured to receive the first clock signal, and a second electrode connected to the gate output node; and An eleventh switch element, including a gate electrode connected to the first node, a first electrode configured to receive the low gate voltage, and a second electrode connected to the gate output node.

10. The gate driver according to claim 1, wherein, The control circuit further includes: A first switch element, including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the third node, and The gate output circuit includes: A seventh switching element, including a gate electrode connected to the second node, a first electrode configured to receive a gate high voltage, and a second electrode connected to the gate output node; and An eighth switching element, including a gate electrode connected to the first node, a first electrode configured to receive the second clock signal, and a second electrode connected to the gate output node.

11. The gate driver according to claim 10, wherein, The first control switching element includes a gate electrode configured to receive the enable signal, a first electrode connected to the fifth node, and a second electrode connected to the first node.

12. The gate driver according to claim 11, wherein, The control circuit further includes: A sixth switching element, including a gate electrode configured to receive a gate low voltage, a first electrode connected to the third node, and a second electrode connected to the fifth node.

13. The gate driver according to claim 12, wherein, The control circuit further includes: A second switching element, including a gate electrode connected to the second node, a first electrode configured to receive the gate high voltage, and a second electrode connected to the fourth node; A third switching element, including a gate electrode configured to receive the second clock signal, a first electrode connected to the fourth node, and a second electrode connected to the third node; A fourth switching element, including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the gate low voltage, and a second electrode connected to the second node; and A fifth switching element, including a gate electrode connected to the third node, a first electrode configured to receive the first clock signal, and a second electrode connected to the second node, and The gate output circuit further includes: A first capacitor, including a first electrode connected to the first node and a second electrode connected to the gate output node; and A second capacitor, including a first electrode configured to receive the gate high voltage and a second electrode connected to the second node.

14. The gate driver according to claim 1, wherein, The first control switching element has a dual-transistor structure including two transistors.

15. The gate driver according to claim 1, wherein, The first control switching element is an N-type transistor.

16. The gate driver according to claim 1, wherein, The control circuit further includes: A second control switching element configured to selectively connect the second node and the gate output circuit in response to the enable signal.

17. The gate driver according to claim 16, wherein, The control circuit further includes: A first switching element, including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the third node, and The gate output circuit includes: A seventh switching element, including a gate electrode connected to the second node, a first electrode configured to receive a gate high voltage, and a second electrode connected to the gate output node; and An eighth switching element, including a gate electrode connected to the first node, a first electrode configured to receive the second clock signal, and a second electrode connected to the gate output node.

18. The gate driver according to claim 17, wherein, The first control switching element includes a gate electrode configured to receive the enable signal, a first electrode connected to the fifth node, and a second electrode connected to the first node.

19. The gate driver according to claim 18, wherein, The second control switch element includes a gate electrode configured to receive the enable signal, a first electrode connected to the sixth node, and a second electrode connected to the second node.

20. The gate driver according to claim 19, wherein, The control circuit further includes: A sixth switch element including a gate electrode configured to receive a low gate voltage, a first electrode connected to the third node, and a second electrode connected to the fifth node.

21. The gate driver according to claim 20, wherein, The control circuit further includes: A second switch element including a gate electrode connected to the sixth node, a first electrode configured to receive the high gate voltage, and a second electrode connected to the fourth node; A third switch element including a gate electrode configured to receive the second clock signal, a first electrode connected to the fourth node, and a second electrode connected to the third node; A fourth switch element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the low gate voltage, and a second electrode connected to the sixth node; and A fifth switch element including a gate electrode connected to the third node, a first electrode configured to receive the first clock signal, and a second electrode connected to the sixth node, and The gate output circuit further includes: A first capacitor including a first electrode connected to the first node and a second electrode connected to the gate output node; and A second capacitor including a first electrode configured to receive the high gate voltage and a second electrode connected to the second node.

22. The gate driver according to claim 16, wherein, The control circuit further includes: A first switch element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the third node, and The gate output circuit includes: A ninth switch element including a gate electrode connected to the second node, a first electrode configured to receive the high gate voltage, and a second electrode connected to the gate output node; and A tenth switch element including a gate electrode connected to the first node, a first electrode configured to receive the low gate voltage, and a second electrode connected to the gate output node.

23. The gate driver according to claim 22, wherein, The first control switch element includes a gate electrode configured to receive the enable signal, a first electrode connected to the third node, and a second electrode connected to the first node.

24. The gate driver according to claim 23, wherein, The second control switch element includes a gate electrode configured to receive the enable signal, a first electrode connected to the seventh node, and a second electrode connected to the second node.

25. The gate driver according to claim 24, wherein, The control circuit further includes: A second switch element including a gate electrode connected to the fifth node, a first electrode configured to receive the high gate voltage, and a second electrode connected to the fourth node; A third switch element including a gate electrode configured to receive the second clock signal, a first electrode connected to the fourth node, and a second electrode connected to the third node; A fourth switching element, comprising a gate electrode configured to receive the first clock signal, a first electrode configured to receive the gate low voltage, and a second electrode connected to the fifth node; A fifth switching element, comprising a gate electrode configured to receive the second clock signal, a first electrode connected to the sixth node, and a second electrode connected to the seventh node; A sixth switching element, comprising a gate electrode connected to the fifth node, a first electrode configured to receive the second clock signal, and a second electrode connected to the sixth node; A seventh switching element, comprising a gate electrode connected to the third node, a first electrode configured to receive the gate high voltage, and a second electrode connected to the second node; An eighth switching element, comprising a gate electrode connected to the third node, a first electrode configured to receive the first clock signal, and a second electrode connected to the fifth node; A first capacitor, comprising a first electrode configured to receive the second clock signal and a second electrode connected to the third node; A second capacitor, comprising a first electrode connected to the fifth node and a second electrode connected to the sixth node; and A third capacitor, comprising a first electrode configured to receive the gate high voltage and a second electrode connected to the seventh node.

26. A display device, wherein, The display device includes: A display panel including a plurality of pixels; A gate driver configured to apply a gate signal to the display panel; and A data driver configured to apply a data voltage to the display panel, wherein the gate driver includes a plurality of stages, and each of the plurality of stages includes: A control circuit configured to control the voltage of the first node and the voltage of the second node in response to an input signal, the first clock signal, and the second clock signal; and A gate output circuit configured to output the gate signal in response to the voltage of the first node and the voltage of the second node, wherein the control circuit includes a first control switching element configured to selectively connect the first node and the gate output circuit in response to an enable signal.

27. The display device according to claim 26, wherein, The gate output circuit is configured to selectively output the gate signal in response to the enable signal.

28. The display device according to claim 27, wherein, When the enable signal has an inactive level that turns off the first control switching element before the input signal has a high level, the gate signal having a low level is output, and wherein, when the enable signal has the inactive level after the input signal has the high level, the gate signal having a high level is output.

29. The display device according to claim 27, wherein When the enable signal has an inactive level that turns off the first control switching element before the input signal has a low level, the gate signal having a high level is output, and wherein, when the enable signal has the inactive level after the input signal has the low level, the gate signal having a low level is output.

30. An electronic device, wherein, The electronic device includes: A display panel including a plurality of pixels; A gate driver configured to apply a gate signal to the display panel; A data driver configured to apply a data voltage to the display panel; A driving controller configured to control the gate driver and the data driver; and A processor configured to apply input image data to the driving controller, wherein the gate driver includes a plurality of stages, and each of the plurality of stages includes: A control circuit configured to control the voltage of a first node and the voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; and A gate output circuit configured to output the gate signal in response to the voltage of the first node and the voltage of the second node, wherein the control circuit includes a first control switch element configured to selectively connect the first node and the gate output circuit in response to an enable signal.

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