Error correction code circuit, repair system and memory
By designing an error correction code circuit that processes short-circuit data bits and check bits in MRAM memory in parallel, the error correction capability of m+1 bit errors is realized, which reduces the delay and improves the performance of MRAM products.
Patent Information
- Application Number
- CN202410115685.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-26
- Publication Date
- 2025-07-29
AI Technical Summary
When MRAM memory reads out data, due to data errors caused by magnetic tunnel junction resistance drift, the existing error correction code circuit has a high delay, which affects the decoding speed.
An error correction code circuit is designed, including a first decoding module and a second decoding module, and processing short-circuited data bits and check bits in parallel, and combining the output logic module to realize the error correction ability of m+1 bit errors and reduce delay.
The error correction capability is improved, the delay of the error correction code circuit is significantly reduced, and the endurance indicator of MRAM products is improved.
Smart Images
Figure CN120388598A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of memories, and particularly to an error correction code circuit, a repair system, and a memory. Background Art
[0002] MRAM is a new memory and storage technology. It has the characteristics of fast random read and write like SRAM / DRAM, and also has the function of permanently retaining data in flash memory after power-off. The core structure of the MRAM storage bit is a magnetic tunnel junction, which is composed of two ferromagnetic materials sandwiching a very thin non-ferromagnetic insulating material. The lower ferromagnetic material is a reference layer with a fixed magnetization direction, and the upper ferromagnetic material is a free layer with a variable magnetization direction. The magnetization direction of the free layer can be parallel or antiparallel to that of the reference layer.
[0003] When reading data from MRAM, the reading circuit needs to detect the resistance of the MRAM storage bit. Since the resistance of the magnetic tunnel junction may drift due to production process, read / write times, temperature, etc., resulting in data errors, the read data bit is opposite to the data bit written in the previous time. To solve this problem, an ECC (Error Correction Code) circuit can be added to encode the original data and add some parity bits to detect and correct data errors. The delay of the ECC circuit directly affects the decoding speed. Therefore, how to reduce the delay of the ECC circuit is a problem that must be considered. Summary of the Invention
[0004] In view of this, the present invention provides an error correction code circuit, a repair system, and a memory, which can basically achieve the error correction ability of m + 1 bits based on an error correction code with an error correction ability of m bits, and reduce the delay of the error correction code circuit under the same error correction ability.
[0005] In a first aspect, the present invention provides an error correction code circuit, including:
[0006] A first decoding module, configured to receive first data, decode the first data based on an error correction code with an error correction ability of m bits, and output a first decoding result and a first number of error bits when there are short-circuited data bits and parity bits, and the short-circuited data bits and parity bits are less than or equal to m + 1 bits. The first data is the original data of the data bits and parity bits.
[0007] A second decoding module, which works in parallel with the first decoding module when there are short-circuited data bits and parity bits and the number of short-circuited data bits and parity bits is less than or equal to m + 1 bits, is used to receive second data, decode the second data based on an error correction code with an error correction ability of m bits, and output a second decoding result and a second number of error bits. The second data is the data obtained by inverting all the data in the first data corresponding to the short-circuited data bits and parity bits;
[0008] An output logic module is used to output one of the first decoding result and the second decoding result or output an error prompt indicating that error correction cannot be performed according to the first number of error bits and the second number of error bits.
[0009] Optionally, the output logic module is used for:
[0010] If the first number of error bits is 0, output the first decoding result; if the first number of error bits is m + 1 bits and the second number of error bits is 0, output the second decoding result; if the first number of error bits is m + 1 bits and the second number of error bits is also m + 1 bits, output an error prompt indicating that error correction cannot be performed.
[0011] Optionally, the error correction code circuit further includes:
[0012] A control module is used to receive first data and short-circuit information of data bits and parity bits. The short-circuit information is used to indicate whether the data bits and parity bits are short-circuited; according to the short-circuit information of the data bits and parity bits, check whether there are short-circuited data bits and parity bits; if there are short-circuited data bits and parity bits and the number of short-circuited data bits and parity bits is less than or equal to m + 1 bits, invert all the data in the first data corresponding to the short-circuited data bits and parity bits to obtain second data; enable the first decoding module and the second decoding module.
[0013] Optionally, the control module is further used to only enable the first decoding module if there are no short-circuited data bits and parity bits, or if the number of short-circuited data bits and parity bits is greater than m + 1 bits;
[0014] The first decoding module is further used to receive the first data and decode the first data based on an error correction code with an error correction ability of m bits to output a third decoding result and a third number of error bits when there are no short-circuited data bits and parity bits, or when the number of short-circuited data bits and parity bits is greater than m + 1 bits;
[0015] The output logic module is further used to output the third decoding result or output an error prompt indicating that error correction cannot be performed according to the third number of error bits.
[0016] Optionally, if the short - circuit information of the data bit and the parity bit is 1, it indicates that the data bit and the parity bit are short - circuited; if the short - circuit information of the data bit and the parity bit is 0, it indicates that the data bit and the parity bit are normal.
[0017] Optionally, the error - correcting code with an error - correcting ability of m bits is any type of error - correcting code that corrects m bits and detects m + 1 bits.
[0018] In a second aspect, the present invention provides a memory repair system, including the error - correcting code circuit provided in the first aspect, and further including:
[0019] A storage bit - cell array for storing data bits of data;
[0020] A parity bit - cell array for storing data of parity bits, and the data of the parity bits is obtained by encoding according to the data of the data bits;
[0021] A data reading circuit, connected to the error - correcting code circuit, the storage bit - cell array, and the parity bit - cell array, for reading the storage bit - cell array and the parity bit - cell array to obtain the original data of the data bits and the parity bits as first data, and obtaining the short - circuit information of the data bits and the parity bits, and inputting the read first data and the short - circuit information of the data bits and the parity bits into the error - correcting code circuit.
[0022] Optionally, the data reading circuit includes:
[0023] A first reference circuit for reading the data of the storage bit - cell array and the parity bit - cell array to obtain the original data of the data bits and the parity bits as first data;
[0024] A second reference circuit for reading the bit - cell states of the storage bit - cell array and the parity bit - cell array to obtain the short - circuit information of the data bits and the parity bits.
[0025] In a third aspect, the present invention provides a memory, and the memory includes the memory repair system provided in the second aspect.
[0026] The error correction code circuit, repair system, and memory provided by the present invention perform parallel decoding by a first decoding module and a second decoding module when there are short-circuited data bits and parity bits, and the number of short-circuited data bits and parity bits is less than or equal to m + 1 bits. The first decoding module decodes the first data, where the first data is the original data of the data bits and parity bits. The second decoding module decodes the second data, where the second data is the data obtained by inverting all the data corresponding to the short-circuited data bits and parity bits in the first data, and the output logic module outputs the decoding result. When the error correction ability of the error correction code is m bits, the error correction ability of m + 1 bits can be basically achieved, improving the error correction ability of the error correction code. Moreover, compared with conventional error correction codes with the same error correction ability, the error correction code circuit of this embodiment has a significant low-latency advantage. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 is a schematic structural diagram of an error correction code circuit in an embodiment;
[0028] Figure 2 is a schematic flowchart of the error correction steps of an error correction code circuit in an embodiment;
[0029] Figure 3 is a schematic diagram of low-latency comparison of an error correction code circuit in an embodiment;
[0030] Figure 4 is a schematic structural diagram of a memory repair system in an embodiment;
[0031] Figure 5 is a schematic diagram of the array structure of a storage bit array and a parity bit array in an embodiment;
[0032] Figure 6 is a schematic structural diagram of a data reading circuit in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only some, rather than all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0035] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0036] One embodiment of the present invention provides an error correction code circuit, such as Figure 1 As shown, the error correction code circuit includes:
[0037] A first decoding module 101 is configured to receive first data, decode the first data based on an error correction code with an error correction capability of m bits, and output a first decoding result and a first number of error bits, where the first data is original data of the data bits and the check bits, when there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits;
[0038] a second decoding module 102, configured to operate in parallel with the first decoding module 101 when there are short-circuited data bits and check bits, and the number of short-circuited data bits and check bits is less than or equal to m+1 bits, to receive second data, decode the second data based on an error correction code with an error correction capability of m bits, and output a second decoding result and a second number of error bits, where the second data is obtained by inverting all data corresponding to the short-circuited data bits and check bits in the first data;
[0039] The output logic module 103 is configured to output one of the first decoding result and the second decoding result or output an error prompt indicating that the error cannot be corrected according to the first number of error bits and the second number of error bits.
[0040] Furthermore, in one embodiment, the output logic module 103 is specifically used to: output a first decoding result if the first error bit number is 0; output a second decoding result if the first error bit number is m+1 bits and the second error bit number is 0; output an error prompt that cannot be corrected if the first error bit number is m+1 bits and the second error bit number is also m+1 bits.
[0041] There are four situations:
[0042] 1) The first error bit number is 0, and the second error bit is m + 1;
[0043] 2) The first error bit number is 0, and the second error bit is also 0;
[0044] 3) The first error bit number is m + 1, and the second error bit is 0;
[0045] 4) The first error bit number is m + 1, and the second error bit is also m + 1;
[0046] For cases 1) and 2), the first decoding result is output; for case 3), the second decoding result is output; for case 4), an error prompt indicating that error correction is not possible is output.
[0047] Based on the above error correction logic, the error correction code circuit of this embodiment can obtain the information that should originally be stored in the memory byte or output an error message indicating that error correction is not possible.
[0048] Further, in one embodiment, referring to Figure 1 , the error correction code circuit further includes:
[0049] A control module 100, configured to receive the first data and the short - circuit information of the data bit and the parity bit, where the short - circuit information is used to indicate whether the data bit and the parity bit are short - circuited; check whether there are short - circuited data bits and parity bits according to the short - circuit information of the data bit and the parity bit; if there are short - circuited data bits and parity bits, and the number of short - circuited data bits and parity bits is less than or equal to m + 1 bits, invert all the data in the first data corresponding to the short - circuited data bits and parity bits to obtain the second data; enable the first decoding module 101 and the second decoding module 102.
[0050] In one embodiment, if the short - circuit information of the data bit and the parity bit is 1, it indicates that the data bit and the parity bit are short - circuited; if the short - circuit information of the data bit and the parity bit is 0, it indicates that the data bit and the parity bit are normal.
[0051] The above analyzes the case where there are short - circuited data bits and parity bits, and the number of short - circuited data bits and parity bits is less than or equal to m + 1 bits. In addition, the following situations may also occur: there are no short - circuited data bits and parity bits, or the number of short - circuited data bits and parity bits is greater than m + 1 bits.
[0052] Further, the control module 100 is further configured to, if there are no short - circuited data bits and parity bits, or the number of short - circuited data bits and parity bits is greater than m + 1 bits, only enable the first decoding module 101;
[0053] Accordingly, the first decoding module 101 is further configured to receive the first data, decode the first data based on an error correction code with an error correction capability of m bits, and output a third decoding result and a third number of error bits when there are no short-circuited data bits and parity bits, or when the number of short-circuited data bits and parity bits is greater than m + 1 bits;
[0054] The output logic module 103 is further configured to output the third decoding result or an error prompt indicating that error correction cannot be performed according to the third number of error bits.
[0055] Next, Figure 1 a simple description of the error correction steps of the error correction code circuit shown below will be given.
[0056] Referring to Figure 2 , the control module 100 first receives the first data and the short-circuit information of the data bits and parity bits, checks whether there are short-circuited data bits and parity bits according to the short-circuit information of the data bits and parity bits; if there are short-circuited data bits and parity bits and the number of short-circuited data bits and parity bits is less than or equal to m + 1 bits, all the data corresponding to the short-circuited data bits and parity bits in the first data are inverted to obtain the second data; the first decoding module 101 and the second decoding module 102 are enabled, where m represents the error correction capability of the error correction code used by the first decoding module 101 and the second decoding module 102.
[0057] Then, when there are short-circuited data bits and parity bits and the number of short-circuited data bits and parity bits is less than or equal to m + 1 bits, the first decoding module 101 and the second decoding module 102 perform parallel decoding. The first decoding module 101 decodes the first data based on an error correction code with an error correction capability of m bits and outputs a first decoding result and a first number of error bits. The second decoding module 102 decodes the second data based on an error correction code with an error correction capability of m bits and outputs a second decoding result and a second number of error bits.
[0058] Finally, the output logic module 103 obtains the information that should originally be stored in the memory byte or outputs an error message indicating that error correction cannot be performed based on the following error correction logic: if the first number of error bits is 0, the first decoding result is output; if the first number of error bits is m + 1 bits and the second number of error bits is 0, the second decoding result is output; if the first number of error bits is m + 1 bits and the second number of error bits is also m + 1 bits, an error prompt indicating that error correction cannot be performed is output.
[0059] Additionally, it should be noted that in the above error correction steps, if there are no short-circuited data bits and parity bits, or if the short-circuited data bits and parity bits are more than m + 1 bits, the control module 100 only enables the first decoding module 101. The first decoding module 101 decodes the first data based on an error correction code with an error correction ability of m bits, and outputs a third decoding result and a third number of error bits; the output logic module 103 outputs the third decoding result or an error prompt indicating that error correction cannot be performed according to the third number of error bits.
[0060] The following is an example to illustrate that the error correction code circuit of the embodiment of the present invention can improve the error correction ability of the error correction code. In this embodiment, the error correction code with an error correction ability of m bits used by the first decoding module 101 and the second decoding module 102 can be any type of error correction code that corrects m and detects m + 1, such as a Hamming code that corrects 1 and detects 2, or a BCH code that corrects 2 and detects 3.
[0061] 1. For a Hamming code that corrects 1 and detects 2 with an inherent error correction ability of 1 bit, analyze the error correction ability in different situations.
[0062] a) When there are 3 or more short circuits in the data bits and parity bits, or when there are no short circuits in the data bits and parity bits, only the first decoding module decodes at this time, and this situation can only correct 1 soft error.
[0063] When there is 1 or 2 short circuits in the data bits and parity bits, the first decoding module and the second decoding module decode in parallel, and the error correction ability of 2 errors can be basically achieved.
[0064] The specific analysis is as follows:
[0065] b) If there is 1 short circuit in the data bits and parity bits, and there is still 1 soft error at this time, then one of the first data and the second data can always be correctly decoded, and the other reports 2 errors, that is, one of the first number of error bits and the second number of error bits is always 0, and the other is 2, so it can be correctly decoded.
[0066] c) If there are 2 short circuits in the data bits and parity bits and no soft error bits, the data situation at the short circuit positions is as follows:
[0067]
[0068] It can be seen that this situation can be correctly decoded.
[0069] In summary, except for the case of 2-bit soft errors, the error correction code circuit according to the embodiments of the present invention is based on a Hamming code that corrects 1 error and detects 2 errors, and combines the short circuit information of the data bits and the parity bits to achieve the error correction ability for 2-bit errors. The probability of having 2-bit soft errors in the data of one error correction unit is very low. Taking a 32-bit array + 7-bit error correction code with a soft error rate of 1 ppm as an example, the probability of having 2-bit soft errors is only 7.4e-10. In contrast, the probability of having 1-bit soft errors is 3.9e-5, which is about 5 orders of magnitude higher. Therefore, it can be considered that the error correction code circuit according to the present embodiment based on the Hamming code that corrects 1 error and detects 2 errors can basically achieve the error correction ability for 2-bit errors, and has advantages in decoding delay and area compared with conventional 2-bit error correction codes.
[0070] 2. For a BCH code that corrects 2 errors and detects 3 errors with an error correction ability of 2 bits itself, analyze the error correction ability in different situations.
[0071] a) When there are 4 or more short circuits in the data bits and the parity bits, or there is no short circuit in the data bits and the parity bits, only the first decoding module decodes at this time, and this situation can only correct 2-bit soft errors.
[0072] When there are 1, 2, or 3 short circuits in the data bits and the parity bits, the first decoding module and the second decoding module decode in parallel, and can basically achieve the error correction ability for 3-bit errors.
[0073] The specific analysis is as follows:
[0074] b) If there is 1 short circuit in the data bits and the parity bits, and there are 2-bit soft errors at this time, then one of the first data and the second data can always be correctly decoded, and the other reports 3-bit errors, that is, one of the first error number and the second error number is always 0, and the other is 3. Therefore, it can be correctly decoded.
[0075] c) If there are 2 short circuits in the data bits and the parity bits, and there is 1-bit soft error, the data situation at the short circuit position is as follows:
[0076]
[0077] It can be seen that this situation can be correctly decoded.
[0078] d) If there are 3 short circuits in the data bits and the parity bits, and there is no soft error bit, the data situation at the short circuit position is as follows:
[0079]
[0080] It can be seen that this situation can be correctly decoded.
[0081] In summary, except for the case of 3-bit soft errors, the error correction code circuit according to the embodiments of the present invention is based on the BCH code with 2-bit error correction and 3-bit error detection, and combines the short circuit information of data bits and parity bits to achieve the error correction ability for 3-bit errors. The probability of 3-bit soft errors existing in the data of one error correction unit is very low. Taking a 32-bit array + 13-bit error correction code with a soft error rate of 1 ppm as an example, the probability of 3-bit soft errors is only 1.4e-14. Therefore, it can be considered that the error correction code circuit according to the embodiments of the present invention based on the BCH code with 2-bit error correction and 3-bit error detection can basically achieve the error correction ability for 3-bit errors, and has advantages in decoding delay and area compared with conventional 3-bit error correction codes.
[0082] The following table shows the repair failure rates of the error data by the error correction code according to the embodiments of the present invention based on the BCH code with 2-bit error correction and 3-bit error detection, conventional 2-bit error correction codes, and conventional 3-bit error correction codes. The calculation object is a 4Mb chip with a bit width of 8 bits. It can be seen that compared with conventional 2-bit error correction codes, the embodiments of the present invention can repair short circuit errors more than one order of magnitude higher, thereby improving the endurance index of the MRAM product by more than 10 times.
[0083] Short - circuit error Soft error This embodiment Conventional double - error - correcting code Conventional triple - error - correcting code 1 ppm 1 ppm 4.3e-10 3.4e-9 2.6e-14 10 ppm 1 ppm 4.4e-10 5.7e-7 2.3e-11 100 ppm 1 ppm 1.7e-7 4.4e-4 1.7e-7
[0084] In addition, Figure 3 The error correction delays of different error correction codes are shown. It can be seen that compared with conventional error correction codes with the same error correction ability, the error correction code circuit according to the embodiments of the present invention has a significant low-delay advantage.
[0085] For the error correction code circuit provided by the embodiments of the present invention, when there are short-circuited data bits and parity bits, and the number of short-circuited data bits and parity bits is less than or equal to m + 1 bits, the first decoding module and the second decoding module perform parallel decoding. The first decoding module decodes the first data, where the first data is the original data of the data bits and parity bits. The second decoding module decodes the second data, where the second data is the data obtained by inverting all the data corresponding to the short-circuited data bits and parity bits in the first data, and the output logic module outputs the decoding result. When the error correction ability of the error correction code is m bits, it can basically achieve the error correction ability for m + 1-bit errors, improving the error correction ability of the error correction code. Moreover, compared with conventional error correction codes with the same error correction ability, the error correction code circuit according to the embodiments of the present invention has a significant low-delay advantage.
[0086] On the other hand, an embodiment of the present invention provides a memory repair system, as Figure 4 shown. The memory repair system includes the error correction code circuit 401 provided in the above embodiments, and further includes:
[0087] A storage bit cell array 402 for storing data bits;
[0088] The parity bit array 403 is used to store the data of parity bits, and the data of the parity bits is obtained by encoding according to the data of data bits;
[0089] The data reading circuit 404 is connected to the error correction code circuit 401, the storage bit array 402 and the parity bit array 403, and is used to read the storage bit array 402 and the parity bit array 403 to obtain the original data of data bits and parity bits as the first data, and obtain the short - circuit information of data bits and parity bits, and input the read first data and the short - circuit information of data bits and parity bits into the error correction code circuit 401.
[0090] Figure 5 is a schematic diagram of the array structure of the storage bit array and the parity bit array. The storage bit array includes M columns of storage bits, and the parity bit array includes N columns of parity bits, where both M and N are positive integers and M > N.
[0091] Taking MRAM as an example, the structure of the data reading circuit 404 can adopt the circuit structure as Figure 6 shown, including:
[0092] The first reference circuit is used to read the data of the storage bit array and the parity bit array to obtain the original data of data bits and parity bits as the first data;
[0093] The second reference circuit is used to read the bit states of the storage bit array and the parity bit array to obtain the short - circuit information of data bits and parity bits.
[0094] As Figure 6 shown, the first reference circuit outputs the first data bit - by - bit by comparing the current flowing through the storage bit / parity bit with the current flowing through the reference resistor Rref through the current comparator 1. The second reference circuit outputs the short - circuit information bit - by - bit by comparing the current flowing through the storage bit / parity bit with the current flowing through the reference resistor Rref_short through the current comparator 2.
[0095] On the other hand, an embodiment of the present invention also provides a memory, and the memory includes the above - mentioned memory repair system.
[0096] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above - mentioned embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer - readable storage medium. When the program is executed, it can include the processes of the embodiments of the above - mentioned methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read - only memory (ROM), or a random access memory (RAM), etc.
[0097] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims
1. An error correction code circuit, characterized in that, The error correction code circuit includes: A first decoding module, configured to receive first data when there are shorted data bits and parity bits, and the number of shorted data bits and parity bits is less than or equal to m + 1 bits, decode the first data based on an error correction code with an error correction capability of m bits, and output a first decoding result and a first number of error bits, where the first data is the original data of the data bits and parity bits; A second decoding module, which works in parallel with the first decoding module when there are shorted data bits and parity bits, and the number of shorted data bits and parity bits is less than or equal to m + 1 bits, configured to receive second data, decode the second data based on an error correction code with an error correction capability of m bits, and output a second decoding result and a second number of error bits, where the second data is the data obtained by inverting all the data corresponding to the shorted data bits and parity bits in the first data; An output logic module, configured to output one of the first decoding result and the second decoding result or output an error prompt indicating that error correction is impossible according to the first number of error bits and the second number of error bits.
2. The error correction code circuit according to claim 1, wherein, The output logic module is configured to: If the first number of error bits is 0, output the first decoding result; if the first number of error bits is m + 1 bits and the second number of error bits is 0, output the second decoding result; If the first number of error bits is m + 1 bits and the second number of error bits is also m + 1 bits, output an error prompt indicating that error correction is impossible.
3. The error correction code circuit according to claim 1, wherein The error correction code circuit further includes: A control module, configured to receive the first data and short circuit information of the data bits and parity bits, where the short circuit information is used to indicate whether the data bits and parity bits are shorted; check whether there are shorted data bits and parity bits according to the short circuit information of the data bits and parity bits; if there are shorted data bits and parity bits, and the number of shorted data bits and parity bits is less than or equal to m + 1 bits, invert all the data corresponding to the shorted data bits and parity bits in the first data to obtain second data; enable the first decoding module and the second decoding module.
4. The error correction code circuit according to claim 3, wherein The control module is further configured to, if there are no shorted data bits and parity bits, or the number of shorted data bits and parity bits is greater than m + 1 bits, only enable the first decoding module; The first decoding module is further configured to, in the case of no shorted data bits and parity bits, or in the case where the number of shorted data bits and parity bits is greater than m + 1 bits, receive the first data, decode the first data based on an error correction code with an error correction capability of m bits, and output a third decoding result and a third number of error bits; The output logic module is further configured to output the third decoding result or output an error prompt indicating that error correction is impossible according to the third number of error bits.
5. The error correction code circuit according to claim 3, wherein If the short circuit information of the data bits and parity bits is 1, it indicates that the data bits and parity bits are shorted; if the short circuit information of the data bits and parity bits is 0, it indicates that the data bits and parity bits are normal.
6. The error correction code circuit according to claim 1, characterized in that, The error correction code with an error correction capability of m bits is any type of error correction code that corrects m errors and detects m + 1 errors.
7. A memory repair system, characterized in that, Including: The error correction code circuit according to any one of claims 1 to 6 further includes: A storage bit array for storing data bits of data; A parity bit array for storing parity bit data, the parity bit data being obtained by encoding based on the data bit data; A data reading circuit connected to the error correction code circuit, the storage bit array, and the parity bit array, for reading the storage bit array and the parity bit array to obtain the original data of the data bits and the parity bits as first data, and for obtaining the short circuit information of the data bits and the parity bits, and inputting the read first data and the short circuit information of the data bits and the parity bits into the error correction code circuit.
8. The memory repair system according to claim 7, wherein The data reading circuit includes: A first reference circuit for reading the data of the storage bit array and the parity bit array to obtain the original data of the data bits and the parity bits as first data; A second reference circuit for reading the bit states of the storage bit array and the parity bit array to obtain the short circuit information of the data bits and the parity bits.
9. A memory, characterized in that, The memory includes the memory repair system according to claim 7 or 8.