Distributed timing trigger system

Abstract

The invention provides a distributed timed triggering system. The distributed timed triggering system comprises a master triggering device and a plurality of slave triggering devices, wherein the main trigger device is used for generating a main clock signal and a main trigger signal of pulse width coding according to a reference clock signal and a reference hardware pulse signal, and modulating the main clock signal by using the main trigger signal to obtain a modulation signal; the plurality of slave trigger devices are used for receiving the modulation signals and recovering slave clock signals, slave trigger signals and pulse width codes from the modulation signals; according to the pulse width code, the trigger period time and the coarse timing information, calculating complete time information from the trigger signal receiving moment; and executing a preset operation according to the slave trigger signal and the complete time information. The system not only effectively reduces the noise of the clock signal obtained from the trigger device, but also reduces the implementation difficulty and cost of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of timing triggering, and in particular to a distributed timing triggering system. Background Art

[0002] Trigger devices play a crucial role in modern control systems. They send trigger signals to each controlled device according to a predetermined time relationship, enabling these devices to work in coordination. A single trigger device usually can only handle a small number of trigger signals due to its limited output capacity. When there are a large number of controlled devices in the system, a more complex trigger system is required to ensure that all devices can operate synchronously. Such a trigger system usually consists of a master trigger device and multiple slave trigger devices, forming a star or tree structure.

[0003] In a distributed trigger system, if the master trigger device and the slave trigger devices use independent clock signal sources, due to the slight differences in the frequencies of the clock sources, the time relationships of the trigger signals generated by different trigger devices cannot be completely locked, and time drift may occur. To solve this problem, usually all slave trigger devices use the same clock signal source as the master trigger device.

[0004] In addition, if the clock signal and the trigger signal sent from the master trigger device to the slave trigger devices do not use the same transmission path (such as cables or optical fibers), then with the change of the ambient temperature, the transmission delays of the two may change inconsistently, resulting in possible jumps in the time when the slave trigger device judges the arrival of the slave trigger signal. To avoid this situation, usually the clock signal and the trigger signal are combined into the same transmission path.

[0005] Sometimes, simple trigger modes cannot meet the actual application requirements. For example, in some cases, some slave trigger signals need to be generated after multiple master trigger signals. To solve this problem, coding information can be added to the master trigger signals so that the slave trigger devices can generate corresponding trigger signals according to specific conditions.

[0006] When multiple controlled devices receive the slave trigger signals and measure multiple sets of data, and then send these data to the upper-layer control system via Ethernet, due to the inconsistent data transmission network delays of each terminal device, the data may arrive at the upper-layer control system at different times, resulting in data confusion and making it impossible to determine which data are the measurement results triggered by the same master trigger signal. For this reason, time information can be added to the trigger signals to ensure that the data can be correctly associated.

[0007] Currently, the most widely used distributed trigger system in the accelerator field is the EVG / EVR system produced by Micro-Research Finland Oy (MRF) in Finland. The EVG serves as the master trigger device, and the EVR as the slave trigger device. The EVG sends the EVR not a simple trigger pulse signal but a data packet containing two bytes of data, encoded using the same 8B10B encoding scheme as Ethernet. The received data packet utilizes the same clock and data recovery (CDR) functionality as the Ethernet PHY (Physical Layer Chip), enabling the EVR to simultaneously recover the clock and data sent by the EVG—the master trigger signal with both encoding and timing information.

[0008] Although EVG / EVR systems achieve simultaneous clock and data transmission by transmitting data packets, the clock signal recovered using CDR technology is noisy, increasing the timing jitter of the trigger signal. Furthermore, while using data packets instead of trigger signals increases flexibility, it also increases application difficulty and cost.

[0009] Therefore, how to solve the problems of high clock signal noise, difficulty in application and high cost in existing distributed trigger systems is an important issue that needs to be urgently addressed in the field of timing triggering. Summary of the Invention

[0010] The present invention provides a distributed timing trigger system to overcome the defects of existing distributed trigger systems such as large clock signal noise, great application difficulty and high cost, effectively reduce the clock signal noise obtained from the trigger device, and make the system implementation simpler and more cost-effective.

[0011] On the one hand, the present invention provides a distributed timing trigger system, comprising: a master trigger device and multiple slave trigger devices; wherein the master trigger device is used to generate a master clock signal and a pulse-width-encoded master trigger signal based on a reference clock signal and a reference hardware pulse signal, and use the master trigger signal to modulate the master clock signal to obtain a modulated signal; the multiple slave trigger devices are connected to the master trigger device, used to receive the modulated signal, and recover the slave clock signal, slave trigger signal and pulse width code from the modulated signal; the complete time information of the slave trigger signal reception moment is calculated based on the pulse width code, trigger cycle time and coarse timing information; and the preset operation is performed based on the slave trigger signal and the complete time information.

[0012] Further, the distributed timing trigger system further includes: a time server, connected to the master clock source and the master trigger device, for receiving the standard time information and clock frequency information provided by the master clock source, generating a reference clock signal and a reference hardware pulse signal according to the standard time information and clock frequency information, and forwarding the reference clock signal and the reference hardware pulse signal to the master trigger device.

[0013] Further, the master trigger device includes: a phase-locked loop, connected to the time server, for generating the master clock signal according to the reference clock signal; a master timer, connected to the time server, for generating a pulse-width encoded master trigger signal according to the reference hardware pulse signal.

[0014] Further, the master trigger device further includes: a modulation chip, connected to the phase-locked loop and the master timer, for modulating the master clock signal according to the master trigger signal to obtain the modulation signal.

[0015] Further, the master timer is implemented using FPGA, CPLD or ASIC.

[0016] Further, the modulation chip is an amplitude shift keying modulation chip, for performing amplitude shift keying modulation on the master clock signal according to the master trigger signal to obtain an amplitude shift keying modulation signal.

[0017] Further, the slave trigger device includes: a jitter cleaning chip, connected to the master trigger device, for receiving the modulation signal and recovering the slave clock signal from the modulation signal; the slave clock signal is used to adjust the slave clock frequency to ensure that the slave clock frequency is consistent with the master clock frequency.

[0018] Further, the slave trigger device further includes: a demodulation chip, connected to the master trigger device, for receiving the modulation signal and demodulating the modulation signal to obtain the slave trigger signal.

[0019] Further, the slave trigger device further includes: a slave timer, connected to the demodulation chip, for determining the pulse-width encoding according to the slave trigger signal.

[0020] Further, the jitter cleaning chip includes: a phase-locked loop, for outputting a clock signal phase-locked with the modulation signal; a low-noise voltage-controlled oscillator, connected to the phase-locked loop, for changing the frequency of the output clock signal by changing the control voltage and reducing the phase noise and jitter of the output clock signal to a set range to obtain the slave clock signal.

[0021] Further, the demodulation chip is an amplitude shift keying demodulation chip, which is used to perform amplitude shift keying demodulation on the modulation signal to recover the slave trigger signal.

[0022] The distributed timing trigger system provided by the present invention includes a master trigger device and multiple slave trigger devices; wherein, the master trigger device is used to generate a master clock signal and a master trigger signal with pulse width coding according to a reference clock signal and a reference hardware pulse signal, and modulate the master clock signal with the master trigger signal to obtain a modulation signal; the multiple slave trigger devices are connected to the master trigger device and are used to receive the modulation signal, and recover a slave clock signal, a slave trigger signal and pulse width coding from the modulation signal; calculate the complete time information of the receiving moment of the slave trigger signal according to the pulse width coding, the trigger cycle time and the coarse timing information; and perform a preset operation according to the slave trigger signal and the complete time information. This system not only effectively reduces the noise of the clock signal obtained by the slave trigger device, but also reduces the implementation difficulty and cost of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 It is a schematic diagram of the generation of the master clock signal and the master trigger signal provided by the embodiment of the present invention.

[0025] Figure 2 It is a modulation-demodulation schematic diagram of the distributed timing trigger system provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] In order to make the purpose, technical solutions and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention with reference to the drawings in the present invention. Obviously, the described embodiments are some embodiments of the present invention, rather than all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0027] It should be noted that although the existing EVG / EVR system realizes the simultaneous transmission of clock and data by transmitting data packets, the clock signal recovered by using the CDR technology has relatively large noise, resulting in an increase in the time jitter of the slave trigger signal. In addition, although using data packets instead of trigger signals improves flexibility, it also increases the application difficulty and cost.

[0028] In view of this, the present invention proposes a new distributed timing trigger system, which includes a master trigger device and multiple slave trigger devices.

[0029] The master trigger device is used to generate a master clock signal and a master trigger signal with pulse width encoding according to a reference clock signal and a reference hardware pulse signal, and modulate the master clock signal with the master trigger signal to obtain a modulation signal; the multiple slave trigger devices are connected to the master trigger device and are used to receive the modulation signal, and recover a slave clock signal, a slave trigger signal and pulse width encoding from the modulation signal; calculate the complete time information of the receiving moment of the slave trigger signal according to the pulse width encoding, the trigger cycle time and the coarse timing information; and execute a preset operation according to the slave trigger signal and the complete time information.

[0030] It is easy to understand that the distributed timing trigger system provided in this embodiment further includes a time server, which communicates with the master clock source and the master trigger device simultaneously through NTP (Network Time Protocol) or PTP (Precision Time Protocol) of Ethernet. Among them, the time server can be a commercial time server or other types of time servers, which are not specifically limited here.

[0031] The master clock source refers to the source device or service that provides standard time information and is used to provide precise time calibration for other clocks or systems. In a specific embodiment, the master clock source is the Global Navigation Satellite System (GNSS), which can be used to provide internationally recognized standard time information and clock frequency information.

[0032] Among them, the standard time information refers to the precise time signals obtained by GNSS from satellites. These time signals are based on atomic clocks and have extremely high accuracy and stability. The clock frequency information refers to the stable frequency reference provided by GNSS.

[0033] The time server can receive the signals of the master clock source, that is, the standard time information and the clock frequency information, and output a reference hardware pulse signal (reference 1PPS signal) and a continuous reference clock signal at each whole second moment. Among them, the frequency of the reference clock signal is usually 10MHz and is phase-locked with the reference 1PPS signal. That is to say, each clock cycle is exactly 1×10-7 seconds for precise timing.

[0034] The time server forwards the output reference 1PPS signal and reference clock signal to the master trigger device, which generates a master clock signal and a pulse-width encoded master trigger signal based on the received reference clock signal and reference 1PPS signal.

[0035] Specifically, Figure 1 FIG. shows a schematic diagram of the generation of the master clock signal and the master trigger signal provided by an embodiment of the present invention. As Figure 1 shown, the master trigger device includes a Phase-Locked Loop (PLL) and a master timer.

[0036] Among them, the PLL is a feedback control system, including a phase detector, a loop filter, and a voltage-controlled oscillator, mainly used to maintain the phase synchronization between the output signal and the reference signal. In this embodiment, the PLL is connected to the time server, can receive the reference clock signal from the time server in real time, and takes the reference clock signal as the input to output the master clock signal. The phase of the master clock signal is consistent with or maintains a fixed relationship with the reference clock signal, and the frequency of the master clock signal is, for example, 125 MHz.

[0037] The master timer refers to the timer of the master trigger device, which is used to ensure the time synchronization of all devices and processes in the system, so as to support various applications and services that rely on accurate timestamps. In this embodiment, the master timer is connected to the time server, and after receiving the reference 1PPS signal transmitted by the time server, it generates a series of pulse-width encoded master trigger signals with a set duration as the cycle period. For example, the pulse width of the first master trigger signal after the set duration is 1 us, the pulse width of the second master trigger signal is 2 us, and so on.

[0038] Among them, the master timer can be implemented by an FPGA (Field-Programmable Gate Array), or can be implemented by other digital chips with similar functions, such as a CPLD (Complex Programmable Logic Device) and an ASIC (Application-Specific Integrated Circuit), which are not specifically limited here.

[0039] The set duration can be set according to actual needs, which is not specifically limited here. For example, in a specific embodiment, a series of pulse-width encoded master trigger signals are generated with a set duration of 1 second as the cycle period.

[0040] It should be noted that the master clock signal provides a unified time reference for all components in the system, ensuring synchronous operation among various components in the system. The master timer measures time based on the period of the master clock signal. For example, if it is necessary to generate two master trigger signals at the time points of 100 μs and 200 μs respectively, the timer can generate these two master trigger signals after recording 12,500 clock cycles (100 μs = 12,500 × 8 ns) and 25,000 clock cycles (200 μs = 25,000 × 8 ns) respectively.

[0041] Subsequently, the master trigger device modulates the master clock signal using the master trigger signal to obtain a modulated signal, and transmits the modulated signal to multiple slave trigger devices.

[0042] Specifically, Figure 2 shows a modulation-demodulation schematic diagram of the distributed timing trigger system provided by the embodiment of the present invention. As Figure 2 shown, the master trigger device further includes a modulation chip. The modulation chip receives the master trigger signal and the master clock signal, and uses the master trigger signal to modulate the master clock signal to obtain a modulated signal.

[0043] There are various applicable modulation methods here. Preferably, the modulation chip in this embodiment is an ASK modulation chip, and the master clock signal is modulated by ASK (Amplitude Shift Keying) using the master trigger signal to obtain an ASK modulated signal.

[0044] ASK modulation is a digital modulation in which the amplitude of a sinusoidal carrier changes with the digital baseband signal. For example, in binary ASK modulation, when the digital signal is 1, a sinusoidal carrier signal is output, and when the digital signal is 0, no sinusoidal carrier signal is output. In this embodiment, the master trigger signal is a digital signal, and the master clock signal is a sinusoidal carrier signal.

[0045] Through ASK modulation, the master trigger signal can be effectively embedded into the master clock signal, and then the modulated signal obtained by modulation is transmitted to multiple slave trigger devices simultaneously.

[0046] According to Figure 2 it can be known that multiple slave trigger device ends include a jitter removal chip and a demodulation chip.

[0047] Among them, the jitter cleaner chip (Jitter Cleaner chip) uses a phase-locked loop (PLL) and a low-noise voltage-controlled oscillator (VCO) to generate a low-noise, continuous slave clock signal that is phase-locked with the input clock signal (i.e., the modulation signal). Specifically, the Jitter Cleaner chip includes a PLL and a VCO. The PLL is used to change the frequency of the output clock signal of the VCO by changing the control voltage, and reduce the phase noise and jitter of the output clock signal to a set range to obtain the slave clock signal. The set range here can be set according to actual needs and is not specifically limited here.

[0048] In a specific embodiment, the Jitter Cleaner chip adopts LMK04828, and its Frequency Holdover function can maintain the frequency and phase stability of the output signal in the case of a short-term loss of the input clock signal, and continue the phase-locked control when the input clock signal is restored. In this embodiment, multiple slave trigger device ends use the Jitter Cleaner chip to restore the modulation signal into a slave clock signal and maintain a very high phase accuracy.

[0049] While using the Jitter Cleaner chip to restore the continuous clock signal, the slave trigger device will also demodulate the received modulation signal through a demodulation chip, obtain the trigger code by measuring the pulse width, and obtain the slave trigger signal.

[0050] Similarly, there are multiple applicable demodulation methods here, but they correspond to the modulation methods applicable to the master trigger device. Preferably, when the master trigger device uses an ASK modulation chip, the demodulation chip in this embodiment is an ASK demodulation chip, which demodulates the modulation signal to obtain the slave trigger signal.

[0051] In addition, the slave trigger device also includes a slave timer. The slave timer adjusts the slave clock frequency according to the restored slave clock signal to ensure that the slave clock frequency is consistent with the master clock frequency. At the same time, the slave timer is also connected to the demodulation chip to determine the pulse width code by measuring the pulse width of the slave trigger signal. Among them, like the master timer, the slave timer can be implemented by an FPGA or other digital chips with similar functions (such as CPLD and ASIC), which is not specifically limited here either.

[0052] After obtaining the time information encoded by the main trigger signal pulse width, obtain the time information published by the time server through the NTP or PTP protocol of Ethernet, round it according to the most recent whole second time point to obtain a coarse timing with a resolution of 1 second, and then combine the time information encoded by the main trigger signal pulse width and the trigger cycle time (i.e., the cycle period in the above text) to calculate the complete time information from the moment the slave trigger signal is received.

[0053] Assume that each trigger cycle is 1 second, and 10 main trigger signals are generated (i.e., a main trigger signal is generated every 0.1 second). The pulse width from 1 μs to 10 μs represents a numerical range (e.g., 0 to 9). For example, if the pulse width is 1 μs, it represents the value 0; if the pulse width is 2 μs, it represents the value 1, and so on. The pulse width encoding within each trigger cycle provides additional time precision, such as a precision of 0.1 second.

[0054] In a specific embodiment, the time returned by the time server is 15:30:45.123456. The slave trigger device rounds this time to 15:30:45, ignoring the decimal part, to obtain a coarse timing with a resolution of 1 second. The pulse width of the trigger signal is 2 μs, representing the value 1. The pulse width encoding represents supplementary time information at the millisecond level. Then, the finally calculated complete time information is 15:30:45.100.

[0055] After calculating the complete time information from the moment the slave trigger signal is received, perform a preset operation at the precise time point. The preset operation here can be set according to actual requirements, including but not limited to data acquisition (such as starting or stopping data acquisition), control operations (such as starting or stopping the operation of a certain device), event recording (such as recording the current time as the time stamp of an event), data transmission (such as immediately sending a data packet to a specified target address), state switching (such as switching the state of a device from one mode to another mode), alarm and notification (such as triggering an alarm device), image or video processing (such as starting a camera to take a photo or record a video).

[0056] It is worth mentioning that in this embodiment, the main trigger signal is used to modulate the main clock signal (ASK) at the main trigger device end, replacing the 8B10B encoded data packet in the prior art, and simultaneously transmitting the modulation signal (i.e., the main trigger signal and the main clock signal) in the same path (cable or optical fiber).

[0057] At the slave trigger device end, a continuous clock signal is recovered from the modulation signal through a Jitter Cleaner chip, replacing the CDR technology and reducing the noise of the clock signal. At the same time, the modulation signal is demodulated through a demodulation chip to recover the slave trigger signal, replacing the CDR technology.

[0058] The distributed timing trigger system provided by the embodiments of the present invention reduces the implementation difficulty and cost while realizing all functions.

[0059] In this embodiment, the distributed timing trigger system includes a master trigger device and multiple slave trigger devices; wherein, the master trigger device is configured to generate a master clock signal and a master trigger signal with pulse width encoding according to a reference clock signal and a reference hardware pulse signal, and modulate the master clock signal with the master trigger signal to obtain a modulation signal; the multiple slave trigger devices are connected to the master trigger device, and are configured to receive the modulation signal, and recover a slave clock signal, a slave trigger signal and pulse width encoding from the modulation signal; calculate the complete time information of the receiving moment of the slave trigger signal according to the pulse width encoding, the trigger cycle time and the coarse timing information; and execute a preset operation according to the slave trigger signal and the complete time information. This system not only effectively reduces the noise of the clock signal obtained by the slave trigger device, but also reduces the system implementation difficulty and cost.

[0060] In addition, the distributed timing trigger system provided by the present invention can be applied to large-scale distributed measurement systems and large-scale distributed control systems, such as cosmic ray observation systems and accelerator control systems, and can also be applicable to other systems with timing requirements, which are not specifically limited herein.

[0061] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A distributed timing trigger system, characterized in that, Comprising: A main trigger device and multiple slave trigger devices; wherein, The main trigger device is configured to generate a main clock signal and a main trigger signal with pulse width encoding according to a reference clock signal and a reference hardware pulse signal, and modulate the main clock signal with the main trigger signal to obtain a modulation signal; The multiple slave trigger devices are connected to the main trigger device, and are configured to receive the modulation signal, and recover a slave clock signal, a slave trigger signal and pulse width encoding from the modulation signal; calculate complete time information of the receiving moment of the slave trigger signal according to the pulse width encoding, trigger cycle time and coarse timing information; and perform a preset operation according to the slave trigger signal and the complete time information.

2. The distributed timing trigger system according to claim 1, wherein Further comprising: A time server, connected to a main clock source and the main trigger device, and is configured to receive standard time information and clock frequency information provided by the main clock source, generate a reference clock signal and a reference hardware pulse signal according to the standard time information and the clock frequency information, and forward the reference clock signal and the reference hardware pulse signal to the main trigger device.

3. The distributed timing trigger system according to claim 2, wherein The main trigger device includes: A phase-locked loop, connected to the time server, and is configured to generate the main clock signal according to the reference clock signal; A main timer, connected to the time server, and is configured to generate a main trigger signal with pulse width encoding according to the reference hardware pulse signal.

4. The distributed timing trigger system according to claim 3, wherein The main trigger device further includes: A modulation chip, connected to the phase-locked loop and the main timer, and is configured to modulate the main clock signal with the main trigger signal to obtain the modulation signal.

5. The distributed timing trigger system according to claim 3, characterized in that The main timer is implemented using FPGA, CPLD or ASIC.

6. The distributed timing trigger system according to claim 4, wherein The modulation chip is an amplitude shift keying modulation chip, and is configured to perform amplitude shift keying modulation on the main clock signal with the main trigger signal to obtain an amplitude shift keying modulation signal.

7. The distributed timing trigger system according to claim 1, wherein, The slave trigger device includes: A jitter removal chip, connected to the main trigger device, and is configured to receive the modulation signal and recover the slave clock signal from the modulation signal; the slave clock signal is used to adjust the slave clock frequency to ensure that the slave clock frequency is consistent with the main clock frequency.

8. The distributed timing trigger system according to claim 1, wherein The slave trigger device further includes: A demodulation chip, connected to the main trigger device, and is configured to receive the modulation signal and demodulate the modulation signal to obtain the slave trigger signal.

9. The distributed timing trigger system according to claim 8, wherein The slave trigger device further includes: A slave timer, connected to the demodulation chip, and is configured to determine the pulse width encoding according to the slave trigger signal.

10. The distributed timing trigger system according to claim 7, wherein The jitter removal chip includes: A phase-locked loop, configured to output a clock signal phase-locked with the modulation signal; A low-noise voltage-controlled oscillator, connected to the phase-locked loop, and is configured to change the frequency of the output clock signal by changing the control voltage, and reduce the phase noise and jitter of the output clock signal to a set range to obtain the slave clock signal.

11. The distributed timing trigger system according to claim 8, wherein, The demodulation chip is an amplitude shift keying demodulation chip, and is configured to perform amplitude shift keying demodulation on the modulation signal to recover the slave trigger signal.

Images