Bus sharing method and device for 10G MAC (Media Access Control) interface

Abstract

The invention discloses a 10G MAC interface bus sharing method and device, and belongs to the technical field of computer information. According to the method, data security is guaranteed through a dual anomaly detection mechanism (packet length / FCS verification-based hardware-level preliminary filtering + flow feature baseline model depth detection), and intelligent scheduling of priority queues is realized in combination with a dynamic weight allocation algorithm (fusing queue depth, interface utilization rate and predicted bandwidth demand). And the reliability and the self-healing capability of high-speed transmission are ensured by adopting a clock-domain-crossing asynchronous FIFO and packet counter reset mechanism, so that the interface safety, the transmission efficiency and the anti-interference capability of a large-scale server in a multi-source data scene are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of computer information technology, and more particularly to a 10G MAC interface shared bus method and apparatus. Background Art

[0002] Currently, in scenarios such as cloud computing, artificial intelligence, big data, and satellite link routing and switching, computers or servers need to complete processes such as data collection, preprocessing, storage, and analysis, and the requirements for computing and processing capabilities are increasing day by day. When the data sources are diverse, the number of high-speed interfaces of processors such as CPUs / DSPs often fails to meet the requirements, and the software scheduling complexity is high and the stability is poor in the multi-interface scenario. Implementing bus sharing through logic circuits and sending data from multiple interfaces into the processor through a single interface has become an important solution to reduce software complexity.

[0003] However, with the development of interface technology to high-speed standards such as 10G MAC, large servers face multiple challenges. Most of the existing solutions only achieve simple bus splitting or low-speed data sharing and cannot meet the secure and reliable acquisition requirements of high-speed interfaces for large servers. Some solutions process data through timestamps or packet scheduling, but large servers require faster and more accurate real-time transmission, and such designs instead increase latency; other solutions lack a multi-level exception protection mechanism and cannot resist the penetration of abnormal packets caused by sudden attacks or link interference, easily leading to abnormal processor loads. In addition, existing shared bus technologies are difficult to balance the security and bandwidth allocation efficiency of high-speed data transmission and difficult to guarantee the transmission quality of critical data in multi-service hybrid scenarios.

[0004] Therefore, how to propose a 10G MAC interface shared bus method and apparatus to improve the security, reliability, and transmission efficiency of interface data of large servers is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention provides a 10G MAC interface shared bus method and apparatus, which have the capabilities of anomaly detection and self-healing and support dynamic bandwidth allocation to meet the stringent requirements of large servers for security, reliability, and transmission efficiency.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] On the one hand, the present invention discloses a 10G MAC interface shared bus method, including:

[0008] Obtaining data information of data to be transmitted, and dividing data priorities according to the data information; meanwhile, establishing a baseline model by analyzing characteristic parameters of normal traffic;

[0009] Use the baseline model to perform anomaly detection on the transmitted data, and identify normal data and abnormal data;

[0010] The normal data is written into the corresponding priority queue according to the priority, the bandwidth requirement is predicted based on the historical traffic data, the queue weight is dynamically adjusted in combination with the MAC interface utilization rate, and the bus resources are allocated according to the queue weight ratio;

[0011] Match the MAC interface rate, and transmit the normal data to the MAC interface according to the allocated bus resources.

[0012] Preferably, a baseline model is established by analyzing the characteristic parameters of normal traffic, including:

[0013] After the system is started or reset, continuously collect traffic for a certain duration, and obtain normal traffic data based on traffic filtering;

[0014] Calculate the characteristic parameters of the normal traffic data and establish an initial baseline;

[0015] Use a sliding window with a fixed duration to calculate the characteristic parameters of the current traffic in real time. If the statistical values of consecutive multiple windows deviate from the initial baseline by more than a preset threshold, automatically trigger baseline update, and use the updated baseline as the new initial baseline;

[0016] Among them, the exponential weighted moving average algorithm is used for baseline update.

[0017] Preferably, using the baseline model to perform anomaly detection on the transmitted data, and identify normal data and abnormal data, including:

[0018] Obtain real-time transmitted data, and perform preliminary filtering on the real-time transmitted data based on the packet length and FCS check; among them, discard the real-time transmitted data with a packet length exceeding the preset range, and determine the real-time transmitted data that meets the preset range and fails the FCS check as abnormal data;

[0019] For the real-time transmitted data that passes the preliminary filtering, extract the traffic characteristics and compare them with the baseline model. The real-time transmitted data whose comparison result meets the passing condition is determined as normal data, and those that do not meet the passing condition are determined as abnormal data;

[0020] Write the abnormal data into an independent security buffer area, perform in-depth analysis on the abnormal data, and perform retransmission or discard according to the analysis result; write the normal data into the RAM.

[0021] Preferably, the queue weight Wi of the i-th priority queue i The calculation formula is as follows:

[0022]

[0023] Wherein, α i is the initial weight of the i-th priority queue, Q i is the queue depth of the i-th priority queue, Q i_max is the maximum queue depth of the i-th priority queue, η is the MAC interface utilization rate, k is a correction coefficient, and the correction coefficient is determined according to the predicted bandwidth requirement.

[0024] Preferably, allocating bus resources according to the queue weight ratio includes:

[0025] Normalize the queue weights of each priority queue;

[0026] Allocate the bus transmission time slots within a transmission period according to the normalized queue weights.

[0027] Preferably, matching the MAC interface rate and transmitting the normal data to the MAC interface according to the allocated bus resources includes:

[0028] According to the allocated transmission time slots, enable the read operation of the corresponding priority queue, and the enable signal activates the index FIFO read pointer of the corresponding queue to read the packet address from the RAM;

[0029] Output data is buffered through a cross-clock-domain asynchronous FIFO to generate a FIFO read enable signal for rate matching;

[0030] Map the output data to the AXI bus format of the MAC interface.

[0031] On the other hand, the present invention also proposes a 10G MAC interface shared bus device, including:

[0032] A data processing module, configured to obtain data information of the data to be transmitted, divide the data priority according to the data information; and establish a baseline model by analyzing the characteristic parameters of normal traffic at the same time;

[0033] A data identification module, configured to use the baseline model to perform anomaly detection on the transmitted data, and identify normal data and abnormal data;

[0034] A resource allocation module, configured to write the normal data into the corresponding priority queue according to the priority, predict the bandwidth requirement based on historical traffic data, dynamically adjust the queue weight in combination with the MAC interface utilization rate, and allocate bus resources according to the queue weight ratio;

[0035] A data transmission module, configured to match the MAC interface rate and transmit the normal data to the MAC interface according to the allocated bus resources.

[0036] Preferably, the data processing module includes:

[0037] A data acquisition unit, after the system is started or reset, continuously collects traffic for a certain duration, and filters the normal traffic data based on the traffic.

[0038] An initial baseline establishment unit, calculates the characteristic parameters of the normal traffic data, and establishes an initial baseline.

[0039] A baseline update unit, uses a sliding window with a fixed duration to calculate the characteristic parameters of the current traffic in real time. If the statistical values of multiple consecutive windows deviate from the initial baseline by more than a preset threshold, it automatically triggers a baseline update, and uses the updated baseline as the new initial baseline.

[0040] Among them, the exponential weighted moving average algorithm is used for baseline update.

[0041] Preferably, the resource allocation module includes:

[0042] A weight adjustment unit, predicts the bandwidth demand based on historical traffic data, and dynamically adjusts the queue weights in combination with the MAC interface utilization rate.

[0043] A calculation unit, normalizes the queue weights of each priority queue.

[0044] A time slot allocation unit, allocates the bus transmission time slots within a transmission cycle according to the normalized queue weights.

[0045] Preferably, the data transmission module includes:

[0046] A data reading unit, according to the allocated transmission time slots, enables the reading operations of the corresponding priority queues, enables the signal to activate the index FIFO read pointer of the corresponding queue, and reads the packet address from the RAM.

[0047] A rate matching unit, buffers the output data through a cross-clock domain asynchronous FIFO, and generates a FIFO read enable signal for rate matching.

[0048] A bus transmission unit, maps the output data to the AXI bus format of the MAC interface.

[0049] As can be seen from the above technical solutions, compared with the prior art, the present invention discloses a 10G MAC interface shared bus method and device, which ensures data security through a dual exception detection mechanism (hardware-level preliminary filtering based on packet length / FCS check + in-depth detection of the traffic feature baseline model), realizes intelligent scheduling of priority queues by combining a dynamic weight allocation algorithm (integrating queue depth, interface utilization rate, and predicted bandwidth demand), and uses a cross-clock domain asynchronous FIFO and a packet counter reset mechanism to ensure the reliability and self-healing ability of high-speed transmission, significantly improving the interface security, transmission efficiency, and anti-interference ability of large servers in multi-source data scenarios. Description of the Drawings

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on the provided drawings.

[0051] Figure 1 It is the flowchart of the method provided by the present invention;

[0052] Figure 2 It is the device architecture diagram provided by the present invention. Specific embodiments

[0053] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0054] On the one hand, referring to Figure 1 , the embodiments of the present invention disclose a method for sharing a 10G MAC interface bus, including:

[0055] S1. Obtain the data information of the data to be transmitted, and divide the data priority according to the data information; at the same time, establish a baseline model by analyzing the characteristic parameters of normal traffic.

[0056] Receive the Ethernet data packets to be transmitted (formatted as AXI streams) from multiple source ports. Parse the destination MAC address, source MAC address, and packet type of each data packet. According to the preset policy (combining MAC address, packet type, service level agreement SLA, etc.) or processor configuration, divide the data packets into different priority categories. In this embodiment, high-priority control signaling, medium-priority real-time data, and low-priority ordinary data.

[0057] In this step, establishing a baseline model by analyzing the characteristic parameters of normal traffic includes:

[0058] After the system starts or resets, continuously collect traffic for a certain duration, and obtain normal traffic data based on traffic filtering; after the system starts, collect 500 ms of normal traffic, and filter out overlong packets (>1518 bytes), ultra-short packets (<64 bytes), and packets with abnormal FCS verification.

[0059] Calculate the characteristic parameters of the normal traffic data, including average packet length, traffic rate, protocol type ratio, etc., and establish an initial baseline.

[0060] Use a sliding window with a fixed duration to calculate the characteristic parameters of the current traffic in real time. If the statistical values of multiple consecutive windows deviate from the initial baseline by more than a preset threshold, automatically trigger baseline update, and use the updated baseline as the new initial baseline. Among them, the exponential weighted moving average algorithm is used for baseline update.

[0061] Specifically, in this embodiment, a 200ms sliding window is used to calculate the current traffic characteristics in real time. If the statistical values of 3 consecutive windows deviate from the initial baseline by ±20%, trigger baseline update, and the update formula is:

[0062] New baseline = a × current window characteristic + (1 - a) × old baseline.

[0063] S2. Use the baseline model to perform anomaly detection on the transmitted data, and identify normal data and abnormal data, including:

[0064] S21. Obtain the real-time transmitted data, and perform preliminary filtering on the real-time transmitted data based on the packet length and FCS check; among them, discard the real-time transmitted data with a packet length exceeding the preset range, and determine the real-time transmitted data that meets the preset range but fails the FCS check as abnormal data.

[0065] First, perform packet length filtering, and design a counter cnt for each data packet. When the valid signal is high, cnt is incremented by 1 in each clock cycle. When the last signal is high, cnt is cleared. If last is high when cnt = 1, it indicates a very short packet with a length less than or equal to 9 bytes (AXI64bit data, the first beat contains the first 8 bytes, and last being pulled high in the first beat means the valid data is less than or equal to 8 bytes, plus possible padding or frame gap issues can be regarded as very short), directly pull down the valid signal of this packet and discard the entire packet. If cnt exceeds the preset threshold (corresponding to the maximum packet length threshold of 1518 bytes), then force the valid of the subsequent data to be pulled down, pull up the last at the position where the threshold is reached, and set the user signal to 0 to mark this packet as an abnormal packet (truncated due to being too long).

[0066] At the end of the packet (when last is valid), calculate the FCS check value of the current packet and compare it with the FCS value carried in the packet. If the check fails, set the user signal to 0 when last is valid to mark this packet as an FCS check anomaly.

[0067] Determine the real-time transmitted data with a packet length exceeding the preset range (marked as truncated due to being too long) or meeting the preset range but failing the FCS check (user = 0) as abnormal data.

[0068] S21. For the real-time transmission data that passes the preliminary filtering (i.e., not discarded by the packet length filtering and passing the FCS check, user = 1), extract the traffic characteristics and compare them with the baseline model. The real-time transmission data whose comparison result meets the passing conditions is determined as normal data, and the data that does not meet the passing conditions is determined as abnormal data.

[0069] S23. Write the abnormal data into the independent security buffer area, perform in-depth analysis on the abnormal data, and retransmit or discard it according to the analysis result; write the normal data into the RAM.

[0070] In this embodiment, the determined normal data packets (AXI data stream) and their metadata (address, length, priority) are written into the main RAM buffer. When writing into the RAM, it is necessary to combine the priority information and write the start address and length information of the packet into the index FIFO corresponding to the priority.

[0071] Specifically, when writing into the RAM, define a write address counter waddr, a register first_addr to record the start address of the current packet, and a counter len to record the valid length of the current packet (the number of beats with valid = 1). When writing the last data of a packet (last = 1):

[0072] If the packet is marked as abnormal at this time (user = 0, whether it is an overlong truncation, FCS error, or baseline model anomaly), then reset the value of waddr back to the first_addr value when this packet started to be written. This means that the subsequent written data will directly overwrite the space of this abnormal packet in the RAM, achieving efficient discarding without wasting bandwidth.

[0073] If the packet is normal at this time (user = 1), then write first_addr and len as index information into the index FIFO corresponding to its priority for subsequent scheduling and reading. Then clear len to prepare for recording the next packet.

[0074] S3. Write the normal data into the corresponding priority queue according to the priority, predict the bandwidth requirement based on the historical traffic data, dynamically adjust the queue weight in combination with the MAC interface utilization rate, and allocate the bus resources according to the queue weight ratio.

[0075] In this step, the system maintains multiple priority queues. Each queue is associated with a RAM buffer and the corresponding index FIFO (storing the address and length information of the normal data packets in this queue in the RAM).

[0076] The queue weight W of the i-th priority queue i The calculation formula is as follows:

[0077]

[0078] where α i is the initial weight of the i-th priority queue, Q i is the queue depth of the i-th priority queue, Q i_max is the maximum queue depth of the i-th priority queue, η is the MAC interface utilization rate, k is a correction factor, and the correction factor is determined according to the predicted bandwidth requirement.

[0079] This weight formula incorporates the initial priority weight α i , the degree of queue congestion , the degree of interface busyness η, and the macro bandwidth prediction k. The more congested the queue (the larger Q i ) or the busier the interface (the larger η), the greater its weight will be magnified and it will be easier to obtain resources; high-priority queues (α i large) have a high basic weight. k micro-adjusts the overall allocation strategy according to the prediction.

[0080] Normalize the queue weights of each priority queue to obtain the resource ratio that each queue should occupy

[0081] Allocate the bus transmission time slot t = P i ×T within a transmission cycle T according to the normalized queue weight, and the scheduler will poll and serve the index FIFO of each queue according to this time slot allocation scheme.

[0082] S4. Match the MAC interface rate and transmit the normal data to the MAC interface according to the allocated bus resources, including:

[0083] S41. According to the allocated transmission time slot, enable the read operation of the corresponding priority queue. The enable signal activates the read pointer of the index FIFO of the corresponding queue, and reads the packet address from the RAM.

[0084] The transmit enable signal activates the read pointer of the index FIFO of this queue.

[0085] Read an entry from the index FIFO to obtain the start address and length (packet length) of a packet to be transmitted in the RAM.

[0086] According to this address and length information, read the packet content from the RAM.

[0087] S42. Buffer and output the data asynchronously through a cross-clock domain FIFO, and generate a FIFO read enable signal for rate matching.

[0088] Since the source data rate (multiple low-speed MAC aggregations) and the target interface rate (10G MAC) may be different, and there are clock domain differences (source port clock, internal processing clock, 10G MAC clock): In this embodiment, the data stream read from the RAM is written into a large-capacity asynchronous FIFO buffer located before the 10G MAC interface. This FIFO is used to smooth out the burst fluctuations of the packet stream and absorb the rate differences.

[0089] This asynchronous FIFO is responsible for handling the conversion from the internal processing clock domain to the 10G MAC clock domain.

[0090] The transmit ready signal (tx_ready) of the 10G MAC interface is ANDed with the not-empty signal (fifo_empty) of this asynchronous FIFO, and the result is used as the read enable (fifo_rd_en) of the asynchronous FIFO. This ensures that data is read only when the MAC interface is ready to receive and there is data in the FIFO, perfectly matching the MAC interface rate and preventing underflow.

[0091] Read the output data from the rate-matching asynchronous FIFO.

[0092] S43. Map the output data to the AXI bus format of the MAC interface to achieve bus sharing of multi-source data.

[0093] On the other hand, the present invention also proposes a 10G MAC interface shared bus device, as Figure 2 shown, including:

[0094] A data processing module, used to obtain the data information of the data to be transmitted, divide the data priority according to the data information; at the same time, establish a baseline model by analyzing the characteristic parameters of normal traffic;

[0095] A data identification module, used to perform anomaly detection on the transmitted data using the baseline model to identify normal data and abnormal data;

[0096] A resource allocation module, used to write the normal data into the corresponding priority queue according to the priority, predict the bandwidth demand based on historical traffic data, dynamically adjust the queue weights in combination with the MAC interface utilization rate, and allocate bus resources according to the queue weight ratio;

[0097] A data transmission module, used to match the MAC interface rate and transmit the normal data to the MAC interface according to the allocated bus resources.

[0098] Preferably, the data processing module includes a priority division unit and a baseline construction unit:

[0099] A data acquisition unit, after the system starts or resets, continuously collects traffic for a certain period of time, and obtains normal traffic data based on traffic filtering;

[0100] An initial baseline establishment unit calculates characteristic parameters of normal traffic data and establishes an initial baseline;

[0101] A baseline update unit uses a sliding window with a fixed duration to calculate characteristic parameters of the current traffic in real time. If the statistical values of multiple consecutive windows deviate from the initial baseline by more than a preset threshold, it automatically triggers a baseline update and uses the updated baseline as the new initial baseline;

[0102] Among them, an exponential weighted moving average algorithm is used for baseline update.

[0103] Preferably, the resource allocation module includes:

[0104] A weight adjustment unit predicts the bandwidth requirement based on historical traffic data and dynamically adjusts the queue weights in combination with the MAC interface utilization rate;

[0105] A calculation unit normalizes the queue weights of each priority queue;

[0106] A time slot allocation unit allocates the bus transmission time slots within a transmission period according to the normalized queue weights.

[0107] Preferably, the data transmission module includes:

[0108] A data reading unit enables the reading operation of the corresponding priority queue according to the allocated transmission time slot. The enable signal activates the index FIFO read pointer of the corresponding queue and reads the packet address from the RAM;

[0109] A rate matching unit buffers the output data through a cross-clock domain asynchronous FIFO and generates a FIFO read enable signal for rate matching;

[0110] A bus transmission unit maps the output data to the AXI bus format of the MAC interface.

[0111] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For the relevant parts, reference can be made to the description in the method part.

[0112] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A 10G MAC interface shared bus method, characterized in that: include: Obtaining data information of data to be transmitted, and dividing the data priority according to the data information; At the same time, a baseline model is established by analyzing the characteristic parameters of normal traffic; Performing anomaly detection on the transmitted data using the baseline model to identify normal data and abnormal data; Normal data is written into the corresponding priority queue according to its priority, bandwidth requirements are predicted based on historical traffic data, queue weights are dynamically adjusted in combination with MAC interface utilization, and bus resources are allocated according to the queue weight ratio; Match the MAC interface rate and transmit the normal data to the MAC interface according to the allocated bus resources.

2. The method for sharing a bus of a 10G MAC interface according to claim 1, wherein A baseline model is established by analyzing the characteristic parameters of normal traffic, including: After the system is started or reset, traffic is continuously collected for a certain period of time, and normal traffic data is obtained based on traffic filtering; Calculate characteristic parameters of normal traffic data and establish an initial baseline; A sliding window with a fixed duration is used to calculate the characteristic parameters of the current traffic in real time. If the statistical values of multiple consecutive windows deviate from the initial baseline by more than a preset threshold, a baseline update is automatically triggered and the updated baseline is used as the new initial baseline. Among them, the exponentially weighted moving average algorithm is used to update the baseline.

3. A 10G MAC interface shared bus method according to claim 1, characterized in that: The baseline model is used to perform anomaly detection on the transmitted data to identify normal data and abnormal data, including: Acquire real-time transmission data, and perform preliminary filtering on the real-time transmission data based on data packet length and FCS check; wherein the real-time transmission data whose data packet length exceeds a preset range is discarded, and the real-time transmission data that meets the preset range and fails the FCS check is determined as abnormal data; For the real-time transmission data that has passed the preliminary filtering, traffic characteristics are extracted and compared with the baseline model. The real-time transmission data that meets the passing conditions is determined as normal data, and the real-time transmission data that does not meet the passing conditions is determined as abnormal data; The abnormal data is written into an independent security cache area, the abnormal data is deeply analyzed, and retransmitted or discarded according to the analysis result; and the normal data is written into RAM.

4. A 10G MAC interface shared bus method according to claim 1, characterized in that Queue weight W of the i-th priority queue i The calculation formula is as follows: where α i is the initial weight of the i-th priority queue, Q i is the queue depth of the i-th priority queue, Q i_max is the maximum queue depth of the i-th priority queue, η is the MAC interface utilization rate, k is a correction factor, and the correction factor is determined according to the predicted bandwidth requirement.

5. A 10G MAC interface shared bus method according to claim 4, characterized in that: Bus resources are allocated according to queue weight ratio, including: Normalize the queue weights of each priority queue; The bus transmission time slots within a transmission cycle are allocated according to the normalized queue weights.

6. A 10G MAC interface shared bus method according to claim 5, characterized in that: Matching the MAC interface rate and transmitting the normal data to the MAC interface according to the allocated bus resources includes: According to the allocated transmission time slot, the read operation of the corresponding priority queue is enabled, the enable signal activates the index FIFO read pointer of the corresponding queue, and reads the data packet address from the RAM; Output data is buffered by asynchronous FIFO across clock domains, generating FIFO read enable signals for rate matching; Maps the output data to the AXI bus format of the MAC interface.

7. A 10G MAC interface shared bus device, characterized in that, include: A data processing module is used to obtain data information of data to be transmitted and to prioritize data according to the data information; At the same time, a baseline model is established by analyzing the characteristic parameters of normal traffic; A data identification module, configured to perform anomaly detection on the transmitted data using the baseline model and identify normal data and abnormal data; A resource allocation module, which is used to write the normal data into the corresponding priority queue according to the priority, predict the bandwidth requirement based on the historical traffic data, dynamically adjust the queue weight in combination with the MAC interface utilization rate, and allocate the bus resources according to the queue weight ratio; A data transmission module, which is used to match the MAC interface rate and transmit the normal data to the MAC interface according to the allocated bus resources.

8. The 10G MAC interface shared bus device according to claim 7, characterized in that: The data processing module includes: A data acquisition unit, which continuously acquires the traffic for a certain period of time after the system starts or resets, and obtains the normal traffic data based on traffic filtering; An initial baseline establishment unit, which calculates the characteristic parameters of the normal traffic data and establishes an initial baseline; A baseline update unit, which uses a sliding window with a fixed duration to calculate the characteristic parameters of the current traffic in real time. If the statistical values of multiple consecutive windows deviate from the initial baseline by more than a preset threshold, it automatically triggers the baseline update and uses the updated baseline as the new initial baseline; Among them, the exponential weighted moving average algorithm is used for baseline update.

9. The 10G MAC interface shared bus device according to claim 7, characterized in that: The resource allocation module includes: A weight adjustment unit, which predicts the bandwidth requirement based on the historical traffic data and dynamically adjusts the queue weight in combination with the MAC interface utilization rate; A calculation unit, which normalizes the queue weights of each priority queue; A time slot allocation unit, which allocates the bus transmission time slots within a transmission cycle according to the normalized queue weights.

10. A 10G MAC interface shared bus device according to claim 9, characterized in that, The data transmission module includes: A data reading unit, which enables the reading operation of the corresponding priority queue according to the allocated transmission time slot, enables the signal to activate the index FIFO read pointer of the corresponding queue, and reads the packet address from the RAM; A rate matching unit, which buffers and outputs the data through a cross-clock domain asynchronous FIFO to generate a FIFO read enable signal for rate matching; A bus transmission unit, which maps the output data to the AXI bus format of the MAC interface.

Images