Image sensor, arrangement structure and control method

Abstract

The invention provides an image sensor, an arrangement structure and a control method, the image sensor comprises a plurality of pixel blocks arranged in an array, and each pixel block comprises a reset unit used for resetting at least one of a floating diffusion node, a photosensitive unit and an overflow unit; the photosensitive unit is used for generating a first charge signal and a second charge signal based on photoelectric conversion, storing the first charge signal and transferring the first charge signal to the floating diffusion node; the overflow unit comprises an overflow path and a quantization path, the overflow path is coupled to the photosensitive unit, the quantization path is coupled to the floating diffusion node, the second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node based on the quantization path; and the readout unit is used for carrying out quantitative readout on at least the first charge signal and the second charge signal. According to the invention, the problem of poor image quality caused by the influence of overflow charges on the floating diffusion nodes of each pixel block of the existing image sensor is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and particularly to an image sensor, an arrangement structure and a control method. Background Art

[0002] An image sensor includes a plurality of pixel blocks 100' arranged in an array, and the circuit structure of each pixel block 100' is as Figure 1 , including a reset transistor M1', a gain transistor M2', a transfer transistor M3', an overflow transistor M4', a source follower transistor M5', a selection transistor M6', a photosensitive element PD' and an overflow capacitor C1', and the specific connection is as shown in the figure. During the exposure stage, the overflow charge generated by the photosensitive element PD' is stored in the overflow capacitor C1' via the transfer transistor M3', the floating diffusion node FD', the gain transistor M2' and the overflow transistor M4'; during the quantization stage, the overflow charge stored in the overflow capacitor C1' is quantized and read out via the overflow transistor M4', the gain transistor M2' and the floating diffusion node FD', and the related timing is as Figure 2 shown.

[0003] The disadvantages of the above circuit are as follows: 1. When the quantization readout is not completed, the floating diffusion node FD' cannot be reset, so the incomplete correlated double sampling (CDS), dark current, fixed pattern noise (FPN), etc. will have a greater impact on the image; 2. Since the reset signal includes some charges that overflow to the floating diffusion node FD', in a strong light state, there are more charges in the floating diffusion node FD', and there will be a great problem of photo-response non-uniformity (PRNU); 3. It may affect the working state of the source follower transistor M5', resulting in various unsatisfactory responses of the image.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an image sensor, an arrangement structure and a control method, which are used to solve the problem that the image quality is poor due to the influence of the overflow charge on the charge of the floating diffusion node in each pixel block of the existing image sensor.

[0006] To achieve the above purpose and other related purposes, the present invention provides an image sensor, including a plurality of pixel blocks arranged in an array, and each pixel block includes a reset unit, a photosensitive unit, an overflow unit and a readout unit;

[0007] The reset unit is coupled to the floating diffusion node and is configured to reset at least one of the floating diffusion node, the photosensitive unit, and the overflow unit;

[0008] The photosensitive unit is coupled to the floating diffusion node, generates a first charge signal and a second charge signal based on photoelectric conversion, stores the first charge signal, and transfers the first charge signal to the floating diffusion node;

[0009] The overflow unit includes an overflow path and a quantization path. The overflow path is coupled to the photosensitive unit, and the quantization path is coupled to the floating diffusion node. The second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node based on the quantization path;

[0010] The readout unit is coupled to the floating diffusion node and at least quantizes and reads out the first charge signal and the second charge signal.

[0011] Optionally, the overflow unit includes an exposure transistor, a quantization transistor, and an overflow capacitor. The control terminal of the exposure transistor receives a first control signal, the first terminal is coupled to the photosensitive unit, and the second terminal is coupled to the first terminal of the overflow capacitor. The control terminal of the quantization transistor receives a second control signal, the first terminal is coupled to the floating diffusion node, and the second terminal is coupled to the first terminal of the overflow capacitor. The second terminal of the overflow capacitor is coupled to a ground potential or a variable potential. Wherein, the exposure transistor forms the overflow path, and the quantization transistor forms the quantization path.

[0012] Optionally, the pixel block further includes a fast reset unit, which is coupled to both ends of the overflow capacitor and is configured to quickly reset the overflow unit.

[0013] Optionally, the fast reset unit includes a fast reset transistor. The control terminal receives a third control signal or is coupled to its second terminal. The first terminal is coupled to the first terminal of the overflow capacitor, and the second terminal is coupled to the second terminal of the overflow capacitor. Wherein, the second terminal of the overflow capacitor is coupled to a variable potential.

[0014] Optionally, the photosensitive unit includes M photosensitive elements and M transfer transistors, which correspond one by one. M is an integer greater than or equal to 1. The control terminal of the transfer transistor receives a transfer control signal, the first terminal is coupled to the floating diffusion node, the second terminal is coupled to the first terminal of the photosensitive element, and the second terminal of the photosensitive element is coupled to a reference potential. Wherein, the overflow path is coupled to the first terminals of S of the photosensitive elements, and S is an integer greater than or equal to 1 and less than M;

[0015] Alternatively, the photosensitive unit includes (N+T) photosensitive elements and N transfer transistors. The (N+T) photosensitive elements include N first photosensitive elements and T second photosensitive elements. The N first photosensitive elements correspond to the N transfer transistors one by one. N is an integer greater than or equal to 1, and T is an integer greater than or equal to 1. The control terminal of the transfer transistor receives a transfer control signal. The first terminal is coupled to the floating diffusion node, and the second terminal is coupled to the first terminal of the first photosensitive element. The second terminal of the first photosensitive element is coupled to a reference potential. The first terminal of the second photosensitive element is coupled to the overflow path, and the second terminal is coupled to the reference potential.

[0016] Optionally, the reset unit includes a reset transistor. The control terminal receives a reset control signal. The first terminal is coupled to a first power supply potential, and the second terminal is coupled to the floating diffusion node.

[0017] And / or, the readout unit includes a source follower transistor and a selection transistor. The control terminal of the source follower transistor is coupled to the floating diffusion node. The first terminal is coupled to a second power supply potential, and the second terminal is coupled to the first terminal of the selection transistor. The control terminal of the selection transistor receives a selection control signal, and the second terminal is coupled to a column line.

[0018] Optionally, the pixel block further includes a gain unit, which is coupled between the reset unit and the floating diffusion node and is used for switching different gain modes.

[0019] Optionally, the gain unit includes a gain transistor. The control terminal receives a gain control signal. The first terminal is coupled to the reset unit, and the second terminal is coupled to the floating diffusion node. Wherein, the quantization path is coupled to the floating diffusion node or a low-gain connection node corresponding to the gain unit.

[0020] The present invention also provides a control method for an image sensor as described above, including:

[0021] Reset stage: performing a reset operation on the floating diffusion node, the photosensitive unit, and the overflow unit;

[0022] Exposure stage: opening the overflow path and closing the quantization path, and storing the second charge signal into the overflow unit through the overflow path;

[0023] Quantization stage: closing the overflow path to perform quantization readout on the first reset signal and the first charge signal based on the floating diffusion node;

[0024] Quantitatively read the second reset signal based on the floating diffusion node, then control the quantization path to open and then close, and transfer the second charge signal to the floating diffusion node through the quantization path for quantitative readout; and / or, open the quantization path, transfer the second charge signal to the floating diffusion node through the quantization path for quantitative readout, and then perform a reset operation on the floating diffusion node to quantitatively read the second reset signal based on the floating diffusion node.

[0025] Optionally, when the pixel block includes a gain unit, the method for quantitatively reading the first reset signal and the first charge signal based on the floating diffusion node includes: controlling the gain unit to open and then close to quantitatively read the first reset signal in different gain modes based on the floating diffusion node, and then controlling the gain unit to close and then open to quantitatively read the first charge signal in different gain modes based on the floating diffusion node; and / or, quantitatively reading the second reset signal based on the floating diffusion node, and before controlling the quantization path to open and then close and transferring the second charge signal to the floating diffusion node through the quantization path for quantitative readout, further includes the step of performing a reset operation on the floating diffusion node.

[0026] Optionally, when the pixel block does not include a fast reset unit, the reset unit performs a reset operation on the floating diffusion node, the photosensitive unit, and the overflow unit during the reset stage; when the pixel block includes a fast reset unit, the fast reset unit or the fast reset unit in cooperation with the reset unit performs a reset operation on the overflow unit during the reset stage.

[0027] Optionally, the reset transistor of the reset unit is turned on during the reset stage and turned off during the quantization stage, where the reset transistor is turned off after or simultaneously with the first turn-on of the selection transistor of the readout unit; and / or, when the control method includes reading the second charge signal first and then reading the second reset signal, during the process of quantitatively reading the second reset signal based on the reset operation, the process of turning on and then off the reset transistor corresponds to the operation of turning off and then on the selection transistor, where the reset transistor is turned off during the off period of the selection transistor; and / or, before reading the second charge signal, further includes the step of opening the overflow path to transfer the charge in the photosensitive unit.

[0028] The present invention also provides an arrangement structure of the image sensor as described above, including:

[0029] The reset unit includes a reset transistor, the photosensitive unit includes at least one photosensitive element and at least one transfer transistor, the overflow unit includes an exposure transistor, a quantization transistor and an overflow capacitor, and the readout unit includes a source follower transistor and a selection transistor;

[0030] The transfer transistor is disposed in the first corner region of the photosensitive element, the source follower transistor is disposed in a receiving area of the transfer transistor away from the photosensitive element, the floating diffusion node is disposed in the receiving area and on one side of the source follower transistor, the exposure transistor is disposed in the second corner region of the photosensitive element, the quantization transistor is disposed outside the receiving area, and the reset transistor and the selection transistor are disposed outside the receiving area.

[0031] Optionally, when the pixel block includes a gain unit and the gain unit includes a gain transistor, the gain transistor is disposed outside the receiving area and between the quantization transistor and the floating diffusion node; and / or, when the pixel block includes a fast reset unit and the fast reset unit includes a fast reset transistor, the fast reset transistor is disposed on a side of a connection area of the overflow capacitor away from the quantization transistor; and / or, the first corner region and the second corner region are arranged facing each other in a horizontal direction; and / or, the quantization transistor is disposed on a side of the floating diffusion node away from the source follower transistor; and / or, a connection area of the overflow capacitor is disposed on a side of the quantization transistor away from the floating diffusion node; and / or, the reset transistor and the selection transistor are respectively disposed above and below the source follower transistor.

[0032] Optionally, the transfer transistor is disposed obliquely in the first corner region at a first angle, and the exposure transistor is disposed obliquely in the second corner region at a second angle, wherein the first angle is equal to the second angle.

[0033] As described above, for the image sensor, the arrangement structure and the control method of the present invention, for overflow charges, an additional overflow path is provided. By separating the overflow path and the quantization path, the overflow charges in the exposure stage directly pass through the overflow path for storage without passing through the floating diffusion node, avoiding the charge influence of the overflow charges on the floating diffusion node, thereby avoiding the influence on subsequent quantization readout, and being beneficial to improving the image quality. Description of the Drawings

[0034] Figure 1 It shows a circuit schematic diagram of a pixel block in a conventional image sensor.

[0035] Figure 2 It shows Figure 1 a timing diagram of the pixel block shown.

[0036] Figure 3 It shows a circuit schematic diagram of a pixel block in the image sensor according to the first embodiment of the present invention.

[0037] Figure 4 It shows another circuit schematic diagram of a pixel block in the image sensor according to the first embodiment of the present invention.

[0038] Figure 5 It shows yet another circuit schematic diagram of a pixel block in the image sensor according to the first embodiment of the present invention.

[0039] Figure 6 It shows a timing diagram of a pixel block in the image sensor according to the first embodiment of the present invention.

[0040] Figure 7 It shows another timing diagram of a pixel block in the image sensor according to the first embodiment of the present invention.

[0041] Figure 8 It shows yet another timing diagram of a pixel block in the image sensor according to the first embodiment of the present invention.

[0042] Figure 9 It shows a circuit schematic diagram of a pixel block in the image sensor according to the second embodiment of the present invention.

[0043] Figure 10 It shows a timing diagram of a pixel block in the image sensor according to the second embodiment of the present invention.

[0044] Figure 11 It shows a circuit schematic diagram of a pixel block in the image sensor according to the third embodiment of the present invention.

[0045] Figure 12 It shows another circuit schematic diagram of a pixel block in the image sensor according to the third embodiment of the present invention.

[0046] Figure 13 It shows a timing diagram of a pixel block in the image sensor according to the third embodiment of the present invention.

[0047] Figure 14 It shows a schematic diagram of the arrangement structure of the image sensor according to the fourth embodiment of the present invention.

[0048] Description of component labels

[0049] 100’, 100 pixel blocks

[0050] 110 reset unit

[0051] 120 photosensitive unit

[0052] 130 overflow unit

[0053] 140 readout unit

[0054] 150 Gain Unit

[0055] 160 Fast Reset Unit Detailed Implementation Manner

[0056] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please refer to Figures 3 to 14 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The form, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout form may also be more complex.

[0058] Embodiment 1

[0059] As Figure 3 shown, this embodiment provides an image sensor, including a plurality of pixel blocks 100 arranged in an array; each pixel block 100 includes a reset unit 110, a photosensitive unit 120, an overflow unit 130, and a readout unit 140; in one implementation, the circuit structures of each pixel block 100 are the same.

[0060] The reset unit 110 is coupled to the floating diffusion node FD and is used to reset at least one of the floating diffusion node FD, the photosensitive unit 130, and the overflow unit 140.

[0061] As an example, the reset unit 110 includes a reset transistor M1, the control terminal receives a reset control signal RST, the first terminal is coupled to the first power supply potential, and the second terminal is coupled to the floating diffusion node FD.

[0062] In one implementation, the reset transistor M1 includes an NMOS transistor. At this time, the gate of the reset transistor M1 receives the reset control signal RST, the drain is connected to the first power supply potential, and the source is connected to the floating diffusion node FD; wherein, the first power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other implementations, it is also feasible for the reset transistor M1 to include a PMOS transistor, which has no substantial impact on this embodiment.

[0063] The photosensitive unit 120 is coupled to the floating diffusion node FD, generates a first charge signal and a second charge signal based on photoelectric conversion, stores the first charge signal, and transfers the first charge signal to the floating diffusion node FD.

[0064] In combination with the actual application scenario, the first charge signal refers to the charge signal corresponding to the potential well part, and the second charge signal refers to the charge signal corresponding to the overflow part after the charge exceeds the potential well; when the amount of charge sensed by the photosensing unit 120 does not reach the overflow state, the converted charge signal only includes the first charge signal and is stored in the photosensing unit 120. At this time, it can be considered that the second charge signal is zero; when the amount of charge sensed by the photosensing unit 120 reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal. Among them, the first charge signal is stored in the photosensing unit 120, and the second charge signal overflows outside the photosensing unit 120 and is stored in the overflow unit 130 based on the overflow path. In some applications, the first charge signal can also be defined as the potential well charge signal, and the second charge signal can be defined as the overflow charge signal.

[0065] As an example, as Figure 3 and Figure 4 shown, the photosensing unit 130 includes M photosensing elements PD and M transfer transistors M2, which correspond to each other one by one, and M is an integer greater than or equal to 1; the control terminal of the transfer transistor M2 receives the transfer control signal TX, the first terminal is coupled to the floating diffusion node FD, the second terminal is coupled to the first terminal of the photosensing element PD, and the second terminal of the photosensing element PD is coupled to the reference potential; among them, the overflow path is coupled to the first terminals of S photosensing elements, S is an integer greater than or equal to 1 and S is less than M. For example, in this example, S is 1. The overflow path of the overflow unit 130 is coupled to the first terminal of the corresponding photosensing element PD to receive the overflow charge signal, which can be coupled to the first terminal of any one photosensing element PD, or can be simultaneously coupled to the first terminals of multiple photosensing elements PD to achieve signal reception; of course, it can also be that the overflow path of the overflow unit 130 is coupled to the second terminal of the corresponding transfer transistor M2 to receive the overflow charge signal, which can be coupled to the second terminal of any one transfer transistor M2, or can be simultaneously coupled to the second terminals of multiple transfer transistors M2 to achieve signal reception. In one implementation manner, when M is greater than 1, the photosensing unit 120 is an M - shared structure. For example, each photosensing element shares the floating diffusion node region, the read - out unit, and the reset unit. In one implementation manner, (M - S) photosensing elements PD are used to obtain traditional image signals, and relevant double - sampled data can be obtained. Further, relevant double - sampled data at different gains can be obtained. S photosensing elements PD are used to obtain image signals with overflow signals, and relevant double - sampled data can be obtained, or non - truly relevant double - sampled data can be obtained.

[0066] In one implementation, the photosensitive element PD includes a photodiode, and the transfer transistor M2 includes an NMOS transistor. At this time, the gate of the transfer transistor M2 receives a transfer control signal TX, the drain is connected to the floating diffusion node FD, the source is connected to the first end of the photosensitive element PD (such as an N-type ion-doped region), and the second end of the photosensitive element PD (such as a P-type ion-doped region) is connected to a reference potential, which is usually a ground potential or a negative potential. Of course, in other implementations, it is also feasible that the photosensitive element PD includes a grating or a photoconductor, and the transfer transistor M2 includes a PMOS transistor, which has no substantial impact on this embodiment.

[0067] As another example, as Figure 5 shown, the photosensitive unit 130 includes (N + T) photosensitive elements and N transfer transistors M2. The (N + T) photosensitive elements include N first photosensitive elements PD1 and T second photosensitive elements PD2. The N first photosensitive elements PD1 and the N transfer transistors M2 are in one-to-one correspondence. N is an integer greater than or equal to 1, and T is an integer greater than or equal to 1. In this example, T is equal to 1. The control end of the transfer transistor M2 receives the transfer control signal TX, the first end is coupled to the floating diffusion node FD, the second end is coupled to the first end of the first photosensitive element PD1, and the second end of the first photosensitive element PD1 is coupled to a reference potential. The first end of the second photosensitive element PD2 is coupled to the overflow path of the overflow unit 130, and the second end is coupled to a reference potential. In this example, when N is greater than 1, the photosensitive unit 120 is an N-sharing structure.

[0068] In one implementation, the first photosensitive element PD1 and the second photosensitive element PD2 include photodiodes, and the transfer transistor M2 includes an NMOS transistor. At this time, the gate of the transfer transistor M2 receives a transfer control signal TX, the drain is connected to the floating diffusion node FD, the source is connected to the first end of the first photosensitive element PD1 (such as an N-type ion-doped region), the second end of the first photosensitive element PD1 (such as a P-type ion-doped region) is connected to a reference potential, the first end of the second photosensitive element PD2 (such as an N-type ion-doped region) is connected to the overflow path of the overflow unit 130, and the second end (such as a P-type ion-doped region) is connected to a reference potential, which is usually a ground potential or a negative potential. Of course, in other implementations, it is also feasible that the first photosensitive element PD1 and the second photosensitive element PD2 include a grating or a photoconductor, and the transfer transistor M2 includes a PMOS transistor, which has no substantial impact on this embodiment.

[0069] The overflow unit 130 includes an overflow path and a quantization path. The overflow path is coupled to the photosensitive unit 120, and the quantization path is coupled to the floating diffusion node FD. The second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node FD based on the quantization path. By adding the overflow path, the overflow path and the quantization path are separated, avoiding the second charge signal overflowing from the photosensitive unit 120 during the exposure stage passing through the floating diffusion node FD and leaving residues, which affects the subsequent quantization and readout.

[0070] As an example, the overflow unit 130 includes an exposure transistor M3, a quantization transistor M4, and an overflow capacitor C1. The control terminal of the exposure transistor M3 receives a first control signal OFG, the first terminal is coupled to the photosensitive unit 120, and the second terminal is coupled to the first terminal of the overflow capacitor C1. The control terminal of the quantization transistor M4 receives a second control signal OF_CTL, the first terminal is coupled to the floating diffusion node FD, and the second terminal is coupled to the first terminal of the overflow capacitor C1. The second terminal of the overflow capacitor C1 is coupled to the ground potential. Among them, the exposure transistor M3 forms the overflow path, and the quantization transistor M4 forms the quantization path.

[0071] In one implementation, the exposure transistor M3 includes an NMOS transistor, and the quantization transistor M4 includes an NMOS transistor. At this time, the gate of the exposure transistor M3 receives the first control signal OFG, the drain is connected to the photosensitive unit 120, and the source is connected to the first terminal of the overflow capacitor C1. The gate of the quantization transistor M4 receives the second control signal OF_CTL, the drain is connected to the floating diffusion node FD, and the source is connected to the first terminal of the overflow capacitor C1. Of course, in other implementations, it is also feasible that the exposure transistor M3 includes a PMOS transistor and the quantization transistor M4 includes a PMOS transistor, which has no substantial impact on this embodiment.

[0072] The readout unit 140 is coupled to the floating diffusion node FD and quantizes and reads out at least the first charge signal and the second charge signal.

[0073] As an example, the readout unit 140 includes a source follower transistor M5 and a selection transistor M6. The control terminal of the source follower transistor M5 is coupled to the floating diffusion node FD, the first terminal is coupled to the second power supply potential, and the second terminal is coupled to the first terminal of the selection transistor M6. The control terminal of the selection transistor M6 receives a selection control signal SEL, and the second terminal is coupled to the column line BIT.

[0074] In one implementation, the source follower transistor M5 is an NMOS transistor, and the selection transistor M6 is an NMOS transistor. At this time, the gate of the source follower transistor M5 is connected to the floating diffusion node FD, the drain is connected to the second power supply potential, the source is connected to the drain of the selection transistor M6, the gate of the selection transistor M6 receives the selection control signal SEL, and the source is connected to the column line BIT; the second power supply potential is usually the same as the first power supply potential, both of which are operating voltage potentials, such as always being at a high potential. Of course, in other implementations, it is also feasible that the source follower transistor M5 is a PMOS transistor and the selection transistor M6 is a PMOS transistor, which has no substantial impact on this embodiment.

[0075] Correspondingly, as Figures 6 to 8 shown, this embodiment also provides a control method for an image sensor, including a reset stage, an exposure stage, and a quantization stage; wherein, the image sensor is implemented by using the circuit structure described above.

[0076] Reset stage:

[0077] Perform a reset operation on the floating diffusion node FD, the photosensitive unit 120, and the overflow unit 130; further, perform a reset operation on the floating diffusion node FD, the photosensitive unit 120, and the overflow unit 130 through the reset unit 110.

[0078] For example, control the reset transistor M1 in the reset unit 110, the transfer transistor M2 in the photosensitive unit 120, and the quantization transistor M4 in the overflow unit 130 to turn on, and perform charge clearing on the floating diffusion node FD, the photosensitive element PD in the photosensitive unit 120, and the overflow capacitor C1 in the overflow unit 130 to achieve signal reset and complete the reset operation. After that, control the reset transistor M1, the transfer transistor M2, and the quantization transistor M4 to turn off. In an optional example, the exposure transistor M3 in the overflow unit 130 can be controlled to turn on simultaneously, which is beneficial to the charge clearing of the overflow capacitor C1 to achieve signal reset.

[0079] Of course, the reset transistor M1 may not be turned off at the end of the reset stage. For example, the reset transistor M1 is turned on during the reset stage and remains on until it is turned off during the quantization stage. Further, the reset transistor M1 is turned off after the selection transistor M6 in the readout unit 140 is turned on for the first time, as Figures 6 to 8 shown, to avoid crosstalk of other pixel blocks to the floating diffusion node FD of the current pixel block during the exposure stage. Of course, it is also feasible to turn off the reset transistor M1 while the selection transistor M6 is turned on.

[0080] Exposure stage:

[0081] Open the overflow path and close the quantization path, and store the second charge signal into the overflow unit 130 through the overflow path.

[0082] For example, control the exposure transistor M3 in the overflow unit 130 to turn on. At this time, the overflow path is opened, and the second charge signal overflowed from the photosensitive element PD in the photosensitive unit 120 is transferred through this overflow path to the overflow capacitor C1 in the overflow unit 130 for storage; since the quantization transistor M4 and the transfer transistor M2 in the overflow unit 130 are turned off during the reset stage, the quantization path is closed, and the overflowed second charge signal will not be transferred to the overflow unit 130 through the quantization path, nor will it pass through the floating diffusion node FD, and will not remain in the floating diffusion node FD. After that, control the exposure transistor M3 to turn off.

[0083] When the amount of charge sensed by the photosensitive element PD in the photosensitive unit 120 does not reach the overflow state, the converted charge signal only includes the first charge signal and is stored on the photosensitive element PD. At this time, although the overflow path is opened, no second charge signal is transferred to the overflow capacitor C1 through the overflow path, and it can be considered that the corresponding second charge signal is zero in this process.

[0084] When the amount of charge sensed by the photosensitive element PD in the photosensitive unit 120 reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal. Among them, the first charge signal is stored on the photosensitive element PD, and the second charge signal is transferred through the overflow path to the overflow capacitor C1 for storage.

[0085] Quantization stage:

[0086] In one implementation, as Figure 6 shown, close the overflow path to perform quantization readout of the first reset signal and the first charge signal based on the floating diffusion node FD to implement correlated double sampling of the first charge signal; and, perform a reset operation on the floating diffusion node FD to perform quantization readout of the second reset signal based on the floating diffusion node FD, then control the quantization path to open and then close, and transfer the second charge signal to the floating diffusion node FD through the quantization path for quantization readout to implement correlated double sampling of the second charge signal.

[0087] For the first reset signal and the first charge signal: since the exposure transistor M3 in the overflow unit 130 is turned off during the exposure stage, the overflow path is closed; first control the selection transistor M6 in the readout unit 150 to turn on to perform quantization readout of the first reset signal (i.e., RST) based on the floating diffusion node FD; then control the transfer transistor M2 in the photosensitive unit 120 to turn on and then off, and transfer the first charge signal (i.e., SIG) stored in the photosensitive element PD to the floating diffusion node FD and perform quantization readout. Further, corresponding to the process of the transfer transistor M2 turning on and then off, the selection transistor M6 performs an operation of turning off and then on.

[0088] For the second reset signal and the second charge signal: First, control the reset transistor M1 in the reset unit 110 to turn on and then off to perform a reset operation on the floating diffusion node FD, so as to perform quantization readout of the second reset signal (i.e., OF_RST1) based on the floating diffusion node FD; then, control the quantization transistor M4 in the overflow unit 130 to turn on and then off, and transfer the second charge signal stored in the overflow capacitor C1 in the overflow unit 140 to the floating diffusion node FD through the quantization path, so as to perform quantization readout of the second charge signal (i.e., OF_SIG1) based on the floating diffusion node FD.

[0089] In another implementation, as Figure 7 shown, close the overflow path to perform quantization readout of the first reset signal and the first charge signal based on the floating diffusion node FD, and implement correlated double sampling of the first charge signal; and, open the quantization path, transfer the second charge signal to the floating diffusion node FD through the quantization path for quantization readout, and then perform a reset operation on the floating diffusion node FD to perform quantization readout of the second reset signal based on the floating diffusion node FD, so as to implement non-genuine correlated double sampling of the second charge signal.

[0090] The quantization readout of the first reset signal and the first charge signal in this implementation is the same as that in the previous implementation, and will not be elaborated here.

[0091] For the second reset signal and the second charge signal: First, control the quantization transistor M4 in the overflow unit 130 to turn on. At this time, the quantization path is opened, and transfer the second charge signal stored in the overflow capacitor C1 in the overflow unit 140 to the floating diffusion node FD through the quantization path, so as to perform quantization readout of the second charge signal (i.e., OF_SIG2) based on the floating diffusion node FD; then, control the reset transistor M1 in the reset unit 110 to turn on and then off to perform a reset operation on the floating diffusion node FD, so as to perform quantization readout of the second reset signal (i.e., OF_RST2) based on the floating diffusion node FD.

[0092] Furthermore, before performing quantization readout of the second charge signal, also control the transfer transistor M2 in the photosensitive unit 120 to turn on and then off. Further, the selection transistor M6 in the readout unit 140 can also be controlled to turn off and then on simultaneously; in addition, before performing quantization readout of the second charge signal, also control the exposure transistor M3 in the overflow unit 130 to turn on and then off, where the turn-on and turn-off of the exposure transistor M3 can be performed simultaneously with the turn-on and turn-off of the transfer transistor M2.

[0093] For the above-mentioned another implementation manner, during the process of quantifying and reading out the second reset signal based on the reset operation, the process of turning on and then off the reset transistor M1 corresponds to the operation of turning off and then on the selection transistor M6 in the readout unit 140. Among them, the reset transistor M1 is turned off during the period when the selection transistor M6 is turned off.

[0094] Of course, in other implementation manners, the correlated double sampling of the first charge signal, the correlated double sampling of the second charge signal, and the non-genuine correlated double sampling of the second charge signal can also be performed successively, as Figure 8 shown. The relevant control can be found in the above text and will not be elaborated here. It should be noted that in one implementation manner, during the process of quantization using the Figure 8 method, the reset step before quantifying and reading out the second reset signal (i.e., OF_RST1) can be omitted. That is, the operation of turning on and then off the reset transistor M1 in the control reset unit 110 is not performed, but the second reset signal (i.e., OF_RST1) is directly read, so as to reduce the signal loss during the subsequent readout process of the overflow signal.

[0095] Embodiment 2

[0096] As Figure 9 shown, the difference between this embodiment and Embodiment 1 is that the pixel block 100 of this embodiment further includes a gain unit 150, which is coupled between the reset unit 110 and the floating diffusion node FD and is used for switching between different gain modes, such as switching between the low conversion gain (LCG) mode and the high conversion gain (HCG) mode.

[0097] Among them, when the pixel block 100 includes the gain unit 150, the quantization path of the overflow unit 130 is coupled to the floating diffusion node FD or the connection node between the reset unit 110 and the gain unit 150, that is, the low-gain connection node corresponding to the gain unit 150. In this embodiment, the quantization path of the overflow unit 130 is coupled to the low-gain connection node corresponding to the gain unit 150 to optimize the quantization gain of the overflow charge signal.

[0098] As an example, the gain unit 150 includes a gain transistor M7, the control terminal receives a gain control signal DCG, the first terminal is coupled to the reset unit 110, and the second terminal is coupled to the floating diffusion node FD. Among them, if the gain transistor M7 is turned on, the image sensor operates in the LCG mode; if the gain transistor M7 is turned off, the image sensor operates in the HCG mode. In this embodiment, the quantization path of the overflow unit 130 is connected between the first terminal of the gain transistor M7 and the reset unit 110.

[0099] In one implementation, the gain transistor M7 includes an NMOS transistor. At this time, the gate of the gain transistor M7 receives the gain control signal DCG, the drain is connected to the source of the reset transistor M1, and the source is connected to the floating diffusion node FD. Of course, in other implementations, it is also feasible that the gain transistor M7 includes a PMOS transistor, which has no substantial impact on this embodiment.

[0100] Correspondingly, as Figure 10 shown, this embodiment also provides a control method for an image sensor, including a reset stage, an exposure stage, and a quantization stage; wherein, the image sensor is implemented by using the circuit structure described above.

[0101] Reset stage:

[0102] Perform a reset operation on the floating diffusion node FD, the photosensitive unit 120, and the overflow unit 130; further, perform a reset operation on the floating diffusion node FD, the photosensitive unit 120, and the overflow unit 130 through the reset unit 110.

[0103] The control method of the reset stage in this embodiment is roughly the same as that in Embodiment 1. The difference is that this embodiment also controls the gain transistor M7 in the gain unit 150 to be turned on to facilitate the execution of the reset operation; wherein, the gain transistor M7 is turned on in the reset stage and turned off in the quantization stage.

[0104] Exposure stage:

[0105] Open the overflow path and close the quantization path, and store the second charge signal into the overflow unit 130 through the overflow path.

[0106] The control method of the exposure stage in this embodiment is the same as that in Embodiment 1. For details, please refer to Embodiment 1 and will not be elaborated here; wherein, in one implementation, the gain transistor M7 remains turned on in the exposure stage and continues until the subsequent corresponding quantization stage.

[0107] Quantization stage:

[0108] The quantization readout of the first reset signal and the first charge signal in this embodiment is different from that in Embodiment 1 in the quantization stage; in this embodiment, the overflow path is closed to perform quantization readout of the first reset signal and the first charge signal based on the floating diffusion node FD in different gain modes, so as to implement correlated double sampling of the first charge signal in different gain modes. Specifically: by controlling the gain unit 150 to be turned on and then off, the quantization readout of the first reset signal in different gain modes is performed based on the floating diffusion node FD, and then by controlling the gain unit 150 to be turned off and then on, the quantization readout of the first charge signal in different gain modes is performed based on the floating diffusion node FD.

[0109] Since the gain transistor M7 in the gain unit 150 is turned on and remains on during the reset phase, the image sensor operates in the LCG mode. Thus, the first reset signal (i.e., L_RST) in the LCG mode is quantized and read out based on the floating diffusion node FD; then, the gain transistor M7 is controlled to turn off, causing the image sensor to switch to the HCG mode. Thus, the first reset signal (i.e., H_RST) in the HCG mode is quantized and read out based on the floating diffusion node FD.

[0110] The transfer transistor M2 in the photosensitive unit 120 is also controlled to turn on and then off, transferring the first charge signal stored in the photosensitive element PD to the floating diffusion node FD, and the first charge signal (i.e., H_SIG) in the HCG mode is quantized and read out based on the floating diffusion node FD; then, the gain transistor M7 is controlled to turn on, causing the image sensor to switch back to the LCG mode again. Further, the transfer transistor M2 can be controlled to turn on and then off simultaneously, transferring the charge signal in the photosensitive element PD to the floating diffusion node FD. In the above state, the first charge signal (i.e., L_SIG) in the LCG mode is quantized and read out based on the floating diffusion node FD.

[0111] Further, corresponding to the process of turning on and then off the transfer transistor M2, the selection transistor M6 is operated to turn off and then on.

[0112] The quantization and readout of the second reset signal and the second charge signal in this embodiment are the same as those in Embodiment 1 during the quantization phase. For details, refer to Embodiment 1, which will not be elaborated here; among them, the gain transistor M7 remains on during the subsequent quantization and readout process. It should be noted that since the gain transistor M7 remains on, it can be considered that the second charge signal is correlated double sampled in the LCG mode. Therefore, Figure 10 OF_LCG_RST is used to represent OF_RST1, and OF_LCG_SIG is used to represent OF_SIG1. At the same time, OF_SIG is used to represent OF_SIG2, and OF_RST is used to represent OF_RST2.

[0113] Embodiment 3

[0114] As Figure 11 shown, the difference between this embodiment and Embodiment 1 and Embodiment 2 is that the pixel block 100 in this embodiment further includes a fast reset unit 160, which is coupled to both ends of the overflow capacitor C1 in the overflow unit 130 and is used to reset the overflow unit 130. Of course, the fast reset unit 160 can cooperate with the reset unit 110 to reset the overflow unit 130.

[0115] As an example, the fast reset unit 160 includes a fast recovery transistor M8, whose control terminal receives a third control signal OF_RST, the first terminal is coupled to the first terminal of the overflow capacitor C1, and the second terminal is coupled to the second terminal of the overflow capacitor C1; in an alternative solution, the second terminal of the overflow capacitor C1 is coupled to a variable potential Vc instead of the ground potential, that is, the second terminal of the fast recovery transistor M8 is coupled to the variable potential Vc. In other examples, according to the threshold condition of the fast recovery transistor M8, the control terminal and the second terminal of the fast recovery transistor M8 can be shorted to enable the fast recovery transistor M8 to be turned on and off in the corresponding stage; at this time, the control terminal of the fast recovery transistor M8 is no longer connected to the third control signal OF_RST, as Figure 12 shown.

[0116] In one implementation, the fast recovery transistor M8 includes an NMOS transistor. At this time, the gate of the fast recovery transistor M8 receives the third control signal OF_RST, the drain is connected to the first terminal of the overflow capacitor C1, and the source is connected to the second terminal of the overflow capacitor C1. Of course, in other implementations, it is also feasible that the fast recovery transistor M8 includes a PMOS transistor, which has no substantial impact on this embodiment.

[0117] Correspondingly, as Figure 13 shown, this embodiment also provides a control method for an image sensor, including a reset stage, an exposure stage, and a quantization stage; wherein, the image sensor is implemented by using the circuit structure described above. In one implementation, the fast reset unit 160 is turned on during the quantization readout of the second reset signal that is not a truly relevant double sampling. Of course, in other embodiments, the fast reset unit 160 can also be turned on during other processes, for example, during the global reset of the circuit or the reset read process of the signal in the overflow capacitor C1.

[0118] Reset stage:

[0119] The reset operations of the floating diffusion node FD, the photosensitive unit 120, and the overflow unit 130 in the reset stage of this embodiment are different from those of the above two embodiments; in this embodiment, the floating diffusion node FD and the photosensitive unit 120 are reset by the reset unit 110, and the overflow unit 130 is reset by the fast reset unit 160.

[0120] It can also be that, in this embodiment, the floating diffusion node FD, the photosensitive unit 120, and the overflow unit 130 are reset by the reset unit 110, and the fast reset unit 160 cooperates with the reset unit 110 to perform a fast reset operation on the overflow unit 130.

[0121] For the case where the pixel block 100 does not include the gain unit 150: Control the reset transistor M1 in the reset unit 110 and the transfer transistor M2 in the photosensitive unit 120 to turn on, and clear the charges of the floating diffusion node FD and the photosensitive element PD in the photosensitive unit 120 to achieve signal reset; at the same time, control the fast reset transistor M8 in the fast reset unit 160 to turn on and control the variable potential to jump to a high potential, such as the power supply potential VDD, to clear the charges of the overflow capacitor C1 in the overflow unit 130 to achieve signal reset; in this way, the reset operation is completed. After that, control the reset transistor M1, the transfer transistor M2, and the fast reset transistor M8 to turn off, and control the variable potential to jump to a low potential, such as the ground potential.

[0122] Among them, during the reset process, at least one of the exposure transistor M3 and the quantization transistor M4 in the overflow unit 130 remains on, which is beneficial to achieving the fast reset of the overflow capacitor C1, that is, based on the reset unit 110 and the fast reset unit 160, the fast reset operation of the overflow capacitor C1 in the overflow unit 130 is realized.

[0123] For the case where the pixel block 100 includes the gain unit 150: When the reset unit 110 performs the reset operation on the floating diffusion node FD and the photosensitive unit 120, the control method is substantially the same as the case where the gain unit 150 is not included, except that the gain transistor M7 in the gain unit 150 is also controlled to turn on, where the gain transistor M7 turns on during the reset stage and turns off during the quantization stage.

[0124] The exposure stage and the quantization stage are the same as those in the above two embodiments. For details, please refer to the relevant embodiments and will not be elaborated here. Among them, in one implementation, during the exposure stage and the quantization stage, the fast reset transistor M8 remains off and the variable potential remains at a low potential, such as the ground potential.

[0125] Embodiment 4

[0126] As Figure 14 shown, this embodiment provides an arrangement structure of an image sensor, including the following arrangement method; among them, the pixel block 100 in the image sensor includes a reset unit 110, a photosensitive unit 120, an overflow unit 130, and a readout unit 140.

[0127] The reset unit 110 includes a reset transistor M1, the photosensitive unit 120 includes at least one photosensitive element PD and at least one transfer transistor M2, the overflow unit 130 includes an exposure transistor M3, a quantization transistor M4, and an overflow capacitor C1, and the readout unit 140 includes a source follower transistor M5 and a selection transistor M6.

[0128] Among them, the transfer transistor M2 is disposed in the first corner region of the photosensitive element PD, the source follower transistor M5 is disposed in the accommodation region away from the photosensitive element PD of the transfer transistor M2, the floating diffusion node FD is disposed in the accommodation region and on one side of the source follower transistor M5, the exposure transistor M3 is disposed in the second corner region of the photosensitive element PD, the quantization transistor M4 is disposed outside the accommodation region, and the reset transistor M1 and the selection transistor M6 are disposed outside the accommodation region.

[0129] In one implementation, the quantization transistor M4 is disposed outside the accommodation region and on the side of the floating diffusion node FD away from the source follower transistor M5, and the connection region of the overflow capacitor C1 is disposed on the side of the quantization transistor M4 away from the floating diffusion node FD. In one implementation, the reset transistor M1 and the selection transistor M6 are disposed outside the accommodation region and respectively above and below the source follower transistor M5. In one implementation, the first corner region and the second corner region are arranged facing each other in the horizontal direction. Further, the transfer transistor M2 is disposed obliquely in the first corner region at a first angle, and the exposure transistor M3 is disposed obliquely in the second corner region at a second angle, wherein the first angle is equal to the second angle.

[0130] Further, the pixel block 100 further includes a gain unit 150; and the gain unit 150 includes a gain transistor M7. At this time, the gain transistor M7 is disposed outside the accommodation region and between the quantization transistor M4 and the floating diffusion node FD.

[0131] Further, the pixel block 100 further includes a fast reset unit 160; and the fast reset unit 160 includes a fast reset transistor M8. In one implementation, the fast reset transistor M8 is disposed on the side of the connection region of the overflow capacitor C1 away from the quantization transistor M4 (not shown in the figure).

[0132] In summary, an image sensor, an arrangement structure and a control method of the present invention provide an additional overflow path for overflow charges. By separating the overflow path and the quantization path, the overflow charges in the exposure stage directly pass through the overflow path for storage without passing through the floating diffusion node, avoiding the charge influence of the overflow charges on the floating diffusion node, and thus avoiding the influence on the subsequent quantization readout, which is beneficial to improving the image quality. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0133] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that, It includes a plurality of pixel blocks arranged in an array. The pixel blocks include a reset unit, a photosensitive unit, an overflow unit, and a readout unit; The reset unit is coupled to a floating diffusion node and is configured to reset at least one of the floating diffusion node, the photosensitive unit, and the overflow unit; The photosensitive unit is coupled to the floating diffusion node, generates a first charge signal and a second charge signal based on photoelectric conversion, stores the first charge signal, and transfers the first charge signal to the floating diffusion node; The overflow unit includes an overflow path and a quantization path. The overflow path is coupled to the photosensitive unit, and the quantization path is coupled to the floating diffusion node. The second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node based on the quantization path; The readout unit is coupled to the floating diffusion node and quantizes and reads at least the first charge signal and the second charge signal.

2. The image sensor according to claim 1, wherein The overflow unit includes an exposure transistor, a quantization transistor, and an overflow capacitor. The control terminal of the exposure transistor receives a first control signal, the first terminal is coupled to the photosensitive unit, and the second terminal is coupled to the first terminal of the overflow capacitor. The control terminal of the quantization transistor receives a second control signal, the first terminal is coupled to the floating diffusion node, and the second terminal is coupled to the first terminal of the overflow capacitor. The second terminal of the overflow capacitor is coupled to a ground potential or a variable potential. Among them, the exposure transistor forms the overflow path, and the quantization transistor forms the quantization path.

3. The image sensor according to claim 2, wherein The pixel block further includes a fast reset unit coupled to both ends of the overflow capacitor for quickly resetting the overflow unit.

4. The image sensor according to claim 3, characterized in that, The fast reset unit includes a fast reset transistor. The control terminal receives a third control signal or is coupled to its second terminal. The first terminal is coupled to the first terminal of the overflow capacitor, and the second terminal is coupled to the second terminal of the overflow capacitor; and / or, the second terminal of the overflow capacitor is coupled to a variable potential.

5. The image sensor according to claim 1, wherein The photosensitive unit includes M photosensitive elements and M transfer transistors, which are in one-to-one correspondence. M is an integer greater than or equal to 1. The control terminal of the transfer transistor receives a transfer control signal, the first terminal is coupled to the floating diffusion node, the second terminal is coupled to the first terminal of the photosensitive element, and the second terminal of the photosensitive element is coupled to a reference potential. Among them, the overflow path is coupled to the first terminals of S photosensitive elements, where S is an integer greater than or equal to 1 and S is less than M; Alternatively, the photosensitive unit includes (N + T) photosensitive elements and N transfer transistors. The (N + T) photosensitive elements include N first photosensitive elements and T second photosensitive elements. The N first photosensitive elements and the N transfer transistors are in one-to-one correspondence. N is an integer greater than or equal to 1, and T is an integer greater than or equal to 1. The control terminal of the transfer transistor receives a transfer control signal, the first terminal is coupled to the floating diffusion node, the second terminal is coupled to the first terminal of the first photosensitive element, and the second terminal of the first photosensitive element is coupled to a reference potential. The first terminal of the second photosensitive element is coupled to the overflow path, and the second terminal is coupled to a reference potential.

6. The image sensor according to claim 1, wherein The reset unit includes a reset transistor, whose control terminal receives a reset control signal, first terminal is coupled to a first power supply potential, and second terminal is coupled to the floating diffusion node; And / or, the readout unit includes a source follower transistor and a selection transistor; the control terminal of the source follower transistor is coupled to the floating diffusion node, first terminal is coupled to a second power supply potential, and second terminal is coupled to the first terminal of the selection transistor; the control terminal of the selection transistor receives a selection control signal, and second terminal is coupled to a column line.

7. The image sensor according to any one of claims 1-6, characterized in that, The pixel block further includes a gain unit, coupled between the reset unit and the floating diffusion node, for switching different gain modes.

8. The image sensor according to claim 7, wherein, The gain unit includes a gain transistor, whose control terminal receives a gain control signal, first terminal is coupled to the reset unit, and second terminal is coupled to the floating diffusion node; And / or, the quantization path is coupled to the floating diffusion node or a low-gain connection node corresponding to the gain unit.

9. A control method for an image sensor according to any one of claims 1-8, characterized in that, Comprising: Reset stage: performing a reset operation on the floating diffusion node, the photosensitive unit and the overflow unit; Exposure stage: turning on the overflow path and turning off the quantization path, and storing the second charge signal into the overflow unit through the overflow path; Quantization stage: turning off the overflow path to perform quantization readout of the first reset signal and the first charge signal based on the floating diffusion node; Performing quantization readout of the second reset signal based on the floating diffusion node, then controlling the quantization path to turn on and then off, and transferring the second charge signal to the floating diffusion node through the quantization path for quantization readout; and / or, turning on the quantization path, transferring the second charge signal to the floating diffusion node through the quantization path for quantization readout, and then performing a reset operation on the floating diffusion node to perform quantization readout of the second reset signal based on the floating diffusion node.

10. The control method of the image sensor according to claim 9, characterized in that, When the pixel block includes a gain unit, the method for performing quantization readout of the first reset signal and the first charge signal based on the floating diffusion node includes: controlling the gain unit to turn on and then off to perform quantization readout of the first reset signal in different gain modes based on the floating diffusion node, and then controlling the gain unit to turn off and then on to perform quantization readout of the first charge signal in different gain modes based on the floating diffusion node; and / or, performing quantization readout of the second reset signal based on the floating diffusion node, and before controlling the quantization path to turn on and then off and transferring the second charge signal to the floating diffusion node through the quantization path for quantization readout, further including: a step of performing a reset operation on the floating diffusion node.

11. The control method of the image sensor according to claim 9, characterized in that, When the pixel block does not include a fast reset unit, in the reset stage, the reset unit performs a reset operation on the floating diffusion node, the photosensitive unit and the overflow unit; when the pixel block includes a fast reset unit, in the reset stage, the fast reset unit or the fast reset unit cooperates with the reset unit to perform a reset operation on the overflow unit.

12. The control method of the image sensor according to any one of claims 9-11, characterized in that, The reset transistor of the reset unit is turned on during the reset phase and turned off during the quantization phase, wherein the reset transistor is turned off after or simultaneously with the first turn-on of the selection transistor of the readout unit; and / or, when the control method includes reading the second charge signal first and then reading the second reset signal, during the process of quantizing and reading the second reset signal based on the reset operation, the process of turning on and then turning off the reset transistor corresponds to the operation of turning off and then turning on the selection transistor, wherein the reset transistor is turned off during the off period of the selection transistor; and / or, before reading the second charge signal, it further includes the step of turning on the overflow path to transfer the charge in the photosensitive unit.

13. An arrangement structure of an image sensor according to any one of claims 1-8, characterized in that, Comprising: The reset unit includes a reset transistor, the photosensitive unit includes at least one photosensitive element and at least one transfer transistor, the overflow unit includes an exposure transistor, a quantization transistor and an overflow capacitor, and the readout unit includes a source follower transistor and a selection transistor; The transfer transistor is disposed in the first corner area of the photosensitive element, the source follower transistor is disposed in the accommodation area away from the photosensitive element of the transfer transistor, the floating diffusion node is disposed in the accommodation area and on one side of the source follower transistor, the exposure transistor is disposed in the second corner area of the photosensitive element, the quantization transistor is disposed outside the accommodation area, and the reset transistor and the selection transistor are disposed outside the accommodation area.

14. The arrangement structure of the image sensor according to claim 13, wherein When the pixel block includes a gain unit and the gain unit includes a gain transistor, the gain transistor is disposed outside the accommodation area and between the quantization transistor and the floating diffusion node; and / or, when the pixel block includes a fast reset unit and the fast reset unit includes a fast reset transistor, the fast reset transistor is disposed on the side of the connection area of the overflow capacitor away from the quantization transistor; and / or, the first corner area and the second corner area are arranged facing each other in the horizontal direction; and / or, the quantization transistor is disposed on the side of the floating diffusion node away from the source follower transistor; and / or, the connection area of the overflow capacitor is disposed on the side of the quantization transistor away from the floating diffusion node; and / or, the reset transistor and the selection transistor are respectively disposed above and below the source follower transistor.

15. The arrangement structure of the image sensor according to claim 14, characterized in that, The transfer transistor is arranged obliquely at a first angle in the first corner area, and the exposure transistor is arranged obliquely at a second angle in the second corner area, wherein the first angle is equal to the second angle.

Images