Back contact solar cell and preparation method thereof

Abstract

The invention relates to the technical field of photovoltaic solar cells, discloses a back contact solar cell and a preparation method thereof, and aims to realize thorough isolation and insulation of a P region and an N region in a back contact solar cell structure and improve the reliability of the back contact solar cell. The back contact solar cell comprises a semiconductor substrate which comprises a first surface and a second surface, the second surface is a backlight surface, and the second surface comprises a first area, a second area and a third area; wherein the first region comprises a tunneling oxide layer, a doped poly silicon layer and an insulating medium layer which are sequentially stacked on the semiconductor substrate; the second region comprises an intrinsic passivation layer, a doped silicon thin film layer and a transparent conductive film layer which are sequentially stacked on the semiconductor substrate; the third region is located between the first region and the second region and used for isolating the first region from the second region in space, and the third region comprises an insulating dielectric layer extending from the first region to the third region.

Description

Technical Field

[0001] This application relates to the technical field of photovoltaic solar cells, for example, relates to a back contact solar cell and a preparation method thereof. Background Art

[0002] At present, back contact (BC) cells have received increasing attention due to their high conversion efficiency and the effect of completely no grid line occlusion on the front side. The BC cell based on passivated contact is most likely a technology close to the theoretical efficiency limit of single-crystalline silicon cells. Therefore, the BC cell based on passivated contact has developed rapidly at present. There are mainly tunnel oxide passivated back contact (TBC) cells based on a tunneling oxide + poly-silicon passivated contact structure, heterojunction back contact (HBC) cells based on an intrinsic amorphous silicon + doped amorphous / microcrystalline passivated contact structure, and hetero junction tunnel oxide back contact (HTBC) cells based on a mixed structure of a tunneling oxide + poly-silicon passivated contact and an intrinsic amorphous silicon + doped amorphous / microcrystalline passivated contact.

[0003] Among them, the HTBC cell combines the structural characteristics of a tunnel oxide passivated contact cell (TOPCon) and a heterojunction (HJT) cell, has very high efficiency potential, relatively simple processes, and a relatively wide process window, and is very suitable for industrialization. The P region and the N region of the HTBC cell are both on the back side, and the isolation and insulation between the P region and the N region are very crucial.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related technologies:

[0005] In the related technologies, generally, a method of forming trenches by laser or etching a transparent conductive oxide (TCO) film is used for insulation between the P region and the N region. However, since the insulation trenches are very narrow, if the insulation is not complete or there are foreign objects on the trenches, it is easy to cause conduction between the P region and the N region, resulting in short-circuit failure of the battery.

[0006] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary is not a general review, nor is it intended to identify key / important constituent elements or delineate the scope of protection of these embodiments, but rather serves as a preface to the subsequent detailed description.

[0008] Embodiments of the present disclosure provide a back-contact solar cell and a method for manufacturing the same, so as to achieve complete isolation and insulation between the P region and the N region in the back-contact solar cell structure (the P region is the first region and the N region is the second region; or the P region is the second region and the N region is the first region), and improve the reliability of the back-contact solar cell.

[0009] In some embodiments, the back-contact solar cell includes: a semiconductor substrate, the semiconductor substrate includes a first surface and a second surface, wherein the first surface is the light-receiving surface and the second surface is the backlight surface, and the second surface includes a first region, a second region, and a third region; wherein, the first region includes a tunneling oxide layer, a doped poly-silicon layer, and an insulating dielectric layer stacked in sequence on the semiconductor substrate; the second region includes an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer stacked in sequence on the semiconductor substrate; the third region is located between the first region and the second region, and is used to spatially isolate the first region and the second region, and the third region includes an insulating dielectric layer extending from the first region to the third region.

[0010] Optionally, the third region is a groove structure to form a height difference between the first region and the second region.

[0011] Optionally, the third region includes a partial surface of the semiconductor substrate and sidewalls formed by the height difference, and the insulating dielectric layer covers the partial surface of the semiconductor substrate and the sidewalls formed by the height difference.

[0012] Optionally, the tunneling oxide layer is a silicon oxide layer with a thickness of 1 - 2.5 nm.

[0013] Optionally, the doped poly-silicon layer is a doped polysilicon layer. Wherein, when the doping type is N-type, the thickness of the doped poly-silicon layer is 100 - 250 nm and the sheet resistance is 30 - 50 Ω / Sq; when the doping type is P-type, the thickness of the doped poly-silicon layer is 250 - 400 nm and the sheet resistance is 120 - 150 Ω / Sq.

[0014] Optionally, the insulating dielectric layer is one or a combination of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide, with a thickness of 70 - 110 nm.

[0015] Optionally, the intrinsic passivation layer is an intrinsic amorphous silicon thin film layer with a thickness of 5 - 15 nm.

[0016] Optionally, the doped silicon thin film layer includes one of an amorphous silicon thin film layer, a microcrystalline silicon thin film layer, and a nanocrystalline silicon thin film layer, with a doping type opposite to that of the doped poly-silicon layer and a thickness of 10 - 30 nm.

[0017] Optionally, the transparent conductive film layer includes one of indium tin oxide (ITO), indium tungsten oxide (IWO), and aluminum zinc oxide target (AZO), with a thickness of 50 - 110 nm.

[0018] Optionally, the surface of the first region is a polished surface, the surface of the second region is a pyramid-textured surface, and the surface of the third region is a pyramid-textured surface.

[0019] Optionally, a surface passivation layer and an antireflection layer are sequentially stacked on the first surface.

[0020] Optionally, the surface passivation layer is alumina or silica, with a thickness of 3 - 8 nm.

[0021] Optionally, the antireflection layer is one of silicon nitride, silicon oxynitride, and silica, with a thickness of 70 - 110 nm.

[0022] Optionally, the first surface is a pyramid-textured surface, where the size of the pyramid-textured surface is 1 - 3 μm.

[0023] Optionally, the back-contact solar cell further includes: a first metal electrode located in the first region and in contact with the doped poly-silicon layer through an insulating dielectric layer; and a second metal electrode located in the second region and in contact with the transparent conductive film layer.

[0024] In some embodiments, a method for fabricating a back-contact solar cell includes:

[0025] Providing a semiconductor substrate, which has opposite first and second surfaces after chemical polishing;

[0026] Forming a tunneling oxide layer, a doped poly-silicon layer, and a texturing protection layer on the second surface in sequence;

[0027] Alternately opening holes in a partial region of the second surface, removing the tunneling oxide layer, the doped poly-silicon layer, and the texturing protection layer, then performing texturing cleaning to form a textured surface structure on the first surface and the opening regions of the second surface, and the unopened region of the second surface is the first region;

[0028] Forming an insulating dielectric layer on the second surface;

[0029] Removing and cleaning a local insulating dielectric layer within the opening regions of the second surface, and the removed region is the second region, where the position between the first region and the second region is set as the third region, and the insulating dielectric layer in the third region is not removed;

[0030] An intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer are sequentially formed in a second region of the second surface.

[0031] Optionally, before forming the insulating dielectric layer on the second surface, it further includes:

[0032] A surface passivation layer and an antireflection layer are sequentially formed on the first surface, wherein the insulating dielectric layer and the antireflection layer are made of the same material.

[0033] Optionally, sequentially forming an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer in a second region of the second surface includes:

[0034] Depositing an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer on the second surface;

[0035] Removing the intrinsic passivation layer, the doped silicon thin film layer, and the transparent conductive film layer covering the surfaces of the first region and the third region on the second surface.

[0036] Optionally, after sequentially forming an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer in a second region of the second surface, it further includes:

[0037] Performing an opening on the insulating dielectric layer on the first region of the second surface;

[0038] Forming metal electrodes at the opening position of the insulating dielectric layer on the first region of the second surface and on the transparent conductive film layer on the second region of the second surface.

[0039] The back-contact solar cell and its manufacturing method provided by the embodiments of the present disclosure can achieve the following technical effects:

[0040] By sequentially stacking a tunneling oxide layer, a doped poly-silicon layer, and an insulating dielectric layer on the semiconductor substrate in the first region, and sequentially stacking an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer on the semiconductor substrate in the second region, and there are no identical and continuous conductive film layers in the first region and the second region of the back-contact solar cell, thereby achieving complete isolation and insulation between the first region and the second region. At the same time, a third region covering the insulating dielectric layer is provided between the first region and the second region. In this way, on the basis that there are no identical and continuous conductive film layers in the first region and the second region, spatial isolation between the first region and the second region is also achieved, further reducing the risk of conduction failure between the first region and the second region and improving the reliability of the back-contact solar cell.

[0041] The above general description and the following description are only exemplary and explanatory, and are not used to limit this application. Description of the Drawings

[0042] One or more embodiments are exemplarily illustrated by corresponding drawings. These exemplary illustrations and the drawings do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation, and wherein:

[0043] Figure 1 is a schematic structural diagram of a back-contact solar cell provided by an embodiment of the present disclosure;

[0044] Figure 2 is a flowchart of a method for manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0045] Figure 3 is a flowchart of another method for manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0046] Figure 4 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0047] Figure 5 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0048] Figure 6 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0049] Figure 7 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0050] Figure 8 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0051] Figure 9 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0052] Figure 10 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0053] Figure 11 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0054] Figure 12 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell provided by an embodiment of the present disclosure;

[0055] Figure 13It is a schematic structural diagram of an intermediate in the preparation process of a back-contact solar cell provided by an embodiment of the present disclosure;

[0056] Figure 14 It is a schematic structural diagram of an intermediate in the preparation process of a back-contact solar cell provided by an embodiment of the present disclosure.

[0057] Reference numerals:

[0058] 1 - semiconductor substrate; 1-1 - first surface; 1-2 - second surface; 2 - tunneling oxide layer; 3 - doped poly-silicon layer; 4 - texturing protection layer; 5 - surface passivation layer; 6 - antireflection layer; 7 - insulating dielectric layer; 8 - intrinsic passivation layer; 9 - doped silicon thin film layer; 10 - transparent conductive film layer; 11 - opening position; 12 - first metal electrode; 13 - second metal electrode. Detailed implementation manners

[0059] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The attached drawings are for reference and illustration only and are not intended to limit the embodiments of the present disclosure. In the following technical description, for the sake of explanation, multiple details are provided to fully understand the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be shown in a simplified manner to simplify the drawings.

[0060] In the embodiments of the present disclosure, the terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present disclosure described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0061] In the embodiments of the present disclosure, the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", etc. is based on the orientation or positional relationship shown in the accompanying drawings. These terms are mainly used to better describe the embodiments of the present disclosure and their embodiments and are not used to limit that the indicated devices, elements or components must have a specific orientation or be constructed and operated in a specific orientation. And, in addition to being able to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0062] In addition, the terms "arranged", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0063] Unless otherwise specified, the term "plurality" means two or more.

[0064] In the embodiments of the present disclosure, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0065] The term "and / or" is an associative relationship describing objects, indicating that there can be three relationships. For example, A and / or B means: A or B, or, A and B.

[0066] It should be noted that, without conflict, the embodiments in the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0067] Combined Figure 1 As shown, the embodiments of the present disclosure provide a back-contact solar cell, including a semiconductor substrate 1. The semiconductor substrate 1 includes a first surface and a second surface. Among them, the first surface is the light-receiving surface, and the second surface is the backlight surface. The second surface includes a first region, a second region, and a third region. Among them, the first region includes a tunneling oxide layer 2, a doped polysilicon layer 3, and an insulating dielectric layer 7 stacked in sequence on the semiconductor substrate 1. The second region includes an intrinsic passivation layer 8, a doped silicon thin film layer 9, and a transparent conductive film layer 10 stacked in sequence on the semiconductor substrate 1. The third region is located between the first region and the second region, and is used to spatially isolate the first region and the second region. And the third region includes the insulating dielectric layer 7 extending from the first region to the third region.

[0068] Using the back-contact solar cell provided by the embodiments of the present disclosure, by sequentially stacking a doped poly-silicon layer 3 and an insulating dielectric layer 7 on the semiconductor substrate 1 in the first region, and sequentially stacking a doped silicon thin film layer 9 and a transparent conductive film layer 10 on the semiconductor substrate 1 in the second region, and there are no identical and continuous conductive film layers in the first region and the second region of the back-contact solar cell, thereby achieving complete isolation and insulation between the first region and the second region. At the same time, a third region covering the insulating dielectric layer 7 is provided between the first region and the second region. In this way, on the basis that there are no identical and continuous conductive film layers in the first region and the second region, spatial isolation between the first region and the second region is also achieved, further reducing the risk of conduction failure between the first region and the second region and improving the reliability of the back-contact solar cell.

[0069] Optionally, the semiconductor substrate 1 of the present application is a silicon substrate, and the doping type is N-type or P-type. Specifically, the widths of the first region and the third region on the second surface 1-2 are related to the semiconductor substrate 1. If it is an N-type semiconductor substrate 1, the P-type doped region is larger than the N-type doped region. If it is a P-type semiconductor substrate 1, the P-type doped region is smaller than the N-type doped region. Preferably, an N-type semiconductor substrate 1 is used, the first region is N-type doped with a width of 400-500 um, the second region is P-type doped with a width of 550-700 um; the width of the third region is 100-200 um.

[0070] Optionally, the doping types of the first region and the second region on the second surface 1-2 are opposite, that is: when the doping type of the first region is N-type, the doping type of the second region is P-type; when the doping type of the first region is P-type, the doping type of the second region is N-type.

[0071] Optionally, the third region of the present application may be a groove structure to form a height difference between the first region and the second region, and the height difference may be 1-8 um, preferably 2-5 um. Specifically, the third region of the present application includes a partial surface of the semiconductor substrate 1 and the side walls formed by the height difference, and the insulating dielectric layer 7 covers the partial surface of the semiconductor substrate 1 and the side walls formed by the height difference. In this way, the insulation effect can be further increased.

[0072] Optionally, in combination with Figure 1 and Figure 4 as shown, the semiconductor substrate 1 of the present application includes a first surface 1-1 and a second surface 1-2, wherein the first surface 1-1 is the light-receiving surface, the second surface 1-2 is the backlight surface, and the first region, the second region, and the third region are located on the second surface 1-2.

[0073] Thus, in order to further enhance the insulation effect, the present application sets a third region between the first region and the second region. The third region includes a partial surface and sidewalls of the semiconductor substrate 1, and an insulating dielectric layer 7 is covered thereon, thereby completely eliminating the risk of conduction failure between the first region and the second region.

[0074] Optionally, in combination with Figure 1 As shown, the back-contact solar cell of the present application further includes a first metal electrode 12 and a second metal electrode 13. Among them, the first metal electrode 12 is located in the first region and contacts the doped poly-silicon layer 3 through the insulating dielectric layer 7. The second metal electrode 13 is located in the second region and contacts the contact transparent conductive film layer 10. Preferably, the first metal electrode 12 can be a silver electrode or a silver-coated copper electrode, and the second metal electrode 13 can be a silver electrode or a silver-coated copper electrode.

[0075] In a specific embodiment of the present application, in combination with Figure 1 As shown, a surface passivation layer 5 and an antireflection layer 6 are sequentially stacked on the first surface 1-1 of the semiconductor substrate 1 of the present application. Among them, the first surface 1-1 is a pyramid texture surface, and the size of the pyramid texture surface is 1-3 μm. The surface passivation layer 5 is alumina or silica, and the thickness is 3-8 nm. The antireflection layer 6 is one of silicon nitride, silicon oxynitride, and silica, and the thickness is 70-110 nm.

[0076] In another specific embodiment of the present application, in combination with Figure 1 As shown, the surface of the first region of the second surface 1-2 of the present application is a polished surface. Among them, the tunneling oxide layer 2 can be a silicon oxide layer, and the thickness of the silicon oxide layer is 1-2.5 nm, preferably 1.5-2.0 nm. The doped poly-silicon layer 3 can be a doped polycrystalline silicon layer. Among them, in the case of N-type doping, the thickness of the doped poly-silicon layer 3 is 100-250 nm, and the sheet resistance is 30-50 Ω / Sq. In the case of P-type doping, the thickness of the doped poly-silicon layer 3 is 250-400 nm, and the sheet resistance is 120-150 Ω / Sq. The insulating dielectric layer 7 is one or a combination of silicon nitride, silica, silicon oxynitride, and alumina, and the thickness is 70-110 nm.

[0077] It should be noted that in the prior art, an intrinsic amorphous silicon layer is used as the insulating dielectric layer 7 between the doped poly-silicon and the doped amorphous silicon / microcrystalline silicon. However, due to the very thin intrinsic amorphous silicon layer, the carrier tunneling phenomenon is likely to occur, thus easily leading to leakage.

[0078] In this regard, the insulating dielectric layer 7 of the present application is one or a combination of silicon nitride, silica, silicon oxynitride, and alumina, and the thickness is 70-110 nm. In this way, the occurrence of the carrier tunneling phenomenon can be reduced, and thus the leakage can be reduced.

[0079] In another specific embodiment of the present application, in combination with Figure 1 As shown, the second region surface of the second surface 1-2 of the present application is a pyramid suede surface. Among them, the intrinsic passivation layer 8 can be an intrinsic amorphous silicon thin film layer with a thickness of 5-15 nm. The doped silicon thin film layer 9 includes one of an amorphous silicon thin film layer, a microcrystalline silicon thin film layer, and a nanocrystalline silicon thin film layer, and the doping type is opposite to that of the poly-silicon layer (that is, when the doping type of the poly-silicon layer is N-type, the doped silicon thin film layer 9 is P-type; when the doping type of the poly-silicon layer is P-type, the doped silicon thin film layer 9 is N-type), and the thickness is 10-30 nm. The transparent conductive film layer 10 includes one of indium tin oxide ITO, indium tin oxide IWO, and aluminum zinc oxide target AZO, and the thickness is 50-110 nm.

[0080] In another specific embodiment of the present application, in combination with Figure 1 As shown, the third region surface of the second surface 1-2 of the present application is a pyramid suede surface, and the insulating dielectric layer 7 covering the surface is one or a combination of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide, and the thickness is 70-110 nm.

[0081] For the back-contact solar cell provided by the present application, by alternately arranging the doped poly-silicon layer 3 and the doped thin film silicon layer on the second surface 1-2 of the semiconductor substrate 1, and providing the insulating dielectric layer 7 on the doped poly-silicon layer 3 and the transparent conductive layer on the doped thin film silicon layer, the P region and the N region are completely insulated and isolated. In addition, in order to further increase the insulation effect, a third region is provided between the P region and the N region and a certain height difference is formed, and the third region surface and the side wall formed by the height difference are all covered with the insulating dielectric layer 7. <{

[0082] In combination with Figure 2 As shown, the present disclosure embodiment provides a preparation method of the back-contact solar cell as described above, including:

[0083] Step 201: Provide a semiconductor substrate, and the semiconductor substrate has opposite first and second surfaces after chemical polishing.

[0084] Step 202: Sequentially form a tunneling oxide layer, a doped poly-silicon layer, and a texturing protection layer on the second surface.

[0085] Step 203: Alternately open holes in some regions of the second surface, remove the tunneling oxide layer, the doped poly-silicon layer, and the texturing protection layer, and then perform texturing cleaning to form a suede surface structure on the first surface and the open-hole regions of the second surface. The unopened region of the second surface is the first region.

[0086] Step 204: Form an insulating dielectric layer on the second surface.

[0087] Step 205: In the opening area of the second surface, locally remove and clean the insulating dielectric layer. The removed area is the second area. Herein, the position between the first area and the second area is set as the third area, and the insulating dielectric layer in the third area is not removed.

[0088] Step 206: Sequentially form an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer in the second area of the second surface.

[0089] By using the method for manufacturing a back-contact solar cell provided by the embodiment of the present disclosure, by sequentially stacking a doped poly-silicon layer and an insulating dielectric layer on the semiconductor substrate in the first area, and sequentially stacking a doped silicon thin film layer and a transparent conductive film layer on the semiconductor substrate in the second area, and the back-contact solar cell is such that there is no identical and continuous conductive film layer in the first area and the second area, thereby achieving complete isolation and insulation between the first area and the second area. Meanwhile, a third area covering the insulating dielectric layer is provided between the first area and the second area. In this way, on the basis that there is no identical and continuous conductive film layer in the first area and the second area, spatial isolation between the first area and the second area is also achieved, further reducing the risk of conduction failure between the first area and the second area and improving the reliability of the back-contact solar cell.

[0090] Combined with Figure 3 As shown in

[0091] Step 301: Provide a semiconductor substrate, and the semiconductor substrate has opposite first and second surfaces after chemical polishing.

[0092] Step 302: Sequentially form a tunneling oxide layer, a doped poly-silicon layer, and a texturing protection layer on the second surface.

[0093] Step 303: Alternately open holes in a partial area of the second surface, remove the tunneling oxide layer, the doped poly-silicon layer, and the texturing protection layer, and then perform texturing cleaning to form a textured surface structure on the first surface and the opening area of the second surface. The unopened area of the second surface is the first area.

[0094] Step 304: Sequentially form a surface passivation layer and an antireflection layer on the first surface.

[0095] Step 305: Form an insulating dielectric layer on the second surface, wherein the insulating dielectric layer and the antireflection layer are made of the same material.

[0096] Step 306: In the opening area of the second surface, locally remove and clean the insulating dielectric layer. The removed area is the second area. Herein, the position between the first area and the second area is set as the third area, and the insulating dielectric layer in the third area is not removed.

[0097] Step 307: Sequentially form an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer in the second area of the second surface.

[0098] Step 308: Open a hole in the insulating dielectric layer on the first area of the second surface.

[0099] Step 309: Form a metal electrode at the opening position of the insulating dielectric layer on the first area of the second surface and on the transparent conductive film layer on the second area of the second surface.

[0100] By using the preparation method of the back-contact solar cell provided by the embodiment of the present disclosure, the insulating dielectric layer and the antireflection layer are made of the same material (such as silicon nitride), and the antireflection layer on the first surface is fabricated first and then the insulating dielectric layer on the second surface is fabricated. In this way, the overplating generated when fabricating the antireflection layer on the first surface will not affect the fabrication of the insulating dielectric layer.

[0101] Optionally, a metal electrode is formed on the transparent conductive film layer or in the opening area of the insulating dielectric layer, and the fabrication method of the metal electrode can be screen printing or laser transfer printing.

[0102] Optionally, sequentially forming an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer in the second area of the second surface includes:

[0103] Deposit an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer on the second surface;

[0104] Remove the intrinsic passivation layer, the doped silicon thin film layer, and the transparent conductive film layer covering the surfaces of the first area and the third area on the second surface.

[0105] In this application, the intrinsic passivation layer, the doped silicon thin film layer, and the transparent conductive film layer are first deposited on the second surface as a whole, and then the intrinsic passivation layer, the doped silicon thin film layer, and the transparent conductive film layer covering the surfaces of the first area and the third area are removed.

[0106] In a specific embodiment of this application, in combination with Figures 4 to 14 As shown, the embodiment of the present disclosure provides another preparation method of the back-contact solar cell as described above, including:

[0107] S01: Provide an N-type semiconductor substrate 1. After chemical polishing, the semiconductor substrate 1 has opposite first surface 1-1 and second surface 1-2.

[0108] Specifically, in combination withFigure 4 As shown, the chemical polishing is alkaline polishing, the solution components are NaOH and commercially available conventional additives, the concentration of NaOH is 1.2 - 2.0 wt%, the reaction temperature is 60 - 70 °C, the process time is 150 - 250 s, and the reflectivity after polishing is ≥ 39%.

[0109] S02: A tunneling oxide layer 2, a doped polysilicon layer 3, and a texturing protection layer 4 are sequentially formed on the second surface 1 - 2.

[0110] Specifically, in combination with Figure 5 As shown, in S02, a tunneling oxide layer, a doped polysilicon layer, and a texturing protection layer are formed by low - pressure chemical vapor deposition (LPCVD) or plasma - enhanced chemical vapor deposition (PECVD).

[0111] Among them, the tunneling oxide layer 2 is a silicon oxide layer, the thickness of the silicon oxide layer is 1 - 2.5 nm, preferably 1.5 - 2.0 nm. The doped polysilicon layer 3 is an N - type doped polysilicon thin film layer or a P - type doped polysilicon thin film layer.

[0112] When preparing an N - type polysilicon thin film layer by LPCVD, the texturing protection layer is a phosphosilicate glass (PSG) thin film layer. By first fabricating an intrinsic polysilicon thin film layer and then diffusing an N - type doping source into the intrinsic polysilicon thin film layer to form an N - type polysilicon thin film layer, the deposition temperature of the intrinsic polysilicon thin film layer is 550 - 650 °C, the N - type doping source is a phosphorus - containing gas, the diffusion temperature is 800 - 900 °C, and the phosphorus doping concentration is 1E 20 ~8E 20 cm -3 , preferably 2E 20 ~5E 20 cm -3 , the sheet resistance is 30 - 50 Ω / Sq; the thickness of the PSG thin film layer is 40 - 60 nm; the N - type doping source is preferably phosphorus oxychloride.

[0113] When preparing a P - type polysilicon thin film layer by LPCVD, the texturing protection layer is a borosilicate glass (BSG) thin film layer. By first fabricating an intrinsic polysilicon thin film layer and then diffusing a P - type doping source into the intrinsic polysilicon thin film layer to form a P - type polysilicon thin film layer, the deposition temperature of the intrinsic polysilicon thin film layer is 550 - 650 °C, the P - type doping source is a boron - containing gas, the diffusion temperature is 850 - 950 °C, and the boron doping concentration is 1E 19 ~8E 19 cm -3 , preferably 3E 19 ~6E 19 cm -3, the sheet resistance is 120 - 150 Ω / Sq; the thickness of the BS G thin film layer is 50 - 70 nm; the P-type doping source is preferably boron tribromide, and can also be boron-containing substances such as boron trichloride.

[0114] When preparing the N-type poly-silicon thin film layer or P-type poly-silicon thin film layer by PECVD, the texturing protection layer is SiO2 or SiNx thin film with a thickness of 30 - 50 nm.

[0115] When preparing the N-type poly-silicon thin film layer by PECVD, the deposition temperature is 350 - 450 °C, the N-type doping source is a phosphorus-containing gas, preferably PH3 gas, and can be partially or completely replaced by other gases, such as PF3, trimethylgallium; the phosphorus doping concentration is 1E 20 ~8E 20 cm -3 ,preferably 2E 20 ~5E 20c m -3 ; the sheet resistance is 30 - 50 Ω / Sq.

[0116] When preparing the P-type poly-silicon thin film layer, the deposition temperature is 350 - 450 °C, the P-type doping source is a boron-containing gas, preferably B2H6 gas, and can be partially or completely replaced by other gases, such as B(CH3)3; the boron doping concentration is 1E 19 ~8E 19 cm -3 ,preferably 3E 19 ~6E 19 cm -3 ; the sheet resistance is 120 - 150 Ω / Sq.

[0117] S03: Open holes alternately in some areas of the second surface 1 - 2, remove the tunneling oxide layer 2, doped poly-silicon layer 3 and texturing protection layer 4, then perform texturing cleaning to form a textured structure on the first surface 1 - 1 and the open-hole areas of the second surface 1 - 2, and the unopened areas of the second surface 1 - 2 are the first areas.

[0118] Specifically, as shown in Figure 6 and Figure 7 , if the poly-silicon in the above step S02 is N-type poly-silicon, the width of the first area is set to 400 - 500 um, and if the poly-silicon in the above step S02 is P-type poly-silicon, the width of the first area is set to 550 - 700 um. The removed thin film layers in the open-hole areas include: tunneling oxide layer 2, doped poly-silicon thin film layer 3 and texturing protection layer 4. Then, perform texturing cleaning on the open-hole areas and the first surface 1 - 1 to form a textured structure.

[0119] Because a certain thickness of thin film layer will also be deposited around the first surface 1-1 due to the wrap-around plating when the doped polysilicon thin film layer 3 and the texturing protective layer 4 are deposited on the second surface 1-2, before the opening area and the first surface 1-1 are texturing, the first surface 1-1 is first immersed on one side in a horizontal etching device to etch away the texturing protective film layer that has been deposited on the first surface 1-1, and then a texturing cleaning process is performed. It should be noted that the wrap-around polysilicon layer will be etched away during the texturing process.

[0120] The S03 is alternately opened on the second surface 1-2, and the opening method is laser etching of the thin film layer, using a short pulse laser such as a picosecond or femtosecond laser to reduce damage to the thin film layer around the etching area. The laser power is 40-60W, and the spot is 30-120um, preferably 60-80um. The texturing and cleaning method is as follows: using the anisotropic corrosion characteristics of low-concentration alkaline solution to form a pyramid velvet surface on the surface of the silicon wafer. The solution composition is NaOH and additives, the NaOH concentration is 0.5-1.2%, the reaction temperature is 75-85°C, and the resulting velvet reflectivity is less than 12%. Since the alkaline solution will corrode downward on the surface of the silicon wafer in the opening area, there will be a height difference between the first area and the velvet area. The height difference is set to 1-8um, preferably 2-5um.

[0121] After the pyramid velvet surface is formed, the velvet protective layer is removed with an acid solution at room temperature. The acid solution is a mixed solution of hydrofluoric acid and hydrochloric acid, wherein the concentration of hydrofluoric acid is 5-8% and the concentration of hydrochloric acid is 2.5-4%. The etching process time is 30-60S.

[0122] S04: forming a surface passivation layer 5 and an anti-reflection layer 6 in sequence on the first surface 1-1.

[0123] Specifically, combined Figure 8 As shown, the surface passivation layer 5 in S04 is usually manufactured by PECVD or atomic layer deposition (ALD), and the anti-reflection layer 6 is often manufactured by PECVD.

[0124] When the surface passivation layer 5 is deposited by PECVD, the passivation layer is a silicon oxide film, the deposition temperature is 450-550° C., and the thickness is 3-8 nm.

[0125] When the surface passivation layer 5 is deposited by ALD, the passivation layer is an aluminum oxide thin film, the deposition temperature is 250-300° C., and the thickness is 3-8 nm.

[0126] When fabricating the antireflection layer 6 by PECVD, the antireflection layer 6 is one of silicon nitride, silicon oxynitride or silicon oxide thin films, with a deposition temperature of 450 - 550 °C, a thickness of 80 - 130 nm, and a refractive index of 2.0 - 2.1. The antireflection layer 6 consists of two parts of film layers. The first part of the film layer functions as an antireflection layer, with a thickness of 70 - 110 nm, and the second part of the film layer serves as the first sacrificial layer during subsequent processing, with a thickness of 10 - 20 nm. This first sacrificial layer will be etched and removed during subsequent processing.

[0127] When depositing the surface passivation layer 5 and the antireflection layer 6 by the above PECVD method, if a plate-type PECVD device is used, there will be no overcoating on the second surface 1-2 of the silicon wafer. If a tube-type PECVD device is used, overcoating will occur on the second surface 1-2 of the silicon wafer.

[0128] S05: Form an insulating dielectric layer 7 on the second surface 1-2.

[0129] Specifically, as shown in Figure 9 , when forming the insulating dielectric layer 7 by depositing an insulating dielectric film in S05 using the PECVD method or a combination of ALD and PECVD, when using the PECVD method, the insulating dielectric film is one or a combination of SiNx, SiOx, SiNxOx, and the deposition temperature is 450 - 550 °C.

[0130] When using a combination of ALD and PECVD, the insulating dielectric film is an Al2O3 / SiNx stack. Among them, ALD is used to deposit Al2O3, with a deposition temperature of 250 - 300 °C and a thickness of 3 - 8 nm. PECVD is used to deposit one or a combination of SiNx, SiOx, SiNxOx, with a deposition temperature of 450 - 550 °C and a thickness of 80 - 130 nm.

[0131] One or a combination of SiNx, SiOx, SiNxOx fabricated by the above PECVD consists of two parts of film layers. The first part of the film layer functions as insulation, with a thickness of 70 - 110 nm. The second part of the film layer serves as the second sacrificial layer during subsequent processing, with a thickness of 10 - 20 nm. This second sacrificial layer will be etched and removed during subsequent processing.

[0132] S06: In the opening area of the second surface 1-2, locally remove and clean the insulating dielectric layer 7. The area where the insulating dielectric layer 7 is removed is the second area. Among them, the position between the first area and the second area is set as the third area, and the insulating dielectric layer 7 in the third area is not removed.

[0133] Specifically, as shown in Figure 10As shown, if the poly silicon in the above step S02 is N-type poly silicon, the width of the second region is set to 550 - 700 um. If the poly silicon in the above step S02 is P-type poly silicon, the width of the second region is set to 400 - 500 um. The position between the first region and the second region is set as the third region, and the width of the third region is set to 100 - 200 um. Since the third region has not been processed, the insulating dielectric layer 7 fabricated in step S05 is retained in this region.

[0134] In S06, the insulating dielectric layer 7 at the local position is removed and cleaned. The implementation method is as follows: It is removed by laser etching. The laser device uses a short-pulse laser such as a picosecond or femtosecond laser to reduce the damage to the film layer around the etching area. The laser power is 40 - 60 W, and the spot size is 30 - 120 um, preferably 60 - 80 um. Since there are often particulate matters on the etched surface after laser etching, therefore, a NaOH + H2O2 solution is used for cleaning to remove the residual particulate matters. Among them, the concentration of NaOH is 0.5 - 1.0%, the concentration of H2O2 is 1 - 2%, the reaction temperature is 65 - 70 °C, and the process time is 100 - 150 S. Finally, an acid solution is used to remove the oxide layer and metal contaminants on the suede. The acid solution is a mixed solution of hydrofluoric acid and hydrochloric acid. Among them, the concentration of hydrofluoric acid is 2 - 4%, the concentration of hydrochloric acid is 2.5 - 4%, and the etching process time is 10 - 40 S. This cleaning process will also remove the first sacrificial layer of the antireflection layer 6 on the first surface 1-1 fabricated in step S04 and the second sacrificial layer of the insulating dielectric layer 7 on the second surface 1-2 fabricated in step S05.

[0135] S07: An intrinsic passivation layer 8, a doped silicon thin film layer 9, and a transparent conductive film layer 10 are sequentially formed in the second region of the second surface 1-2.

[0136] Specifically, as shown in Figure 11 In step S07, first, an intrinsic passivation layer 8, a doped silicon thin film layer 9, and a transparent conductive thin film layer 10 are deposited on the second surface 1-2, and then the intrinsic passivation layer 8, the doped silicon thin film layer 9, and the transparent conductive film layer 10 in the first region and the third region are removed from the second surface 1-2. Among them, the intrinsic passivation layer 8 is an intrinsic amorphous silicon thin film layer with a thickness of 5 - 15 nm. It is fabricated using a plate-type PECVD device or a hot-wire chemical vapor deposition HWCVD device, and the deposition temperature is 170 - 230 °C. This fabrication process will not cause overplating.

[0137] The doped silicon thin film layer 9 is one or a combination of amorphous silicon thin film, microcrystalline silicon thin film, and nanocrystalline silicon thin film, with a thickness of 10 - 30 nm. It is fabricated using a PECVD device or an HWCVD device, and the deposition temperature is 170 - 250 °C. This fabrication process does not produce overplating. If the poly silicon in the above step S02 is N-type poly silicon, then a P-type doped silicon thin film is deposited in the second region. If the poly silicon in the above step S02 is P-type poly silicon, then an N-type doped silicon thin film is deposited in the second region.

[0138] The transparent conductive thin film is one or a combination of ITO, IWO, and AZO, with a thickness of 50 - 110 nm. It is fabricated using PVD or RPD methods, and the deposition temperature is 150 - 200 °C. This fabrication process does not produce overplating.

[0139] Specifically, in combination with Figure 12 As shown, in step S07, the transparent conductive thin film layer 10 in the first region and the third region is removed by laser etching. Then, the doped silicon thin film layer 9 and the intrinsic passivation layer 8 are removed by alkaline solution etching. The laser etching uses a short-pulse laser such as a picosecond or femtosecond laser to reduce the damage to the film layer around the etching area. The laser power is 15 - 25 W, and the spot size is 30 - 120 μm, preferably 60 - 100 μm. The alkaline solution etching removes the doped silicon thin film layer 9 and the intrinsic passivation layer 8. The alkaline solution consists of a NaOH solution and an additive. The NaOH concentration is 1.0 - 1.6%, the reaction temperature is 65 - 75 °C, and the process time is 200 - 300 s.

[0140] S08: Open holes on the insulating dielectric layer 7 in the first region of the second surface 1-2.

[0141] Specifically, in combination with Figure 13 As shown, in step S08, laser etching is used to open holes in the insulating dielectric film in the first region of the second surface 1-2. The laser power is 15 - 25 W, and the hole width is 15 - 30 μm. A short-pulse laser such as a picosecond or femtosecond laser is used to reduce the damage to the film layer around the hole position 11.

[0142] S09: Form metal electrodes at the hole position 11 of the insulating dielectric layer 7 in the first region of the second surface 1-2 and on the transparent conductive film layer 10 in the second region of the second surface 1-2.

[0143] Specifically, in combination with Figure 13As shown, in step S09, a metal electrode is formed by screen printing or laser transfer printing. The metal electrode is one of a silver electrode and a silver-coated copper electrode. The curing temperature of the paste is 180 to 220 °C, and the process time is 20 to 40 minutes. Among them, the metal electrode includes a first metal electrode 12 and a second metal electrode 13. The first metal electrode 12 is located in the first region and contacts the doped poly-silicon layer 3 through the insulating dielectric layer 7. The second metal electrode 13 is located in the second region and contacts the transparent conductive film layer 10.

[0144] The above description and the drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, the individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or substituted for parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A back-contact solar cell, characterized in that, Comprising: A semiconductor substrate, the semiconductor substrate including a first surface and a second surface, wherein the first surface is a light-receiving surface, the second surface is a backlight surface, and the second surface includes a first region, a second region, and a third region; Wherein the first region includes a tunneling oxide layer, a doped polysilicon layer, and an insulating dielectric layer sequentially stacked on the semiconductor substrate; The second region includes an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer sequentially stacked on the semiconductor substrate; The third region is located between the first region and the second region for spatially isolating the first region and the second region, and the third region includes the insulating dielectric layer extending from the first region to the third region.

2. The back contact solar cell according to claim 1, characterized in that, The third region is a groove-shaped structure to form a height difference between the first region and the second region.

3. The back-contact solar cell according to claim 2, wherein, The third region includes a partial surface of the semiconductor substrate and sidewalls formed by the height difference, and the insulating dielectric layer covers the partial surface of the semiconductor substrate and the sidewalls formed by the height difference.

4. The back contact solar cell according to claim 1, characterized in that, The tunneling oxide layer is a silicon oxide layer with a thickness of 1 - 2.5 nm.

5. The back-contact solar cell according to claim 1, characterized in that, The doped polysilicon layer is a doped polycrystalline silicon layer. Wherein, when the doping type is N-type, the thickness of the doped polysilicon layer is 100 - 250 nm and the sheet resistance is 30 - 50 Ω / Sq; when the doping type is P-type, the thickness of the doped polysilicon layer is 250 - 400 nm and the sheet resistance is 120 - 150 Ω / Sq.

6. The back contact solar cell according to claim 1, characterized in that, The insulating dielectric layer is one or a combination of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide, with a thickness of 70 - 110 nm.

7. The back-contact solar cell according to claim 1, characterized in that, The intrinsic passivation layer is an intrinsic amorphous silicon thin film layer with a thickness of 5 - 15 nm.

8. The back contact solar cell according to claim 1, characterized in that, The doped silicon thin film layer includes one of an amorphous silicon thin film layer, a microcrystalline silicon thin film layer, and a nanocrystalline silicon thin film layer, with a doping type opposite to that of the doped polysilicon layer and a thickness of 10 - 30 nm.

9. The back-contact solar cell according to claim 1, characterized in that, The transparent conductive film layer includes one of ITO, IWO, and AZO, with a thickness of 50 - 110 nm.

10. The back contact solar cell according to claim 1, characterized in that, The surface of the first region is a polished surface, the surface of the second region is a pyramid texture surface, and the surface of the third region is a pyramid texture surface.

11. The back contact solar cell according to claim 1, characterized in that, A surface passivation layer and an antireflection layer are sequentially stacked on the first surface.

12. The back contact solar cell according to claim 11, characterized in that, The surface passivation layer is aluminum oxide or silicon oxide, with a thickness of 3 - 8 nm.

13. The back-contact solar cell according to claim 11, wherein, The antireflection layer is one of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 70 - 110 nm.

14. The back contact solar cell according to claim 1, characterized in that, The first surface is a pyramid texture surface, wherein the size of the pyramid texture surface is 1 - 3 um.

15. The back-contact solar cell according to any one of claims 1 to 14, further comprising: A first metal electrode located in the first region and contacting the doped polysilicon layer through the insulating dielectric layer; A second metal electrode located in the second region and contacting the transparent conductive film layer.

16. A method for preparing a back-contact solar cell according to any one of claims 1 to 15, characterized in that, Comprising: Providing a semiconductor substrate, the semiconductor substrate having the opposite first surface and second surface after chemical polishing; A tunneling oxide layer, a doped polysilicon layer, and a texturing protection layer are sequentially formed on the second surface; Open holes alternately in some areas of the second surface, remove the tunneling oxide layer, the doped polysilicon layer, and the texturing protection layer, and then perform texturing cleaning to form a textured surface structure on the first surface and the open-hole areas of the second surface. The unopened area of the second surface is the first area; Form an insulating dielectric layer on the second surface; In the open-hole areas of the second surface, remove and clean a part of the insulating dielectric layer. The removed area is the second area. Among them, the position between the first area and the second area is set as the third area, and the insulating dielectric layer in the third area is not removed; An intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer are sequentially formed in the second area of the second surface.

17. The method for preparing a back-contact solar cell according to claim 16, characterized in that, Before forming the insulating dielectric layer on the second surface, it further includes: Form a surface passivation layer and an antireflection layer sequentially on the first surface, where the insulating dielectric layer and the antireflection layer are made of the same material.

18. The method for preparing a back-contact solar cell according to claim 16, wherein, Sequentially forming an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer in the second area of the second surface includes: Deposit an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer on the second surface; Remove the intrinsic passivation layer, the doped silicon thin film layer, and the transparent conductive film layer covering the surfaces of the first area and the third area on the second surface.

19. The method for preparing a back-contact solar cell according to claim 16, characterized in that, After sequentially forming an intrinsic passivation layer, a doped silicon thin film layer, and a transparent conductive film layer in the second area of the second surface, it further includes: Open holes in the insulating dielectric layer on the first area of the second surface; Form metal electrodes at the open-hole positions of the insulating dielectric layer on the first area of the second surface and on the transparent conductive film layer on the second area of the second surface.

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