Array substrate, preparation method thereof and display device

Abstract

The invention discloses an array substrate (5), a preparation method thereof and a display device. The array substrate (5) comprises a substrate (30), at least one transistor (20) arranged on the substrate (30), at least one data line (DL) arranged on the substrate (30) and at least one first electrode arranged on the substrate (30); at least one transistor (20) comprising an active layer (18) and a gate (19); the grid electrode (19) is located on the side, away from the substrate (30), of the active layer (18), and orthographic projections of the grid electrode (19) and the active layer (18) on the plane where the substrate (30) is located are at least partially overlapped; the active layer (18) has at least one connection surface (40) on a side close to the substrate (30), the connection surface (40) being configured to be electrically connected to the data line (DL) or the first electrode.

Description

Array substrate, manufacturing method thereof, and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] Liquid crystal displays (LCDs) are a common type of display. LCDs use two polarized materials with a liquid crystal solution (liquid crystal) between them. Applying a voltage across the two polarized materials causes the liquid crystal to deflect. The degree of deflection can be controlled by controlling the applied voltage. Currently, LCDs are being developed to be lightweight, thin, short, and compact.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device.

[0006] In one aspect, an embodiment of the present disclosure provides an array substrate. The array substrate includes a substrate, at least one transistor disposed on the substrate, at least one data line disposed on the substrate, and at least one first electrode disposed on the substrate;

[0007] The at least one transistor includes an active layer and a gate; the gate is located on a side of the active layer away from the substrate, and the gate and the active layer have at least partial overlap in their orthographic projections on the plane where the substrate is located; the active layer has at least one connection surface on a side close to the substrate, and the connection surface is configured to be electrically connected to the data line or the first electrode.

[0008] In an exemplary embodiment, the active layer has two connection surfaces on a side close to the substrate, one connection surface is configured to be electrically connected to the first electrode, and the other connection surface is configured to be electrically connected to the data line.

[0009] In an exemplary embodiment, in a plane perpendicular to the array substrate, the array substrate includes the substrate, a first conductive layer located on one side of the substrate, a first insulating layer located on a side of the first conductive layer away from the substrate, and a semiconductor layer located on a side of the first insulating layer away from the substrate; the semiconductor layer includes the active layer; the first conductive layer includes at least one first connecting electrode, the first insulating layer is provided with at least one first through hole, the at least one first through hole exposes a portion of the surface of the at least one first connecting electrode away from the substrate, and one of the connecting surfaces is located in the first through hole and contacts the portion of the surface of the first connecting electrode, and the first connecting electrode is configured to be electrically connected to the first electrode.

[0010] In an exemplary embodiment, in a plane perpendicular to the array substrate, the array substrate further comprises at least one insulating layer located on a side of the transistor away from the substrate, and a portion of the first electrode is located on a side of the at least one insulating layer away from the substrate;

[0011] The at least one insulating layer is provided with at least one via hole, and the at least one via hole exposes a portion of the surface of the first connecting electrode away from the substrate; a portion of the first electrode is located in the via hole and contacts the portion of the surface of the first connecting electrode.

[0012] In an exemplary embodiment, the at least one insulating layer includes a first passivation layer, a planarization layer, and a second passivation layer sequentially disposed in a direction away from the substrate; and a material of the planarization layer includes an organic material.

[0013] In an exemplary embodiment, the at least one insulating layer includes a first passivation layer, a flat layer, and a second passivation layer arranged in sequence along a direction away from the substrate; the at least one via includes a second through hole and a third through hole that are connected to each other, the flat layer is provided with at least one second through hole, the second passivation layer is provided with at least one third through hole, and the orthographic projection of the at least one third through hole on the plane where the array substrate is located is at least partially overlapped with the orthographic projection of the at least one second through hole on the plane where the array substrate is located, and the third through hole exposes a portion of the surface of the first connecting electrode away from the substrate, and a portion of the first electrode is located in the third through hole and contacts the portion of the surface of the first connecting electrode away from the substrate.

[0014] In an exemplary embodiment, the orthographic projection of the third through hole on the plane where the array substrate is located includes the orthographic projection of the second through hole on the plane where the array substrate is located; the orthographic projection of the third through hole on the plane where the array substrate is located does not overlap with the orthographic projection of the first through hole on the plane where the array substrate is located, or the orthographic projection of the third through hole on the plane where the array substrate is located partially overlaps with the orthographic projection of the first through hole on the plane where the array substrate is located.

[0015] In an exemplary embodiment, the first conductive layer also includes the at least one data line, and the first insulating layer is further provided with at least one fourth through hole, the at least one fourth through hole exposing a portion of the surface of the at least one data line away from the substrate, and the other connecting surface is located in the fourth through hole and in contact with the portion of the surface of the data line.

[0016] In an exemplary embodiment, the first conductive layer further includes at least one first data connection electrode, and the first insulating layer is further provided with at least one fifth through hole, the at least one fifth through hole exposing a portion of the surface of the at least one first data connection electrode away from the substrate, and the other connection surface is located in the fifth through hole and in contact with the portion of the surface of the first data connection electrode, and the first data connection electrode is configured to be electrically connected to the data line.

[0017] In an exemplary embodiment, in a plane perpendicular to the array substrate, the array substrate further includes a metal wiring layer, and the metal wiring layer is located on a side of the transistor away from the substrate, and the metal wiring layer includes the at least one data line.

[0018] In an exemplary embodiment, in a plane perpendicular to the array substrate, the array substrate further includes an interlayer insulating layer, and the interlayer insulating layer is located between the transistor and the metal wiring layer, and the interlayer insulating layer is provided with at least one sixth through hole, the at least one sixth through hole exposes a portion of the surface of the first data connection electrode away from the substrate, and a portion of the at least one data line is located in the sixth through hole and contacts the portion of the surface of the first data connection electrode away from the substrate.

[0019] In an exemplary embodiment, the array substrate further includes at least one second data connection electrode, and the at least one second data connection electrode and the first electrode are in the same layer structure, and the at least one data line is electrically connected to the first data connection electrode via the second data connection electrode.

[0020] In an exemplary embodiment, the metal wiring layer further includes at least one second connecting electrode, and a portion of a surface of the first electrode close to the substrate contacts a portion of a surface of the second connecting electrode away from the substrate.

[0021] On the other hand, another embodiment of the present disclosure further provides a display device, which includes the array substrate, opposing substrate and liquid crystal layer described in any of the above embodiments; the array substrate and the opposing substrate are arranged opposite to each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

[0022] On the other hand, another embodiment of the present disclosure further provides a method for preparing an array substrate, the method comprising:

[0023] At least one transistor, at least one data line, and at least one first electrode are formed on the same side of a substrate; the at least one transistor includes an active layer and a gate; the gate is located on a side of the active layer away from the substrate, and the gate and the active layer have at least partial overlap in their orthographic projections on the plane where the substrate is located; the active layer has at least one connection surface on a side close to the substrate, and the connection surface is configured to be electrically connected to the data line or the first electrode.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0025] Summary of the Figures

[0026] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0027] FIG1 is a schematic front view of an array substrate according to an embodiment of the present disclosure;

[0028] FIG2A is a partial top view of an array substrate according to an embodiment of the present disclosure;

[0029] FIG2B is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0030] 3A is a schematic plan view of an array substrate after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0031] 3B is a cross-sectional schematic diagram of an array substrate after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0032] 4A is a schematic plan view of an array substrate after an initial pattern of a first insulating layer is formed in an embodiment of the present disclosure;

[0033] 4B is a schematic cross-sectional view of an array substrate after an initial pattern of a first insulating layer is formed according to an embodiment of the present disclosure;

[0034] 5A is a schematic plan view of an array substrate after a semiconductor layer pattern is formed according to an embodiment of the present disclosure;

[0035] 5B is a schematic cross-sectional view of an array substrate after a semiconductor layer pattern is formed according to an embodiment of the present disclosure;

[0036] FIG6A is a plan view of an array substrate after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0037] 6B is a schematic cross-sectional view of the array substrate after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0038] 7A is a plan view of an array substrate after a fourth insulating layer pattern is formed according to an embodiment of the present disclosure;

[0039] 7B is a schematic cross-sectional view of the array substrate after forming a fourth insulating layer pattern according to an embodiment of the present disclosure;

[0040] FIG8A is a plan view of an array substrate after a third conductive layer pattern is formed according to an embodiment of the present disclosure;

[0041] 8B is a schematic cross-sectional view of the array substrate after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0042] 9A is a schematic plan view of an array substrate after a fifth insulating layer pattern is formed according to an embodiment of the present disclosure;

[0043] 9B is a schematic cross-sectional view of the array substrate after forming a fifth insulating layer pattern according to an embodiment of the present disclosure;

[0044] FIG10A is a schematic plan view of an array substrate after a fourth conductive layer pattern is formed according to an embodiment of the present disclosure;

[0045] FIG10B is a schematic cross-sectional view of an array substrate after forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0046] FIG11A is a partial top view of an array substrate according to another embodiment of the present disclosure;

[0047] FIG11B is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0048] FIG12A is a plan view of an array substrate after forming a first conductive layer pattern according to another embodiment of the present disclosure;

[0049] 12B is a schematic cross-sectional view of an array substrate after forming a first conductive layer pattern according to another embodiment of the present disclosure;

[0050] 13A is a plan view of an array substrate after forming an initial pattern of a first insulating layer according to another embodiment of the present disclosure;

[0051] 13B is a cross-sectional schematic diagram of an array substrate after forming an initial pattern of the first insulating layer according to another embodiment of the present disclosure;

[0052] 14A is a plan view of an array substrate after a semiconductor layer pattern is formed according to another embodiment of the present disclosure;

[0053] 14B is a schematic cross-sectional view of an array substrate after a semiconductor layer pattern is formed according to another embodiment of the present disclosure;

[0054] FIG15A is a plan view of an array substrate after forming a second conductive layer pattern according to another embodiment of the present disclosure;

[0055] 15B is a cross-sectional view of an array substrate after forming a second conductive layer pattern according to another embodiment of the present disclosure;

[0056] FIG16A is a plan view of an array substrate after a metal wiring layer pattern is formed according to another embodiment of the present disclosure;

[0057] FIG16B is a cross-sectional view of an array substrate after a metal wiring layer pattern is formed according to another embodiment of the present disclosure;

[0058] 17A is a plan view of an array substrate after a fourth insulating layer pattern is formed according to another embodiment of the present disclosure;

[0059] 17B is a schematic cross-sectional view of an array substrate after forming a fourth insulating layer pattern according to another embodiment of the present disclosure;

[0060] FIG18A is a plan view of an array substrate after forming a third conductive layer pattern according to another embodiment of the present disclosure;

[0061] 18B is a schematic cross-sectional view of an array substrate after forming a third conductive layer pattern according to another embodiment of the present disclosure;

[0062] 19A is a schematic plan view of an array substrate after a fifth insulating layer pattern is formed according to another embodiment of the present disclosure;

[0063] 19B is a schematic cross-sectional view of an array substrate after forming a fifth insulating layer pattern according to another embodiment of the present disclosure;

[0064] FIG20A is a plan view of an array substrate after forming a fourth conductive layer pattern according to another embodiment of the present disclosure;

[0065] FIG20B is a schematic cross-sectional view of an array substrate after forming a fourth conductive layer pattern according to another embodiment of the present disclosure;

[0066] FIG21 is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0067] FIG22 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure.

[0068] Reference numerals:

[0069] 10-pixel electrode, 10-1-connecting portion, 10-2-comb-tooth portion, 11-first insulating layer, 11-1-initial pattern of the first insulating layer, 12-second insulating layer, 13-3rd insulating layer, 13-1-third insulating film, 14-fourth insulating layer, 15-fifth insulating layer, 16-first connecting electrode, 17-light shielding block, 18-active layer, 18-1-first region, 18-2-second region, 18-3-channel region, 18a-first portion, 18b-second portion, 18c-third portion, 19-gate, 21-common electrode, GL-1-first line segment, GL-2-second line segment, GL-3-third line segment, DL-1-first data connecting electrode, DL-2-second data connecting electrode, 22-interlayer insulating layer, 23-second connecting electrode, 20-transistor, 30-substrate, 40-connecting surface, DL-3-first extending segment, DL-4-second extending segment;

[0070] 1-countering substrate, 2-liquid crystal layer, 3-black matrix, 4-color filter layer, 5-array substrate.

[0071] Details

[0072] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0073] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0074] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0075] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0076] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0077] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0078] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0079] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0080] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0081] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0082] In the present disclosure, “about” and “approximately” refer to values ​​that are not strictly defined and allow for process and measurement errors.

[0083] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0084] An embodiment of the present disclosure provides an array substrate, the array substrate comprising a substrate, at least one transistor disposed on the substrate, at least one data line disposed on the substrate, and at least one first electrode disposed on the substrate;

[0085] The at least one transistor includes an active layer and a gate; the gate is located on a side of the active layer away from the substrate, and the gate and the active layer have at least partial overlap in their orthographic projections on the plane where the substrate is located; the active layer has at least one connection surface on a side close to the substrate, and the connection surface is configured to be electrically connected to the data line or the first electrode.

[0086] The array substrate provided by the embodiment of the present disclosure avoids setting a via hole for achieving electrical connection on a side of the active layer away from the substrate by arranging the connection surface for electrically connecting the active layer with the data line or the first electrode on the side of the active layer close to the substrate. This can avoid damage to the active layer caused by etching the via hole, thereby avoiding affecting the performance of the transistor, and can improve the display quality of the display device.

[0087] Figure 1 is a schematic front view of an array substrate according to one embodiment of the present disclosure. As shown in Figure 1 , the array substrate may include a display area AA and a border area BB located on at least one side of the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top, left, and right borders of the array substrate.

[0088] In one exemplary embodiment, as shown in FIG1 , the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers; for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL closer to the substrate.

[0089] In an exemplary embodiment, as shown in FIG1 , a plurality of data lines DL and a plurality of gate lines GL may intersect to form a plurality of sub-pixel areas. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel area. A sub-pixel may be provided in a corresponding sub-pixel area. The sub-pixel area may include an opening area and a non-opening area surrounding the opening area. The non-opening area may be an area obscured by the black matrix of the opposing substrate of the array substrate, and the opening area may be an area not obscured by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL may both be located within the non-opening area. The array substrate of the disclosed embodiment may be used to implement a display function, and the opening area of ​​each sub-pixel area may be configured for display. The non-opening area may surround the opening area and not display. However, the disclosed embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0090] In one exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, red sub-pixel, and green sub-pixel. As shown in FIG1 , at least one sub-pixel may include: a pixel electrode 10 and a common electrode (not shown in FIG1 ), and the orthographic projections of the pixel electrode 10 and the common electrode of the sub-pixel on the substrate may partially overlap. The common electrode of the plurality of sub-pixels in the display area AA may be an integral structure. For example, the common electrode may be located on the side of the pixel electrode 10 closest to the substrate. The sub-pixel may also include a transistor 20. The transistor 20 may be located adjacent to the intersection of a data line DL and a gate line GL. The transistor 20 may include a gate, a first electrode, and a second electrode. The gate may be electrically connected to the gate line GL, the first electrode of the transistor 20 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of a sub-pixel. The transistor 20 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0091] In an exemplary embodiment, the second border area B2 may include at least a gate drive circuit (e.g., including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to the plurality of gate lines GL in the display area AA. The gate drive circuit may further include a transistor. The structure of the transistor located in the second border area B2 may be the same as or different from the structure of the transistor located in the display area AA.

[0092] Liquid crystal display devices have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In the ADS mode, the pixel electrode and common electrode are both located on one side of the array substrate. In the TN and VA modes, the pixel electrode and common electrode are respectively arranged on opposite sides of the liquid crystal layer, with the pixel electrode located on one side of the array substrate and the common electrode on the opposite substrate.

[0093] The ADS mode operates on the principle that liquid crystal molecules lie in a plane parallel to the glass substrate. When no voltage is applied, light passing through the lower polarizer becomes linearly polarized, parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from exiting. When voltage is applied, a transverse electric field forms on the liquid crystal, aligning the liquid crystal molecules along the direction of the electric field. After passing through the lower polarizer and the liquid crystal layer, the light becomes elliptically polarized, allowing it to pass through the upper polarizer and exit.

[0094] The TN mode operates under the principle that in the absence of voltage, the liquid crystal molecules are twisted into a 90° alignment by the alignment films. Light passes through the lower polarizer and the liquid crystal molecules before exiting through the upper polarizer. When voltage is applied, most of the liquid crystal molecules, except for those near the upper and lower polarizers, align vertically. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. However, since its polarization axis is parallel to the upper polarizer, the light is absorbed and cannot be emitted.

[0095] The VA mode operates on the principle that liquid crystal molecules are aligned perpendicular to the glass substrate. When no voltage is applied, light passing through the lower polarizer forms linear polarization parallel to the short axis of the liquid crystal molecules. This polarization cannot be rotated, and is therefore absorbed by the upper polarizer and prevented from being emitted. When voltage is applied, the liquid crystal molecules are deflected in the direction of the electric field. Light passing through the lower polarizer and liquid crystal layer becomes elliptically polarized, allowing it to pass through the upper polarizer and be emitted.

[0096] The structure of the array substrate is described below by taking the ADS mode array substrate structure as an example.

[0097] Figure 2A is a partial top view schematic diagram of an array substrate according to an embodiment of the present disclosure, and Figure 2B is a partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure. Figure 2B is a cross-sectional schematic diagram at the position marked AA in Figure 2A. As shown in Figure 2A, only two pixel units are shown. One pixel unit may include three sub-pixels, and the three sub-pixels may be a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along a first direction X. For example, the first sub-pixel may be a blue sub-pixel, the second sub-pixel may be a red sub-pixel, and the third sub-pixel may be a green sub-pixel. In the embodiment of the present disclosure, i may be a positive integer greater than or equal to 1, and j may be a positive integer greater than or equal to 2.

[0098] In the embodiment of the present disclosure, the direction perpendicular to the array substrate is defined as a third direction Z, which can also be referred to as the thickness direction of the array substrate. As shown in Figure 2B, within a plane perpendicular to the array substrate, the array substrate can include a substrate 30, and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on one side of the substrate 30. The array substrate can also include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, a third insulating layer 13 and a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer. In the embodiment of the present disclosure, the first insulating layer can also be referred to as a buffer layer, the second insulating layer can also be referred to as a gate insulating (GI) layer, the third insulating layer can also be referred to as a first passivation (PVX1) layer, the fourth insulating layer can also be referred to as a planarization (PLN) layer, and the fifth insulating layer can also be referred to as a second passivation (PVX2) layer.

[0099] As shown in FIG2B , the first conductive layer may include a plurality of first connection electrodes 16, a plurality of light shielding blocks 17, and a plurality of data lines DL. The first connection electrodes 16 and the data lines DL may be respectively disposed on opposite sides of the light shielding blocks 17 along the first direction X. The first connection electrodes 16 are configured to be electrically connected to both the transistor 20 and the pixel electrode 10. Arranging the light shielding blocks and the data lines in the same layer structure can reduce the number of film layers of the array substrate, simplify the preparation process of the array substrate, and reduce the production cost of the array substrate.

[0100] As shown in FIG2B , the semiconductor layer may include an active layer 18 for multiple transistors 20. The active layer 18 may include a channel region 18-3, a first region 18-1 located on opposite sides of the channel region 18-3, and a second region 18-2 located on opposite sides of the channel region 18-3. For example, during the process of manufacturing the array substrate, a portion of the active layer 18 may be subjected to a conductorization treatment so that portions of the active layer 18 form the first region 18-1 and the second region 18-2, respectively. The first region 18-1 of the active layer 18 may serve as the first electrode of the transistor, and the second region 18-2 of the active layer 18 may serve as the second electrode of the transistor. By conducting a conductorization treatment on a portion of the active layer to form the first and second electrodes of the transistor, the area of ​​the transistor gate can be reduced, thereby preventing the gate from affecting the aperture ratio of the display area and improving the aperture ratio of the display area. The active layer 18 has two connection surfaces 40 on the side closest to the substrate 30. One connection surface 40 is configured to be electrically connected to the data line DL, and the other connection surface 40 is configured to be electrically connected to the pixel electrode 10.

[0101] As shown in FIG2B , a connection surface 40 is in contact with the data line DL, which can avoid setting a via for electrical connection on the side of the active layer 18 away from the substrate 30, prevent damage to the active layer 18 caused by the preparation of the via, and avoid problems such as poor transistor performance due to damage to the active layer.

[0102] As shown in FIG2B , the other connection surface 40 is in contact with the first connection electrode 16 , which can avoid setting a via hole for electrical connection on the side of the active layer 18 away from the substrate 30 , thereby preventing damage to the active layer 18 caused by the preparation of the via hole, and avoiding problems such as poor transistor performance due to damage to the active layer.

[0103] As shown in FIG2B , the second conductive layer may include gates 19 of a plurality of transistors 20. The orthographic projection of the gate 19 on the plane where the array substrate is located may at least partially overlap with the orthographic projection of the channel region 18-3 on the plane where the array substrate is located. The gate may block at least part of the influence of light on the channel region, thereby improving the performance of the transistor. In the embodiment of the present disclosure, the transistor is set to a top gate structure, which can solve the shortcomings of the bottom gate structure: on the one hand, the top gate structure does not have the problem of excessive etching damaging the active layer. The gate in the top gate structure is located on the side of the active layer away from the substrate, which can play a role in protecting the active layer; on the other hand, the top gate structure has the advantage of achieving self-alignment, and the process is relatively simple. The use of a self-aligned structure can avoid the generation of overlapping areas and overlapping capacitance, which is conducive to accurately controlling the size of the channel region of the transistor, realizing a shorter channel region design, and optimizing the structural layout of the transistor.

[0104] As shown in Figure 2B, the third conductive layer may include a common electrode 21, and the fourth conductive layer may include a plurality of pixel electrodes 10. The orthographic projection of the common electrode 21 on the plane where the array substrate is located may at least partially overlap with the orthographic projection of the pixel electrode 10 on the plane where the array substrate is located. In the embodiment of the present disclosure, the pixel electrode may also be referred to as the first electrode of a sub-pixel, and the common electrode may also be referred to as the second electrode of a sub-pixel. Alternatively, the pixel electrode may also be referred to as the second electrode of a sub-pixel, and the common electrode may also be referred to as the first electrode of a sub-pixel.

[0105] As shown in Figure 2B, part of the surface of the pixel electrode 10 close to the substrate 30 contacts part of the surface of the first connecting electrode 16 away from the substrate 30 to achieve electrical connection between the pixel electrode 10 and the second pole of the transistor. This can avoid setting a via hole for achieving electrical connection on the side of the active layer 18 away from the substrate 30, prevent damage to the active layer 18 caused by the preparation of the via hole, and avoid problems such as poor transistor performance due to damage to the active layer.

[0106] In an exemplary embodiment, the substrate 30 may be a transparent substrate. For example, the substrate 30 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the present disclosure is not limited to this.

[0107] In an exemplary embodiment, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be metal materials, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be alloy materials of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), and molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer, the second conductive layer, and the third conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0108] In one exemplary embodiment, the thickness of the first conductive layer may range from 1500 angstroms to 3000 angstroms.

[0109] In one exemplary embodiment, the second conductive layer may have a thickness ranging from 1800 angstroms to 5000 angstroms.

[0110] In one exemplary embodiment, the thickness of the third conductive layer may range from 500 angstroms to 1000 angstroms.

[0111] In one exemplary embodiment, the fourth conductive layer may be made of a transparent conductive oxide material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the fourth conductive layer may be a single layer structure or a multilayer composite structure, such as ITO / Al / ITO. The thickness of the fourth conductive layer may range from 500 angstroms to 1000 angstroms.

[0112] In an exemplary embodiment, the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fifth insulating layer 15 may be made of inorganic materials. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO xThe first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fifth insulating layer 15 can be a single layer or a multi-layer or composite layer structure.

[0113] In one exemplary embodiment, the fourth insulating layer 14 can be made of an organic material. Examples of such organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. The fourth insulating layer 14 can be a single layer, a multilayer structure, or a composite layer structure. In the disclosed embodiment, providing an organic insulating layer can reduce crosstalk from the gate to the common electrode.

[0114] In an exemplary embodiment, the active layer 18 may include two or more sub-active layers. For example, the active layer may include two sub-active layers, or the active layer may include three sub-active layers, etc. The materials of the two or more sub-active layers may be the same or different.

[0115] In one exemplary embodiment, the material of the semiconductor layer may include one or more of indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), indium gallium zinc Y oxide (IGZYO, where Y represents doped tin), etc. In one example, the material of the semiconductor layer may be various materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene. The array substrate provided in the embodiments of the present disclosure is suitable for transistors manufactured using oxide technology, silicon technology, and organic technology.

[0116] In one exemplary embodiment, the semiconductor layer may have a thickness ranging from 300 angstroms to 800 angstroms.

[0117] The structure of the array substrate is described below using an example of its fabrication process. The "patterning process" referred to in the embodiments of this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. The deposition process can be any one or more of sputtering, evaporation, and chemical vapor deposition; the coating process can be any one or more of spray coating, spin coating, and inkjet printing; and the etching process can be any one or more of dry etching and wet etching, although this disclosure does not limit this. A "thin film" refers to a thin layer of a material formed on a substrate using deposition, coating, or other processes. If a "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If a "thin film" requires a patterning process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern." The term "A and B in the same layer" as used in this disclosure means that A and B are formed through the same patterning process.

[0118] The preparation process of the array substrate may include the following steps, which are illustrated by taking a transistor and a partial line segment of a data line as an example:

[0119] (11) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: depositing a first conductive film on one side of the substrate 30, and patterning the first conductive film through a patterning process to form a first conductive layer pattern located on one side of the substrate 30. The first conductive layer may include a plurality of first connection electrodes 16, a plurality of light shielding blocks 17, and a plurality of data lines DL, as shown in FIG3A and FIG3B, where FIG3B is a cross-sectional view taken along line BB in FIG3A.

[0120] As shown in FIG3A , the orthographic projection of the first connecting electrode 16 on the plane where the array substrate is located may be a rectangular shape extending along the first direction X. For example, the orthographic projection of the first connecting electrode 16 on the plane where the array substrate is located may be a rounded rectangle. The orthographic projection of the light shielding block 17 on the plane where the array substrate is located may be a rhombus shape. For example, the orthographic projection of the light shielding block 17 on the plane where the array substrate is located may be a rounded rhombus shape. The data line DL may be a line shape extending along the second direction Y. As shown in FIG3A , the first connecting electrode 16 and the data line DL may be respectively arranged on opposite sides of the light shielding block 17 along the first direction X, and the orthographic projection of the first connecting electrode 16 on the plane where the array substrate is located, the orthographic projection of the light shielding block 17 on the plane where the array substrate is located, and the orthographic projection of the data line DL on the plane where the array substrate is located do not overlap.

[0121] In some possible exemplary embodiments, the first connection electrode 16 and the light shielding block 17 may be connected to each other as an integral structure. Alternatively, the light shielding block 17 and the data line DL may be connected to each other as an integral structure.

[0122] (12) Forming a first insulating layer initial pattern. Forming the first insulating layer initial pattern may include: depositing a first insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, patterning the first insulating film through a patterning process to form a first insulating layer initial pattern located on the side of the first conductive layer away from the substrate 30, the first insulating layer initial pattern 11-1 may include a plurality of vias, the plurality of vias may include at least a first via K1 and a second via K2, and the first insulating film in the first via K1 and the second via K2 is etched away. The first via K1 exposes a portion of the surface of the data line DL away from the substrate 30, and the first via K1 is configured so that the subsequently formed active layer is electrically connected to the data line DL via the via. The second via K2 exposes a portion of the surface of the first connecting electrode 16 away from the substrate 30, and the second via K2 is configured so that the subsequently formed active layer is electrically connected to the first connecting electrode 16 via the via, as shown in FIG. 4A and FIG. 4B , FIG. 4B is a cross-sectional view taken along line BB in FIG. 4A .

[0123] As shown in Figure 4A, the orthographic projections of the first via K1 and the second via K2 on the plane of the array substrate can be rectangular. In one example, the orthographic projections of the first via K1 and the second via K2 on the plane of the array substrate can be circular, elliptical, pentagonal, hexagonal, etc. The orthographic projection of the first via K1 on the plane of the array substrate can partially overlap with the orthographic projection of the data line DL on the plane of the array substrate. For example, the orthographic projection of the first via K1 on the plane of the array substrate can be located within the orthographic projection of the data line DL on the plane of the array substrate. The orthographic projection of the second via K2 on the plane of the array substrate can partially overlap with the orthographic projection of the first connection electrode 16 on the plane of the array substrate. For example, the orthographic projection of the second via K2 on the plane of the array substrate can be located within the orthographic projection of the first connection electrode 16 on the plane of the array substrate.

[0124] In an exemplary embodiment, the apertures of the first via hole K1 and the second via hole K2 may be between 4.0 μm and 6.0 μm. For example, the first via hole K1 may be a 4.0 μm square hole, or the first via hole K2 may be a 6.0 μm square hole.

[0125] In an exemplary embodiment, the first insulating film may have a thickness in a range of 3000 angstroms to 5000 angstroms.

[0126] (13) Forming a semiconductor layer pattern. Forming the semiconductor layer pattern may include: depositing a semiconductor thin film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern located on a side of the first insulating layer initial pattern 11-1 away from the substrate 30. The semiconductor layer may include an active layer 18 of a transistor, as shown in FIG5A and FIG5B, where FIG5B is a cross-sectional view taken along line BB in FIG5A.

[0127] As shown in FIG5A , the active layer 18 may include a first portion 18a, a second portion 18b, and a third portion 18c, which are sequentially connected. The first portion 18a may be located on one side of the second portion 18b along the first direction X, and the third portion 18c may be located on the side of the second portion 18b opposite to the first direction X. As shown in FIG5A , the orthographic projections of the first portion 18a and the third portion 18c on the plane of the array substrate may both be rectangular, and the orthographic projection of the second portion 18b on the array substrate may be linear. As shown in FIG5A , the orthographic projection of the first portion 18a on the plane of the array substrate may partially overlap with the orthographic projection of the data line DL on the plane of the array substrate, the orthographic projection of the second portion 18b on the plane of the array substrate may partially overlap with the orthographic projection of the light shielding block 17 on the plane of the array substrate, and the orthographic projection of the third portion 18c on the plane of the array substrate may partially overlap with the orthographic projection of the first connection electrode 16 on the plane of the array substrate. A first electrode of the transistor may be located in the first portion 18 a , a second electrode of the transistor may be located in the third portion 18 c , and a channel region of the transistor may be located in the second portion 18 b .

[0128] As shown in Figure 5A, the orthographic projection of the first via hole K1 on the plane where the array substrate is located may partially overlap with the orthographic projection of the first portion 18a on the plane where the array substrate is located. For example, the orthographic projection of the first via hole K1 on the plane where the array substrate is located may be located within the orthographic projection of the first portion 18a on the plane where the array substrate is located. The orthographic projection of the second via hole K2 on the plane where the array substrate is located may partially overlap with the orthographic projection of the third portion 18c on the plane where the array substrate is located. For example, the orthographic projection of the second via hole K2 on the plane where the array substrate is located may be located within the orthographic projection of the third portion 18c on the plane where the array substrate is located.

[0129] As shown in FIG. 5B , a portion of the active layer 18 close to the substrate 30 is in contact with the data line DL via the first via hole K1 , and a portion of the active layer 18 close to the substrate 30 is in contact with the first connection electrode 16 via the second via hole K2 .

[0130] (14) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process to form a second insulating layer pattern located on a side of the semiconductor layer away from the substrate 30 and a second conductive layer pattern located on a side of the second insulating layer 12 away from the substrate 30. The second conductive layer may include a gate line GL and a gate 19 of a transistor, as shown in FIG6A and FIG6B , with FIG6B being a cross-sectional view taken along line BB in FIG6A .

[0131] As shown in Figure 6A, the main portion of the gate line GL can be a line shape extending along the first direction X. For example, the gate line GL can be a straight line shape extending along the first direction X, or the gate line GL can be a broken line shape extending along the first direction X. For example, the gate line GL can include a first line segment GL-1, a second line segment GL-2, and a third line segment GL-3 connected in sequence. The first line segment GL-1 can include a first end and a second end arranged opposite to each other, and the second end of the first line segment GL-1 can extend along the first direction X. The first end of the second line segment GL-2 can be connected to the second end of the first line segment GL-1, and the second end of the second line segment GL-2 can extend in a direction different from the first direction X and the second direction Y. For example, the second end of the second line segment GL-2 can extend in a diagonal direction (fourth direction) between the first direction X and the second direction Y. The first end of the third line segment GL-3 can be connected to the second end of the second line segment GL-2, and the second end of the third line segment GL-3 can extend along the first direction X.

[0132] As shown in Figure 6B, the orthographic projection of the gate line GL on the plane where the array substrate is located may partially overlap with the orthographic projection of the active layer 18 on the plane where the array substrate is located. The part of the active layer 18 located in the overlapping area can be used as the channel region 18-3, and the part of the gate line GL located in the overlapping area can be used as the gate 19.

[0133] As shown in FIG6B , forming the second conductive layer pattern may further include using the gate electrode 19 as a mask to partially conduction process the active layer 18, so that the active layer 18 forms a first region 18-1 and a second region 18-2. The first region 18-1 of the active layer 18 can be used as a first electrode of a transistor, and the second region 18-2 of the active layer 18 can be used as a second electrode of the transistor.

[0134] In one exemplary embodiment, the thickness of the second insulating layer 12 may range from 1000 angstroms to 2000 angstroms.

[0135] In an exemplary embodiment, as shown in FIG6A , the first line segment GL-1 may include a first end and a second end disposed opposite each other, and the second end of the first line segment GL-1 may extend along a first direction X. The first end of the second line segment GL-2 may be connected to the second end of the first line segment GL-1, and the second end of the second line segment GL-2 may extend along a direction different from the first direction X and the second direction Y. As shown in FIG6A , an angle α is formed between the second line segment GL-2 and the first line segment GL-1, and α may be greater than 0 degrees and less than or equal to 45 degrees. For example, α may be 10 degrees, 20 degrees, 30 degrees, etc. During the design of the array substrate, the arrangement of the gate lines GL may be changed by changing the value of α, thereby adapting to various arrangement layouts of the array substrate and enhancing the diversity and adjustment flexibility of the display product design.

[0136] (15) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: sequentially depositing a third insulating film and a fourth insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern located on the side of the third insulating film 13-1 away from the substrate 30, the fourth insulating layer 14 may include a plurality of vias, the plurality of vias may include at least a third via K3, and the fourth insulating film located within the third via K3 is etched away to expose a portion of the surface of the third insulating film 13-1 away from the substrate 30, as shown in FIG7A and FIG7B, FIG7B is a cross-sectional view taken along line BB in FIG7A. The third via K3 is configured so that a pixel electrode formed subsequently is electrically connected to the first connection electrode 16 via the via.

[0137] 7A , the orthographic projection of the third via hole K3 on the plane where the array substrate is located may be a rectangle. In one example, the orthographic projection of the third via hole K3 on the plane where the array substrate is located may be a circle, an ellipse, a pentagon, a hexagon, or the like.

[0138] As shown in Figure 7A, the orthographic projection of the third via K3 in the plane where the array substrate is located does not overlap with the orthographic projection of the second via K2 in the plane where the array substrate is located, and the orthographic projection of the third via K3 in the plane where the array substrate is located does not overlap with the orthographic projection of the active layer 18 in the plane where the array substrate is located, which can avoid damage to the active layer in the subsequent etching process of the via, so as not to affect the performance of the transistor.

[0139] As shown in Figure 7A, the orthographic projection of the third via hole K3 in the plane where the array substrate is located may at least partially overlap with the orthographic projection of the first connecting electrode 16 in the plane where the array substrate is located. For example, the orthographic projection of the third via hole K3 in the plane where the array substrate is located is located within the orthographic projection of the first connecting electrode 16 in the plane where the array substrate is located.

[0140] In an exemplary embodiment, the diameter of the third via hole K3 may range from 4.0 micrometers to 6.0 micrometers. For example, the third via hole K3 may be a square hole with a diameter of 4.0 micrometers, or the third via hole K3 may be a square hole with a diameter of 6.0 micrometers.

[0141] In an exemplary embodiment, the thickness of the third insulating film may range from 2000 angstroms to 4000 angstroms.

[0142] In one exemplary embodiment, the fourth insulating layer 14 may have a thickness ranging from 20,000 angstroms to 30,000 angstroms.

[0143] (16) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on a side of the fourth insulating layer 14 away from the substrate 30. The third conductive layer may include a common electrode 21, as shown in FIG8A and FIG8B, with FIG8B being a cross-sectional view taken along line BB in FIG8A.

[0144] As shown in FIG. 8A , the orthographic projection of the common electrode 21 on the plane where the array substrate is located may be a rectangle or the like.

[0145] (17) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include: depositing a fifth insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, patterning the fifth insulating film through a patterning process to form a fifth insulating layer pattern located on a side of the third conductive layer away from the substrate 30, such that the first insulating layer initial pattern 11-1 forms the first insulating layer 11, and the third insulating film 13-1 forms the third insulating layer 13, as shown in FIG9A and FIG9B, FIG9B being a cross-sectional view taken along line BB in FIG9A.

[0146] As shown in FIG9A , the fifth insulating layer 15 may include a plurality of via holes, which may include at least a fourth via hole K4. The fifth insulating film, the third insulating film, and the first insulating film located within the fourth via hole K4 are all etched away, exposing a portion of the surface of the first connecting electrode 16 on a side away from the substrate 30. The fourth via hole K4 is configured to electrically connect a subsequently formed pixel electrode to the first connecting electrode 16 via the via hole.

[0147] As shown in Figure 9A , the orthographic projection of the fourth via K4 on the plane of the array substrate can at least partially overlap with the orthographic projection of the third via K3 on the plane of the array substrate. For example, the orthographic projection of the fourth via K4 on the plane of the array substrate can include the orthographic projection of the third via K3 on the plane of the array substrate, which can increase the contact area between the subsequently formed pixel electrode and the first connection electrode 16 and ensure the reliability of the electrical connection. As shown in Figure 9A , the orthographic projection of the fourth via K4 on the plane of the array substrate does not overlap with the orthographic projection of the second via K2 on the plane of the array substrate, which can prevent damage to the active layer during the etching process and ensure the performance of the transistor.

[0148] In an exemplary embodiment, the orthographic projection of the fourth via hole K4 on the plane of the array substrate may be rectangular, circular, elliptical, pentagonal, hexagonal, etc. The aperture of the fourth via hole K4 may range from 5.0 μm to 7.0 μm. For example, the fourth via hole K4 may be a 5.0 μm square hole, or the fourth via hole K4 may be a 7.0 μm square hole.

[0149] In an exemplary embodiment, the fifth insulating layer 15 may have a thickness ranging from 2000 angstroms to 4000 angstroms.

[0150] (18) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern located on a side of the fifth insulating layer 15 away from the substrate 30. The fourth conductive layer may include a pixel electrode 10, as shown in FIG10A and FIG10B, with FIG10B being a cross-sectional view taken along line BB in FIG10A.

[0151] As shown in Figure 10A, the pixel electrode 10 may include a connecting portion 10-1 and a plurality of comb-tooth portions 10-2. The orthographic projection of the connecting portion 10-1 on the plane where the array substrate is located may be a rectangle extending along the second direction Y. The plurality of comb-tooth portions 10-2 may extend along the first direction X and be arranged at intervals along the second direction Y. For example, the plurality of comb-tooth portions 10-2 may be arranged at equal intervals along the second direction Y. The orthographic projections of the plurality of comb-tooth portions 10-2 on the plane where the array substrate is located may partially overlap with the orthographic projections of the common electrode 21 on the plane where the array substrate is located.

[0152] As shown in FIG. 10B , a portion of the pixel electrode 10 is in contact and connected to a portion of the surface of the first connection electrode 16 away from the substrate 30 via the fourth via hole K4 .

[0153] In the exemplary embodiment of the present disclosure, the second via hole K2 may also be referred to as the first via hole, the third via hole K3 may also be referred to as the second via hole, the fourth via hole K4 may also be referred to as the third via hole, and the first via hole K1 may also be referred to as the fourth via hole.

[0154] Figure 11A is a partial top view of an array substrate according to another embodiment of the present disclosure, and Figure 11B is a partial cross-sectional view of an array substrate according to another embodiment of the present disclosure. Figure 11B is a cross-sectional view at the position marked CC in Figure 11A. As shown in Figure 11A, only two pixel units are shown, and one pixel unit may include three sub-pixels, which may be a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along a first direction X. For example, the first sub-pixel may be a blue sub-pixel, the second sub-pixel may be a red sub-pixel, and the third sub-pixel may be a green sub-pixel. In the embodiment of the present disclosure, i may be a positive integer greater than or equal to 1, and j may be a positive integer greater than or equal to 2.

[0155] In the embodiment of the present disclosure, the direction perpendicular to the array substrate is defined as a third direction Z, which can also be referred to as the thickness direction of the array substrate. As shown in Figure 11B, within a plane perpendicular to the array substrate, the array substrate can include a substrate 30, and a first conductive layer, a semiconductor layer, a second conductive layer, a metal trace layer, a third conductive layer, and a fourth conductive layer, sequentially arranged on one side of the substrate 30. The array substrate can also include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, an interlayer insulating layer 22 located between the second conductive layer and the metal trace layer, a third insulating layer 13 and a fourth insulating layer 14 located between the metal trace layer and the third conductive layer, and a fifth insulating layer 15 located between the third and fourth conductive layers. In the embodiment of the present disclosure, the first insulating layer can also be referred to as a buffer layer, the second insulating layer can also be referred to as a gate insulating (GI) layer, the third insulating layer can also be referred to as a first passivation (PVX1) layer, the fourth insulating layer can also be referred to as a planarization (PLN) layer, and the fifth insulating layer can also be referred to as a second passivation (PVX2) layer.

[0156] As shown in Figure 11B, the first conductive layer may include a plurality of first connection electrodes 16, a plurality of light shielding blocks 17, and a plurality of first data connection electrodes DL-1. The first connection electrodes 16 and the first data connection electrodes DL-1 may be respectively arranged on opposite sides of the light shielding block 17 along the first direction X. The first connection electrode 16 is configured to be electrically connected to both the transistor 20 and the pixel electrode 10. Providing the light shielding blocks and the first data connection electrodes in the same layer structure can reduce the number of film layers of the array substrate, simplify the preparation process of the array substrate, and reduce the production cost of the array substrate.

[0157] As shown in FIG11B , the semiconductor layer may include an active layer 18 for multiple transistors 20. The active layer 18 may include a channel region 18-3, a first region 18-1 located on opposite sides of the channel region 18-3, and a second region 18-2 located on opposite sides of the channel region 18-3. For example, during the process of manufacturing the array substrate, a portion of the active layer 18 may be subjected to a conductorization treatment so that portions of the active layer 18 form the first region 18-1 and the second region 18-2, respectively. The first region 18-1 of the active layer 18 may serve as the first electrode of the transistor, and the second region 18-2 of the active layer 18 may serve as the second electrode of the transistor. By conducting a conductorization treatment on a portion of the active layer to form the first and second electrodes of the transistor, the area of ​​the transistor gate can be reduced, thereby preventing the gate from affecting the aperture ratio of the display area and improving the aperture ratio of the display area. The active layer 18 has two connection surfaces 40 on the side closest to the substrate 30. One connection surface 40 is configured to be electrically connected to the data line DL, and the other connection surface 40 is configured to be electrically connected to the pixel electrode 10.

[0158] As shown in FIG11B , a connection surface 40 is in contact with the first data connection electrode DL-1, which can avoid setting a via hole for electrical connection on the side of the active layer 18 away from the substrate 30, thereby preventing damage to the active layer 18 caused by the preparation of the via hole, and avoiding problems such as poor transistor performance due to damage to the active layer.

[0159] As shown in FIG11B , another connection surface 40 is in contact with and connected to the first connection electrode 16 , which can avoid setting a via for electrical connection on the side of the active layer 18 away from the substrate 30 , prevent damage to the active layer 18 caused by the preparation of the via, and avoid problems such as poor transistor performance due to damage to the active layer.

[0160] As shown in FIG11B , the second conductive layer may include gates 19 of multiple transistors 20. The orthographic projection of the gate 19 on the plane where the array substrate is located may at least partially overlap with the orthographic projection of the channel region 18-3 on the plane where the array substrate is located. The gate may block at least some of the light from affecting the channel region, thereby improving the performance of the transistor.

[0161] As shown in Figure 11B, the metal wiring layer may include multiple second connection electrodes 23 and multiple data lines DL. The data lines DL are electrically connected to the active layer 18 via the second data connection electrode DL-2 and the first data connection electrode DL-1. The second data connection electrode DL-2 is located in the fourth conductive layer, which can be made of a transparent conductive oxide material. Therefore, the second data connection electrode DL-2 has good climbing performance. The data lines DL are electrically connected to the active layer 18 via the second data connection electrode DL-2 and the first data connection electrode DL-1, which can provide high connection stability and improve the reliability of the array substrate.

[0162] As shown in Figure 11B, the third conductive layer may include a common electrode 21, and the fourth conductive layer may include a plurality of pixel electrodes 10 and a second data connection electrode DL-2. The orthographic projection of the common electrode 21 on the plane where the array substrate is located may at least partially overlap with the orthographic projection of the pixel electrode 10 on the plane where the array substrate is located. In the embodiment of the present disclosure, the pixel electrode may also be referred to as the first electrode of a sub-pixel, and the common electrode may also be referred to as the second electrode of a sub-pixel. Alternatively, the pixel electrode may also be referred to as the second electrode of a sub-pixel, and the common electrode may also be referred to as the first electrode of a sub-pixel.

[0163] As shown in FIG11B , a portion of the surface of the pixel electrode 10 on the side closest to the substrate 30 contacts a portion of the surface of the first connection electrode 16 on the side closest to the substrate 30, thereby achieving electrical connection between the pixel electrode 10 and the second terminal of the transistor. This avoids the need for providing a via hole for electrical connection on the side of the active layer 18 away from the substrate 30, prevents damage to the active layer 18 caused by the formation of the via hole, and avoids problems such as poor transistor performance caused by damage to the active layer. A portion of the surface of the pixel electrode 10 on the side closest to the substrate 30 contacts and connects to a portion of the surface of the second connection electrode 23 on the side closest to the substrate 30.

[0164] In one exemplary embodiment, the thickness of the metal trace layer may range from 2000 angstroms to 5000 angstroms.

[0165] In one exemplary embodiment, the thickness of the interlayer insulating layer 22 may range from 2000 angstroms to 4000 angstroms.

[0166] In an exemplary embodiment, the material of the interlayer insulating layer 22 may be an inorganic material. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x The interlayer insulating layer 22 may be a single layer, a multi-layer structure, or a composite layer structure.

[0167] The preparation process of the array substrate may include the following steps, which are illustrated by taking a transistor and a partial line segment of a data line as an example:

[0168] (21) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: depositing a first conductive film on one side of the substrate 30, and patterning the first conductive film through a patterning process to form a first conductive layer pattern located on one side of the substrate 30. The first conductive layer may include a plurality of first connection electrodes 16, a plurality of light shielding blocks 17, and a plurality of first data connection electrodes DL-1, as shown in FIG12A and FIG12B, where FIG12B is a cross-sectional view taken along the DD line in FIG12A.

[0169] As shown in FIG12A , the orthographic projection of the first connection electrode 16 on the plane where the array substrate is located can be a rectangle extending along the first direction X. For example, the orthographic projection of the first connection electrode 16 on the plane where the array substrate is located can be a rounded rectangle. The orthographic projection of the light shielding block 17 on the plane where the array substrate is located can be a rhombus shape. For example, the orthographic projection of the light shielding block 17 on the plane where the array substrate is located can be a rounded rhombus shape.

[0170] As shown in Figure 12A, the first data link electrode DL-1 may include a first extension segment DL-3 and a second extension segment DL-4 that are connected to each other. The first extension segment DL-3 may include a first end and a second end that are oppositely disposed. The second end of the first extension segment DL-3 may extend along a first direction X. The first end of the second extension segment DL-4 may be connected to the second end of the first extension segment DL-3, and the second end of the second extension segment DL-4 may extend along a second direction Y. The orthographic projection of the first data link electrode DL-1 within the plane of the array substrate may be L-shaped.

[0171] As shown in Figure 12A, the first connecting electrode 16 and the first data connecting electrode DL-1 can be respectively arranged on both sides of the light-shielding block 17, and the orthographic projection of the first connecting electrode 16 on the plane where the array substrate is located, the orthographic projection of the light-shielding block 17 on the plane where the array substrate is located, and the orthographic projection of the first data connecting electrode DL-1 on the plane where the array substrate is located do not overlap.

[0172] In some possible exemplary embodiments, the first connection electrode 16 and the light shielding block 17 may be connected to each other as an integral structure. Alternatively, the light shielding block 17 and the first data link electrode DL- 1 may be connected to each other as an integral structure.

[0173] (22) Forming a first insulating layer initial pattern. Forming the first insulating layer initial pattern may include: depositing a first insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, patterning the first insulating film through a patterning process to form a first insulating layer initial pattern 11-1 located on the side of the first conductive layer away from the substrate 30, the first insulating layer initial pattern 11-1 may include a plurality of vias, the plurality of vias may include at least a first via K1 and a second via K2, and the first insulating film within the first via K1 and the second via K2 is etched away. The first via K1 exposes a portion of the surface of the first data connection electrode DL-1 away from the substrate 30, and the first via K1 is configured so that a subsequently formed active layer is electrically connected to the first data connection electrode DL-1 via the via. The second via K2 exposes a portion of the surface of the first connection electrode 16 away from the substrate 30, and the second via K2 is configured so that the subsequently formed active layer is electrically connected to the first connection electrode 16 via the via, as shown in Figures 13A and 13B, with Figure 13B being a cross-sectional view taken along the DD axis in Figure 13A. The orthographic projection of the first via K1 on the plane where the array substrate is located may at least partially overlap with the orthographic projection of the first data connection electrode DL-1 on the plane where the array substrate is located. For example, the orthographic projection of the first via K1 on the plane where the array substrate is located may be within the orthographic projection of the first data connection electrode DL-1 on the plane where the array substrate is located. For other descriptions of the first via K1 and the second via K2, reference may be made to the aforementioned embodiments and will not be elaborated upon here.

[0174] (23) Forming a semiconductor layer pattern. Forming the semiconductor layer pattern may include: depositing a semiconductor thin film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern located on a side of the first insulating layer initial pattern 11-1 away from the substrate 30. The semiconductor layer may include an active layer 18 of a transistor, as shown in FIG14A and FIG14B, where FIG14B is a cross-sectional view taken along line DD in FIG14A.

[0175] As shown in FIG14A , the active layer 18 may include a first portion 18a, a second portion 18b, and a third portion 18c, which are sequentially connected. The first portion 18a may be located on one side of the second portion 18b along the first direction X, and the third portion 18c may be located on the side of the second portion 18b opposite to the first direction X. As shown in FIG14A , the orthographic projections of the first portion 18a and the third portion 18c on the plane of the array substrate may both be rectangular, and the orthographic projection of the second portion 18b on the array substrate may be linear. As shown in FIG14A , the orthographic projection of the first portion 18a on the plane of the array substrate may partially overlap with the orthographic projection of the first data link electrode DL-1 on the plane of the array substrate, the orthographic projection of the second portion 18b on the plane of the array substrate may partially overlap with the orthographic projection of the light shielding block 17 on the plane of the array substrate, and the orthographic projection of the third portion 18c on the plane of the array substrate may partially overlap with the orthographic projection of the first connection electrode 16 on the plane of the array substrate. A first electrode of the transistor may be located in the first portion 18 a , a second electrode of the transistor may be located in the third portion 18 c , and a channel region of the transistor may be located in the second portion 18 b .

[0176] As shown in Figure 14A, the orthographic projection of the first via hole K1 on the plane of the array substrate may partially overlap with the orthographic projection of the first portion 18a on the plane of the array substrate. For example, the orthographic projection of the first via hole K1 on the plane of the array substrate may be located within the orthographic projection of the first portion 18a on the plane of the array substrate. The orthographic projection of the second via hole K2 on the plane of the array substrate may partially overlap with the orthographic projection of the third portion 18c on the plane of the array substrate. For example, the orthographic projection of the second via hole K2 on the plane of the array substrate may be located within the orthographic projection of the third portion 18c on the plane of the array substrate.

[0177] As shown in FIG14B , the portion of the active layer 18 close to the substrate 30 is in contact with the first data link electrode DL- 1 via the first via hole K1 , and the portion of the active layer 18 close to the substrate 30 is in contact with the first link electrode 16 via the second via hole K2 .

[0178] (24) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process to form a second insulating layer pattern located on a side of the semiconductor layer away from the substrate 30 and a second conductive layer pattern located on a side of the second insulating layer 12 away from the substrate 30. The second conductive layer may include a gate line GL and a gate 19 of a transistor, as shown in FIG15A and FIG15B , FIG15B being a cross-sectional view taken along line DD in FIG15A .

[0179] As shown in FIG15A , the gate line GL may include a first line segment GL-1, a second line segment GL-2, and a third line segment GL-3 that are sequentially connected. The first line segment GL-1 may include a first end and a second end that are oppositely disposed, and the second end of the first line segment GL-1 may extend along the first direction X. The first end of the second line segment GL-2 may be connected to the second end of the first line segment GL-1, and the second end of the second line segment GL-2 may extend along a direction different from the first direction X and the second direction Y. For example, the second end of the second line segment GL-2 may extend along a diagonal direction (a fourth direction) between the first direction X and the second direction Y. The first end of the third line segment GL-3 may be connected to the second end of the second line segment GL-2, and the second end of the third line segment GL-3 may extend along the first direction X.

[0180] As shown in FIG15B , forming the second conductive layer pattern may further include using gate 19 as a mask to partially conduction process active layer 18, so that the active layer 18 forms a first region 18-1 and a second region 18-2. The first region 18-1 of the active layer 18 can be used as a first electrode of a transistor, and the second region 18-2 of the active layer 18 can be used as a second electrode of the transistor.

[0181] (25) Forming a metal wiring layer pattern. Forming the metal wiring layer pattern may include: sequentially depositing an interlayer insulating film 22-1 and a metal conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, patterning the metal conductive film through a patterning process to form a metal wiring layer pattern located on a side of the interlayer insulating film 22-1 away from the substrate 30. The metal wiring layer may include a second connection electrode 23 and a data line DL, as shown in FIG16A and FIG16B. FIG16B is a cross-sectional view taken along the DD direction in FIG16A.

[0182] As shown in Figure 16A, the orthographic projection of the second connection electrode 23 on the plane where the array substrate is located can be a rectangle. In one example, the orthographic projection of the second connection electrode 23 on the plane where the array substrate is located can be a circle, an ellipse, a hexagon, etc. The orthographic projection of the second connection electrode 23 on the plane where the array substrate is located can at least partially overlap with the orthographic projection of the active layer 18 on the plane where the array substrate is located. For example, the orthographic projection of the second connection electrode 23 on the plane where the array substrate is located can be located within the orthographic projection of the active layer 18 on the plane where the array substrate is located. The orthographic projection of the second connection electrode 23 on the plane where the array substrate is located can at least partially overlap with the orthographic projection of the first connection electrode 16 on the plane where the array substrate is located. For example, the orthographic projection of the second connection electrode 23 on the plane where the array substrate is located can be located within the orthographic projection of the first connection electrode 16 on the plane where the array substrate is located.

[0183] As shown in FIG16A , the orthographic projection of the data line DL on the plane where the array substrate is located may be a line extending along the second direction Y. The orthographic projection of the data line DL on the plane where the array substrate is located may partially overlap with the orthographic projection of the first data link electrode DL- 1 on the plane where the array substrate is located.

[0184] (26) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: sequentially depositing a third insulating film 13-1 and a fourth insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern located on the side of the third insulating film 13-1 away from the substrate 30, the fourth insulating layer 14 may include a plurality of vias, the plurality of vias may include at least a third via K3 and a fourth via K4, and the fourth insulating film located in the third via K3 and the fourth via K4 is etched away to expose a portion of the surface of the third insulating film 13-1 away from the substrate 30, as shown in Figures 17A and 17B, Figure 17B is a cross-sectional view taken along the DD direction in Figure 17A. The third via K3 is configured so that the second data connection electrode formed subsequently is electrically connected to the data line DL and the first data connection electrode DL-1 via the via. The fourth via K4 is configured so that the pixel electrode formed subsequently is electrically connected to the first connection electrode 16 and the second connection electrode 23 via the via.

[0185] As shown in Figure 17A, the orthographic projections of the third via hole K3 and the fourth via hole K4 on the plane of the array substrate may be rectangular. In one example, the orthographic projections of the third via hole K3 and the fourth via hole K4 on the plane of the array substrate may be circular, elliptical, pentagonal, hexagonal, etc.

[0186] As shown in Figure 17A , the orthographic projection of the third via K3 within the plane of the array substrate does not overlap with the orthographic projection of the first via K1 within the plane of the array substrate. As shown in Figure 17A , the orthographic projection of the third via K3 within the plane of the array substrate may at least partially overlap with the orthographic projections of the data line DL and the first data connection electrode DL-1 within the plane of the array substrate. For example, the orthographic projection of the third via K3 within the plane of the array substrate may lie within the orthographic projection of the first data connection electrode DL-1 within the plane of the array substrate.

[0187] As shown in Figure 17A, the orthographic projection of the fourth via hole K4 on the plane of the array substrate does not overlap with the orthographic projection of the second via hole K2 on the plane of the array substrate. The orthographic projection of the fourth via hole K4 on the plane of the array substrate may at least partially overlap with the orthographic projections of the first connection electrode 16 and the second connection electrode 23 on the plane of the array substrate. For example, the orthographic projection of the fourth via hole K4 on the plane of the array substrate may be located within the orthographic projection of the first connection electrode 16 on the plane of the array substrate.

[0188] (27) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on a side of the fourth insulating layer 14 away from the substrate 30. The third conductive layer may include a common electrode 21, as shown in FIG18A and FIG18B, with FIG18B being a cross-sectional view taken along line DD in FIG18A.

[0189] (28) Forming a fifth insulating layer pattern. Forming the fifth insulating layer pattern may include: depositing a fifth insulating film on one side of the substrate 30 on which the aforementioned pattern is formed, patterning the fifth insulating film through a patterning process to form a fifth insulating layer pattern located on a side of the third conductive layer away from the substrate 30, and forming the first insulating layer initial pattern 11-1 into the first insulating layer 11, forming the interlayer insulating film 22-1 into the interlayer insulating layer 22, and forming the third insulating film 13-1 into the third insulating layer 13, as shown in FIG19A and FIG19B, FIG19B is a cross-sectional view taken along line DD in FIG19A.

[0190] As shown in FIG19A , the fifth insulating layer 15 may include multiple vias, which may include at least a fifth via K5 and a sixth via K6. The fifth insulating film, the third insulating film, the interlayer insulating film, and the first insulating film within the fifth and sixth vias K5 and K6 are all etched away. The fifth via K5 exposes a portion of the surface of the data line DL and the first data link electrode DL-1 on a side away from the substrate 30. The fifth via K5 is configured to electrically connect a subsequently formed second data link electrode to the data line DL and the first data link electrode DL-1 via the via. The sixth via K6 exposes a portion of the surface of the first and second link electrodes 16 and 23 on a side away from the substrate 30. The sixth via K6 is configured to electrically connect a subsequently formed pixel electrode to both the first and second link electrodes 16 and 23 via the via.

[0191] As shown in Figure 19A, the orthographic projection of the fifth via K5 on the plane where the array substrate is located may at least partially overlap with the orthographic projection of the third via K3 on the plane where the array substrate is located. The orthographic projection of the sixth via K6 on the plane where the array substrate is located may at least partially overlap with the orthographic projection of the fourth via K4 on the plane where the array substrate is located. For example, the orthographic projection of the sixth via K6 on the plane where the array substrate is located may include the orthographic projection of the fourth via K4 on the plane where the array substrate is located.

[0192] (29) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive film on one side of the substrate 30 on which the aforementioned pattern is formed, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern located on a side of the fifth insulating layer 15 away from the substrate 30. The fourth conductive layer may include the pixel electrode 10 and the second data link electrode DL-2, as shown in FIG20A and FIG20B, with FIG20B being a cross-sectional view taken along the DD line in FIG20A.

[0193] As shown in FIG20A , the pixel electrode 10 may include a connecting portion 10-1 and a plurality of comb-tooth portions 10-2, which are connected to each other. The orthographic projection of the connecting portion 10-1 on the plane of the array substrate may be a rectangle extending along the second direction Y. The plurality of comb-tooth portions 10-2 may extend along the first direction X and be spaced apart along the second direction Y. For example, the connecting portion 10-1 and the plurality of comb-tooth portions 10-2 may be an integral structure connected to each other. As shown in FIG20A , the orthographic projection of the second data link electrode DL-2 on the plane of the array substrate may be a rectangle, etc.

[0194] As shown in FIG20B , a portion of the pixel electrode 10 may be connected to the first connection electrode 16 and a portion of the surface of the second connection electrode 23 away from the substrate 30 via the sixth via hole K6. A portion of the second data link electrode DL-2 may be connected to the data line DL and a portion of the surface of the first data link electrode DL-1 away from the substrate 30 via the fifth via hole K5.

[0195] In the exemplary embodiment of the present disclosure, the second via hole K2 may also be referred to as the first via hole, the fourth via hole K4 may also be referred to as the second via hole, the sixth via hole K6 may also be referred to as the third via hole, and the first via hole K1 may also be referred to as the fifth via hole.

[0196] Figure 21 is a partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure. As shown in Figure 21, within a plane perpendicular to the array substrate, the array substrate may include a substrate 30, and a first conductive layer, a semiconductor layer, a second conductive layer, a metal trace layer, a third conductive layer, and a fourth conductive layer, sequentially arranged on one side of the substrate 30. The array substrate may also include a first insulating layer 11 located between the first conductive layer and the semiconductor layer, a second insulating layer 12 located between the semiconductor layer and the second conductive layer, an interlayer insulating layer 22 located between the second conductive layer and the metal trace layer, a third insulating layer 13 and a fourth insulating layer 14 located between the metal trace layer and the third conductive layer, and a fifth insulating layer 15 located between the third and fourth conductive layers.

[0197] As shown in FIG21 , the first conductive layer may include a plurality of first connection electrodes 16, a plurality of light shielding blocks 17, and a plurality of first data connection electrodes DL-1. The first connection electrodes 16 and the first data connection electrodes DL-1 may be respectively disposed on opposite sides of the light shielding block 17 along the first direction X. The first connection electrodes 16 are configured to be electrically connected to both the transistor 20 and the pixel electrode 10. As shown in FIG21 , the semiconductor layer may include an active layer 18 for the plurality of transistors 20. The active layer 18 may include a channel region 18-3, and first and second regions 18-1 and 18-2 located on opposite sides of the channel region 18-3. As shown in FIG21 , a portion of the surface of the active layer 18 on the side closest to the substrate 30 is in contact with the first data connection electrodes DL-1. This avoids the need for vias for electrical connection on the side of the active layer 18 away from the substrate 30, prevents damage to the active layer 18 caused by the vias, and avoids problems such as poor transistor performance caused by damage to the active layer.

[0198] As shown in Figure 21, the interlayer insulating layer 22 is provided with at least one sixth through hole D6, which exposes a portion of the surface of the first data link electrode DL-1 on the side facing away from the substrate 30. The metal routing layer may include a plurality of second connection electrodes 23 and a plurality of data lines DL. A portion of at least one data line DL may be in contact with and connected to the first data link electrode DL-1 via the sixth through hole D6. The other structures of the array substrate can be referred to in the aforementioned embodiments and will not be further described here.

[0199] Figure 22 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure. As shown in Figure 22 , an embodiment of the present disclosure further provides a display device. For example, a display device capable of implementing an Advanced Super Dimension Switch (ADS) mode may include an array substrate 5 , which may be any of the array substrates provided in the aforementioned embodiments.

[0200] The display device may further include an opposing substrate 1 and a liquid crystal layer 2 disposed between an array substrate 5 and the opposing substrate 1. The pixel electrodes and common electrodes included in the array substrate 5 may be configured to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer 2. As shown in FIG22 , the liquid crystal molecules in the liquid crystal layer 2 may be horizontally aligned on the array substrate 5. In the disclosed embodiment, the horizontal direction is parallel to the plane of the array substrate 5.

[0201] In an exemplary embodiment, as shown in Figure 22 , the counter substrate 1 may include a base substrate, and a black matrix 3 and a color filter layer 4 disposed on the base substrate. However, the present disclosure is not limited thereto.

[0202] The present disclosure also provides a display device. The display device includes the array substrate described in any of the preceding embodiments. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. The present disclosure is not limited thereto.

[0203] The present disclosure also provides a method for preparing an array substrate, including:

[0204] At least one transistor, at least one data line, and at least one first electrode are formed on the same side of a substrate; the at least one transistor includes an active layer and a gate; the gate is located on a side of the active layer away from the substrate, and the gate and the active layer have at least partial overlap in their orthographic projections on the plane where the substrate is located; the active layer has at least one connection surface on a side close to the substrate, and the connection surface is configured to be electrically connected to the data line or the first electrode.

[0205] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. An array substrate, comprising a substrate, at least one transistor disposed on the substrate, at least one data line disposed on the substrate, and at least one first electrode disposed on the substrate; The at least one transistor includes an active layer and a gate; the gate is located on a side of the active layer away from the substrate, and at least a part of a positive projection of the gate and the active layer in a plane of the substrate overlaps; the side of the active layer close to the substrate has at least one connection surface, and the connection surface is configured to be electrically connected to the data line or the first electrode.

2. The array substrate according to claim 1, wherein, the side of the active layer close to the substrate has two connection surfaces, one connection surface is configured to be electrically connected to the first electrode, and the other connection surface is configured to be electrically connected to the data line.

3. The array substrate according to claim 2, wherein, in a plane perpendicular to the plane of the array substrate, the array substrate includes the substrate, a first conductive layer on one side of the substrate, a first insulating layer on a side of the first conductive layer away from the substrate, and a semiconductor layer on a side of the first insulating layer away from the substrate; the semiconductor layer includes the active layer; the first conductive layer includes at least one first connection electrode, the first insulating layer is provided with at least one first via hole, at least a part of a surface of the at least one first connection electrode away from the substrate is exposed by the at least one first via hole, and one connection surface is located in the first via hole and contacts the part of the surface of the first connection electrode, and the first connection electrode is configured to be electrically connected to the first electrode.

4. The array substrate according to claim 3, wherein, in a plane perpendicular to the plane of the array substrate, the array substrate further includes at least one insulating layer on a side of the transistor away from the substrate, and a part of the first electrode is located on a side of the at least one insulating layer away from the substrate; the at least one insulating layer is provided with at least one via hole, and at least a part of a surface of the first connection electrode away from the substrate is exposed by the at least one via hole; a part of the first electrode is located in the via hole and contacts the part of the surface of the first connection electrode.

5. The array substrate according to claim 4, wherein, the at least one insulating layer includes a first passivation layer, a planarization layer, and a second passivation layer sequentially arranged along a direction away from the substrate; the material of the planarization layer includes an organic material.

6. The array substrate according to claim 4, wherein, The at least one insulating layer includes a first passivation layer, a planarization layer, and a second passivation layer that are sequentially disposed along a direction away from the substrate; the at least one via hole includes a second via hole and a third via hole that are in communication with each other. The planarization layer is provided with at least one of the second via holes, and the second passivation layer is provided with at least one of the third via holes. At least a part of the orthographic projection of the at least one third via hole on the plane of the array substrate overlaps with at least a part of the orthographic projection of the at least one second via hole on the plane of the array substrate. The third via hole exposes a part of the surface of the first connection electrode on the side away from the substrate, and a part of the first electrode is located in the third via hole and contacts the part of the surface of the first connection electrode on the side away from the substrate.

7. The array substrate according to claim 6, wherein, the orthographic projection of the third via hole on the plane of the array substrate includes the orthographic projection of the second via hole on the plane of the array substrate; the orthographic projection of the third via hole on the plane of the array substrate does not overlap with the orthographic projection of the first via hole on the plane of the array substrate, or at least a part of the orthographic projection of the third via hole on the plane of the array substrate overlaps with at least a part of the orthographic projection of the first via hole on the plane of the array substrate.

8. The array substrate according to any one of claims 3 to 7, wherein, the first conductive layer further includes the at least one data line, the first insulating layer is further provided with at least one fourth via hole, the at least one fourth via hole exposes a part of the surface of the at least one data line on the side away from the substrate, and the other connection surface is located in the fourth via hole and contacts the part of the surface of the data line.

9. The array substrate according to any one of claims 3 to 7, wherein, the first conductive layer further includes at least one first data connection electrode, the first insulating layer is further provided with at least one fifth via hole, the at least one fifth via hole exposes a part of the surface of the at least one first data connection electrode on the side away from the substrate, and the other connection surface is located in the fifth via hole and contacts the part of the surface of the first data connection electrode, and the first data connection electrode is configured to be electrically connected to the data line.

10. The array substrate according to claim 9, wherein, in a plane perpendicular to the plane of the array substrate, the array substrate further includes a metal wiring layer, and the metal wiring layer is located on the side of the transistor away from the substrate, and the metal wiring layer includes the at least one data line.

11. The array substrate according to claim 10, wherein, in a plane perpendicular to the plane of the array substrate, the array substrate further includes an interlayer insulating layer, and the interlayer insulating layer is located between the transistor and the metal wiring layer, and the interlayer insulating layer is provided with at least one sixth via hole, the at least one sixth via hole exposes a part of the surface of the first data connection electrode on the side away from the substrate, and a part of the at least one data line is located in the sixth via hole and contacts the part of the surface of the first data connection electrode on the side away from the substrate.

12. The array substrate according to claim 10 further includes at least one second data connection electrode, and the at least one second data connection electrode and the first electrode are in the same layer structure, and the at least one data line is electrically connected to the first data connection electrode via the second data connection electrode.

13. The array substrate according to claim 10, wherein, the metal trace layer further includes at least one second connection electrode, and a partial surface of the first electrode on the side close to the substrate contacts a partial surface of the second connection electrode on the side far from the substrate.

14. A display device includes the array substrate according to any one of claims 1 to 13, a counter substrate, and a liquid crystal layer; the array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate and the counter substrate.

15. A method for manufacturing an array substrate, comprising: forming at least one transistor, at least one data line, and at least one first electrode on the same side of a substrate; the at least one transistor includes an active layer and a gate; the gate is located on the side of the active layer far from the substrate, and at least a part of the orthographic projection of the gate and the active layer on the plane where the substrate is located overlaps; the side of the active layer close to the substrate has at least one connection surface configured to be electrically connected to the data line or the first electrode.

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