Wafer test data visualization method, device, equipment and medium
By visualizing the wafer test data and generating color-coded wafer test visualization diagrams, the problem of low intuitiveness of wafer test data is solved and the chip yield is improved.
Patent Information
- Application Number
- CN202410138582.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-31
- Publication Date
- 2025-08-01
AI Technical Summary
In the prior art, the wafer test data is low in intuitiveness and cannot intuitively reflect the distribution and frequency of the chip that failed the test, making it difficult to determine the influencing factors.
By conducting wafer tests on multiple wafers, we determine the number of times each test item fails at each chip position, and generate a corresponding wafer test visualization diagram, and use color data to represent the number of times the test fails, improving the visualization effect of the data.
It realizes the intuitiveization of wafer test data, and can intuitively determine the chip position distribution and frequency of failed tests, help identify process problems that lead to failed tests, and improve chip yield.
Smart Images
Figure CN120405393A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular, to a method, apparatus, device, and medium for visualizing wafer test data. Background Art
[0002] In the chip manufacturing industry, chip yield is a concern. To improve chip yield, it is necessary to identify the influencing factors that affect chip quality. To identify the influencing factors, it is necessary to perform chip probing (CP) tests on wafers, also known as wafer tests, and then analyze the wafer test data to determine the influencing factors.
[0003] In the prior art, for determining the influencing factors, it is usually to manually obtain the wafer test data of multiple wafers, and then determine the number and location of the chips that failed the test for each test item in the wafer test. Then, combined with personal experience, the influencing factors are determined. However, this method cannot intuitively reflect the characteristics of the wafer test data.
[0004] Therefore, there is an urgent need for a method for visualizing wafer test data that can visualize the wafer test data. Summary of the Invention
[0005] Embodiments of this application provide a method, apparatus, device, and medium for visualizing wafer test data to solve the problem of the urgent need for a method for visualizing wafer test data that can visualize the wafer test data.
[0006] In a first aspect, embodiments of this application provide a method for visualizing wafer test data, including:
[0007] Providing a plurality of wafers, and performing wafer tests on each of the wafers, where the wafer tests include a plurality of test items performed in sequence;
[0008] For each of the test items, determining the number of times of test failure at the same chip position among the plurality of wafers;
[0009] For each of the test items, generating a corresponding wafer test visualization graph according to the number of times of test failure at each chip position.
[0010] In a specific embodiment, the step of, for each of the test items, determining the number of times of test failure at the same chip position among the plurality of wafers includes:
[0011] For each test item, taking the number of the identifiers of the test item in the test results at the same chip position among the plurality of wafers as the number of times of test failure; the identifier of the test item in the test results is the identifier of the test item that failed the test.
[0012] In a specific embodiment, for each of the test items, a corresponding wafer test visualization graph is generated according to the number of times of test failure at each chip position, including:
[0013] For each of the test items, the maximum value among the number of times of test failure at each chip position is taken as the target number of test failures;
[0014] According to the target number of test failures, the number of test failures of the test item at each chip position is normalized to obtain the standard test failure data of the test item at each chip position;
[0015] For each of the test items, a corresponding wafer test visualization graph is generated according to the standard test failure data of the test item at each chip position.
[0016] In a specific embodiment, for each of the test items, a corresponding wafer test visualization graph is generated according to the standard test failure data of the test item at each chip position, including:
[0017] For each of the test items, according to the standard test failure data of the test item at each chip position and the corresponding relationship between the preset standard test failure data and color data, the color data of the test item at each chip position is determined;
[0018] For each of the test items, a corresponding wafer test visualization graph of the test item is generated according to the color data of the test item at each chip position.
[0019] In a specific embodiment, the method further includes:
[0020] Obtain a plurality of chip defects existing in the plurality of wafers and the chip positions where each chip defect is located;
[0021] For each of the test items, according to the number of times of test failure of the test item at each chip position and the chip positions where each chip defect is located, determine the matching degree between the test item and each chip defect.
[0022] In a specific embodiment, for each of the test items, according to the number of times of test failure of the test item at each chip position and the chip positions where each chip defect is located, determining the matching degree between the test item and each chip defect includes:
[0023] For each of the chip positions, if the number of times of test failure of the test item at the chip position is greater than zero, the chip position is taken as the first chip position;
[0024] For each of the chip defects, select the chip position where the chip defect is located in the first chip position and determine it as the second chip position;
[0025] Determine the ratio of the number of the second chip positions to the number of the first chip positions as the matching data;
[0026] According to the matching data and the preset corresponding relationship between the matching data and the matching degree, determine the matching degree between the test item and each of the chip defects.
[0027] In a second aspect, an embodiment of the present application provides a wafer test data visualization device, including:
[0028] A test module, configured to provide a plurality of wafers and perform wafer tests on each of the wafers, where the wafer tests include a plurality of test items performed in sequence;
[0029] A processing module, configured to, for each of the test items, determine the number of times of failed tests at the same chip positions in the plurality of wafers;
[0030] A generation module, configured to, for each of the test items, generate a corresponding wafer test visualization graph according to the number of times of failed tests at each of the chip positions.
[0031] In a third aspect, an embodiment of the present application provides an electronic device, including:
[0032] A processor, a memory, and a communication interface;
[0033] The memory is used to store executable instructions of the processor;
[0034] Wherein, the processor is configured to execute the wafer test data visualization method according to any one of the first aspects by executing the executable instructions.
[0035] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the wafer test data visualization method according to any one of the first aspects is implemented.
[0036] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it is used to implement the wafer test data visualization method according to any one of the first aspects.
[0037] The embodiments of the present application provide a method, apparatus, device and medium for visualizing wafer test data. By performing wafer tests on multiple wafers, the wafer tests include a plurality of test items performed in sequence. Furthermore, for each test item, the number of times of test failure at the same chip position among multiple wafers can be determined; and then it is converted into corresponding color data, and then a corresponding wafer test visualization graph is generated. This solution generates a wafer test visualization graph by determining the number of times of test failure at the same chip position of each test item among multiple wafers, realizes the visualization of wafer test data, and improves the intuitiveness of wafer test data. Description of the Drawings
[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0039] Figure 1a It is a schematic flowchart of the first embodiment of the method for visualizing wafer test data provided by the present application;
[0040] Figure 1b It is a chip position diagram provided by the present application;
[0041] Figure 1c It is a schematic diagram of the number of times of test failure of each test item at each chip position provided by the present application;
[0042] Figure 1d It is a wafer visualization graph provided by the present application;
[0043] Figure 2 It is a schematic flowchart of the second embodiment of the method for visualizing wafer test data provided by the present application;
[0044] Figure 3 It is a schematic flowchart of the third embodiment of the method for visualizing wafer test data provided by the present application;
[0045] Figure 4 It is a schematic structural diagram of the embodiment of the apparatus for visualizing wafer test data provided by the present application;
[0046] Figure 5 It is a schematic structural diagram of an electronic device provided by the present application. Detailed Embodiments
[0047] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application under the inspiration of this embodiment belong to the scope of protection of this application.
[0048] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.
[0049] In the chip manufacturing industry, chip yield is a concern. To improve chip yield, it is necessary to identify the influencing factors that affect chip quality. To identify the influencing factors, it is necessary to perform chip probing (CP) tests on wafers, also known as wafer tests, and then analyze the wafer test data to determine the influencing factors.
[0050] Wafer testing refers to the process between wafer manufacturing and packaging. The testing equipment directly contacts the chips through the probes of the probe card to complete the testing of the performance and functions of the chips. The testing can be performed on multiple test items. The test items can be testing whether the circuit is on or off, testing whether the storage module is available, connection testing, digital circuit testing, etc.
[0051] For the analysis of wafer test data, usually, the wafer test data of multiple wafers are manually obtained. Then, after determining the number and location of the chips that failed the test for each test item, the influencing factors are determined based on personal experience.
[0052] However, this method cannot intuitively reflect the wafer test data, such as the distribution of the chips that failed the test in the wafer, the frequency of test failures, etc. Therefore, there is an urgent need for a wafer test data visualization method that can visualize the wafer test data and solve the problem of low intuitiveness of the wafer test data.
[0053] In view of the problems existing in the prior art, the inventors found during the research on the method for visualizing wafer test data that in order to improve the intuitiveness of wafer test data, multiple wafers can be subjected to wafer tests. The wafer test includes multiple test items performed in sequence. Therefore, for the chips at the same chip position in multiple wafers, the same test item is tested multiple times. After determining the number of test failures corresponding to each test item at each chip position, a wafer test visualization graph corresponding to each test item is generated according to the number of test failures. In this wafer test visualization graph, each chip position corresponds to a corresponding color, and different colors indicate different numbers of test failures. Therefore, the frequency of test failures and the distribution of chips with test failures in the wafer can be intuitively seen. Based on the above inventive concept, the wafer test data visualization solution in this application is designed.
[0054] The following is an example to illustrate the application scenario of the wafer test data visualization method provided in this application.
[0055] Exemplarily, in this application scenario, after a batch of wafers are manufactured, the user uses a test device to perform wafer tests on these wafers, and the test device can generate the test results of each chip position in each wafer.
[0056] Based on the test results of each chip position in each wafer, the test device can determine the number of test failures of each test item at the same chip position in these wafers.
[0057] Then, color conversion is performed on the number of test failures to determine the color data corresponding to each test item at each chip position.
[0058] Furthermore, for each test item, according to the color data corresponding to each test item at each chip position, a wafer test visualization graph corresponding to the test item is generated. The user can intuitively determine the position distribution of the chips with test failures under this test item in the wafer and the frequency of test failures at each chip position from the wafer test visualization graph.
[0059] Subsequently, the user can determine which processes cause the problems according to the graph formed by the colors. For example, if the color forms a rectangle, since the photomask is rectangular in the lithography process, it can be determined that the lithography process causes the test item to fail the test.
[0060] It should be noted that the above scenario is only an example of an application scenario provided by the embodiments of this application. The embodiments of this application do not limit the actual forms of various devices included in this scenario, and can be set according to actual needs in the specific application of the solution.
[0061] Next, the technical solutions of the present application will be described in detail through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.
[0062] Figure 1a FIG. 4 is a schematic flowchart of the first embodiment of the wafer test data visualization method provided by the present application. In the embodiment of the present application, after the test equipment performs wafer tests on multiple wafers and then determines the number of test failures of each test item at each chip position, a wafer test visualization graph corresponding to each test item is generated. The method in this embodiment can be implemented by software, hardware, or a combination of software and hardware. As Figure 1a shown, the wafer test data visualization method specifically includes the following steps:
[0063] S101: Provide multiple wafers and perform wafer tests on each wafer.
[0064] In this step, in order to realize the visualization of wafer test data, multiple wafers need to be provided to the test equipment, and then the test equipment performs wafer tests on each wafer. The wafer test includes multiple test items performed in sequence.
[0065] It should be noted that the test items in the wafer test can be electrical device open / short circuit tests, transistor leakage tests, ring oscillator frequency tests, etc. The embodiments of the present application do not limit the test items in the wafer test, and can be determined according to actual situations.
[0066] S102: For each test item, determine the number of test failures at the same chip positions in multiple wafers.
[0067] In this step, the test equipment performs wafer tests on each wafer, and the test results at each same chip position in the wafer for each wafer test can be obtained. In the test result of a wafer test at a chip position, it includes the identifier of the test item that fails the test, or includes an identifier indicating that the chip test passes.
[0068] For each test item, the test equipment takes the number of identifiers of the test item in the test results at the same chip positions in multiple wafers as the number of test failures; the identifier of the test item in the test result is the identifier of the test item that fails the test.
[0069] Exemplarily, wafer testing is performed on 5 wafers, and there are 10 chips in each wafer, that is, there are 10 chip positions. For each test item, there are 5 test results at each chip position. For the first chip position, among the 5 test results at this chip position, there are the identifications of 4 test items that failed the test; among the identifications of the 4 test items that failed the test, there are 3 identifications of test item A and 1 identification of test item B. Therefore, the number of times test item A failed the test at this chip position is 3, and the number of times test item B failed the test at this chip position is 1. The process of determining the number of times test item A and test item B failed the test at the remaining 9 chip positions will not be elaborated here.
[0070] Exemplarily, Figure 1b The chip position map provided by this application is as Figure 1b shown. The chip position map is a circle, representing the wafer; there are grids in the circle, and each grid represents a chip position.
[0071] Exemplarily, on the basis of Figure 1b Figure 1c This is a schematic diagram of the number of times each test item failed the test at each chip position provided by this application. As Figure 1c shown, the number in each grid in the figure represents the number of times the test at this chip position failed.
[0072] S103: For each test item, generate a corresponding wafer test visualization graph according to the number of times the test failed at each chip position.
[0073] In this step, after the test equipment obtains the number of times each test item failed the test at each chip position, for each test item, a corresponding wafer test visualization graph is generated according to the number of times the test failed at each chip position of this test item.
[0074] For each test item, the maximum value among the number of times the test failed at each chip position of this test item can be determined. Then, according to this maximum value, the number of times the test failed at each chip position of this test item is normalized to obtain the test failure standard data of this test item at each chip position.
[0075] Furthermore, after performing color conversion on the test failure standard data of the test item at each chip position to obtain the color data of the test item at each chip position, a corresponding wafer test visualization graph of this test item can be generated.
[0076] Exemplarily, on the basis of Figure 1c Figure 1d This is the wafer visualization graph provided by this application. As Figure 1dAs shown, in this figure, each chip position shows a corresponding color. The user can intuitively determine the position distribution of the chips that failed the test under this test item in the wafer, and can also intuitively determine the number of chips that failed the test at each chip position under this test item.
[0077] It should be noted that in order to improve the efficiency of generating the wafer test visualization diagram, the number of times of test failure can be not normalized, and the number of times of test failure at each chip position of this test item can be directly subjected to color conversion to obtain the color data of this test item at each chip position, and then the wafer test visualization diagram can be generated.
[0078] Subsequently, the user can determine whether some processes are the reasons for the test failure according to the wafer test visualization diagram. Exemplarily, the color data is a gray value, the gray values of different chip positions are different, and the gray levels of the colors in the wafer visualization diagram are also different. The chip positions with larger gray levels form a rectangle, indicating that there is a problem with the lithography process, which is the reason for the test failure of this test item. The chip positions with larger gray levels form a circle and are located at the edge of the wafer, indicating that there is a problem with the etching process, which is the reason for the test failure of this test item. Improving the process can increase the yield.
[0079] The wafer test data visualization method provided in this embodiment performs wafer tests on multiple wafers, and the wafer tests include a plurality of test items performed in sequence. Then, for each test item, the number of times of test failure at the same chip positions in the multiple wafers can be determined; then it is converted into corresponding color data, and then the corresponding wafer test visualization diagram is generated. This solution generates a wafer test visualization diagram by determining the number of times of test failure at the same chip positions in multiple wafers for each test item, realizing the visualization of wafer test data and improving the intuitiveness of wafer test data.
[0080] Figure 2 This is a schematic flowchart of the second embodiment of the wafer test data visualization method provided by this application. On the basis of the above embodiment, this application embodiment describes the situation of the wafer test visualization diagram generated after normalizing the number of times of test failure. As Figure 2 shown, this wafer test data visualization method specifically includes the following steps:
[0081] S201: For each test item, use the maximum value among the number of times of test failure at each chip position as the target number of times of test failure.
[0082] In this step, after the test equipment obtains the number of failed tests for each test item at each chip position, in order to compare the subsequent wafer test visualization graphs corresponding to different test items, the data needs to be normalized. For each test item, the maximum value of the number of failed tests for this test item at each chip position is used as the target number of failed tests.
[0083] Exemplarily, based on Figure 1c it can be known from Figure 1c that for a certain test item, the target number of failed tests is 17.
[0084] S202: According to the target number of failed tests, normalize the number of failed tests for this test item at each chip position to obtain the standard data of the number of failed tests for this test item at each chip position.
[0085] In this step, after the test equipment determines the target number of failed tests, according to the target number of failed tests, normalize the number of failed tests for this test item at each chip position to obtain the standard data of the number of failed tests for this test item at each chip position.
[0086] Specifically, for each chip position, divide the number of failed tests for this test item at this chip position by the target number of failed tests to obtain the standard data of the number of failed tests for this test item at this chip position.
[0087] Exemplarily, the number of failed tests for this test item at this chip position is 2, and the target number of failed tests is 5. The standard data of the number of failed tests for this test item at this chip position is 0.4.
[0088] S203: For each test item, generate a corresponding wafer test visualization graph according to the standard data of the number of failed tests for this test item at each chip position.
[0089] In this step, after the test equipment obtains the standard data of the number of failed tests for each test item at each chip position, for each test item, according to the standard data of the number of failed tests for this test item at each chip position and the preset correspondence between the standard data of the number of failed tests and the color data, determine the color data for this test item at each chip position.
[0090] For each test item, generate a wafer test visualization graph corresponding to the test item according to the color data for this test item at each chip position. That is, first determine the color for this test item at each chip position according to the color data for this test item at each chip position, and then fill this color at this chip position to generate a wafer test visualization graph corresponding to this test item.
[0091] It should be noted that for different color data corresponding to different test failure standard data, in order to more intuitively reflect the test failure standard data, the smaller the gray value of the color data corresponding to the test failure standard data can be set, the darker the color.
[0092] It should be noted that the color data can be RGB format data, or hexadecimal format data, gray value, etc. The embodiments of the present application do not limit the color data, and can be determined according to the actual situation.
[0093] Exemplarily, Table 1 is a correspondence table between test failure standard data and color data provided by the present application, where the color data is the gray value.
[0094] Table 1
[0095] Test failed standard data Color data 0 255 0.2 204 0.4 153 0.6 102 0.8 51 1 0
[0096] As shown in Table 1, the larger the test failure standard data, the smaller the corresponding color data, that is, the gray value, and the darker the color. The embodiments of the present application do not limit the correspondence between the test failure standard data and the color data, and can be set according to the actual situation.
[0097] The wafer test data visualization method provided by this embodiment normalizes the number of test failures, places the number of test failures corresponding to different test items within the same range, eliminates differences, and can realize an intuitive comparison of the wafer test visualization diagrams corresponding to different test items. At the same time, in the case of executing this solution multiple times, the number of wafers for each wafer test is different, and the wafer test visualization diagrams corresponding to different test items obtained can still be intuitively compared. In addition, by normalizing the number of test failures, each execution of this solution can adopt a correspondence between a test failure standard data and color data to determine the color data, improving the convenience of determining the color data.
[0098] Figure 3 It is a schematic flowchart of Embodiment 3 of the wafer test data visualization method provided by the present application. On the basis of the above embodiments, the embodiments of the present application illustrate the situation of determining the matching degree between chip defects and test items by combining the test equipment with the chip positions where the chip defects are located. As Figure 3 shown, the wafer test data visualization method specifically includes the following steps:
[0099] S301: Obtain multiple chip defects existing in multiple wafers, and the chip positions where each chip defect is located.
[0100] In this step, after the test equipment determines the number of failed tests corresponding to each test item at each chip position, it can also obtain multiple chip defects existing in multiple wafers and the chip positions where each chip defect is located, so as to subsequently determine the matching degree between the chip defect and the test item, and reflect the degree to which the chip defect is the reason for the failure of the test item.
[0101] It should be noted that the chip defect can be an electrical device parameter that causes failure determined during the Wafer Acceptance Test (WAT for short), or a defect in the process determined by a Yield Enhancement (YE) engineer.
[0102] S302: For each test item, determine the matching degree between the test item and each chip defect according to the number of failed tests of the test item at each chip position and the chip position where each chip defect is located.
[0103] In this step, after the test equipment obtains multiple chip defects existing in multiple wafers and the chip positions where each chip defect is located, for each test item, determine the matching degree between the test item and each chip defect according to the number of failed tests of the test item at each chip position and the chip position where each chip defect is located.
[0104] Specifically, for each chip position, if the number of failed tests of the test item at this chip position is greater than zero, regard this chip position as the first chip position, that is, the chip at the first chip position fails the test for this test item.
[0105] For each chip defect, select the chip position where the chip defect is located from the first chip positions and determine it as the second chip position, that is, the chip at the second chip position fails the test for this test item and there is a chip defect.
[0106] Determine the ratio of the number of second chip positions to the number of first chip positions as the matching data;
[0107] According to the matching data and the preset corresponding relationship between the matching data and the matching degree, determine the matching degree between the chip defect and the test item. The larger the matching data, the larger the matching degree.
[0108] Subsequently, the user can repair the chip defect according to the matching degree to improve the yield.
[0109] The wafer test data visualization method provided in this embodiment determines the matching degree between chip defects and test items based on the chip positions of the chip defects and the number of times of test failures corresponding to each chip position for each test item, enabling the staff to know which test items can be affected by the chip defects and the magnitude of the impact, and then perform targeted repairs.
[0110] The following is an embodiment of the device of the present application, which can be used to execute the method embodiment of the present application. For details not disclosed in the device embodiment of the present application, please refer to the method embodiment of the present application.
[0111] Figure 4 It is a schematic structural diagram of an embodiment of the wafer test data visualization device provided by the present application. As Figure 4 shown, the wafer test data visualization device 40 includes:
[0112] A test module 41, configured to provide a plurality of wafers and perform wafer tests on each of the wafers, where the wafer tests include a plurality of test items performed in sequence;
[0113] A processing module 42, configured to determine the number of test failures at the same chip positions in the plurality of wafers for each of the test items;
[0114] A generation module 43, configured to generate a corresponding wafer test visualization graph for each of the test items according to the number of test failures at each of the chip positions.
[0115] Further, the processing module 42 is specifically configured to:
[0116] For each test item, use the number of identifiers of the test item in the test results at the same chip positions in the plurality of wafers as the number of test failures; the identifier of the test item in the test results is the identifier of the test item with a test failure.
[0117] Further, the generation module 43 is specifically configured to:
[0118] For each of the test items, use the maximum value among the number of test failures at each of the chip positions as the target number of test failures;
[0119] Normalize the number of test failures of the test item at each of the chip positions according to the target number of test failures to obtain the normalized test failure standard data of the test item at each of the chip positions;
[0120] For each of the test items, generate a corresponding wafer test visualization graph according to the normalized test failure standard data of the test item at each of the chip positions.
[0121] Further, the generation module 43 is specifically configured to:
[0122] For each of the test items, determine the color data of the test item at each chip position according to the test failure standard data of the test item at each chip position and the corresponding relationship between the preset test failure standard data and the color data;
[0123] For each of the test items, generate a wafer test visualization graph corresponding to the test item according to the color data of the test item at each chip position.
[0124] Further, the acquisition module 44 is configured to acquire multiple chip defects existing in the multiple wafers and the chip positions where each chip defect is located;
[0125] Further, the processing module 42 is further configured to, for each of the test items, determine the matching degree between the test item and each chip defect according to the number of test failures of the test item at each chip position and the chip positions where each chip defect is located.
[0126] Further, the processing module 42 is further configured to:
[0127] For each of the chip positions, if the number of test failures of the test item at the chip position is greater than zero, use the chip position as the first chip position;
[0128] For each of the chip defects, select the chip position where the chip defect is located from the first chip positions and determine it as the second chip position;
[0129] Determine the ratio of the number of the second chip positions to the number of the first chip positions as the matching data;
[0130] According to the matching data and the corresponding relationship between the preset matching data and the matching degree, determine the matching degree between the test item and each chip defect.
[0131] The wafer test data visualization device provided in this embodiment is used to execute the technical solutions in any of the foregoing method embodiments, and its implementation principle and technical effects are similar, which will not be elaborated here.
[0132] Figure 5 It is a schematic structural diagram of an electronic device provided by this application. As Figure 5 shown, the electronic device 50 includes:
[0133] A processor 51, a memory 52, and a communication interface 53;
[0134] The memory 52 is used to store the executable instructions of the processor 51;
[0135] Among them, the processor 51 is configured to execute the technical solutions in any of the foregoing method embodiments by executing the executable instructions.
[0136] Optionally, the memory 52 can be either independent or integrated with the processor 51.
[0137] Optionally, when the memory 52 is a device independent of the processor 51, the electronic device 50 may further include:
[0138] A bus 54, through which the memory 52 and the communication interface 53 are connected to the processor 51 to complete mutual communication, and the communication interface 53 is used to communicate with other devices.
[0139] Optionally, the communication interface 53 can be specifically implemented by a transceiver. The communication interface is used to implement communication between the database access device and other devices (such as clients, read-write libraries, and read-only libraries). The memory may include a random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.
[0140] The bus 54 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity, only a thick line is used in the figure to represent it, but it does not mean that there is only one bus or one type of bus.
[0141] The foregoing processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
[0142] This electronic device is used to execute the technical solutions in any of the foregoing method embodiments, and its implementation principle and technical effects are similar, which will not be elaborated here.
[0143] The embodiment of the present application also provides a readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the technical solutions provided in any of the foregoing method embodiments are implemented.
[0144] The embodiments of the present application also provide a computer program product, including a computer program, which is used to implement the technical solutions provided in any of the foregoing method embodiments when executed by a processor.
[0145] Those of ordinary skill in the art can understand that all or part of the steps of implementing the foregoing method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the foregoing method embodiments; and the foregoing storage medium includes: various media such as ROM, RAM, magnetic disk, or optical disk that can store program codes.
[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method for visualizing wafer test data, characterized in that, Including: Providing a plurality of wafers, and performing wafer testing on each of the wafers, where the wafer testing includes a plurality of test items performed in sequence; For each of the test items, determining the number of times the test fails at the same chip positions among the plurality of wafers; For each of the test items, generating a corresponding wafer test visualization graph based on the number of times the test fails at each of the chip positions.
2. The method according to claim 1, characterized in that, The step of, for each of the test items, determining the number of times the test fails at the same chip positions among the plurality of wafers includes: For each test item, taking the number of identifications of the test item in the test results at the same chip positions among the plurality of wafers as the number of times the test fails; the identifications of the test item in the test results are the identifications of the test items that fail the test.
3. The method according to claim 1, characterized in that, The step of, for each of the test items, generating a corresponding wafer test visualization graph based on the number of times the test fails at each of the chip positions includes: For each of the test items, taking the maximum value among the number of times the test fails at each of the chip positions as the target number of times the test fails; Normalizing the number of times the test fails at each of the chip positions for the test item according to the target number of times the test fails to obtain the standardized data of the number of times the test fails at each of the chip positions for the test item; For each of the test items, generating a corresponding wafer test visualization graph based on the standardized data of the number of times the test fails at each of the chip positions for the test item.
4. The method according to claim 3, wherein The step of, for each of the test items, generating a corresponding wafer test visualization graph based on the standardized data of the number of times the test fails at each of the chip positions for the test item includes: For each of the test items, determining the color data at each of the chip positions for the test item according to the standardized data of the number of times the test fails at each of the chip positions for the test item and the preset correspondence between the standardized data of the number of times the test fails and the color data; For each of the test items, generating the wafer test visualization graph corresponding to the test item according to the color data at each of the chip positions for the test item.
5. The method according to claim 1, wherein The method further includes: Obtaining a plurality of chip defects existing in the plurality of wafers and the chip positions where each chip defect is located; For each of the test items, determining the matching degree between the test item and each of the chip defects according to the number of times the test fails at each of the chip positions for the test item and the chip positions where each chip defect is located.
6. The method according to claim 5, characterized in that The step of, for each of the test items, determining the matching degree between the test item and each of the chip defects according to the number of times the test fails at each of the chip positions for the test item and the chip positions where each chip defect is located includes: For each of the chip positions, if the number of times the test fails at the chip position for the test item is greater than zero, taking the chip position as the first chip position; For each of the chip defects, selecting the chip position where the chip defect is located from the first chip positions and determining it as the second chip position; Taking the ratio of the number of the second chip positions to the number of the first chip positions as the matching data; Determine the matching degree between the test item and each chip defect according to the matching data and the corresponding relationship between the preset matching data and the matching degree.
7. A wafer test data visualization device, characterized in that, Comprising: A test module, configured to provide a plurality of wafers and perform wafer tests on each of the wafers, where the wafer tests include a plurality of test items performed in sequence; A processing module, configured to determine, for each of the test items, the number of times of failed tests at the same chip position among the plurality of wafers; A generating module, configured to generate a corresponding wafer test visualization graph for each of the test items according to the number of times of failed tests at each chip position.
8. An electronic device, characterized in that, Comprising: A processor, a memory, and a communication interface; The memory is configured to store executable instructions of the processor; Wherein, the processor is configured to execute the wafer test data visualization method according to any one of claims 1 to 6 by executing the executable instructions.
9. A readable storage medium, on which a computer program is stored, characterized in that, When the computer program is executed by the processor, it implements the wafer test data visualization method according to any one of claims 1 to 6.
10. A computer program product, characterized in that, Comprising a computer program, which is used to implement the wafer test data visualization method according to any one of claims 1 to 6 when executed by the processor.