MEMS (Micro Electro Mechanical System) deformable mirror based on double-silicon gold bonding and preparation method thereof

Abstract

The invention provides an MEMS deformable mirror based on double-silicon gold bonding and a preparation method thereof. The MEMS deformable mirror comprises a silicon wafer substrate, a silicon nitride insulating layer, a lower polycrystalline silicon electrode, a first phosphorosilicate glass sacrificial layer, an upper interdigital electrode, a first bonding electrode layer, an SOI wafer structure, a second bonding electrode layer and a gold-based reflecting mirror surface. The preparation method sequentially comprises the steps of silicon wafer substrate pretreatment, silicon nitride insulating layer deposition, lower-layer polycrystalline silicon electrode formation, first phosphorosilicate glass sacrificial layer deposition and thinning, upper-layer interdigital electrode and related structure etching, first bonding electrode layer formation, SOI wafer pretreatment and solution channel formation, second phosphorosilicate glass sacrificial layer filling, high-temperature sintering, high-temperature sintering, high-temperature sintering, high-temperature sintering, high-temperature sintering, high-temperature sintering, high-temperature sintering, high-temperature sintering, high-temperature sintering, high-temperature sintering, high-temperature sintering and high-temperature sintering. The method comprises the following steps: preparing a first bonding electrode layer, forming a second bonding electrode layer, performing gold-gold hot pressing bonding, performing deep silicon etching, performing structure release and annealing treatment, and preparing and packaging a gold-based reflecting mirror surface. The method can simplify the technological process, improves the correction performance of the optical system, and has a wide market application prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of micro-nano processing of deformable mirror structures, and particularly relates to a dual-silicon-gold-bonded MEMS deformable mirror and a preparation method thereof. Background Art

[0002] The manufacturing technology of micro-electro-mechanical system (MEMS) deformable mirrors is a core challenge in the field of adaptive optics, and its performance directly affects the beam wavefront correction accuracy. The traditional process prepares a multi-layer electrode structure through step-by-step deposition and etching methods. The main processes include substrate cleaning, insulating layer deposition, electrode lithography, sacrificial layer release, and reflective mirror coating, etc. However, such a process has the following technical defects: the traditional wet etching process will expose the reflective layer to the etching solution for a long time, resulting in an increase in surface defects and roughness, and an irreversible attenuation of the optical reflection performance; the difference in the thermal expansion coefficients of the electrode material and the reflective layer causes the accumulation of interfacial stress during annealing, increasing the mirror deformation error and affecting the accuracy and stability of the optical system; the single-channel back hole design limits the diffusion of the etching solution, resulting in uneven sacrificial layer release and easy adhesion of the movable structure, reducing the device yield; preparing a multi-layer electrode structure requires multiple photolithography mask alignments, with complex processes and low fault tolerance, restricting the mass production efficiency and cost control.

[0003] Although existing improvement schemes, by optimizing the etching solution formula, introducing a porous backplane design, or adopting a low-temperature bonding process, can to some extent help alleviate the problem of structural adhesion or reduce the influence of thermal stress, there are still the following limitations: for example, although the porous backplane design can improve the diffusion efficiency of the etching solution, the complex micro-hole processing technology greatly increases the manufacturing cost and easily leads to a decrease in mechanical strength; although the low-temperature bonding technology can reduce the accumulation of thermal stress, its bonding strength is insufficient and it is difficult to meet the strict requirements of high-precision devices for interface stability; in addition, the post-treatment protection measures for the reflective mirror in the existing process are still imperfect, and it is impossible to completely avoid the secondary pollution of the mirror surface finish by etching residues. Summary of the Invention

[0004] Object of the Invention: The technical problem to be solved by the present invention is to provide a dual-silicon-gold-bonded MEMS deformable mirror and a preparation method thereof in view of the deficiencies of the prior art. Through the gold-to-gold bonding technology, the collaborative design of the V-shaped solution channel and the double-sided alignment mark, and the post-processing of the mirror, the high-precision and high-stability device can be mass-produced efficiently, and the correction performance of the optical system can be improved.

[0005] The present invention first provides a dual-silicon-gold-bonded MEMS deformable mirror, including a silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphosilicate glass sacrificial layer, an in-situ doped polysilicon layer, a first bonding electrode layer, an SOI wafer structure, a second bonding electrode layer, and a gold-based reflective mirror surface; On the silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphosilicate glass sacrificial layer, and an in-situ doped polysilicon layer are sequentially arranged from near to far; An upper interdigital electrode, a stress relief hole, and a solution diversion trench are etched on the in-situ doped polysilicon layer; The first bonding electrode layer is arranged on the upper interdigital electrode; The SOI wafer structure is arranged on the first bonding electrode layer; The top silicon of the SOI wafer structure is etched and patterned to form a solution channel; The second bonding electrode layer is arranged on the top silicon of the SOI wafer structure; The first bonding electrode layer and the second bonding electrode layer perform gold-to-gold bonding to complete the double-sided silicon wafer connection; After the SOI wafer structure undergoes deep silicon etching and structure release, a mirror support layer is formed on the back of the top silicon of the SOI wafer structure; The gold-based reflective mirror is arranged on the mirror support layer.

[0006] The depth of the trapezoidal alignment mark on the back of the silicon wafer substrate is 3 - 5 μm. This depth range ensures sufficient visibility of the alignment mark in subsequent process steps, while avoiding excessive weakening of the mechanical strength of the silicon wafer, and guaranteeing the accuracy and reliability of subsequent bonding.

[0007] The thickness of the silicon nitride insulating layer is 500 - 600 nm. This thickness range ensures good insulation performance between the lower polysilicon electrode and the silicon wafer substrate, while effectively buffering the stress caused by the difference in thermal expansion coefficients and reducing the mirror deformation error.

[0008] The thickness of the lower polysilicon electrode is 450 - 550 nm, and the line width accuracy is ±0.1 - 0.2 μm. This thickness range combined with the line width accuracy requirement can ensure the performance stability of the electrode in high-frequency signal transmission, while adapting to the accuracy limitations of micro-nano processing technology.

[0009] The thickness of the first phosphosilicate glass sacrificial layer is 2 - 3 μm. This thickness range balances the diffusion efficiency of the etching solution and the uniformity of structure release, while avoiding excessive increase in the vertical size of the device.

[0010] The thickness of the in-situ doped polysilicon layer is 2.5 - 3.5 μm, the stress relief holes are arranged in an array, the aperture of the stress relief holes is 1.5 - 2.5 μm, the spacing is 4 - 6 μm, and the width of the solution diversion trench is 2 - 5 μm. The thickness of the polysilicon layer ensures the mechanical strength and conductivity of the electrode; the size and spacing of the stress relief holes are designed to optimize the local stress distribution and reduce structural deformation; the width of the solution diversion trench affects the flow efficiency and release uniformity of the etching solution.

[0011] The thicknesses of both the first bonding electrode layer and the second bonding electrode layer are 500 - 600 nm. This thickness range reduces the risk of interface defects caused by uneven thickness while ensuring good electrical conductivity and bonding strength.

[0012] The solution channel has a V-shaped structure with a depth-to-width ratio of 8:1 - 12:1 and sidewall angles of 50° - 60°. This design of the depth-to-width ratio and sidewall angles significantly improves the diffusion efficiency of the etching solution, reduces the release time, optimizes the freedom of movement of the movable structure, and reduces the risk of adhesion.

[0013] The present invention also provides a method for manufacturing the above-mentioned MEMS deformable mirror based on dual silicon-gold bonding, comprising the following steps: Step 1: Clean a 4-inch or 6-inch n-type double-sided polished silicon wafer substrate with a thickness of 675 μm using an RCA standard cleaning solution, and etch alignment marks on the back of the silicon wafer substrate using a deep reactive ion etching process. Step 2: Deposit a silicon nitride insulating layer on the front of the silicon wafer substrate using a low-pressure chemical vapor deposition process, and control the stress to be less than 100 Mpa. Step 3: Deposit a polysilicon layer on the front of the silicon nitride insulating layer using a plasma-enhanced chemical vapor deposition process, and form a lower polysilicon electrode after thinning and ion implantation and patterning. Step 4: Deposit a first phosphosilicate glass sacrificial layer on the front of the lower polysilicon electrode using a plasma-enhanced chemical vapor deposition process and perform a thinning treatment. Step 5: Deposit an in-situ doped polysilicon layer on the front of the first phosphosilicate glass sacrificial layer using a low-pressure chemical vapor deposition process, and synchronously etch after thinning to form an upper interdigitated electrode, an array of stress release holes, and a solution diversion trench. Step 6: Magnetron sputter a gold layer on the front of the upper interdigitated electrode, align it with the alignment marks etched on the back of the silicon wafer substrate in Step 1, and complete double-layer overlay etching to form a first bonding electrode layer. Step 7: Ultrasonically clean the SOI wafer structure, etch the back of the bottom silicon of the SOI wafer structure using a deep reactive ion etching process to form alignment marks, and etch and pattern the top silicon surface of the SOI wafer structure to form a solution channel. Step 8: Deposit a second phosphosilicate glass sacrificial layer on the front of the top silicon of the SOI wafer structure using a plasma-enhanced chemical vapor deposition process, selectively remove the excess phosphosilicate glass material (usually selected manually), and only retain the solution channel area for filling. Step 9: Magnetron sputter a gold layer on the front of the top silicon of the SOI wafer structure, align it with the alignment marks etched on the back of the bottom silicon of the SOI wafer structure in Step 7, and complete double-layer overlay etching to form a second bonding electrode layer. Step 10, the first bonding electrode layer and the second bonding electrode layer perform Au-Au thermocompression bonding to complete the mechanical and electrical connection of the double-sided silicon wafer; Step 11, according to the alignment mark positions formed on the back of the bottom silicon of the SOI wafer structure in Step 7, using deep silicon etching process, etch the bottom silicon of the SOI wafer structure to its buried oxide layer (here, "its" refers to the SOI wafer structure, which has three layers: bottom silicon, buried oxide layer, and top silicon); Step 12, remove the first phosphosilicate glass sacrificial layer, the second phosphosilicate glass sacrificial layer and the buried oxide layer of the SOI wafer structure to complete the structure release, and complete the annealing treatment in an inert gas environment to form ohmic contacts between the first bonding electrode layer, the second bonding electrode layer and silicon; Step 13, sputter and pattern a gold layer on the back of the top silicon of the SOI wafer structure to form a gold-based reflecting mirror surface, and perform vacuum bonding and encapsulation; In Step 8, the thickness of the second phosphosilicate glass sacrificial layer is 1 - 1.5 μm; the thinner second phosphosilicate glass sacrificial layer helps to reduce the etching time and chemical residues, while maintaining sufficient structural support.

[0014] In Step 11, the deep silicon etching includes an etching stage and a passivation stage. In the etching stage, SF6 gas with a flow rate of 200 sccm and a radio frequency power of 800 W is used. In the passivation stage, it is switched to C4F8 gas with a flow rate of 100 sccm and a power of 600 W, and the Bosch process is realized by cyclic alternation. The etching rate reaches 8 μm / min. During the deep silicon etching process, the thickness of the silicon layer is monitored in real time by a laser interferometer. When etching to the buried oxide layer of the SOI wafer structure, the reflectivity changes suddenly, and the etching is terminated.

[0015] The core innovation of the present invention is mainly reflected in the systematic reconstruction of the traditional process flow through the collaborative optimization of the introduction of Au-Au bonding technology and the reflector postposition process. Specifically, the collaborative design of the double-sided alignment marks and the V-shaped high aspect ratio solution channels significantly improves the diffusion uniformity of the etching solution and completely solves the problem of structure adhesion; the reflecting mirror surface is prepared by a post-sputtering process, avoiding direct damage to the mirror surface quality by the etching solution, reducing the surface roughness (Ra) to the sub-nanometer level, and significantly improving the optical performance. At the same time, the application of Au-Au bonding technology not only simplifies the alignment steps of multi-layer electrodes, but also its high-strength bonding interface greatly enhances the mechanical stability of the device, effectively suppressing the deformation and interface failure caused by thermal stress, providing a reliable technical path for the high-volume production of high-precision MEMS deformable mirrors.

[0016] Beneficial effects: 1. Through the reflector post-sputtering process, direct contact between the etching solution and the mirror surface is avoided, reducing the surface roughness Ra to the sub-nanometer level, specifically less than 1 nm, and increasing the optical reflectivity by more than 15%, significantly enhancing the beam wavefront correction accuracy; 2. The high-strength bonding interface of the gold-to-gold bonding technology has a shear strength of not less than 50 Mpa, combined with excellent thermal matching, reducing the accumulation of interface stress caused by differences in thermal expansion coefficients during the annealing process, controlling the mirror deformation error within plus or minus 0.1 μm, and enhancing the long-term stability of the optical system; 3. Adopting a V-shaped high aspect ratio solution channel with an aspect ratio of 8:1 to 12:1, combined with a double-sided alignment mark design, the etching solution diffusion efficiency is increased by 40%, the sacrificial layer release time is shortened to one-third of the traditional process, completely eliminating the problem of movable structure adhesion, and the yield rate is increased to over 95%; 4. Through gold-to-gold bonding, the mechanical and electrical synchronous connection of double-sided silicon wafers is achieved. The number of alignment times for multi-layer electrode overlay etching is reduced from the traditional 5 times to 2 times, the process steps are reduced by 20%, and the mass production efficiency is increased by more than 30%; 5. By precisely controlling the thickness of the first phosphosilicate glass sacrificial layer to be 2 - 3 μm and the second layer to be 1 - 1.5 μm, and adopting a Bosch deep silicon etching process with an etching rate of 8 μm / min and a termination accuracy of ±0.5 μm, the integrity and uniformity of the micromirror support layer and electrode structure are ensured, and the device life is extended to more than 100,000 cycles. Description of the Drawings

[0017] Figure 1 It is a schematic structural diagram of a MEMS deformable mirror.

[0018] Figure 2 It is a schematic structural diagram of the silicon wafer substrate pretreatment in Step 1.

[0019] Figure 3 It is a schematic structural diagram of the silicon nitride insulating layer in Step 2.

[0020] Figure 4 It is a schematic structural diagram of the lower polysilicon electrode in Step 3.

[0021] Figure 5 It is a schematic structural diagram of the treatment of the first phosphosilicate glass sacrificial layer in Step 4..

[0022] Figure 6 It is a schematic structural diagram of the upper interdigital electrode in Step 5.

[0023] Figure 7 It is a schematic structural diagram of the first bonding electrode layer in Step 6.

[0024] Figure 8 It is a schematic structural diagram of the pretreatment of the SOI wafer structure and the solution channel structure in Step 7.

[0025] Figure 9 It is a schematic structural diagram of the treatment of the second phosphosilicate glass sacrificial layer in Step 8.

[0026] Figure 10Schematic diagram of the second bonding electrode layer structure for Step 9.

[0027] Figure 11 Schematic diagram of the Au-Au thermocompression bonding structure of the double-sided silicon wafer for Step 10.

[0028] Figure 12 Schematic diagram of the deep silicon etching process structure for Step 11.

[0029] Figure 13 Schematic diagram of the structure release and annealing treatment for Step 12.

[0030] Explanation of reference numerals: 1 is the silicon wafer substrate; 2 is the silicon nitride insulating layer; 3 is the lower polysilicon electrode; 4 is the first phosphosilicate glass sacrificial layer; 5 is the upper interdigital electrode; 6 is the first bonding electrode layer; 7 is the SOI wafer structure; 8 is the second phosphosilicate glass sacrificial layer; 9 is the second bonding electrode layer; 10 is the Au-based reflecting mirror surface. Detailed implementation manners

[0031] The following further specifically describes the present invention in conjunction with the accompanying drawings and specific implementation manners, and the above and / or other advantages of the present invention will become clearer.

[0032] Combined with Figure 1 As shown in The embodiments of the present invention provide a double-silicon-gold-bonded MEMS deformable mirror, including: a silicon wafer substrate 1, a silicon nitride insulating layer 2 provided on the silicon wafer substrate 1, a lower polysilicon electrode 3 provided on the silicon nitride insulating layer 2, a first phosphosilicate glass sacrificial layer 4 provided on the lower polysilicon electrode 3, an in-situ doped polysilicon layer provided on the first phosphosilicate glass sacrificial layer 4, an upper interdigital electrode 5, stress release holes and solution diversion grooves etched on the in-situ doped polysilicon layer, a first bonding electrode layer 6 provided on the upper interdigital electrode 5, an SOI wafer structure 7 provided on the first bonding electrode layer, a solution channel formed after etching and patterning the top silicon of the SOI wafer structure 7, a second bonding electrode layer 9 provided on the top silicon of the SOI wafer structure 7, the first bonding electrode layer 6 and the second bonding electrode layer 9 perform Au-Au bonding to complete the connection of the double-sided silicon wafer. After the SOI wafer structure 7 undergoes deep silicon etching and structure release, a mirror support layer is formed on the back of its top silicon, and an Au-based reflecting mirror surface 10 provided on the mirror support layer.

[0033] The depth of the trapezoidal alignment mark on the back of the silicon wafer substrate is 3 - 5 μm.

[0034] The thickness of the silicon nitride insulating layer is 500 - 600 nm.

[0035] The thickness of the lower polysilicon electrode is 450 - 550 nm, and the line width accuracy is ±0.1 - 0.2 μm.

[0036] Furthermore, the thickness of the first phosphosilicate glass sacrificial layer is 2 - 3 μm.

[0037] The thickness of the in-situ boron-doped polysilicon layer is 2.5 - 3.5 μm, the aperture of the arrayed stress relief holes is 1.5 - 2.5 μm, the spacing is 4 - 6 μm, and the width of the solution diversion grooves is 2 - 5 μm.

[0038] The thicknesses of both the first bonding electrode layer and the second bonding electrode layer are 500 - 600 nm.

[0039] The solution channel on the top silicon of the SOI wafer structure is in a V-shaped structure, with an aspect ratio of 8:1 - 12:1 and a sidewall angle of 50 - 60°.

[0040] In the second embodiment of the present invention, a preparation method of a dual-silicon-gold-bonded MEMS deformable mirror is provided, including the following steps: Combined with Figure 2 , step 1, perform RCA standard cleaning on the silicon wafer substrate 1, and use SC-1 and SC-2 solutions to remove surface organic contaminants and metal ions. Subsequently, on the back of the silicon wafer substrate 1, adopt a deep reactive ion etching process with a mixed gas of SF6 and C4F8, a flow ratio of 3:1, etch to form a trapezoidal alignment mark with a depth of 3 - 5 μm, a sidewall angle of 80°, and an etching rate of 3 μm / min.

[0041] Combined with Figure 3 , step 2, deposit a silicon nitride insulating layer 2 on the front of the silicon wafer substrate 1 by low-pressure chemical vapor deposition. The reaction gases are SiH2Cl2 and NH3, with a flow ratio of 1:2, a deposition temperature of 780 °C, and a thickness of 500 - 600 nm. By adjusting the gas flow ratio, control the compressive stress of the silicon nitride layer at 80 MPa, and monitor the stress distribution in real time through a laser interferometer.

[0042] Combined with Figure 4 , step 3, deposit a polysilicon layer on the silicon nitride insulating layer 2 by plasma-enhanced chemical vapor deposition, with a thickness of 500 - 600 nm, and thin it to 450 - 550 nm by chemical mechanical polishing. Subsequently, inject boron ions with a dose of 1×10¹ 5 cm⁻² and an energy of 30 keV, and form a lower polysilicon electrode layer 3 with a line width accuracy of ±0.1 - 0.2 μm by dry etching with Cl2 and HBr.

[0043] Combined with Figure 5 , step 4, deposit a first phosphosilicate glass sacrificial layer 4 on the front of the lower polysilicon electrode layer 3 by plasma-enhanced chemical vapor deposition, with a thickness of 2 - 3 μm, and the gas components are SiH4, O2, and PH3 with a volume ratio of 1:3:0.1. Polish it by chemical mechanical polishing to a surface roughness of less than 5 nm to ensure the flatness between subsequent layers.

[0044] Combined with Figure 6 , step 5, deposit an in-situ boron-doped polysilicon layer on the front of the first phosphosilicate glass sacrificial layer 4 by low-pressure chemical vapor deposition, with a thickness of 2.5 - 3.5 μm and a doping concentration of 1×10² 0 cm⁻³, and simultaneously etch to form the upper interdigitated electrode 5, arrayed stress relief holes with a pore diameter of 1.5 - 2.5 μm and a pitch of 4 - 6 μm, and solution diversion trenches with a width of 2 - 5 μm. The etching uses Bosch process, and the sidewall perpendicularity deviation is less than 1°.

[0045] Combined with Figure 7 , step 6, sputter a gold layer on the surface of the upper interdigitated electrode 5 by magnetron sputtering. The sputtering parameters are an Ar gas flow rate of 20 sccm, a power of 300 W, and a substrate temperature of 200 °C, and the coating thickness is 500 - 600 nm. Use an infrared aligner to achieve double-sided alignment, and the overlay error is less than 0.4 μm to form the first bonding electrode layer 6.

[0046] Combined with Figure 8 , step 7, ultrasonically clean the SOI wafer structure 7, and use a mixed solvent of acetone and isopropyl alcohol to thoroughly remove surface particle contaminants; then etch alignment marks with a depth of 3 - 5 μm on the back of the bottom silicon of the SOI wafer structure 7 by deep reactive ion etching process. The etching gas is a fluorine-based mixed gas, and the sidewall steepness is controlled at 88° ± 2°; then perform deep reactive ion etching on the top silicon to process a V-shaped solution channel with an aspect ratio of 8:1 - 12:1, a sidewall angle of 50° - 60°, and a channel depth of 50 μm; after etching, introduce O2 plasma to remove the residual photoresist and clean the surface to ensure that the channel structure is pollution-free.

[0047] Combined with Figure 9 , step 8, deposit a second phosphosilicate glass sacrificial layer 8 on the surface of the top silicon of the SOI wafer structure 7 by plasma-enhanced chemical vapor deposition, with a thickness of 1 - 1.5 μm. Retain the solution channel area through a photomask, and wet-etch the remaining area with a solution with a volume ratio of HF to H2O of 1:10. The second phosphosilicate glass sacrificial layer 8 has a thickness of 1 - 1.5 μm and is used to fill the solution channel.

[0048] Combined with Figure 10 , step 9, magnetron sputter a gold layer on the surface of the top silicon of the SOI wafer structure 7, with the same parameters as in step 6, and the overlay alignment accuracy is less than 0.5 μm to form the second bonding electrode layer 9.

[0049] Combined with Figure 11, Step 10, thermally compressively bond the first bonding electrode layer 6 and the second bonding electrode layer 9 at 300 °C and a pressure of 10 MPa for 30 minutes. Before bonding, perform Ar plasma pre-cleaning. After bonding, ultrasonic scanning is used to detect that the void ratio is less than 0.8%.

[0050] Bond Figure 12 , Step 11, according to the alignment mark positions formed on the back of the bottom silicon of the SOI wafer structure 7 in Step 7, etch the bottom silicon of the SOI wafer structure 7 using the Bosch process. In the etching stage, use SF6 gas with a flow rate of 200 sccm and a power of 800 W. In the passivation stage, switch to C4F8 gas with a flow rate of 100 sccm and a power of 600 W. The etching rate is 8 μm / min. The thickness is monitored in real time by a laser interferometer and the etching is terminated when reaching the buried oxide layer with an accuracy of ±0.5 μm.

[0051] Bond Figure 13 , Step 12, remove the first phosphosilicate glass sacrificial layer 4 and the second phosphosilicate glass sacrificial layer 8 successively with 49% HF solution, and remove the buried oxide layer with BOE solution. Subsequently, anneal in an N2 environment at 450 °C for 1 hour to form an ohmic contact with a contact resistance of 0.8 Ω·cm².

[0052] Sputter a gold plating layer on the back of the top silicon of the SOI wafer structure 7 with a thickness of 500 nm, and form a gold-based reflective mirror surface 10 by photolithographic patterning. Finally, perform vacuum bonding with a glass cover plate, with a vacuum degree less than 1×10⁻³ Pa, a temperature of 200 °C, and a pressure of 5 MPa to complete the hermetic packaging.

[0053] The embodiment of the present invention also provides another preparation method of a MEMS deformable mirror based on dual silicon-gold bonding, which is different from the second embodiment in that: (1) Substrate optimization: Use an 8-inch SOI wafer structure to replace a 6-inch silicon wafer, adjust the thickness of the top silicon of the SOI to 10 - 15 μm, and the thickness of the buried oxide layer to 1 - 2 μm; (2) Bonding process improvement: The temperature of the gold-to-gold thermocompression bonding is increased to 350 - 400 °C, the pressure is increased to 15 - 20 MPa, the bonding time is shortened to 15 - 20 minutes, the thickness of the bonding layer is controlled to 800 - 1000 nm, and the shear strength is increased to more than 70 MPa; (3) Solution channel design: The depth-to-width ratio of the V-shaped solution channel is adjusted to 10:1 - 15:1, the sidewall angle is optimized to 55° - 65°, and the etching rate is increased to 10 μm / min; (4) Sacrificial layer material adjustment: The second phosphosilicate glass sacrificial layer adopts a boron-phosphorus co-doping process, with a boron doping concentration of 2 - 4 wt% and a phosphorus doping concentration of 6 - 8 wt%, and the etching uniformity is improved to within ±3%.

[0054] The embodiment of the present invention also provides another preparation method of a MEMS deformable mirror based on dual silicon-gold bonding, which is different from the second embodiment in that: (1) Electrode structure innovation: The first bonding electrode layer adopts an Au / TiW composite structure, the thickness of the TiW transition layer is 50 - 80 nm, the surface roughness Ra < 0.5 nm, and the interfacial adhesion is increased by 30%; (2) Flow guiding groove optimization: The solution flow guiding groove introduces a bionic spiral fractal design, the main groove width is 4 - 8 μm, the branch groove width is 1 - 3 μm, and the fractal iteration times are 3 - 5 times, and the flow guiding efficiency is increased by 50%; (3) Etching monitoring technology: In step 11, in-situ X-ray diffraction technology is used to monitor the deep silicon etching depth in real time, and the termination accuracy reaches ±0.2 μm; (4) Reflective layer composite process: The gold-based reflective mirror surface adopts an Au / Ag / NiCr three-layer gradient coating, the reflectivity in the visible light band is > 99.8%, the thermal stability is increased to 600 °C, and the surface roughness RMS is further reduced to 0.1 - 0.2 nm.

[0055] The present invention provides a MEMS deformable mirror based on dual silicon-gold bonding and its preparation method. There are many specific methods and ways to implement this technical solution. The above is only the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention. Each component not clearly defined in this embodiment can be realized by existing technologies.

Claims

1. A dual-silicon-gold-bonded MEMS deformable mirror, characterized in that, It includes a silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphosilicate glass sacrificial layer, an in-situ doped polysilicon layer, a first bonding electrode layer, an SOI wafer structure, a second bonding electrode layer, and a gold-based reflective mirror surface; On the silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphosilicate glass sacrificial layer, and an in-situ doped polysilicon layer are sequentially arranged from near to far; An upper interdigital electrode, a stress relief hole, and a solution diversion trench are etched and formed on the in-situ doped polysilicon layer; The first bonding electrode layer is disposed on the upper interdigital electrode; The SOI wafer structure is disposed on the first bonding electrode layer; The top silicon of the SOI wafer structure is etched and patterned to form a solution channel; The second bonding electrode layer is disposed on the top silicon of the SOI wafer structure; The first bonding electrode layer and the second bonding electrode layer perform gold-to-gold bonding to complete the double-sided silicon wafer connection; After the SOI wafer structure undergoes deep silicon etching and structure release, a mirror support layer is formed on the back surface of the top silicon of the SOI wafer structure; The gold-based reflective mirror surface is disposed on the mirror support layer.

2. The deformable mirror based on dual-silicon-gold bonding MEMS according to claim 1, wherein The depth of the trapezoidal alignment mark on the back surface of the silicon wafer substrate is 3 - 5 μm.

3. A dual-silicon-gold-bonded MEMS deformable mirror according to claim 1, characterized in that, The thickness of the silicon nitride insulating layer is 500 - 600 nm.

4. A dual-silicon-gold-bonded MEMS deformable mirror according to claim 1, characterized in that, The thickness of the lower polysilicon electrode is 450 - 550 nm, and the line width accuracy is ±0.1 - 0.2 μm.

5. A dual-silicon-gold-bonded MEMS deformable mirror according to claim 1, characterized in that, The thickness of the first phosphosilicate glass sacrificial layer is 2 - 3 μm.

6. The deformable mirror based on double-silicon-gold bonding MEMS according to claim 1, characterized in that, The thickness of the in-situ doped polysilicon layer is 2.5 - 3.5 μm. The stress relief holes are arranged in an array, the aperture of the stress relief holes is 1.5 - 2.5 μm, the spacing is 4 - 6 μm, and the width of the solution diversion trench is 2 - 5 μm.

7. A kind of MEMS deformable mirror based on double silicon-gold bonding according to claim 1, characterized in that, The thicknesses of both the first bonding electrode layer and the second bonding electrode layer are 500 - 600 nm.

8. A deformable mirror based on dual-silicon-gold bonding MEMS according to claim 1, characterized in that The solution channel has a V-shaped structure, the depth-to-width ratio is 8:1 - 12:1, and the sidewall angle is 50° - 60°.

9. A preparation method of a dual-silicon-gold-bonded MEMS deformable mirror according to any one of claims 1 to 8, characterized in that, It includes the following steps: Step 1: Clean a 4-inch or 6-inch n-type double-sided polished silicon wafer substrate with a thickness of 675 μm using an RCA standard cleaning solution, and etch alignment marks on the back surface of the silicon wafer substrate using a deep reactive ion etching process; Step 2: Deposit a silicon nitride insulating layer on the front surface of the silicon wafer substrate using a low-pressure chemical vapor deposition process, and control the stress to be less than 100 Mpa; Step 3: Deposit a polysilicon layer on the front surface of the silicon nitride insulating layer using a plasma-enhanced chemical vapor deposition process, and pattern it into a lower polysilicon electrode after thinning and ion implantation; Step 4: Deposit a first phosphosilicate glass sacrificial layer on the front surface of the lower polysilicon electrode using a plasma-enhanced chemical vapor deposition process and perform a thinning treatment; Step 5: Deposit an in-situ doped polysilicon layer on the front surface of the first phosphosilicate glass sacrificial layer using a low-pressure chemical vapor deposition process, and synchronously etch it after thinning to form an upper interdigital electrode, an array of stress relief holes, and a solution diversion trench; Step 6: Magnetron sputter a gold layer on the front surface of the upper interdigital electrode, align it with the alignment marks etched on the back surface of the silicon wafer substrate in Step 1, and complete double-layer overlay etching to form a first bonding electrode layer; Step 7, ultrasonically clean the SOI wafer structure, etch the backside of the bottom silicon layer of the SOI wafer structure using deep reactive ion etching process to form alignment marks, etch and pattern the top silicon surface of the SOI wafer structure to form solution channels; Step 8, deposit a second phosphosilicate glass sacrificial layer on the front side of the top silicon layer of the SOI wafer structure using plasma enhanced chemical vapor deposition process, selectively remove the excess phosphosilicate glass material, and only retain the solution channel area for filling; Step 9, magnetron sputter a gold layer on the front side of the top silicon layer of the SOI wafer structure, align with the alignment marks etched on the backside of the bottom silicon layer of the SOI wafer structure in Step 7 and complete double patterning to form the second bonding electrode layer; Step 10, perform Au-Au thermocompression bonding on the first bonding electrode layer and the second bonding electrode layer to complete the mechanical and electrical connection of the double-sided silicon wafer; Step 11, according to the position of the alignment marks formed on the backside of the bottom silicon layer of the SOI wafer structure in Step 7, use deep silicon etching process to etch the bottom silicon layer of the SOI wafer structure to its buried oxide layer; Step 12, remove the first phosphosilicate glass sacrificial layer, the second phosphosilicate glass sacrificial layer and the buried oxide layer of the SOI wafer structure to complete structure release, and complete annealing treatment in an inert gas environment to form ohmic contacts between the first bonding electrode layer and the second bonding electrode layer and silicon; Step 13, sputter a gold layer on the backside of the top silicon layer of the SOI wafer structure and pattern it to form a gold-based reflective mirror surface, and perform vacuum bonding and encapsulation.

10. The method according to claim 9, wherein In Step 8, the thickness of the second phosphosilicate glass sacrificial layer is 1 - 1.5 μm; In Step 11, the deep silicon etching includes an etching stage and a passivation stage. In the etching stage, SF6 gas with a flow rate of 200 sccm and a radio frequency power of 800 W is used. In the passivation stage, it is switched to C4F8 gas with a flow rate of 100 sccm and a power of 600 W. The Bosch process is realized by cyclic alternation, and the etching rate reaches 8 μm / min. During the deep silicon etching process, the thickness of the silicon layer is monitored in real time by a laser interferometer. When etching reaches the buried oxide layer of the SOI wafer structure, the reflectivity changes abruptly and the etching is terminated.

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