Display panel and display terminal

Abstract

The invention relates to a display panel and a display terminal. The display panel comprises a substrate, a first metal layer, a second metal layer and a pixel electrode layer, wherein the first metal layer comprises a scanning line extending along a first direction; the second metal layer comprises a data line and a shared electrode line which extend along a second direction; the pixel electrode layer comprises a plurality of pixel electrodes; the display panel comprises a plurality of sub-pixels, each sub-pixel comprises a main pixel area and a sub-pixel area, each sub-pixel at least comprises a first transistor, a second transistor, a third transistor and a fourth transistor, a first source, a second source and a third source are connected, and a second drain is connected with a third drain. When the channel size of the second transistor is changed due to reduction of patterning precision, current can be input to the pixel electrode corresponding to the sub-pixel region through the channel of the second transistor and the channel of the third transistor at the same time, so that the influence of fluctuation of the channel width of the transistor corresponding to the sub-pixel region on the pixel voltage is reduced; and uneven display caused by voltage fluctuation of the pixel electrode is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0002] With the rapid development of technology, future application scenarios are rapidly moving toward "ubiquitous displays." Display products are no longer limited to traditional televisions and computer screens but are increasingly permeating every corner of our lives. From the micro-displays of smart wearable devices to the screens of smart appliances in the home, to ubiquitous electronic billboards in public areas, display technology has become a critical bridge connecting people and information. As a mature and widely used display technology, LCD panels hold a significant position in the large-size display market, enjoying a substantial market share.

[0003] The display panel includes a multi-layer film layer stacked together, and the multi-layer film layer is produced by a patterning process. The patterning process includes steps such as coating photoresist, exposure and development, and etching. Among them, exposure and development are mainly carried out using exposure equipment. In order to improve production efficiency, multiple small display panels are usually made on a display motherboard, and then the display motherboard is cut into multiple display panels. Since the size of the display motherboard exceeds the limit of the exposure equipment, multiple splicing exposures are usually used to achieve exposure and development of the same display motherboard. Multiple splicing exposures will lead to a decrease in the accuracy of the patterning process, resulting in electrical deviation of the thin film transistor, causing display unevenness (Mura), and affecting the display effect of the display panel.

[0004] Therefore, it is urgent to solve the above technical problems. Summary of the Invention

[0005] Embodiments of the present application provide a display panel and a display terminal to improve the technical problem of uneven display caused by decreased precision of the patterning process of the display panel due to splicing exposure, resulting in electrical deviation of thin film transistors.

[0006] In order to achieve the above-mentioned objective, according to a first aspect of the present application, a display panel is provided, comprising:

[0007] substrate;

[0008] a first metal layer disposed on one side of the substrate, the first metal layer comprising a scanning line extending along a first direction;

[0009] a second metal layer, disposed on a side of the first metal layer facing away from the substrate, the second metal layer comprising data lines and shared electrode lines both extending along a second direction;

[0010] a pixel electrode layer, disposed on a side of the second metal layer facing away from the substrate, the pixel electrode layer comprising a plurality of pixel electrodes;

[0011] Among them, the display panel includes a plurality of sub-pixels. The sub-pixels include a main pixel region and a sub-pixel region. The scanning line is disposed between the main pixel region and the sub-pixel region. The sub-pixel includes at least a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first source electrode and a first drain electrode disposed on the second metal layer. The second transistor includes a second source electrode and a second drain electrode disposed on the second metal layer. The third transistor includes a third source electrode and a third drain electrode disposed on the second metal layer. The fourth transistor includes a fourth source electrode and a fourth drain electrode disposed on the second metal layer. The first source electrode is connected to the data line. The first drain electrode is connected to the pixel electrode corresponding to the main pixel region. The fourth drain electrode is connected to the shared electrode line. The first source electrode, the second source electrode, and the third source electrode are connected. The second drain electrode is connected to the third drain electrode, and the third drain electrode is connected to the pixel electrode corresponding to the sub-pixel region.

[0012] Optionally, the display panel further includes:

[0013] A semiconductor layer disposed between the first metal layer and the second metal layer. The semiconductor layer includes an active portion corresponding to each transistor.

[0014] Among them, the sum of the channel widths of the active portions of the second transistor and the third transistor is greater than or equal to twice the channel width of the active portion of the fourth transistor.

[0015] Optionally, the first transistor, the second transistor, the third transistor, and the fourth transistor are arranged in sequence along the first direction. ;

[0016] Optionally, both the first transistor and the second transistor are U-shaped thin-film transistors, and both the third transistor and the fourth transistor are I-shaped thin-film transistors.

[0017] Optionally, the opening directions of the first source electrode and the second source electrode are the same.

[0018] Optionally, the fourth transistor includes an auxiliary electrode disposed on the second metal layer. The auxiliary electrode is disposed between the fourth source electrode and the fourth drain electrode, and the auxiliary electrode is spaced apart from both the fourth source electrode and the fourth drain electrode. The orthographic projection of the active portion of the fourth transistor on the substrate surrounds the orthographic projection of the auxiliary electrode on the substrate.

[0019] Optionally, the fourth source electrode and the fourth drain electrode are arranged along the first direction.

[0020] Optionally, the first drain and the pixel electrode corresponding to the main pixel region are electrically connected through a first via, the second drain and the pixel electrode corresponding to the sub-pixel region are electrically connected through a second via, and the first via and the second via are arranged along the first direction.

[0021] Optionally, the display panel includes a common electrode portion extending along the first direction, and the shared electrode line is electrically connected to the common electrode portion through a third via.

[0022] Optionally, the display panel includes a common electrode portion extending along the first direction, and the shared electrode line is insulated from the common electrode portion.

[0023] Optionally, the pixel electrode includes a main electrode extending along the second direction, and the shared electrode line overlaps with the main electrode.

[0024] According to a second aspect of the present application, there is provided a display terminal including the above-mentioned display panel.

[0025] In the display panel of the embodiments of the present application, by connecting the second source electrode and the third source electrode, and connecting the second drain electrode and the third drain electrode, when the channel size of the second transistor changes due to a decrease in patterning accuracy, the current can be input to the pixel electrode corresponding to the sub-pixel region through the channels of the second transistor and the third transistor at the same time, thereby reducing the influence of the fluctuation of the channel width of the transistor corresponding to the sub-pixel region on the pixel voltage, and improving the display unevenness caused by the voltage fluctuation of the pixel electrode.

[0026] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application, and those skilled in the art can obtain other drawings without creative efforts based on these drawings.

[0028] In order to more fully understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.

[0029] Figure 1 is a top view structural schematic diagram of a display panel provided in an exemplary embodiment of the present disclosure;

[0030] Figure 2A is Figure 1 an enlarged structural schematic diagram of a sub-pixel in

[0031] Figure 2B is Figure 1 a schematic cross-sectional structure diagram of a display panel;

[0032] Figure 3A is Figure 2A a schematic structure diagram of a partial film layer of a sub-pixel in;

[0033] Figure 3B is Figure 3A a schematic enlarged structure diagram at position B in;

[0034] Figure 3C is Figure 3A another schematic enlarged structure diagram at position B in;

[0035] Figure 4 is Figure 1 another schematic enlarged structure diagram of a sub-pixel in;

[0036] Figure 5 is Figure 3B an equivalent circuit diagram of a pixel architecture in;

[0037] Figure 6 is a schematic structure diagram of a display terminal provided in an exemplary embodiment of the present disclosure.

[0038] Description of reference numerals:

[0039] 1 - display panel; AA - display area; NA - non - display area; 11 - sub - pixel; 11a - main pixel area; 11b - sub - pixel area; 12 - counter substrate; 13 - liquid crystal layer; 14 - common electrode layer; 15 - color filter layer;

[0040] 10 - substrate;

[0041] 20 - first metal layer; 21 - scan line; 22 - gate portion; 23 - common electrode portion;

[0042] 30 - second metal layer; 31 - data line; 32 - shared electrode line; 331a - first source; 331b - first drain; 332a - second source; 332b - second drain; 333a - third source; 333b - third drain; 334a - fourth source; 334b - fourth drain; 334c - auxiliary electrode;

[0043] 40 - pixel electrode layer; 41 - pixel electrode; 411 - main electrode; 412 - branch electrode;

[0044] 50 - semiconductor layer; 51 - active portion;

[0045] 60 - insulating layer;

[0046] T1 - First transistor; T2 - Second transistor; T3 - Third transistor; T4 - Fourth transistor;

[0047] D1 - First direction; D2 - Second direction;

[0048] HL1 - First via; HL2 - Second via; HL3 - Third via;

[0049] W T2 - Channel width of the active portion of the second transistor; W T3 - Channel width of the active portion of the third transistor; W T4 - Channel width of the active portion of the fourth transistor;

[0050] 2 - Display terminal; 3 - Terminal body. Detailed implementation manners

[0051] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0052] To achieve the above object, according to the first aspect of the present application, as Figures 1 to 3BAs shown in the figure, a display panel 1 is provided, which includes a substrate 10, a first metal layer 20, a second metal layer 30, and a pixel electrode layer 40. The first metal layer 20 is disposed on one side of the substrate 10, and the first metal layer 20 includes a scanning line 21 extending along a first direction D1; the second metal layer 30 is disposed on the side of the first metal layer 20 away from the substrate 10, and the second metal layer 30 includes a data line 31 and a shared electrode line 32 both extending along a second direction D2; the pixel electrode layer 40 is disposed on the side of the second metal layer 30 away from the substrate 10, and the pixel electrode layer 40 includes a plurality of pixel electrodes 41; wherein, the display panel 1 includes a plurality of sub-pixels 11, the sub-pixel 11 includes a main pixel region 11a and a sub-pixel region 11b, and the scanning line 21 is disposed between the main pixel region 11a and the sub-pixel region 11b; the sub-pixel 11 at least includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first transistor T1 includes a first source electrode 331a and a first drain electrode 331b disposed on the second metal layer 30. The second transistor T2 includes a second source electrode 332a and a second drain electrode 332b disposed on the second metal layer 30. The third transistor T3 includes a third source electrode 333a and a third drain electrode 333b disposed on the second metal layer 30. The fourth transistor T4 includes a fourth source electrode 334a and a fourth drain electrode 334b disposed on the second metal layer 30; the first source electrode 331a is connected to the data line 31, the first drain electrode 331b is connected to the pixel electrode 41 corresponding to the main pixel region 11a, and the fourth drain electrode 334b is connected to the shared electrode line 32; the first source electrode 331a, the second source electrode 332a, and the third source electrode 333a are connected, the second drain electrode 332b is connected to the third drain electrode 333b, and the third drain electrode 333b is connected to the pixel electrode 41 corresponding to the sub-pixel region 11b.

[0053] The display panel 1 can be an LCD panel. The LCD panel is a non-self-emitting panel, and a backlight module is required to provide a backlight source for the display panel 1. The backlight source is a white planar light source. The display panel 1 can be any one of a vertical alignment (VA) type, a twisted nematic (TN) type, a super twisted nematic (STN) type, an in-plane switching (IPS) type, and a fringe field switching (FFS) type.

[0054] As Figure 1As shown, the display panel 1 includes a display area AA and a non-display area NA disposed around the display area AA. The display area AA may be provided with a plurality of sub-pixels 11, and the sub-pixels 11 may include red sub-pixels, green sub-pixels, and blue sub-pixels. The non-display area NA may be provided with a driving circuit, such as a gate driving circuit, etc., and the driving circuit may provide driving signals for the sub-pixels 11.

[0055] As Figure 2B As shown, the display panel 1 includes a substrate 10 and a counter substrate 12 that are opposite and spaced apart, and a liquid crystal layer 13 is disposed between the substrate 10 and the counter substrate 12. A pixel electrode layer 40 is disposed on the substrate 10, and a common electrode layer 14 is disposed on the counter substrate 12. The liquid crystal molecules in the liquid crystal layer 13 are deflected under the action of the electric fields of the pixel electrode layer 40 and the common electrode layer 14. The pixel electrode layer 40 includes a plurality of pixel electrodes 41, and the pixel electrodes 41 are correspondingly disposed with the sub-pixels 11. By controlling the voltage of the pixel electrode 41, the deflection of the liquid crystal molecules in each sub-pixel 11 can be controlled, thereby controlling the brightness of the display screen.

[0056] In some other embodiments, both the pixel electrode layer 40 and the common electrode layer 14 may be disposed on the substrate 10.

[0057] The materials of the common electrode layer 14 and the pixel electrode layer 40 are both transparent materials, such as transparent metal oxides, etc. The transparent metal oxides include ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), IGO (indium gallium oxide), InO (indium oxide), etc.

[0058] A color filter layer 15 is disposed on one of the substrate 10 or the counter substrate 12. The color filter layer 15 can convert the white light of the backlight module into colored light, thereby presenting a color image.

[0059] Specifically, the color filter layer 15 includes a red color resist, a green color resist, and a blue color resist. The red color resist only allows red light to pass through, the green color resist only allows green light to pass through, and the blue color resist only allows blue light to pass through. The white light source of the backlight module is converted into corresponding colored light after passing through the color filter layer 15, thereby presenting a color image. The red sub-pixels roughly correspond to the red color resist regions, the green sub-pixels roughly correspond to the green color resist regions, and the blue sub-pixels roughly correspond to the blue color resist regions.

[0060] In some embodiments, a light-shielding structure may be disposed between two adjacent color resists of different colors. The light-shielding structure may be a black matrix or other light-shielding materials. The light-shielding structure blocks the transmission of light of various colors and can reduce the light crosstalk between sub-pixels 11 of different colors.

[0061] In some embodiments, as Figure 2B shown, the substrate 10 may be an array substrate, and the counter substrate 12 may be a color filter substrate. At this time, the driving circuit of the display panel 1 is disposed on the substrate 10, and the color filter layer 15 is disposed on the counter substrate 12.

[0062] In some embodiments, the display panel 1 may be a COA (Color Filter On Array) panel, in which case the driving circuit and the color filter layer 15 may both be disposed on the substrate 10.

[0063] In some embodiments, the substrate 10 may be a rigid substrate, such as a glass substrate, a quartz substrate, or a silicon wafer.

[0064] In some embodiments, the substrate 10 may be a flexible substrate, such as one of polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET).

[0065] As Figure 2A and Figure 2B shown, the first metal layer 20 includes scan lines 21 that extend along a first direction D1; the second metal layer 30 includes data lines 31 that extend along a second direction D2. The scan lines 21 and the data lines 31 intersect to form a grid. One scan line 21 corresponds to a row of sub-pixels 11 arranged along the first direction D1, and one data line 31 corresponds to a column of sub-pixels 11 arranged along the second direction D2.

[0066] In some embodiments, both the first metal layer 20 and the second metal layer 30 are conductive materials, such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0067] As Figure 3A shown, the first metal layer 20 includes a gate portion 22 that is connected to the scan line 21. The gate portion 22 serves as the gate of the thin film transistor. The gates of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be connected and arranged, thereby reducing the difficulty of the patterning process of the display panel 1.

[0068] The second metal layer 30 further includes a shared electrode line 32 (Sharebar) that may be connected to a fixed voltage signal, and the shared electrode line 32 may provide a common voltage for the sub-pixels 11.

[0069] It should be understood that, as Figure 2BAs shown, an insulating layer 60 is provided between the first metal layer 20 and the second metal layer 30, thereby achieving insulation between the two metal materials. When the pattern of the first metal layer 20 needs to be electrically connected to the pattern of the second metal, it can be achieved through vias passing through the insulating layer 60, and conductive materials can be deposited in the vias.

[0070] In some embodiments, the material of the insulating layer 60 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0071] In some embodiments, the first direction D1 and the second direction D2 form an acute or right angle. In this application, the right angle is taken as an example for illustration, and it should not be construed as a limitation on the embodiments of this application.

[0072] As Figure 2A shown, the sub-pixel 11 includes a main pixel region 11a and a sub-pixel region lb. That is to say, the display panel 1 can adopt a liquid crystal panel with a multi-domain display technology. The multi-domain display technology can reduce the large viewing angle color shift of the liquid crystal panel. In the multi-domain display technology, each sub-pixel 11 includes a main pixel region 11a and a sub-pixel region 11b, and the scan line 21 is disposed between the main pixel region 11a and the sub-pixel region 11b. The first transistor T1 is used to control the pixel voltage of the pixel electrode 41 in the main pixel region 11a, and the second transistor T2 and the third transistor T3 are used to control the pixel voltage of the pixel electrode 41 in the sub-pixel region 11b. The fourth transistor T4 is connected to the shared electrode line 32, and can divide the pixel voltage in the sub-pixel region 11b, so that the pixel voltage in the sub-pixel region 11b is reduced, and the display brightness in the sub-pixel region 11b is lower than the display brightness in the main pixel region 11a, thereby reducing the large viewing angle color shift of the display panel 1 and improving the display effect.

[0073] By connecting the second source 332a to the third source 333a and the second drain 332b to the third drain 333b, when the channel size of the second transistor T2 changes due to the decrease in patterning accuracy, the current can be input to the pixel electrode 41 corresponding to the sub-pixel region 11b through the channels of both the second transistor T2 and the third transistor T3, thereby reducing the influence of the fluctuation of the channel width of the transistor corresponding to the sub-pixel region 11b on the pixel voltage of the sub-pixel region 11b and improving the display unevenness caused by the voltage fluctuation of the pixel electrode 41.

[0074] Please refer to Figure 5 , Figure 5 is Figure 3B the equivalent circuit diagram of the pixel structure in lc_main . The pixel electrode 41 in the main pixel region 11a forms a liquid crystal capacitor C with the common electrode layer 14st_main 。The pixel electrode 41 in the sub-pixel region 11b forms a liquid crystal capacitor C with the common electrode layer 14 lc_sub 。The pixel electrode 41 in the sub-pixel region 11b forms a storage capacitor C with a common electrode st_sub 。The pixel voltage of the main pixel region 11a is V main ,The pixel electrode 41 of the sub-pixel region 11b is V sub 。A com1 is the common voltage, A com2 is the voltage of the shared electrode line 32, CF Com is the voltage of the common electrode layer 14.

[0075] As Figure 5 shown, the first source electrode 331a is connected to the data line 31, the first drain electrode 331b is connected to the pixel electrode 41 corresponding to the main pixel region 11a, and the data signal Data input from the data line 31 is input to the pixel electrode 41 of the main pixel region 11a through the first transistor T1. The pixel voltage of the pixel electrode 41 in the main pixel region 11a is V main ,The liquid crystal molecules in the main pixel region 11a are deflected in the electric field formed by the pixel voltage V main and the voltage CF of the common electrode layer 14 Com formed.

[0076] The fourth drain electrode 334b is connected to the shared electrode line 32; the first source electrode 331a, the second source electrode 332a, and the third source electrode 333a are connected, the second drain electrode 332b is connected to the third drain electrode 333b, and the third drain electrode 333b is connected to the pixel electrode 41 corresponding to the sub-pixel region 11b. The data signal Data input from the data line 31 is input to the pixel electrode 41 of the sub-pixel region 11b through the second transistor T2 and the third transistor T3. The pixel voltage of the pixel electrode 41 in the sub-pixel region 11b is V sub ,The liquid crystal molecules in the sub-pixel region 11b are deflected in the electric field formed by the pixel voltage V sub and the voltage CF of the common electrode layer 14 Com formed.

[0077] Since there is a shared electrode line 32 in the sub-pixel region 11b, the shared electrode line 32 will divide the pixel voltage of the pixel electrode 41 in the sub-pixel region 11b. Therefore, V main and V sub have different values, resulting in different display brightnesses of the main pixel region 11a and the sub-pixel region 11b.

[0078] The inventor of the present application found that the pixel voltage V sub of the pixel electrode 41 in the sub-pixel region 11b is related to the channel width of the transistor controlling the sub-pixel region 11b. V subThe channel width of the transistor controlling the sub-pixel region 11b satisfies the following relationship:

[0079] V sub = K * W sub / (W sub + W T ) (1);

[0080] where W sub is the channel width of the transistor on the loop between Data and V sub in the sub-pixel region 11b, and W T is the channel width of the transistor on the loop between V sub and A com2 in the sub-pixel region 11b. K is a constant value that can be canceled out in subsequent calculations, that is, V sub is proportional to W sub / (W sub + W T ). For example, in Figure 5 , W sub = W T2 + W T3 , and W T = W T4 .

[0081] Due to the precision deviation of the patterning process, the channel width will deviate, that is, the values of W sub and W T will change. Denote the changed W sub as W subnew , denote the changed W T as W Tnew , and denote the changed V sub as V subnew .

[0082] Then the fluctuation value of the pixel voltage is:

[0083] ΔV sub＝ |V subnew - V sub | (2);

[0084] When the pixel architecture is a 3T pixel architecture, the channel width will deviate, and there is the following relationship:

[0085] W subnew = W sub -2Δw (3);

[0086] W Tnew = W T -2Δw (4);

[0087] After substituting Formula (1), Formula (3) and Formula (4) into Formula (2), the following can be calculated:

[0088] ΔV sub = K * |2Δw * (W T - W sub ) / ((W sub + W T ) * ((W sub + W T ) - 4Δw))| (5);

[0089] When the pixel architecture is the 4T pixel architecture in this application, as Figure 3B shown, the channel width will have an offset, and there is the following relationship:

[0090] W subnew = W sub - 4Δw (6);

[0091] W Tnew = W T - 2Δw (7);

[0092] After substituting Formula (1), Formula (6) and Formula (7) into Formula (2), the following can be calculated:

[0093] ΔV sub = K * |2Δw * (W T - W sub ) / ((W sub + W T ) * ((W sub + W T ) - 6Δw))| (8);

[0094] Since W T < (W sub ) / 2, that is, the value of ΔV sub in Formula (8) is less than the value of ΔV sub in Formula (6). Through the above settings, the value of ΔV sub can be reduced, thereby reducing the fluctuation of the pixel voltage of the pixel electrode 41 in the sub-pixel region 11b and improving the display unevenness.

[0095] It should be noted that the channel length of a thin-film transistor refers to the length of the conductive channel between the source and the drain in the thin-film transistor, and the channel width refers to the width of the conductive channel between the source and the drain in the direction perpendicular to the channel length. The channel length is usually denoted as L, and the channel width is usually denoted as W. When the patterning accuracy of the source and the drain decreases due to the exposure process, the channel width also changes. The channel width may increase or decrease, and the change trends of the channel widths of multiple transistors are the same. That is to say, the channels of multiple thin-film transistors in the same sub-pixel 11 may all increase or all decrease. By forming the 4T pixel structure of the embodiments of the present application, the fluctuation of the pixel voltage in the sub-pixel region 11b can be reduced, thereby improving display unevenness.

[0096] It should be understood that the embodiments of the present application may also include a greater number of thin-film transistors. For example, the embodiments of the present application may be a 5T pixel structure, a 6T pixel structure, etc., but are not limited thereto.

[0097] Optionally, the display panel 1 further includes a semiconductor layer 50. The semiconductor layer 50 is disposed between the first metal layer 20 and the second metal layer 30. The semiconductor layer 50 includes an active portion 51 corresponding to each transistor. Among them, the channel width W of the active portion 51 of the second transistor T2 T2 and the channel width W of the active portion 51 of the third transistor T3 T3 sum is greater than twice the channel width W of the active portion 51 of the fourth transistor T4. T4

[0098] In some embodiments, the material of the semiconductor layer 50 may be amorphous silicon, low-temperature polycrystalline silicon, metal oxide semiconductor, etc.

[0099] As Figure 3B shown, the channel width W of the active portion 51 of the second transistor T2 T2 refers to the width of the active portion 51 between the second source 332a and the second drain 332b in the direction perpendicular to the current direction. W T2 is the length of the U-shaped dotted line. The channel width W of the active portion 51 of the third transistor T3 T3 refers to the width of the active portion 51 between the third source 333a and the third drain 333b in the direction perpendicular to the current direction. The channel width W of the active portion 51 of the fourth transistor T4 T4 refers to the width of the active portion 51 between the fourth source 334a and the fourth drain 334b in the direction perpendicular to the current direction.

[0100] In some embodiments, the channel of the second transistor T2 is U-shaped, and the channels of the third transistor T3 and the fourth transistor T4 are I-shaped. Since in the same area, the U-shaped can increase the channel width compared with the I-shaped, so that W T2 ​+W T3 >2W T4 。

[0101] Optionally, as Figure 3B shown, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are arranged in sequence along the first direction D1. Since the scanning line 21 extends along the first direction D1, therefore, the space of the sub-pixel 11 in the first direction D1 is relatively sufficient. Adopting the above arrangement can reduce the occupation of the effective display area of the sub-pixel 11 and improve the aperture ratio.

[0102] Optionally, the third source 333a and the third drain 333b are arranged along the first direction D1, and the fourth source 334a and the fourth drain 334b are arranged along the first direction D1.

[0103] Optionally, the fourth source 334a and the fourth drain 334b are arranged along the first direction D1.

[0104] Optionally, both the first transistor T1 and the second transistor T2 are U-shaped thin film transistors, and both the third transistor T3 and the fourth transistor T4 are I-shaped thin film transistors.

[0105] The pattern of the projection of the source of the U-shaped thin film transistor on the substrate 10 is a U-shaped structure, which is composed of two bar-shaped arms and a connecting arm, and the connecting arm is connected to the ends of the two bar-shaped arms. The pattern of the projection of the drain of the U-shaped thin film transistor on the substrate 10 is a bar-shaped arm, and the bar-shaped arm of the drain is located inside the opening of the U-shaped structure. The bar-shaped arm of the drain is located between the two bar-shaped arms of the source, and the extending direction of the bar-shaped arm of the drain is substantially parallel to the extending direction of the bar-shaped arm of the source.

[0106] For the I-shaped thin film transistor, the active part 51, the source, and the drain form an I-shaped structure in the projection on the substrate 10, and the source and the drain are respectively located at both ends of the active part 51.

[0107] Optionally, the opening directions of the first source 331a and the second source 332a are the same. The patterns of the projections of the first source 331a and the second source 332a on the substrate 10 are both U-shaped structures, and the opening directions face the same direction. As Figure 3A shown, both the first source 331a and the second source 332a are vertically upward. Through the above settings, the arrangement of the first transistor T1 and the second transistor T2 can be made more compact, and the area occupied by the thin film transistors can be reduced.

[0108] Optionally, as Figure 3CAs shown, the fourth transistor T4 includes an auxiliary electrode 334c disposed on the second metal layer 30. The auxiliary electrode 334c is disposed between the fourth source electrode 334a and the fourth drain electrode 334b, and the auxiliary electrode 334c is spaced apart from both the fourth source electrode 334a and the fourth drain electrode 334b. The orthographic projection of the active part 51 of the fourth transistor T4 on the substrate 10 surrounds the periphery of the orthographic projection of the auxiliary electrode 334c on the substrate 10.

[0109] The auxiliary electrode 334c is disposed between the fourth source electrode 334a and the fourth drain electrode 334b, and the auxiliary electrode 334c is spaced apart from both the fourth source electrode 334a and the fourth drain electrode 334b. That is to say, the auxiliary electrode 334c does not contact other conductive materials, and there is no input voltage signal on the auxiliary electrode 334c.

[0110] As Figure 3C shown, the orthographic projection of the active part 51 of the fourth transistor T4 on the substrate 10 surrounds the periphery of the orthographic projection of the auxiliary electrode 334c on the substrate 10. That is to say, the active part 51 is a closed annular structure, the auxiliary electrode 334c is located inside the annular structure, and the orthographic projection of the auxiliary electrode 334c on the substrate 10 does not overlap with the orthographic projection of the annular structure on the substrate 10.

[0111] In the fourth transistor T4, current flows from the fourth source electrode 334a to the fourth drain electrode 334b. Since the active part 51 of the fourth transistor T4 is an annular structure, it is equivalent to that the current can flow along two branches of the active part 51, that is, the effective channel width of the fourth transistor T4 is increased.

[0112] At this time, when the pixel architecture is a 4T pixel architecture, as Figure 3C shown, there is the following relationship:

[0113] W subnew = W sub - 4Δw (9);

[0114] W Tnew = W T - Δw (10);

[0115] Substituting formula (1), formula (9) and formula (10) into formula (2) and calculating, we can get:

[0116] ΔV sub＝ K * |Δw * (4W T - W sub ) / ((W sub + W T ) * ((W sub + W T ) - 5Δw))| (11);

[0117] In some embodiments, W T can be about 10 um, and Wsub can be about 30 um.

[0118] Since W T <(W sub ) / 2, that is, ΔV in formula (11) sub is less than ΔV in formula (8) sub . Through the above settings, ΔV sub can be reduced, thereby reducing the fluctuation of the pixel voltage of the pixel electrode 41 in the sub-pixel region 11b and improving the display unevenness.

[0119] Optionally, as Figure 3A shown, the display panel 1 includes a common electrode portion 23 extending along the first direction D1, and the shared electrode line 32 is electrically connected to the common electrode portion 23 through a third via hole HL3. That is to say, the shared electrode line 32 and the common electrode portion 23 can input the same common voltage signal, thereby simplifying the circuit of the display panel 1.

[0120] Optionally, as Figure 4 shown, the display panel 1 includes a common electrode portion 23 extending along the first direction D1, and the shared electrode line 32 is insulated from the common electrode portion 23. That is to say, the shared electrode line 32 and the common electrode portion 23 can input different common voltage signals. For example, the common electrode portion 23 inputs A com1 , and the shared electrode line 32 inputs A com2 .

[0121] As Figure 2A shown, the common electrode portion 23 is used to provide a common voltage for a plurality of sub-pixels 11, and the common electrode portion 23 can form a storage capacitor with the pixel electrode 41.

[0122] The scan line 21 can be arranged adjacent to the common electrode portion 23. The common electrode portion 23 and the shared electrode line 32 intersect to form a grid.

[0123] Optionally, as Figure 2A and Figure 3A shown, the first drain 331b and the pixel electrode 41 corresponding to the main pixel region 11a are electrically connected through a first via hole HL1, and the second drain 332b and the pixel electrode 41 corresponding to the sub-pixel region 11b are electrically connected through a second via hole HL2. The first via hole HL1 and the second via hole HL2 are arranged along the first direction D1. Through the above settings, the structures of the first via hole HL1 and the second via hole HL2 can be made more compact, and the aperture ratio of the display panel 1 can be improved.

[0124] Optionally, as Figure 2AAs shown, the pixel electrode 41 includes a main electrode 411 extending along the second direction D2, and the shared electrode line 32 overlaps with the main electrode 411.

[0125] In some embodiments, as Figure 2A shown, the pixel electrode 41 includes a main electrode 411 extending along the second direction D2, and a branch electrode 412 is connected to the main electrode 411 and extends in a direction away from the main electrode 411. A slit is formed between two adjacent branch electrodes 412. The extending directions of the branch electrodes 412 of the same pixel electrode 41 can be different to form a multi-domain structure.

[0126] According to the second aspect of the present application, as Figure 6 shown, a display terminal 2 is provided, which includes the above-mentioned display panel 1.

[0127] In this embodiment, as Figure 6 shown, the display terminal 2 includes a display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined into one body.

[0128] In this embodiment, the display terminal 2 can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0129] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0130] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0131] The embodiments, implementation manners and related technical features of the present application can be combined and replaced with each other without conflict.

[0132] The above are only the preferred embodiments of the present application, and do not impose any formal limitations on the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel (1), characterized in that, Comprising: A substrate (10); A first metal layer (20) disposed on one side of the substrate (10), the first metal layer (20) including scan lines (21) extending along a first direction (D1); A second metal layer (30) disposed on a side of the first metal layer (20) facing away from the substrate (10), the second metal layer (30) including data lines (31) and common electrode lines (32) both extending along a second direction (D2); A pixel electrode layer (40) disposed on a side of the second metal layer (30) facing away from the substrate (10), the pixel electrode layer (40) including a plurality of pixel electrodes (41); Wherein, the display panel (1) includes a plurality of sub-pixels (11), the sub-pixels (11) include a main pixel region (11a) and a sub-pixel region (11b), and the scan lines (21) are disposed between the main pixel region (11a) and the sub-pixel region (11b); the sub-pixels (11) at least include a first transistor (T1), a second transistor (T2), a third transistor (T3), and a fourth transistor (T4), the first transistor (T1) includes a first source electrode (331a) and a first drain electrode (331b) disposed on the second metal layer (30), the second transistor (T2) includes a second source electrode (332a) and a second drain electrode (332b) disposed on the second metal layer (30), the third transistor (T3) includes a third source electrode (333a) and a third drain electrode (333b) disposed on the second metal layer (30), the fourth transistor (T4) includes a fourth source electrode (334a) and a fourth drain electrode (334b) disposed on the second metal layer (30); the first source electrode (331a) is connected to the data line (31), the first drain electrode (331b) is connected to the pixel electrode (41) corresponding to the main pixel region (11a), the fourth drain electrode (334b) is connected to the common electrode line (32); the first source electrode (331a), the second source electrode (332a), and the third source electrode (333a) are connected, the second drain electrode (332b) is connected to the third drain electrode (333b), and the third drain electrode (333b) is connected to the pixel electrode (41) corresponding to the sub-pixel region (11b).

2. The display panel (1) according to claim 1, wherein The display panel (1) further includes: A semiconductor layer (50) disposed between the first metal layer (20) and the second metal layer (30), the semiconductor layer (50) including active portions (51) corresponding to each transistor; Among them, the channel width (W T2 ) of the active part of the second transistor and the channel width (W T3 ) of the active part of the third transistor add up to be greater than or equal to twice the channel width (W T4 ) of the active part of the fourth transistor.

3. The display panel (1) according to claim 2, wherein The first transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) are arranged in sequence along the first direction (D1).

4. The display panel (1) according to claim 3, characterized in that, Both the first transistor (T1) and the second transistor (T2) are U-shaped thin film transistors, and both the third transistor (T3) and the fourth transistor (T4) are I-shaped thin film transistors.

5. The display panel (1) according to claim 4, characterized in that, The opening directions of the first source electrode (331a) and the second source electrode (332a) are the same.

6. The display panel (1) according to claim 2, characterized in that, The fourth transistor (T4) includes an auxiliary electrode (334c) disposed on the second metal layer (30). The auxiliary electrode (334c) is disposed between the fourth source electrode (334a) and the fourth drain electrode (334b), and the auxiliary electrode (334c) is spaced apart from both the fourth source electrode (334a) and the fourth drain electrode (334b). The orthographic projection of the active portion (51) of the fourth transistor (T4) on the substrate (10) surrounds the periphery of the orthographic projection of the auxiliary electrode (334c) on the substrate (10).

7. The display panel (1) according to claim 6, characterized in that, The fourth source electrode (334a) and the fourth drain electrode (334b) are arranged along the first direction (D1).

8. The display panel (1) according to claim 1, characterized in that, The first drain electrode (331b) and the pixel electrode (41) corresponding to the main pixel region (11a) are electrically connected through a first via hole (HL1), and the second drain electrode (332b) and the pixel electrode (41) corresponding to the sub-pixel region (11b) are electrically connected through a second via hole (HL2). The first via hole (HL1) and the second via hole (HL2) are arranged along the first direction (D1).

9. The display panel (1) according to claim 1, wherein, The display panel (1) includes a common electrode portion (23) extending along the first direction (D1), and the shared electrode line (32) is electrically connected to the common electrode portion (23) through a third via hole (HL3).

10. The display panel (1) according to claim 1, characterized in that, The display panel (1) includes a common electrode portion (23) extending along the first direction (D1), and the shared electrode line (32) is insulated from the common electrode portion (23).

11. The display panel (1) according to claim 1, wherein, The pixel electrode (41) includes a main electrode (411) extending along the second direction (D2), and the shared electrode line (32) overlaps with the main electrode (411).

12. A display terminal (2), characterized in that, A display panel (1) according to any one of claims 1 to 11 is included.

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