Computer system and server

Abstract

The invention discloses a computer system and a server, relates to the technical field of computers, and divides the computer system into three modules, namely a general computing resource pool, a switching unit and an accelerated computing resource pool. Clock signals in two modes of a common clock signal and an independent clock signal are simultaneously provided in each large module, and flexible switching between the common clock signal and the independent clock signal can be realized according to a clock switching circuit, thereby realizing dynamic adjustment of the clock mode according to an actual application scene, improving diversification and flexibility of the clock mode, and realizing wide application range. When one clock mode is abnormal, the clock mode can be switched to the other clock mode, normal operation of the resource pooling system can be guaranteed as much as possible, abnormal operation of the resource pooling system caused by the abnormal clock is avoided, and the stability of the resource pooling system is improved. Therefore, in the operation process of the resource pooling system, the common clock signal or the independent clock signal can be selected according to the actual scene requirement.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to computer systems and servers. Background Art

[0002] A server is a device used for various operations. Its commonly used computing architecture is a resource pooling system, which can interconnect multiple Graphics Processing Units (GPUs) to improve the computing power of the server by increasing the number of GPUs.

[0003] In related technologies, the clock mode of the resource pooling system can adopt a common clock mode, an independent clock mode, or a digital clock mode. However, there are problems such as a single mode and poor stability. Summary of the Invention

[0004] This application provides a computer system and a server to at least solve the problems of a single clock mode and poor stability in related technologies.

[0005] This application provides a computer system, including:

[0006] A general computing resource pool, including: a central processing unit, a first clock generator, and a first clock switching circuit. The first clock switching circuit is used to switch the common clock signal generated by the central processing unit and the independent clock signal generated by the first clock generator;

[0007] A switching unit, including: a second clock generator, a second clock switching circuit, and a data switching circuit. The second clock switching circuit is used to switch the common clock signal and the independent clock signal generated by the second clock generator, and output them to the data switching circuit;

[0008] An accelerated computing resource pool, including: a third clock generator, a third clock switching circuit, and a graphics processor interface. The third clock switching circuit is used to switch the common clock signal and the independent clock signal generated by the third clock generator, and output them to the graphics processor interface.

[0009] This application also provides a server, characterized by including the aforementioned computer system.

[0010] Through this application, the computer system is divided into three major modules: a general computing resource pool, a switching unit, and an accelerated computing resource pool. In each major module, clock signals in two modes, namely a common clock signal and an independent clock signal, are provided simultaneously, and flexible switching between the two can be achieved according to the clock switching circuit, realizing dynamic adjustment of the clock mode according to the actual application scenario, improving the diversity and flexibility of the clock mode. When an abnormality occurs in one of the clock modes, it can be switched to the other clock mode, which can ensure the normal operation of the resource pooling system as much as possible, avoid abnormal operation of the resource pooling system caused by clock abnormalities, and contribute to improving the stability of the resource pooling system. In this way, during the operation of the resource pooling system in the embodiments of this application, the common clock signal or the independent clock signal can be selected according to the actual scenario requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0012] Figure 1 is a schematic diagram of the transmission of a common clock signal provided by an embodiment of this application;

[0013] Figure 2 is a schematic diagram of the transmission of an independent clock signal provided by an embodiment of this application;

[0014] Figure 3 is a schematic diagram of the transmission of a data clock signal provided by an embodiment of this application;

[0015] Figure 4 is a schematic diagram of the structure of a computer system provided by an embodiment of this application;

[0016] Figure 5 is a schematic diagram of the transmission process of a common clock signal provided by an embodiment of this application;

[0017] Figure 6 is a schematic diagram of the transmission process of an independent clock signal provided by an embodiment of this application;

[0018] Figure 7 is a schematic diagram of the structure of another computer system provided by an embodiment of this application;

[0019] Figure 8 is a schematic diagram of the structure of a selector provided by an embodiment of this application;

[0020] Figure 9 is a schematic diagram of the transmission process of a common clock signal provided by an embodiment of this application;

[0021] Figure 10 It is a schematic diagram of the transmission process of an independent clock signal provided by an embodiment of the present application;

[0022] Figure 11 It is a schematic diagram of the combined setting of a common clock driving circuit and a clock driving circuit in a switching unit provided by an embodiment of the present application;

[0023] Figure 12 It is a schematic diagram of the control of a clock generator, a clock driving circuit, and a selector by a control unit provided by an embodiment of the present application. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0025] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0026] The resource pooling system can interconnect multiple GPUs on a server to improve the data processing ability of the server. Such a resource pooling system is widely applied to servers relying on high-performance GPUs such as digital transformation, artificial intelligence and big data technology-driven, and deep learning training, driving the rapid development of heterogeneous computing servers. For example, in the training of artificial intelligence large models, the resource pooling system becomes a key solution. The resource pooling system interconnects GPUs and performs vertical (ScaleOut) expansion through a switch, reconstructing from a tree topology to a mesh topology to enhance large-scale GPU deployment to meet big data requirements.

[0027] The interconnection of the above GPUs can be achieved through a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interface. The PCIe interface is widely used for connecting various high-speed devices, and the high-speed devices can be GPUs, graphics cards, network cards, solid-state drives, etc. The data transmission stability and efficiency of PCIe have a crucial impact on the overall performance of the server.

[0028] During the operation of the above resource pooling system, large data interactions will occur, and the large data interactions rely on clock signals. The clock signal of PCIe, as the core signal for coordinating the system operation and the time reference for data transmission, directly determines the accuracy and reliability of data transmission.

[0029] In some related technologies, the clock signal of the resource pooling system usually provides a fixed clock mode, which has problems of poor singularity and stability.

[0030] To solve the above technical problems, the embodiments of the present application provide two clock modes, namely a common clock and an independent clock, in the resource pooling system, and can flexibly switch between the two according to a clock switching circuit, realizing dynamic adjustment of the clock mode according to the actual application scenario, improving the diversity and flexibility of the clock mode. When one of the clock modes is abnormal, it can be switched to the other clock mode, which can ensure the normal operation of the resource pooling system as much as possible, avoid the abnormal operation of the resource pooling system caused by clock anomalies, and help improve the stability of the resource pooling system. In this way, during the operation of the resource pooling system of the embodiments of the present application, the common clock signal or the independent clock signal can be selected according to the actual scenario requirements.

[0031] In related technologies, the common clock mode (Common Clock) is a relatively commonly used mode, where the transmitter and the receiver share the same clock signal, and this shared clock signal is the common clock signal. Figure 1 It is a schematic diagram of the transmission of a common clock signal provided by the embodiments of the present application. Refer to Figure 1 As shown, in the common clock mode, there is a clock generator, which is used to generate a common clock signal and send it to both the transmitter and the receiver simultaneously, so as to control the transmitter to send data to the receiver through this common clock signal.

[0032] Different from the above common clock mode, in the independent clock mode, the transmitter and the receiver use their own clock signals respectively, which are called independent clock signals. Figure 2 It is a schematic diagram of the transmission of an independent clock signal provided by the embodiments of the present application. Refer to Figure 2As shown, there is a clock generator corresponding to the sending end, called the sending-end clock generator, and there is another clock generator corresponding to the receiving end, called the receiving-end clock generator. The two are two independent clock generators. The sending-end clock generator generates a clock signal as the sending-end independent clock signal and sends it to the sending end. The receiving-end clock generator generates another clock signal as the receiving-end independent clock signal and sends it to the receiving end. The sending end controls the sending of data through the sending-end independent clock signal, and the receiving end controls the receiving of data through the receiving-end independent clock signal to achieve data transmission between the sending end and the receiving end.

[0033] In the related art, the data clock mode is the third clock mode. The data clock mode is a clock mode between the above-mentioned common clock mode and the independent clock mode. In the data clock mode, only the sending end has a clock generator. Figure 3 It is a schematic diagram of the transmission of a data clock signal provided by an embodiment of the present application. Refer to Figure 3 As shown, the sending end has a clock generator, called the sending-end clock generator, and the receiving end does not have a clock generator. The sending-end clock generator generates a clock signal, which is sent to the sending end as the data clock signal. The sending end sends data to the receiving end under the control of this data clock signal. At the same time, the sending end also sends this data clock signal to the receiving end so that the receiving end can recover this data clock signal and receive data based on this data clock signal.

[0034] Among the above three clock modes, the common clock mode has a simple structure, and the delay and jitter are relatively small. However, it requires the sending end and the receiving end to strictly synchronously use the same clock generator, and the clock offsets of all devices must be kept within a certain range (12 ns, 12 nanoseconds). Otherwise, it will cause the sampling window to be misaligned and trigger data errors. Therefore, the common clock mode is suitable for short-distance transmission and not suitable for long-distance transmission.

[0035] The sending end and the receiving end of the independent clock mode use completely independent clock signals, and data synchronization completely depends on two clock generators, requiring relatively small jitter of the clock generators, and having relatively high requirements for the clock generators.

[0036] Data synchronization in the data clock mode completely depends on the clock data recovery circuit at the receiving end to extract the data clock signal from the data stream, thereby limiting its relatively low transmission rate. The highest rate is 8 GT / s (Giga Transfers per Second, one billion data transfers per second), and thus it is only applicable to some low-rate transmission scenarios, such as PCIe Gen2 (generation 2, second generation), Gen3 (Generation 3, third generation), and not applicable to high-rate transmission scenarios, such as PCIe5.0.

[0037] Considering the above characteristics of the above three clock modes, the present application uses the independent clock mode and the common clock mode in the resource pooling system and flexibly switches according to the actual application scenario requirements.

[0038] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] Figure 4 It is a schematic structural diagram of a computer system provided by an embodiment of the present application. As Figure 4 shown, an embodiment of the present application provides a computer system including: a general computing resource pool, a switching unit, and an accelerated computing resource pool. The switching unit is respectively connected to the general computing resource pool and the accelerated computing resource pool.

[0040] The general computing resource pool includes: a central processing unit (CPU, Central Processing Unit), a first clock generator, and a first clock switching circuit. The central processing unit and the first clock generator are connected to the first clock switching circuit. The first clock switching circuit is used to switch the common clock signal generated by the central processing unit and the independent clock signal generated by the first clock generator. That is to say, clock switching is performed between the common clock signal generated by the central processing unit and the independent clock signal generated by the first clock generator.

[0041] The switching unit includes: a second clock generator, a second clock switching circuit, and a data switching circuit (Switch, SW). The second clock switching circuit is connected to the second clock generator and the data switching circuit. The second clock switching circuit is used to switch the common clock signal and the independent clock signal generated by the second clock generator. That is to say, clock switching is performed between the common clock signal and the independent clock signal generated by the second clock generator, and the clock signal is output to the data switching circuit. The data switching circuit serves as the core data switching center and is used to perform the data switching function between the CPU and the GPU.

[0042] The accelerated computing resource pool includes: a third clock generator, a third clock switching circuit, and a graphics processor interface. The third clock switching circuit is connected to the third clock generator and the graphics processor interface. The third clock switching circuit is used to switch the common clock signal and the independent clock signal generated by the third clock generator. That is to say, clock switching is performed between the common clock signal and the independent clock signal generated by the third clock generator, and the clock signal is output to the graphics processor interface.

[0043] Based on the above architecture, the common clock signal passes through the general computing resource pool, the switching unit, and the accelerated computing resource pool.

[0044] From Figure 4As can be seen, the switching unit connects the accelerated computing resource pool to the general computing resource pool to enhance the computing power of the CPU in the general computing resource pool through the GPUs in the accelerated computing resource pool. Based on this, the common clock signal of this application is generated by the CPU in the general computing resource pool and is sequentially sent to the switching unit and the accelerated computing resource pool. The general computing resource pool is used to provide basic computing functions, and the accelerated computing resource pool is used to provide accelerated computing functions to achieve higher computing performance, parallelism, and energy efficiency ratio. The switching unit is a high-speed data interconnection module, which is closely combined with the basic software and connects the general computing resource pool and the accelerated computing resource pool through high-speed cables to improve the resource access efficiency of the accelerated computing resource pool. In this way, many GPUs can be extended through the switching unit to make full use of GPU resources. Multiple data exchange circuits can be set in the switching unit to improve the data exchange performance between the CPU and the GPU and reduce the GPU access latency.

[0045] Specifically, in the above general computing resource pool, the CPU is used to generate the common clock signal, and the first clock generator is used to generate the independent clock signal of the general computing resource pool. The output terminals of the CPU and the first clock generator are respectively connected to the two input terminals of the first clock switching circuit to input the common clock signal and the independent clock signal of the general computing resource pool into the first clock switching circuit. The first clock switching circuit can select one of the common clock signal and the independent clock signal of the general computing resource pool as the current clock signal of the general computing resource pool to drive the operation of the clock usage circuit in the general computing resource pool. Therefore, the output terminal of the first clock switching circuit can be connected to the reference clock input terminal of the clock usage circuit in the general computing resource pool, and the clock usage circuit can operate based on the current clock signal of the general computing resource pool.

[0046] In the above switching unit, the second clock generator is used to generate the independent clock signal of the switching unit, and the common clock signal used by the switching unit is the common clock signal sent by the general computing resource pool. The output terminal of the second clock generator is connected to one input terminal of the second clock switching circuit to input the independent clock signal of the switching unit into the second clock switching circuit. The other input terminal of the second clock switching circuit is connected to the output terminal of the first clock switching circuit to input the common clock signal into the second clock switching circuit. The second clock switching circuit can select one of the common clock signal and the independent clock signal of the switching unit as the current clock signal of the switching unit, and the current clock signal of the switching unit is used to drive the operation of the data exchange circuit in the switching unit. Therefore, the output terminal of the second clock switching circuit is connected to the reference clock input terminal of the data exchange circuit.

[0047] In the above acceleration computing resource pool, the third clock generator is used to generate an independent clock signal for the acceleration computing resource pool, and the common clock signal used by the acceleration computing resource pool is the common clock signal sent by the switching unit. The output end of the third clock generator is connected to one input end of the third clock switching circuit, and is used to input the independent clock signal of the acceleration computing resource pool into the third clock switching circuit. The other input end of the third clock switching circuit is connected to the output end of the second clock switching circuit, and is used to input the common clock signal into the third clock switching circuit. The third clock switching circuit can select one clock signal from the common clock signal and the independent clock signal of the acceleration computing resource pool as the current clock signal of the acceleration computing resource pool, and the current clock signal of the acceleration computing resource pool is used to drive the GPU in the acceleration computing resource pool to operate. Therefore, the GPU is connected to the output end of the third clock switching circuit through the graphics processor interface. Specifically, the input end of the graphics processor interface is connected to the output end of the third clock switching circuit, and the reference clock input end of the GPU is connected to the output end of the graphics processor interface.

[0048] It can be seen from Figure 4 that the connection between the output end of the first clock switching circuit and the input end of the second clock switching circuit realizes the connection between the general computing resource pool and the switching unit, and is used to transmit the common clock signal from the general computing resource pool to the switching unit. The connection between the output end of the second clock switching circuit and the input end of the third clock switching circuit realizes the connection between the switching unit and the acceleration computing resource pool, and is used to transmit the common clock signal from the switching unit to the acceleration computing resource pool. In this way, the common clock signal is transmitted from the general computing resource pool through the switching unit to the acceleration computing resource pool, so that the general computing resource pool, the switching unit and the acceleration computing resource pool share the common clock signal.

[0049] It can be understood that based on the above Figure 4 computer system shown, the clock signal transmission processes corresponding to the common clock mode and the independent clock mode are different.

[0050] In the common clock mode, the first clock switching circuit, the second clock switching circuit and the third clock switching circuit all select to output the common clock signal. Figure 5 FIG. Figure 5 shows a schematic diagram of the transmission process of a common clock signal provided by an embodiment of the present application. As shown in

[0051] In the independent clock mode, the first clock switching circuit, the second clock switching circuit, and the third clock switching circuit all select to output the independent clock signal. Figure 6 It is a schematic diagram of the transmission process of an independent clock signal provided by an embodiment of the present application. Refer to Figure 6 As shown, there is no need to transmit a clock signal between the general computing resource pool, the switching unit, and the accelerated computing resource pool. The independent clock signal of the general computing resource pool is transmitted from the first clock generator to the first clock switching circuit, the independent clock signal of the switching unit is sequentially transmitted from the second clock generator to the second clock switching circuit and the data switching unit, and the independent clock signal of the accelerated computing resource pool is sequentially transmitted from the third clock generator to the third clock switching circuit and the graphics processor interface. When a graphics processor is connected to the graphics processor interface, it is further transmitted to the graphics processor by the graphics processor interface.

[0052] In summary, the embodiment of the present application can implement the clock mode switching of the computer system through three clock switching circuits, which can avoid the abnormal operation of the resource pooling system caused by clock anomalies, and help improve the clock diversity and stability of the resource pooling system.

[0053] In a possible implementation manner, refer to Figure 7 As shown, any one of the first clock switching circuit, the second clock switching circuit, or the third clock switching circuit may include a clock driving circuit, and the clock driving circuit is used to drive the common clock signal for long-distance transmission. In this way, in the common clock mode, it is possible to ensure that the common clock signal has relatively high quality and small clock offset when reaching the switching unit and the accelerated computing resource pool, which can ensure that the switching unit and the accelerated computing resource pool accurately process data, and help improve the data processing accuracy of the resource pooling system. The data driving circuit is a circuit for amplifying signals.

[0054] In some embodiments, refer to Figure 7 As shown, any one of the first clock switching circuit, the second clock switching circuit, or the third clock switching circuit includes: a control unit and a clock switching unit. The control unit is connected to the clock switching unit, and the control unit is used to control the clock switching unit to switch between the independent clock signal and the common clock signal. In this way, by inputting a control instruction to the control unit, the clock mode switching can be controlled based on the control unit, which helps improve the clock switching accuracy.

[0055] The above control unit can be any integrated circuit with a control function. For example, a commonly used control unit can be a BMC (Board Management Controller, out-of-band management unit).

[0056] In a general computing resource pool, the two data input terminals of the clock switching unit of the first clock switching circuit are respectively connected to the output terminal of the CPU and the output terminal of the first clock generator to receive the common clock signal output by the CPU and the independent clock signal output by the first clock generator. The control input terminal of the clock switching unit of the first clock switching circuit is connected to the output terminal of the control unit of the first clock switching circuit to receive the control signal output by the control unit of the first clock switching circuit. The control signal of the control unit of the first clock switching circuit is used to indicate that the clock switching unit of the first clock switching circuit selects one clock signal from the common clock signal output by the CPU and the independent clock signal output by the first clock generator as the current clock signal of the general computing resource pool. The output terminal of the clock switching unit of the first clock switching circuit is connected to the data input terminal of the clock usage circuit in the general computing resource pool to drive the operation of the clock usage circuit.

[0057] In a switching unit, the two data input terminals of the clock switching unit of the second clock switching circuit are respectively connected to the output terminal of the clock switching unit of the first clock switching circuit and the output terminal of the second clock generator to receive the common clock signal output by the clock switching unit of the first clock switching circuit and the independent clock signal output by the second clock generator. The control input terminal of the clock switching unit of the second clock switching circuit is connected to the output terminal of the control unit of the second clock switching circuit to receive the control signal output by the control unit of the second clock switching circuit. The control signal is used to indicate that the clock switching unit of the second clock switching circuit selects one clock signal from the common clock signal and the independent clock signal output by the second clock generator as the current clock signal of the switching unit. The output terminal of the clock switching unit of the second clock switching circuit is connected to the data input terminal of the data switching circuit in the switching unit to drive the operation of the data switching circuit.

[0058] In an accelerated computing resource pool, the two data input terminals of the clock switching unit of the third clock switching circuit are respectively connected to the output terminal of the clock switching unit of the third clock switching circuit and the output terminal of the third clock generator to receive the common clock signal output by the clock switching unit of the second clock switching circuit and the independent clock signal output by the third clock generator. The control input terminal of the clock switching unit of the third clock switching circuit is connected to the output terminal of the control unit of the third clock switching circuit to receive the control signal output by the control unit of the third clock switching circuit. The control signal is used to indicate that the clock switching unit of the third clock switching circuit selects one clock signal from the common clock signal and the independent clock signal output by the third clock generator as the current clock signal of the accelerated computing resource pool. The output terminal of the clock switching unit of the second clock switching circuit is connected to the clock input terminal of the GPU through a graphics processor interface to drive the operation of the GPU.

[0059] It can be understood that the control units of the above-mentioned first clock switching circuit, second clock switching circuit, and third clock switching circuit can be reused or independently set.

[0060] In some embodiments, any one of the above-mentioned first clock switching circuit, second clock switching circuit, and third clock switching circuit includes a selector and a clock buffer. The selector is connected to the control unit and is used to cache the common clock signal or the independent clock signal into the clock buffer under the control of the control unit. In this way, signal selection can be achieved through the selector, and the clock signal can be cached through the clock buffer, which can facilitate more clock usage circuits to access multiple output channels of the clock buffer.

[0061] In the general computing resource pool, the two data input terminals of the selector of the first clock switching circuit are respectively connected to the output terminal of the CPU and the output terminal of the first clock generator to receive the common clock signal output by the CPU and the independent clock signal output by the first clock generator. The control input terminal of the selector of the first clock switching circuit is connected to the output terminal of the control unit of the first clock switching circuit to receive the control signal output by the control unit of the first clock switching circuit. The control signal of the control unit of the first clock switching circuit is used to indicate that the selector of the first clock switching circuit selects one of the common clock signal output by the CPU and the independent clock signal output by the first clock generator as the current clock signal of the general computing resource pool. The output terminal of the selector of the first clock switching circuit is connected to the input channel of the clock buffer of the first clock switching circuit, and the output channel of the clock buffer of the first clock switching circuit is connected to the data input terminal of the clock usage circuit in the general computing resource pool to drive the operation of the clock usage circuit.

[0062] In the switching unit, the two data input terminals of the selector of the second clock switching circuit are respectively connected to the output terminal of the selector of the first clock switching circuit and the output terminal of the second clock generator to receive the common clock signal output by the selector of the first clock switching circuit and the independent clock signal output by the second clock generator. The control input terminal of the selector of the second clock switching circuit is connected to the output terminal of the control unit of the second clock switching circuit to receive the control signal output by the control unit of the second clock switching circuit. The control signal is used to indicate that the selector of the second clock switching circuit selects one of the common clock signal and the independent clock signal output by the second clock generator as the current clock signal of the switching unit. The output terminal of the selector of the second clock switching circuit is connected to the input channel of the clock buffer of the second clock switching circuit, and the output channel of the clock buffer of the second clock switching circuit is connected to the data input terminal of the data switching circuit in the switching unit to drive the operation of the data switching circuit.

[0063] In the acceleration computing resource pool, the two data input terminals of the selector of the third clock switching circuit are respectively connected to the output terminal of the selector of the third clock switching circuit and the output terminal of the third clock generator to receive the common clock signal output by the selector of the second clock switching circuit and the independent clock signal output by the third clock generator. The control input terminal of the selector of the third clock switching circuit is connected to the output terminal of the control unit of the third clock switching circuit to receive the control signal output by the control unit of the third clock switching circuit. This control signal is used to instruct the selector of the third clock switching circuit to select one of the common clock signal and the independent clock signal output by the third clock generator as the current clock signal of the acceleration computing resource pool. The output terminal of the selector of the second clock switching circuit is connected to the input channel of the clock buffer of the second clock switching circuit, and the output channel of the clock buffer of the second clock switching circuit is connected to the clock input terminal of the GPU through the graphics processor interface to drive the GPU to operate.

[0064] Figure 8 FIG. is a schematic structural diagram of a selector provided by an embodiment of the present application. Refer to Figure 8 As shown, the selector has three contacts C1, C2, and C3. C1 and C2 are respectively connected to two data input terminals IN1 and IN2, and C3 is connected to the output terminal OUT. The control signal CTL can control C1 or C2 to be connected to C3, so as to implement different data input terminals as the output.

[0065] For the selector of the general computing resource pool, the data input terminals IN1 and IN2 can be respectively connected to the clock output terminal of the CPU and the output terminal of the first clock generator to receive the common clock signal and the independent clock signal respectively. When the control signal CTL controls the connection between the contact C1 and the contact C3, the selector uses the common clock signal as the current clock signal of the general computing resource pool. When the control signal CTL controls the connection between the data contact C2 and the contact C3, the selector uses the independent clock signal as the current clock signal of the general computing resource pool.

[0066] For the selector of the switching unit, the data input terminals IN1 and IN2 can be respectively connected to the output terminals of the general computing resource pool and the second clock generator to receive the common clock signal and the independent clock signal respectively. When the control signal CTL controls the connection between the contact C1 and the contact C3, the selector uses the common clock signal as the current clock signal of the switching unit. When the control signal CTL controls the connection between the data contact C2 and the contact C3, the selector uses the independent clock signal as the current clock signal of the switching unit. Specifically, the connection between the data input terminal IN1 and the general computing resource pool is as follows: the data input terminal IN1 is connected to the output terminal of the common clock driving circuit of the switching unit, and the input terminal of the common clock driving circuit is connected to the output terminal of the clock driving circuit of the general computing resource pool.

[0067] For the selector of the accelerated computing resource pool, data input terminals IN1 and IN2 can be connected to the output terminals of the switching unit and the third clock generator, respectively, to receive a common clock signal and an independent clock signal, respectively. When the control signal CTL controls the connection between contact C1 and contact C3, the selector uses the common clock signal as the current clock signal of the accelerated computing resource pool. When the control signal CTL controls the connection between data contact C2 and contact C3, the selector uses the independent clock signal as the current clock signal of the accelerated computing resource pool. Specifically, the connection between the data input terminal IN1 and the switching unit is as follows: the data input terminal IN1 is connected to the output terminal of the clock drive circuit of the switching unit.

[0068] In some embodiments, reference Figure 7 As shown, the clock driver circuit can be connected after the clock buffer. This way, the common clock is not driven before it is used within the general computing resource pool and the switching unit. Instead, it is driven before the common clock signal is transmitted from the general computing resource pool to the switching unit over long distances, and before it is transmitted from the switching unit to the accelerated computing resource pool over long distances. This minimizes premature driving of the common clock signal, which can cause it to attenuate within the general computing resource pool and the switching unit. This maximizes the quality of the common clock signal transmitted to the switching unit and the accelerated computing resource pool, and reduces clock skew of the common clock signal.

[0069] In the general computing resource pool, the data input terminal of the clock driving circuit of the first clock switching circuit is connected to the output channel of the clock buffer of the first clock switching circuit.

[0070] In the switching unit, two data input terminals of the selector of the second clock switching circuit are respectively connected to the output terminal of the second clock generator and the output terminal of the clock driving circuit of the first clock switching circuit, and are configured to receive the independent clock signal generated by the second clock generator and the driven common clock signal output by the first clock switching circuit. The data input terminal of the clock driving circuit of the second clock switching circuit is connected to the output channel of the clock buffer of the second clock switching circuit.

[0071] In the switching unit, the two data input terminals of the selector of the third clock switching circuit are respectively connected to the output terminal of the third clock generator and the output terminal of the clock driving circuit of the second clock switching circuit, and are configured to receive the independent clock signal generated by the third clock generator and the driven common clock signal output by the second clock switching circuit. The data input terminal of the clock driving circuit of the third clock switching circuit is connected to the output channel of the clock buffer of the third clock switching circuit, and the output terminal of the clock driving circuit of the third clock switching circuit is connected to the graphics processor interface, so that the graphics processor connected to the graphics processor interface can operate based on the driven clock signal.

[0072] In some embodiments, with reference to Figure 7 as shown, the above control unit is further connected to the above clock driving circuit, and the control unit is further configured to control the working state of the clock driving circuit, and the working states include: driving state, bridging state, and disconnect state. In this way, the clock driving circuit can be accurately controlled by the control unit to make the clock driving circuits of the general computing resource pool, the switching unit, and the accelerated computing resource pool all in the driving state in the common clock mode, or, in the independent clock mode, to control the clock driving circuits of the general computing resource pool and the switching unit to be in the disconnect state, and the driving circuit of the accelerated computing resource pool to be in the bridging state. Thus, not only can the signal strength of the common clock signal be ensured, but also energy can be saved in the independent clock state.

[0073] Among them, the above driving state is used to amplify the signal. The bridging state is used for connection and does not process the signal. At this time, the clock driving circuit is only used for transmission and can be regarded as a transmission line. The disconnect state is used to disconnect the connection and does not transmit the signal.

[0074] In a possible embodiment, with reference to Figure 7 as shown, the above control unit is further connected to respective clock generators, and is configured to control the clock generators to be in the working state or the idle state, and the working states include the spread spectrum state and the non-spread spectrum state. In this way, it is possible to select whether the clock generator performs spread spectrum according to the actual scenario. In a scenario with severe electromagnetic interference, the quality of the independent clock signal is poor, and the clock generator can be controlled to perform spread spectrum. This SRIS (Separate Reference Input with Spread Spectrum, independent reference clock using spread spectrum technology) can improve the quality of the independent clock signal; in a scenario with small electromagnetic interference in the independent clock signal, the clock generator is controlled not to perform spread spectrum. This SRNS (Separate Reference Input without Spread Spectrum, independent reference clock without using spread spectrum technology) can reduce the complexity of the independent clock signal, and reduce the delay and jitter of the independent clock signal. In this way, it is possible to flexibly control whether the clock generator is in the working state according to the actual scenario.

[0075] Specifically, the output end of the control unit of the general computing resource pool is connected to the input end of the first clock generator, the output end of the control unit of the switching unit is connected to the input end of the second clock generator, and the output end of the control unit of the accelerated computing resource pool is connected to the input end of the third clock generator.

[0076] In some embodiments, the above-mentioned general computing resource pool includes a main board and an expansion board. A first clock generator, a central processing unit, a control unit, a multiplexer (MUX), and a clock buffer (ClkBuffer) are provided on the main board. A clock driving circuit and an expansion slot for inserting a connector are provided on the expansion board. The connector is used to connect to a switching unit. In this way, when the clock signal output is abnormal, only the main board needs to be removed for inspection, which is convenient for maintenance.

[0077] Among them, the above-mentioned central processing unit is connected to an oscillator for generating a common clock signal. Therefore, the above-mentioned oscillator and the above-mentioned central processing unit are both located on the main board.

[0078] The expansion slot here is used to insert a connector, and the connector is used to connect the switching unit and the general computing resource pool. A commonly used expansion slot can be a PCIe Slot (PCIe expansion slot), and the expansion board is a PCIe expansion board, on which multiple PCIe expansion slots can be provided, and each PCIe expansion slot is connected to a CDFP connector (Common Development and Footprint Pluggable). For example, 8 PCIe expansion slots can be provided on the PCIe expansion board, each PCIe expansion slot is connected to a CDFP connector, and each CDFP can be connected to one or more data switching circuits. The CDFP connector here can be provided in a retimer (retimer card), and the retimer is used to recover and re-time the input signal. In this way, the common clock signal can be recovered again, which helps to improve the signal strength of the common clock signal, and further ensures the stability of the system in the common clock mode.

[0079] In some embodiments, referring to Figure 7 As shown, in the general computing resource pool, the output end of the central processing unit is connected to the first data input end of the selector, the output end of the first clock generator is connected to the second data input end of the selector, and the output end of the control unit is connected to the control input end of the selector; the output end of the selector is connected to the input channel of the clock buffer; the output channel of the clock buffer is connected to the input channel of the clock driving circuit, and the output channel of the clock driving circuit is connected to the switching unit through a connector; the clock driving circuit is in a driving state or a disconnected state under the control of the control unit. In this way, the embodiment of the present application can select a common clock signal or an independent clock signal through the selector, and accurately control the state of the clock driving circuit in combination with the control unit, so as to ensure the normal operation of the general computing element pool in two different modes.

[0080] It can be seen that the first data input terminal and the second input terminal of the selector serve as the two data input terminals of the clock switching unit and also as the two input terminals of the first clock switching circuit.

[0081] Referring to Figure 9 As shown, in the common clock mode, the control unit of the general computing resource pool can control the clock driving circuit of the general computing resource pool to be in a driving state to drive and amplify the common clock signal of the general computing resource pool. The selector of the general computing resource pool receives the common clock signal from the CPU and, under the control of the control unit, uses the common clock signal as the current clock signal of the general computing resource pool and outputs it to the clock buffer of the general computing resource pool. The clock buffer can output the common clock signal to the clock driving circuit. Therefore, referring to Figure 9 As shown, the common clock signal of the general computing resource pool successively passes through the central processing unit, the selector, and the clock buffer to reach the clock driving circuit and is transmitted to the common clock driving circuit of the switching unit.

[0082] In the independent clock mode, the control unit of the general computing resource pool can control the common clock driving circuit and the clock driving circuit of the general computing resource pool to be in a disconnected state. The selector of the general computing resource pool receives the independent clock signal from the first clock generator of the general computing resource pool, and the selector of the general computing resource pool, under the control of the control unit, uses the independent clock signal as the current clock signal of the general computing resource pool and outputs it to the clock buffer of the general computing resource pool. Therefore, referring to Figure 10 As shown, the independent clock signal of the general computing resource pool successively passes through the first clock generator, the selector, and the clock buffer.

[0083] In addition, in the common clock mode, the control unit can control the first clock generator to be in an idle state, that is, not working, thereby saving energy. In the independent clock mode, the control unit can control the first clock generator to be in a working state and further control the first clock generator to be specifically in a spread spectrum state or a non-spread spectrum state.

[0084] In some embodiments, referring to Figure 7 As shown, in the second clock switching circuit, a common clock driving circuit is further included before the clock switching unit for driving the common clock signal before it enters the selector. In this way, when the internal line of the switching unit is relatively long and / or the connection line from the general computing resource pool to the switching unit is relatively long, the quality of the common clock signal can be improved by two drives, further reducing the clock skew.

[0085] Specifically, the BMC can monitor the quality of the clock signal output by the clock buffer. When the quality is less than or equal to a preset quality threshold, it can control the common clock driving circuit to be in a driving state; when the quality is greater than or equal to the preset quality threshold, it can control the common clock driving circuit to be in a bridging state. In this way, the clock driving circuit can be controlled more accurately according to the actual scenario, and driving can be avoided when the signal quality is relatively good, which can save energy.

[0086] In some possible implementation manners, the above-mentioned common clock driving circuit and the clock driving circuit after the clock buffer are combined and set. In this way, the two clock driving circuits can be reused, and the size of the second clock switching circuit can be minimized as much as possible.

[0087] Figure 11 It is a schematic structural diagram of the combined setting of the common clock driving circuit and the clock driving circuit in the switching unit provided by the embodiment of the present application. In order to achieve the combined setting of the above-mentioned clock driving circuit and the common clock driving circuit, refer to Figure 11 As shown, in the switching unit, the first input channel of the clock driving circuit is connected to the general computing resource pool, the first output channel of the clock driving circuit is connected to the first data input end of the selector, the output end of the second clock generator is connected to the second data input end of the selector, the output end of the control unit is connected to the control input end of the selector, and the output end of the selector is connected to the input channel DIF_IN_P / N of the clock buffer, for caching the common clock signal output by the general computing resource pool into the clock buffer after the first drive by the clock driving circuit. For example, the first input channel of the clock driving circuit can be connected to the CDFP connector J24 to connect to the general computing resource pool through the CDFP connector J24.

[0088] The first output channel of the clock buffer, for example, four first output channels DIF2_P / N to DIF5_P / N, is connected to the second input channel of the clock driving circuit, for outputting the common clock signal after two drives through the second output channel of the clock driving circuit, and the second output channel of the clock driving circuit is connected to the accelerated computing resource pool. For example, the four second output channels of the clock driving circuit are connected to four CDFP connectors J20 to J23 to connect to the accelerated computing resource pool through these four CDFP connectors J20 to J23.

[0089] Under the control of the control unit, the clock driving circuit is in a driving state or a disconnected state. Specifically, in the common clock mode, the clock driving circuit is in a driving state to perform two drives on the common clock signal. In the independent clock mode, the clock driving circuit is in a disconnected state and does not transmit the independent clock signal. The independent clock signal enters the data switching circuit from the second clock generator via the selector and the clock buffer.

[0090] It can be understood that the first input channels of the above second clock switching circuit, for example, four first input channels DIF0_P / N, are connected to the output terminal of the clock driving circuit of the general computing resource pool to receive the common clock signal from the general computing resource pool; the second output channels of the second clock switching circuit are connected to one data input terminal of the selector of the acceleration computing resource pool to transmit the common clock signal to the acceleration computing resource pool.

[0091] In the embodiment of the present application, the different output channels of the clock driving circuit can be used to drive the common clock signal twice, thereby realizing the reuse of the clock driving circuit, which helps to reduce the circuit complexity and circuit size.

[0092] In some embodiments, referring to Figure 7 As shown, the second output channel of the clock buffer of the above second clock switching circuit, for example, one second output channel DIF0_P / N, is connected to the reference clock input terminal of the data exchange circuit, for example, SYS_REF_CLK_P / N, to output the common clock signal after the first drive to the data exchange circuit. In this way, the clock signals can be output to the clock driving circuit and the data exchange circuit respectively through two different output channels of the clock buffer, so as to facilitate different subsequent processing of the two identical clock signals and avoid interference between the two clock signals.

[0093] Referring to Figure 9 As shown, in the common clock mode, the control unit of the switching unit can control the clock driving circuit and the common clock driving circuit of the switching unit to be in the driving state to drive and amplify the common clock signal of the switching unit twice. The common clock driving circuit of the switching unit receives the common clock signal from the clock driving circuit of the general computing resource pool and transmits it to the selector. The selector receives the common clock signal from the common clock driving circuit of the switching unit and, under the control of the control unit, uses the common clock signal as the current clock signal of the switching unit and outputs it to the clock buffer of the switching unit. The clock buffer can output the common clock signal to the data exchange circuit and the clock driving circuit. Therefore, referring to Figure 9 As shown, the common clock signal of the switching unit reaches the data exchange circuit successively through the common clock driving circuit, the selector, and the clock buffer, and in addition, the common clock signal of the switching unit also reaches the clock driving circuit through the above clock buffer to be transmitted to the selector of the acceleration computing resource pool.

[0094] In the independent clock mode, the control unit of the switching unit can control the common clock driving circuit and the clock driving circuit of the switching unit to be in a disconnected state. The selector of the switching unit receives an independent clock signal from the second clock generator of the switching unit. Under the control of the control unit, the selector of the switching unit uses the independent clock signal as the current clock signal of the switching unit and outputs it to the clock buffer of the switching unit. The clock buffer can output the independent clock signal to the data switching circuit. Therefore, as shown in Figure 10 the independent clock signal of the switching unit reaches the data switching circuit via the second clock generator, the selector, and the clock buffer in sequence.

[0095] In addition, in the common clock mode, the control unit can control the second clock generator to be in an idle state, that is, not working, so as to save energy. In the independent clock mode, the control unit can control the second clock generator to be in a working state and further control the second clock generator to be in a specific spread spectrum state or non-spread spectrum state.

[0096] In some embodiments, the switching unit includes a management board and a data switching single board. The data switching single board includes a data switching circuit, a selector, a clock buffer, and a clock driving circuit. The management board includes a control unit and a second clock generator. A connector interface is provided on the data switching single board for inserting a connector. In this application, the switching unit is set in blocks, which is convenient for detecting and maintaining the data switching single board when an abnormality occurs in the core module data switching single board. For the multiple data switching circuits of multiple data switching single boards, in order to make them use the same second clock generator, the second clock generator needs to be set on the management board. Each data switching single board is connected to the second clock generator through an MCIO connector to receive an independent clock signal.

[0097] Among them, one end of the connector is inserted into the connector interface, and the other end of the connector is inserted into the expansion slot of the general computing resource pool. In this way, the connection between the general computing resource pool and the switching unit can be realized.

[0098] In one example, the above switching unit is provided with 10 PCIe x16 CDFP interfaces, two of which are used to connect to the general computing resource pool, and the remaining 8 CDFP interfaces are used to connect to the accelerated computing resource pool. The switching unit is also provided with 8 x16 PCIe MCIO (Modular Connector Input Output) connectors, and the MCIO connectors realize the interconnection between 8 data switching circuits through the internal MCIO cables of the chassis.

[0099] In some embodiments, one or more data exchange single boards are stacked, and one or more juxtaposed data exchange circuits are provided on each data exchange single board. Each data exchange single board can be connected to an expansion slot of a general computing resource pool through a connector, so that the number of data exchange circuits that the general computing resource pool can be connected to is M×N, where M is the number of expansion slots of the general computing resource pool and N is the number of data exchange circuits on each data exchange single board. For example, when M is 8 and N is 4, the general computing resource pool can be expanded to connect up to 32 data exchange circuits. When each data exchange circuit is connected to a GPU, the general computing resource pool can be connected to 32 GPUs. In this way, a large number of GPU expansions can be achieved, effectively improving the processing power of the server. And setting multiple data exchange circuits on each data exchange single board can improve the stability of the data exchange single board and prevent the abnormal operation of the data exchange single board caused by the abnormality of one of the data exchange circuits.

[0100] In the embodiments of the present application, each data exchange circuit corresponds to a clock buffer, but multiple data exchange circuits on the same data exchange single board share a clock drive circuit.

[0101] In some embodiments, the accelerated computing resource pool includes one or more chassis, each chassis includes one or more graphics processor boards, and each graphics processor board includes a graphics processor interface, a third clock generator, a control unit, a selector, a clock buffer, and a clock drive circuit. The graphics processor interface can be connected to a GPU. In the embodiments of the present application, the accelerated computing resource pool can be set layer by layer through the chassis and the graphics processor board, which can facilitate the management and maintenance of the accelerated computing resource pool.

[0102] In addition to the above-mentioned graphics processor boards, each chassis may further include: a fan module, an IO (In-Out, input-output) board, multiple GPUs, a GPU fixing bracket, a wind deflector, a graphics processor board, and a PSU (Power supply unit, power supply unit). Multiple GPUs and multiple Retimer cards are provided on each graphics processor board. In this way, the number of GPUs can be greatly expanded. This structure can make the best use of the internal space of the accelerated computing resource pool and connect as many GPUs as possible. For example, when the accelerated computing resource pool is provided with two graphics processor boards and each graphics processor board is provided with 6 GPUs, the accelerated computing resource pool can accommodate up to 32 GPUs at most, meeting the requirements of the fusion architecture.

[0103] A third clock generator is provided on each of the above-mentioned graphics processor boards to generate independent clock signals for each graphics processor respectively.

[0104] Each chassis in the accelerated computing resource pool has two graphics processing unit (GPU) boards: a left GPU board and a right GPU board. A third clock generator is provided on each GPU board. The CK440 clock generator is selected as the third clock generator on each GPU board. The third clock generator can output 8 independent clock signals, which are respectively transmitted to two Retimer cards. Each Retimer card receives 4 independent clock signals. Each independent clock signal of each Retimer card passes through a 1-to-2 clock buffer to output two independent clock signals, which are respectively supplied to the Retimer card and the GPU. There are two third clock generators in total for the two GPU boards in each chassis. That is to say, each chassis provides 16 independent clock signals, which are output to 16 GPUs through two clock driver circuits. Every 8 GPUs are respectively connected to 8 output channels of a clock driver circuit through 8 expansion slots. Each third clock generator is connected to the CDFP connector through 4 MUX3 selectors. When using independent clocks, the CK440 clock signal can be selected. When using a common clock, the signal output by the CDFP connector can be selected. After selection, it enters the CLK BUFFER, and each CLK BUFFER provides two clock signals for output. After being output from the CLK BUFFER, it enters the clock drive module, which is connected to 16 PCIe Slot slots to provide clock signals for 16 GPUs.

[0105] It should be noted that each of the above independent clock signals needs to correspond to a Figure 8 selector as shown. The multiple selectors corresponding to multiple independent clock signals can be regarded as a multi-input multi-output selection circuit.

[0106] It can be understood that the GPUs connected to the respective GPU interfaces on each of the above GPU boards share a third clock generator, and the clock buffer has one input channel and one or more output channels. In this way, the number of clock generators can be minimized as much as possible, the circuit complexity of the accelerated computing resource pool can be reduced, and the independence between different GPU boards can be ensured, avoiding the abnormal situation of the entire accelerated computing resource pool caused by abnormal clock signals on the GPU boards simultaneously.

[0107] Referring to Figure 7 as shown, in the accelerated computing resource pool, the first data input terminal of the selector is connected to the switching unit, the output terminal of the third clock generator is connected to the second data input terminal of the selector, and the output terminal of the control unit is connected to the control input terminal of the selector; the output terminal of the selector is connected to the input channel of the clock buffer; the output channel of the clock buffer is connected to the input channel of the clock driver circuit, and the output channel of the clock driver circuit is connected to the GPU interface through the expansion slot and the connector; the clock driver circuit is in a driving state or a bridging state under the control of the control unit.

[0108] In the common clock mode, the control unit of the acceleration computing resource pool can control the clock driving circuit of the acceleration computing resource pool to be in a driving state to drive and amplify the common clock signal of the acceleration computing resource pool. The selector of the acceleration computing resource pool receives the common clock signal from the clock driving circuit of the switching unit and, under the control of the control unit, uses the common clock signal as the current clock signal of the acceleration computing resource pool and outputs it to the clock buffer of the acceleration computing resource pool. The clock buffer can output the common clock signal to the GPU. Therefore, as shown in Figure 9 shown, the common clock signal of the acceleration computing resource pool reaches the graphics processor via the selector, the clock buffer, the clock driving circuit, and the graphics processor interface in sequence.

[0109] In the independent clock mode, the control unit of the acceleration computing resource pool can control the clock driving circuit of the acceleration computing resource pool to be in a bridging state to transmit the independent clock signal. The selector of the acceleration computing resource pool receives the independent clock signal from the third clock generator of the acceleration computing resource pool and, under the control of the control unit, uses the independent clock signal as the current clock signal of the acceleration computing resource pool and outputs it to the clock buffer of the acceleration computing resource pool. The clock buffer can output the independent clock signal to the GPU. Therefore, as shown in Figure 10 shown, the independent clock signal of the acceleration computing resource pool reaches the graphics processor via the third clock generator, the selector, the clock buffer, the clock driving circuit, and the graphics processor interface in sequence.

[0110] In addition, in the common clock mode, the control unit can control the third clock generator to be in an idle state, that is, not working, so as to save energy. In the independent clock mode, the control unit can control the third clock generator to be in a working state and further control the third clock generator to be specifically in a spread spectrum state or a non-spread spectrum state.

[0111] In summary, as shown in Figure 9 shown, in the common clock mode, the control unit controls the clock driving circuits of the general computing resource pool, the switching unit, the common clock driving circuit of the switching unit, and the clock driving circuit of the acceleration computing resource pool to be in a driving state. At this time, the common clock signal passes through the central processor, the selector of the general computing resource pool, the clock buffer of the general computing resource pool, the clock driving circuit of the general computing resource pool, the common clock driving circuit of the switching unit, the selector of the switching unit, the clock buffer of the switching unit, the clock driving circuit of the switching unit, the selector of the acceleration computing resource pool, the clock buffer of the acceleration computing resource pool, the clock driving circuit of the acceleration computing resource pool, and the graphics processor interface of the acceleration computing resource pool in sequence, and finally reaches the graphics processor.

[0112] As shown inFigure 10 As shown, in the independent clock mode, the control unit controls the clock driver circuits of the general computing resource pool, the switch unit, and the common clock driver circuit of the switch unit to be in the off state, and controls the clock driver circuit of the acceleration computing resource pool to be in the bridging state. At this time, the independent clock signal of the general computing resource pool sequentially passes through the first clock generator, the selector of the general computing resource pool, and the clock buffer of the general computing resource pool. The independent clock signal of the switch unit sequentially passes through the second clock generator, the selector of the switch unit, the clock buffer of the switch unit, and the data switching circuit of the switch unit. The independent clock signal of the acceleration computing resource pool sequentially passes through the third clock generator, the selector of the acceleration computing resource pool, the clock buffer of the acceleration computing resource pool, the clock driver circuit of the acceleration computing resource pool, and the graphics processor interface of the acceleration computing resource pool, and finally reaches the graphics processor.

[0113] In some possible implementation manners, a clock usage circuit is further connected after any one of the clock buffers in the general computing resource pool, the switch unit, and the acceleration computing resource pool, and is used to operate based on a common clock signal or an independent clock signal. For example, in the acceleration computing resource pool, a retimer card may be further connected after the clock buffer to drive the retimer card. Embodiments of the present application can drive any circuit in the general computing resource pool, the switch unit, and the acceleration computing resource pool through a common clock signal or an independent clock signal to ensure the normal operation of the general computing resource pool, the switch unit, and the acceleration computing resource pool.

[0114] It can be understood that all connectors in the embodiments of the present application are connectors provided in the retimer, and the connectors are used to recover and re-time the input signals. In this way, the transmission quality of the signals by the connectors can be improved as much as possible, which helps to improve the data processing accuracy of the server.

[0115] Finally, it should be noted that the connections between the general computing resource pool, the switch unit, and the acceleration computing resource pool of the present application can be implemented through the above-mentioned connectors.

[0116] It can be seen from the above description that the control unit of the present application has multiple control functions, including: controlling the working state of the clock generator and the working state of the clock driver circuit. Therefore, the control unit can output two control signals, namely the first control signal and the second control signal.

[0117] Figure 12 It is a schematic diagram of the control of the clock generator, the clock driver circuit, and the selector by a control unit provided by an embodiment of the present application. Figure 12 The clock generators in it include a first clock generator, a second clock generator, and a third clock generator.

[0118] Reference Figure 12 As shown, the first control signal is used to indicate the common clock mode or the independent clock mode, and is output to the clock driving circuit, the clock generator, and the selector. The clock driving circuit determines its operating state as the driving state, the bridging state, or the disconnect state according to the common clock mode or the independent clock mode. The clock generator determines whether it is in the operating state or the idle state according to the common clock mode or the independent clock mode. The selector determines to select the common clock signal or the independent clock signal as the output clock signal according to the common clock mode or the independent clock mode.

[0119] Reference Figure 12 As shown, the second control signal is used to indicate spread spectrum or non-spread spectrum, and is output to the clock generator. The clock generator determines whether it is in the spread spectrum state or the non-spread spectrum state according to the second control signal.

[0120] This application also provides a server, which is characterized by including the aforementioned computer system.

[0121] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this application can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0122] The above has introduced in detail a computer system and a server provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A computer system, characterized in that, Comprising: A general computing resource pool, including: a central processing unit, a first clock generator, and a first clock switching circuit, where the first clock switching circuit is used to switch between a common clock signal generated by the central processing unit and an independent clock signal generated by the first clock generator; A switching unit, including: a second clock generator, a second clock switching circuit, and a data switching circuit, where the second clock switching circuit is used to switch between the common clock signal and an independent clock signal generated by the second clock generator, and output it to the data switching circuit; An accelerated computing resource pool, including: a third clock generator, a third clock switching circuit, and a graphics processor interface, where the third clock switching circuit is used to switch between the common clock signal and an independent clock signal generated by the third clock generator, and output it to the graphics processor interface.

2. The system according to claim 1, wherein Any one of the first clock switching circuit, the second clock switching circuit, or the third clock switching circuit includes a clock driving circuit, and the clock driving circuit is used to drive the long-distance transmission of the common clock signal.

3. The system according to claim 2, wherein The clock switching circuit further includes: a control unit and a clock switching unit, the control unit is connected to the clock switching unit, and the control unit is used to control the clock switching unit to switch between the independent clock signal and the common clock signal.

4. The system according to claim 3, wherein The clock switching unit includes a selector and a clock buffer, the selector is connected to the control unit, and is used to cache the common clock signal or the independent clock signal into the clock buffer under the control of the control unit.

5. The system according to claim 4, wherein The clock driving circuit is connected after the clock buffer.

6. The system according to claim 5, characterized in that, The control unit is further connected to the clock driving circuit, and the control unit is further used to control the working state of the clock driving circuit, and the working state includes: a driving state, a bridging state, and a disconnect state.

7. The system according to claim 4, wherein The control unit is further connected to the respective clock generators, and is used to control the clock generators to be in a working state or an idle state, and the working state includes a spread spectrum state and a non-spread spectrum state.

8. The system according to claim 5, wherein The general computing resource pool includes a main board and an expansion board, the first clock generator, the central processing unit, the control unit, the selector, and the clock buffer are arranged on the main board, and the clock driving circuit and an expansion slot for inserting a connector are arranged on the expansion board.

9. The system according to claim 8, characterized in that, In the general computing resource pool, the output end of the central processing unit is connected to the first data input end of the selector, the output end of the first clock generator is connected to the second data input end of the selector, and the output end of the control unit is connected to the control input end of the selector; The output end of the selector is connected to the input channel of the clock buffer; The output channel of the clock buffer is connected to the input channel of the clock driving circuit, and the output channel of the clock driving circuit is connected to the switching unit through the connector; The clock driving circuit is in a driving state or a disconnect state under the control of the control unit.

10. The system according to claim 5, characterized in that, In the second clock switching circuit, a common clock driving circuit is further included before the clock switching unit for driving the common clock signal before it enters the selector.

11. The system according to claim 10, wherein The common clock driving circuit and the clock driving circuit after the clock buffer are combined and arranged.

12. The system according to claim 11, wherein In the switching unit, the first input channel of the clock driving circuit is connected to the general computing resource pool, the first output channel of the clock driving circuit is connected to the first data input end of the selector, the output end of the second clock generator is connected to the second data input end of the selector, the output end of the control unit is connected to the control input end of the selector, and the output end of the selector is connected to the input channel of the clock buffer, for caching the common clock signal output by the general computing resource pool into the clock buffer after being driven for the first time by the clock driving circuit; The first output channel of the clock buffer is connected to the second input channel of the clock driving circuit for outputting the common clock signal after being driven twice through the second output channel of the clock driving circuit, and the second output channel of the clock driving circuit is connected to the accelerated computing resource pool; Under the control of the control unit, the clock driving circuit is in a driving state or a disconnected state.

13. The system according to claim 12, wherein, The second output channel of the clock buffer is connected to the data switching circuit for outputting the common clock signal after being driven for the first time to the data switching circuit.

14. The system according to claim 5, wherein The switching unit includes a management board and a data switching single board. The data switching single board includes the data switching circuit, the selector, the clock buffer, and the clock driving circuit. The management board includes the control unit and the second clock generator. A connector interface is provided on the data switching single board for inserting a connector.

15. The system according to claim 14, characterized in that, One or more of the data switching single boards are stacked, and one or more juxtaposed data switching circuits are provided on each data switching single board.

16. The system according to claim 5, wherein The accelerated computing resource pool includes one or more chassis, each chassis includes one or more graphics processor boards, and the graphics processor boards include the graphics processor interface, the third clock generator, the control unit, the selector, the clock buffer, and the clock driving circuit.

17. The system according to claim 16, wherein The graphics processors connected to the graphics processor interface on the graphics processor board share one third clock generator, and the clock buffer has one input channel and one or more output channels.

18. The system according to claim 5, wherein In the accelerated computing resource pool, the first data input end of the selector is connected to the switching unit, the output end of the third clock generator is connected to the second data input end of the selector, and the output end of the control unit is connected to the control input end of the selector; The output end of the selector is connected to the input channel of the clock buffer; The output channel of the clock buffer is connected to the input channel of the clock driving circuit, and the output channel of the clock driving circuit is connected to the graphics processor interface through an expansion slot and a connector; Under the control of the control unit, the clock driving circuit is in a driving state or a bridging state.

19. The system according to claim 5, wherein The clock buffer is further connected to a clock usage circuit, which operates based on the common clock signal or the independent clock signal.

20. The system according to claim 8, 9, 14 or 18, characterized in that, The connector is disposed in the retimer and is configured to recover and retime the input common clock signal or the independent clock signal.

21. A server, characterized in that, A system according to any one of claims 1 to 20 is included.

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