Computer systems and servers

Abstract

The present application discloses a computer system and server, which relates to the field of computer technology, and divides the computer system into three large modules: a general computing resource pool, a switching unit, and an accelerated computing resource pool. In each large module, clock signals in two modes, a common clock signal and an independent clock signal, are provided at the same time, and can be flexibly switched between the two according to the clock switching circuit, so that the clock mode is dynamically adjusted according to the actual application scenario, and the diversification and flexibility of the clock mode are improved. When an abnormality occurs in one of the clock modes, it can be switched to another clock mode, which can ensure the normal operation of the resource pooling system as much as possible, avoid abnormal operation of the resource pooling system due to clock abnormalities, and help improve the stability of the resource pooling system. In this way, during the operation of the resource pooling system in the embodiment of the present application, a common clock signal or an independent clock signal can be selected according to the actual scenario requirements.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to computer systems and servers. Background Art

[0002] A server is a device used to perform various calculations. Its commonly used computing architecture is a resource pooling system, which can interconnect multiple graphics processing units (GPUs) to improve the server's computing power by increasing the number of GPUs.

[0003] In related technologies, the clock mode of a resource pooling system may adopt a common clock mode, an independent clock mode, or a digital clock mode. However, there are problems of a single mode and poor stability. Summary of the Invention

[0004] The present application provides a computer system and a server to at least solve the problems of single clock mode and poor stability in the related art.

[0005] The present application provides a computer system, comprising:

[0006] A general computing resource pool, comprising: a central processing unit, a first clock generator, and a first clock switching circuit, wherein the first clock switching circuit is used to switch between a common clock signal generated by the central processing unit and an independent clock signal generated by the first clock generator;

[0007] The switching unit includes: a second clock generator, a second clock switching circuit, and a data switching circuit, wherein the second clock switching circuit is used to switch the common clock signal and the independent clock signal generated by the second clock generator, and output the switching signal to the data switching circuit;

[0008] The accelerated computing resource pool includes: a third clock generator, a third clock switching circuit and a graphics processor interface. The third clock switching circuit is used to switch the common clock signal and the independent clock signal generated by the third clock generator, and output it to the graphics processor interface.

[0009] The present application also provides a server, characterized in that it includes the aforementioned computer system.

[0010] Through this application, the computer system is divided into three large modules: a general computing resource pool, a switching unit, and an accelerated computing resource pool. In each large module, clock signals in two modes, a common clock signal and an independent clock signal, are provided at the same time, and can be flexibly switched between the two according to the clock switching circuit, so that the clock mode is dynamically adjusted according to the actual application scenario, and the diversification and flexibility of the clock mode are improved. When an abnormality occurs in one of the clock modes, it can be switched to another clock mode, which can ensure the normal operation of the resource pooling system as much as possible, avoid clock abnormalities and cause abnormal operation of the resource pooling system, and help improve the stability of the resource pooling system. In this way, during the operation of the resource pooling system in the embodiment of the present application, a common clock signal or an independent clock signal can be selected according to the actual scenario requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 This is a schematic diagram of a transmission of a common clock signal provided in an embodiment of the present application;

[0013] Figure 2 This is a schematic diagram of the transmission of an independent clock signal provided in an embodiment of the present application;

[0014] Figure 3 This is a schematic diagram of a data clock signal transmission provided by an embodiment of the present application;

[0015] Figure 4 A schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0016] Figure 5 This is a schematic diagram of a common clock signal transmission process provided by an embodiment of the present application;

[0017] Figure 6 This is a schematic diagram of a transmission process of an independent clock signal provided in an embodiment of the present application;

[0018] Figure 7 is a structural diagram of another computer system provided in an embodiment of the present application;

[0019] Figure 8 This is a schematic diagram of the structure of a selector provided in an embodiment of the present application;

[0020] Figure 9 This is a schematic diagram of a common clock signal transmission process provided by an embodiment of the present application;

[0021] Figure 10 This is a schematic diagram of a transmission process of an independent clock signal provided in an embodiment of the present application;

[0022] Figure 11 This is a schematic diagram of the structure of the combined arrangement of a common clock driving circuit and a clock driving circuit in a switching unit provided in an embodiment of the present application;

[0023] Figure 12 This is a schematic diagram of a control unit providing a control of a clock generator, a clock drive circuit and a selector in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0026] Resource pooling systems interconnect multiple GPUs on a server to improve its data processing capabilities. These systems are widely used in applications such as digital transformation, AI and big data technology, and deep learning training, all of which rely on high-performance GPUs. This has driven the rapid development of heterogeneous computing servers. For example, resource pooling systems are a key solution for training large AI models. These systems interconnect GPUs and scale them out using switches, reconfiguring the tree topology into a mesh topology. This facilitates large-scale GPU deployment to meet big data demands.

[0027] The aforementioned GPUs can be interconnected using the PCIe (Peripheral Component Interconnect Express) interface. The PCIe interface is widely used to connect various high-speed devices, including GPUs, graphics cards, network cards, and solid-state drives. The stability and efficiency of PCIe data transmission are crucial to overall server performance.

[0028] During the operation of the resource pooling system described above, large amounts of data will interact, and this interaction relies on clock signals. The PCIe clock signal is the core signal that coordinates system operations and serves as the time reference for data transmission. Its quality directly determines the accuracy and reliability of data transmission.

[0029] In some related technologies, the clock signal of the resource pooling system usually provides an inherent clock mode, which has the problems of singleness and poor stability.

[0030] In order to solve the above technical problems, the embodiment of the present application provides two clock modes, namely, a common clock and an independent clock, in the resource pooling system, and can flexibly switch between the two according to the clock switching circuit, thereby realizing dynamic adjustment of the clock mode according to the actual application scenario, improving the diversity and flexibility of the clock mode, and when an abnormality occurs in one of the clock modes, it can switch to another clock mode, which can ensure the normal operation of the resource pooling system as much as possible, avoid abnormal operation of the resource pooling system due to clock abnormalities, and help improve the stability of the resource pooling system. In this way, during the operation of the resource pooling system in the embodiment of the present application, a common clock signal or an independent clock signal can be selected according to the actual scenario requirements.

[0031] In related technologies, a common clock mode is a relatively common mode, where a transmitting end and a receiving end share the same clock signal, which is also called a common clock signal. Figure 1 This is a transmission diagram of a common clock signal provided by an embodiment of the present application. Figure 1 As shown, in the common clock mode, there is a clock generator, which is used to generate a common clock signal and send it to the transmitter and the receiver at the same time, so as to control the transmitter to send data to the receiver through the common clock signal.

[0032] Different from the common clock mode mentioned above, the independent clock mode is that the transmitter and receiver use their own clock signals, which are called independent clock signals. Figure 2 This is a transmission diagram of an independent clock signal provided by an embodiment of the present application. Figure 2As shown in the figure, the transmitter has a clock generator, called the transmitter clock generator, and the receiver has another clock generator, called the receiver clock generator. These two are independent clock generators. The transmitter clock generator generates a clock signal, known as the independent transmitter clock signal, and sends it to the transmitter. The receiver clock generator generates another clock signal, known as the independent receiver clock signal, and sends it to the receiver. The transmitter uses the independent transmitter clock signal to control data transmission, and the receiver uses the independent receiver clock signal to control data reception, thus enabling data transmission between the transmitter and receiver.

[0033] In related technologies, the data clock mode is a third clock mode. It is a clock mode between the common clock mode and the independent clock mode. In the data clock mode, only the transmitting end has a clock generator. Figure 3 This is a transmission diagram of a data clock signal provided by an embodiment of the present application. Figure 3 As shown, the transmitting end has a clock generator, called the transmitting end clock generator, while the receiving end does not have a clock generator. The transmitting end clock generator generates a clock signal and sends it to the transmitting end as the data clock signal. The transmitting end sends data to the receiving end under the control of the data clock signal. At the same time, the transmitting end also sends the data clock signal to the receiving end so that the receiving end can recover the data clock signal and receive data based on it.

[0034] Of the three clock modes mentioned above, the common clock mode offers a simple structure and relatively low latency and jitter. However, it requires the transmitter and receiver to be strictly synchronized using the same clock generator, and the clock offset of all devices must be kept within a certain range (12ns). Otherwise, the sampling window will be misaligned, causing data errors. Therefore, the common clock mode is suitable for short-distance transmission but not for long-distance transmission.

[0035] In independent clock mode, the transmitter and receiver use completely independent clock signals. Data synchronization relies entirely on two clock generators, requiring the clock generators to have relatively small jitter and placing high demands on the clock generators.

[0036] Data clock mode's data synchronization relies entirely on the receiving end's clock data recovery circuit to extract the data clock signal from the data stream, which limits its transmission rate to a low maximum rate of 8GT / s (Giga Transfers per Second). Therefore, it is only suitable for some low-rate transmission scenarios, such as PCIe Gen2 (generation 2) and Gen3 (generation 3), but not for high-speed transmission scenarios, such as PCIe5.0.

[0037] Taking into account the above characteristics of the above three clock modes, this application uses independent clock mode and public clock mode in the resource pooling system, and flexibly switches according to the actual application scenario requirements.

[0038] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0039] Figure 4 A schematic diagram of the structure of a computer system provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, an embodiment of the present application provides a computer system comprising: a general computing resource pool, a switching unit, and an accelerated computing resource pool. The switching unit is connected to the general computing resource pool and the accelerated computing resource pool respectively.

[0040] The general computing resource pool includes a central processing unit (CPU), a first clock generator, and a first clock switching circuit. The CPU and the first clock generator are connected to the first clock switching circuit. The first clock switching circuit is used to switch between a common clock signal generated by the CPU and an independent clock signal generated by the first clock generator. In other words, it performs clock switching between the common clock signal generated by the CPU and the independent clock signal generated by the first clock generator.

[0041] The switching unit includes a second clock generator, a second clock switching circuit, and a data switching circuit (Switch, SW). The second clock switching circuit is connected to the second clock generator and the data switching circuit. The second clock switching circuit switches between the common clock signal and the independent clock signal generated by the second clock generator, that is, it switches between the common clock signal and the independent clock signal generated by the second clock generator and outputs the clock signal to the data switching circuit. The data switching circuit serves as the core data exchange center, performing data exchange functions between the CPU and GPU.

[0042] The accelerated computing resource pool includes: a third clock generator, a third clock switching circuit and a graphics processor interface. The third clock switching circuit is connected to the third clock generator and the graphics processor interface. The third clock switching circuit is used to switch the common clock signal and the independent clock signal generated by the third clock generator, that is, to perform clock switching between the common clock signal and the independent clock signal generated by the third clock generator, and output the clock signal to the graphics processor interface.

[0043] Based on the above architecture, the common clock signal passes through the general computing resource pool, the switching unit and the accelerated computing resource pool.

[0044] from Figure 4As can be seen in the figure, the switching unit connects the accelerated computing resource pool to the general computing resource pool to enhance the computing power of the CPU of the general computing resource pool through the GPU of the accelerated computing resource pool. Based on this, the common clock signal of the present application is generated by the CPU of the above-mentioned general computing resource pool and sent to the switching unit and the accelerated computing resource pool in sequence. The general computing resource pool is used to provide basic computing functions, and the accelerated computing resource pool is used to provide accelerated computing functions to achieve higher computing performance, parallelism, and energy efficiency. The switching unit is a high-speed data interconnection module that is closely integrated with the basic software. It connects the general computing resource pool and the accelerated computing resource pool through high-speed cables to improve the resource access efficiency of the accelerated computing resource pool. In this way, many GPUs can be expanded through the switching unit to make full use of GPU resources. Multiple data exchange circuits can be set in the switching unit to improve the data exchange performance between the CPU and GPU of the two and reduce the GPU access latency.

[0045] Specifically, in the above-mentioned general computing resource pool, the CPU is used to generate a common clock signal, and the first clock generator is used to generate an independent clock signal for the general computing resource pool. The output end of the CPU and the output end of the first clock generator are respectively connected to the two input ends of the first clock switching circuit to input the common clock signal and the independent clock signal of the general computing resource pool into the first clock switching circuit. The first clock switching circuit can select a clock signal from the common clock signal and the independent clock signal of the general computing resource pool as the current clock signal of the general computing resource pool to drive the clock using circuit of the general computing resource pool to operate. Therefore, the output end of the first clock switching circuit can be connected to the reference clock input end of the clock using circuit in the general computing resource pool, and the clock using circuit can operate based on the current clock signal of the general computing resource pool.

[0046] In the above-mentioned switching unit, the second clock generator is used to generate an independent clock signal for the switching unit, and the common clock signal used by the switching unit is the common clock signal sent by the general computing resource pool. The output end of the second clock generator is connected to an input end of the second clock switching circuit, which is used to input the independent clock signal of the switching unit into the second clock switching circuit. The other input end of the second clock switching circuit is connected to the output end of the first clock switching circuit, which is used to input the common clock signal into the second clock switching circuit. The second clock switching circuit can select a clock signal from the common clock signal and the independent clock signal of the switching unit as the current clock signal of the switching unit, and the current clock signal of the switching unit is used to drive the operation of the data exchange circuit in the switching unit. Therefore, the output end of the second clock switching circuit is connected to the reference clock input end of the data exchange circuit.

[0047] In the above-mentioned accelerated computing resource pool, the third clock generator is used to generate an independent clock signal for the accelerated computing resource pool, and the common clock signal used by the accelerated computing resource pool is the common clock signal sent by the switching unit. The output end of the third clock generator is connected to an input end of the third clock switching circuit, which is used to input the independent clock signal of the accelerated computing resource pool into the third clock switching circuit. The other input end of the third clock switching circuit is connected to the output end of the second clock switching circuit, which is used to input the common clock signal into the third clock switching circuit. The third clock switching circuit can select a clock signal from the common clock signal and the independent clock signal of the accelerated computing resource pool as the current clock signal of the accelerated computing resource pool, and the current clock signal of the accelerated computing resource pool is used to drive the GPU in the accelerated computing resource pool to run. Therefore, the GPU is connected to the output end of the third clock switching circuit through the graphics processor interface. Specifically, the input end of the graphics processor interface is connected to the output end of the third clock switching circuit, and the reference clock input end of the GPU is connected to the output end of the graphics processor interface.

[0048] from Figure 4 As can be seen, the output of the first clock switching circuit and the input of the second clock switching circuit are connected, establishing a connection between the general computing resource pool and the switching unit, for transmitting the common clock signal from the general computing resource pool to the switching unit. The output of the second clock switching circuit and the input of the third clock switching circuit are connected, establishing a connection between the switching unit and the accelerated computing resource pool, for transmitting the common clock signal from the switching unit to the accelerated computing resource pool. In this way, the common clock signal is transmitted from the general computing resource pool through the switching unit to the accelerated computing resource pool, allowing the general computing resource pool, the switching unit, and the accelerated computing resource pool to share a common clock signal.

[0049] It is understandable that based on the above Figure 4 In the computer system shown, the clock signal transmission processes corresponding to the common clock mode and the independent clock mode are different.

[0050] In the common clock mode, the first clock switching circuit, the second clock switching circuit, and the third clock switching circuit all choose to output the common clock signal. Figure 5 This is a schematic diagram of a transmission process of a common clock signal provided by an embodiment of the present application. Figure 5 As shown, the common clock signal has two transmission paths. In the first transmission path, the common clock signal sequentially passes through the CPU, the first clock switching circuit, the second clock switching circuit, the third clock switching circuit, and the graphics processor interface. In the second transmission path, the common clock signal also passes through the second clock switching circuit to reach the data exchange circuit.

[0051] In the independent clock mode, the first clock switching circuit, the second clock switching circuit, and the third clock switching circuit all choose to output independent clock signals. Figure 6 This is a schematic diagram of the transmission process of an independent clock signal provided by an embodiment of the present application. Figure 6 As shown, no clock signal transmission is required between the general computing resource pool, the switching unit, and the accelerated computing resource pool. The general computing resource pool's independent clock signal is transmitted by the first clock generator to the first clock switching circuit. The switching unit's independent clock signal is transmitted by the second clock generator, in sequence, to the second clock switching circuit and the data switching unit. The accelerated computing resource pool's independent clock signal is transmitted by the third clock generator, in sequence, to the third clock switching circuit and the graphics processor interface. When a graphics processor is connected to the graphics processor interface, the independent clock signal is further transmitted by the graphics processor interface to the graphics processor.

[0052] In summary, the implementation of this application can realize the clock mode switching of the computer system through three clock switching circuits, which can avoid abnormal operation of the resource pooling system caused by clock anomalies, and help improve the clock diversity and stability of the resource pooling system.

[0053] In one possible implementation, refer to Figure 7 As shown, any one of the first clock switching circuit, the second clock switching circuit, or the third clock switching circuit may include a clock driving circuit, which is used to drive the common clock signal for long-distance transmission. In this way, in the common clock mode, it is possible to ensure that the common clock signal has high quality when it reaches the switching unit and the accelerated computing resource pool, and the clock offset is small, which can ensure that the switching unit and the accelerated computing resource pool accurately process data, and help improve the data processing accuracy of the resource pooling system. The data driving circuit is a circuit used to amplify the signal.

[0054] In some embodiments, reference Figure 7 As shown, any of the first, second, or third clock switching circuits includes a control unit and a clock switching unit. The control unit is connected to the clock switching unit and is configured to control the clock switching unit to switch between an independent clock signal and a common clock signal. Thus, by inputting a control instruction to the control unit, the control unit can control clock mode switching based on the control unit, thereby improving clock switching accuracy.

[0055] The control unit may be any integrated circuit having a control function. For example, a commonly used control unit may be a BMC (Board Management Controller, out-of-band management unit).

[0056] In the general computing resource pool, the two data input terminals of the clock switching unit of the first clock switching circuit are respectively connected to the output terminal of the CPU and the output terminal of the first clock generator to receive the common clock signal output by the CPU and the independent clock signal output by the first clock generator. The control input terminal of the clock switching unit of the first clock switching circuit is connected to the output terminal of the control unit of the first clock switching circuit to receive the control signal output by the control unit of the first clock switching circuit. The control signal of the control unit of the first clock switching circuit is used to instruct: the clock switching unit of the first clock switching circuit selects a clock signal from the common clock signal output by the CPU and the independent clock signal output by the first clock generator as the current clock signal of the general computing resource pool. The output terminal of the clock switching unit of the first clock switching circuit is connected to the data input terminal of the clock using circuit in the general computing resource pool to drive the clock using circuit to operate.

[0057] In the switching unit, the two data input terminals of the clock switching unit of the second clock switching circuit are connected to the output terminal of the clock switching unit of the first clock switching circuit and the output terminal of the second clock generator, respectively, to receive the common clock signal output by the clock switching unit of the first clock switching circuit and the independent clock signal output by the second clock generator. The control input terminal of the clock switching unit of the second clock switching circuit is connected to the output terminal of the control unit of the second clock switching circuit to receive the control signal output by the control unit of the second clock switching circuit. The control signal is used to instruct the clock switching unit of the second clock switching circuit to select a clock signal from the common clock signal and the independent clock signal output by the second clock generator as the current clock signal of the switching unit. The output terminal of the clock switching unit of the second clock switching circuit is connected to the data input terminal of the data switching circuit in the switching unit to drive the operation of the data switching circuit.

[0058] In the accelerated computing resource pool, the two data input terminals of the clock switching unit of the third clock switching circuit are connected to the output terminal of the clock switching unit of the third clock switching circuit and the output terminal of the third clock generator, respectively, to receive the common clock signal output by the clock switching unit of the second clock switching circuit and the independent clock signal output by the third clock generator. The control input terminal of the clock switching unit of the third clock switching circuit is connected to the output terminal of the control unit of the third clock switching circuit to receive the control signal output by the control unit of the third clock switching circuit. The control signal is used to instruct the clock switching unit of the third clock switching circuit to select a clock signal from the common clock signal and the independent clock signal output by the third clock generator as the current clock signal of the accelerated computing resource pool. The output terminal of the clock switching unit of the second clock switching circuit is connected to the clock input terminal of the GPU through the graphics processor interface to drive the GPU to operate.

[0059] It can be understood that the control units of the first clock switching circuit, the second clock switching circuit and the third clock switching circuit can be reused or independently set.

[0060] In some embodiments, any one of the clock switching units in the first, second, and third clock switching circuits includes a selector and a clock buffer. The selector is connected to a control unit and configured to cache a common clock signal or an independent clock signal in the clock buffer under control of the control unit. In this manner, signal selection can be implemented by the selector, and clock signals can be cached by the clock buffer, facilitating access of multiple clock-using circuits to multiple output channels of the clock buffer.

[0061] In a general computing resource pool, the two data input terminals of the selector of the first clock switching circuit are connected to the output terminal of the CPU and the output terminal of the first clock generator, respectively, to receive the common clock signal output by the CPU and the independent clock signal output by the first clock generator. The control input terminal of the selector of the first clock switching circuit is connected to the output terminal of the control unit of the first clock switching circuit to receive the control signal output by the control unit of the first clock switching circuit. The control signal of the control unit of the first clock switching circuit is used to instruct the selector of the first clock switching circuit to select one clock signal from the common clock signal output by the CPU and the independent clock signal output by the first clock generator as the current clock signal of the general computing resource pool. The output terminal of the selector of the first clock switching circuit is connected to the input channel of the clock buffer of the first clock switching circuit, and the output channel of the clock buffer of the first clock switching circuit is connected to the data input terminal of the clock using circuit in the general computing resource pool to drive the clock using circuit to operate.

[0062] In the switching unit, the two data input terminals of the selector of the second clock switching circuit are connected to the output terminal of the selector of the first clock switching circuit and the output terminal of the second clock generator, respectively, to receive the common clock signal output by the selector of the first clock switching circuit and the independent clock signal output by the second clock generator. The control input terminal of the selector of the second clock switching circuit is connected to the output terminal of the control unit of the second clock switching circuit to receive the control signal output by the control unit of the second clock switching circuit. The control signal is used to instruct the selector of the second clock switching circuit to select a clock signal from the common clock signal and the independent clock signal output by the second clock generator as the current clock signal of the switching unit. The output terminal of the selector of the second clock switching circuit is connected to the input channel of the clock buffer of the second clock switching circuit, and the output channel of the clock buffer of the second clock switching circuit is connected to the data input terminal of the data switching circuit in the switching unit to drive the operation of the data switching circuit.

[0063] In the accelerated computing resource pool, the two data input terminals of the selector of the third clock switching circuit are connected to the output terminal of the selector of the third clock switching circuit and the output terminal of the third clock generator, respectively, to receive the common clock signal output by the selector of the second clock switching circuit and the independent clock signal output by the third clock generator. The control input terminal of the selector of the third clock switching circuit is connected to the output terminal of the control unit of the third clock switching circuit to receive the control signal output by the control unit of the third clock switching circuit. The control signal is used to instruct the selector of the third clock switching circuit to select a clock signal from the common clock signal and the independent clock signal output by the third clock generator as the current clock signal of the accelerated computing resource pool. The output terminal of the selector of the second clock switching circuit is connected to the input channel of the clock buffer of the second clock switching circuit, and the output channel of the clock buffer of the second clock switching circuit is connected to the clock input terminal of the GPU through the graphics processor interface to drive the GPU to operate.

[0064] Figure 8 This is a schematic diagram of the structure of a selector provided by an embodiment of the present application. Figure 8 As shown, the selector has three contacts C1, C2 and C3, C1 and C2 are connected to two data input terminals IN1 and IN2 respectively, C3 is connected to the output terminal OUT, and the control signal CTL can control C1 or C2 to be connected to C3, thereby realizing different data input terminals as outputs.

[0065] For the selector of the universal computing resource pool, data input terminals IN1 and IN2 can be connected to the CPU's clock output terminal and the output terminal of the first clock generator, respectively, to receive a common clock signal and an independent clock signal. When control signal CTL connects contact C1 to contact C3, the selector uses the common clock signal as the current clock signal for the universal computing resource pool. When control signal CTL connects data contact C2 to contact C3, the selector uses the independent clock signal as the current clock signal for the universal computing resource pool.

[0066] For the selector of the switching unit, data input terminals IN1 and IN2 can be connected to the output terminals of the universal computing resource pool and the second clock generator, respectively, to receive a common clock signal and an independent clock signal, respectively. When control signal CTL controls the connection between contact C1 and contact C3, the selector uses the common clock signal as the current clock signal of the switching unit. When control signal CTL controls the connection between data contact C2 and contact C3, the selector uses the independent clock signal as the current clock signal of the switching unit. Specifically, the connection between data input terminal IN1 and the universal computing resource pool is as follows: data input terminal IN1 is connected to the output terminal of the common clock drive circuit of the switching unit, and the input terminal of the common clock drive circuit is connected to the output terminal of the clock drive circuit of the universal computing resource pool.

[0067] For the selector of the accelerated computing resource pool, data input terminals IN1 and IN2 can be connected to the output terminals of the switching unit and the third clock generator, respectively, to receive a common clock signal and an independent clock signal, respectively. When the control signal CTL controls the connection between contact C1 and contact C3, the selector uses the common clock signal as the current clock signal of the accelerated computing resource pool. When the control signal CTL controls the connection between data contact C2 and contact C3, the selector uses the independent clock signal as the current clock signal of the accelerated computing resource pool. Specifically, the connection between the data input terminal IN1 and the switching unit is as follows: the data input terminal IN1 is connected to the output terminal of the clock drive circuit of the switching unit.

[0068] In some embodiments, reference Figure 7 As shown, the clock driver circuit can be connected after the clock buffer. This way, the common clock is not driven before it is used within the general computing resource pool and the switching unit. Instead, it is driven before the common clock signal is transmitted from the general computing resource pool to the switching unit over long distances, and before it is transmitted from the switching unit to the accelerated computing resource pool over long distances. This minimizes premature driving of the common clock signal, which can cause it to attenuate within the general computing resource pool and the switching unit. This maximizes the quality of the common clock signal transmitted to the switching unit and the accelerated computing resource pool, and reduces clock skew of the common clock signal.

[0069] In the general computing resource pool, the data input terminal of the clock driving circuit of the first clock switching circuit is connected to the output channel of the clock buffer of the first clock switching circuit.

[0070] In the switching unit, two data input terminals of the selector of the second clock switching circuit are respectively connected to the output terminal of the second clock generator and the output terminal of the clock driving circuit of the first clock switching circuit, and are configured to receive the independent clock signal generated by the second clock generator and the driven common clock signal output by the first clock switching circuit. The data input terminal of the clock driving circuit of the second clock switching circuit is connected to the output channel of the clock buffer of the second clock switching circuit.

[0071] In the switching unit, the two data input terminals of the selector of the third clock switching circuit are respectively connected to the output terminal of the third clock generator and the output terminal of the clock driving circuit of the second clock switching circuit, and are configured to receive the independent clock signal generated by the third clock generator and the driven common clock signal output by the second clock switching circuit. The data input terminal of the clock driving circuit of the third clock switching circuit is connected to the output channel of the clock buffer of the third clock switching circuit, and the output terminal of the clock driving circuit of the third clock switching circuit is connected to the graphics processor interface, so that the graphics processor connected to the graphics processor interface can operate based on the driven clock signal.

[0072] In some embodiments, reference Figure 7 As shown, the control unit is also connected to the clock driving circuit, and the control unit is also used to control the working state of the clock driving circuit, which includes: driving state, bridging state and disconnected state. In this way, the clock driving circuit can be accurately controlled by the control unit to control the clock driving circuit of the general computing resource pool, the clock driving circuit of the switching unit and the driving circuit of the accelerated computing resource pool in the common clock mode to be in the driving state, or, in the independent clock mode, to control the clock driving circuit of the general computing resource pool, the clock driving circuit of the switching unit to be in the disconnected state, and the driving circuit of the accelerated computing resource pool to be in the bridged state. Thereby, not only can the signal strength of the common clock signal be guaranteed, but also energy can be saved in the independent clock state.

[0073] The aforementioned driving state is used to amplify the signal. The bridge state is used for connection without processing the signal. In this case, the clock driving circuit is only used for transmission and can be regarded as a transmission line. The disconnect state is used for disconnection without transmitting the signal.

[0074] In one possible implementation, refer to Figure 7 As shown, the control units are also connected to their respective clock generators to control their active and idle states. Active states include spread spectrum and non-spread spectrum. This allows the clock generators to be configured for spread spectrum according to the actual scenario. In scenarios with severe electromagnetic interference, where the quality of the independent clock signals is poor, the clock generators can be configured for spread spectrum. This SRIS (Separate Reference Input with Spread Spectrum) technology improves the quality of the independent clock signals. In scenarios with minimal electromagnetic interference, the clock generators can be configured for non-spread spectrum. This SRNS (Separate Reference Input without Spread Spectrum) technology reduces the complexity of the independent clock signals and minimizes their delay and jitter. This allows for flexible control of the clock generators' active state based on the actual scenario.

[0075] Specifically, the output end of the control unit of the general computing resource pool is connected to the input end of the first clock generator, the output end of the control unit of the switching unit is connected to the input end of the second clock generator, and the output end of the control unit of the accelerated computing resource pool is connected to the input end of the third clock generator.

[0076] In some embodiments, the general computing resource pool includes a mainboard and an expansion board. The mainboard is provided with a first clock generator, a central processing unit, a control unit, a multiplexer, and a clock buffer (ClkBuffer). The expansion board is provided with a clock driver circuit and an expansion slot for inserting a connector, which is used to connect to a switching unit. This facilitates maintenance by removing the mainboard for inspection when an abnormal clock signal output occurs.

[0077] The central processing unit is connected to an oscillator for generating a common clock signal. Therefore, the oscillator and the central processing unit are located together on the mainboard.

[0078] The expansion slots are used to insert connectors, which connect the switching unit to the general computing resource pool. A common expansion slot is a PCIe slot. The expansion board is a PCIe expansion board, which can have multiple PCIe expansion slots. Each PCIe expansion slot is connected to a CDFP (Common Development and Footprint Pluggable) connector. For example, a PCIe expansion board can have eight PCIe expansion slots, each connected to a CDFP connector. Each CDFP can connect to one or more data switching circuits. The CDFP connector can be installed in a retimer card, which is used to recover and retime the input signal. This allows the common clock signal to be recovered again, helping to improve the signal strength and thus ensure system stability in common clock mode.

[0079] In some embodiments, reference Figure 7 As shown, in the general computing resource pool, the output end of the central processing unit is connected to the first data input end of the selector, the output end of the first clock generator is connected to the second data input end of the selector, and the output end of the control unit is connected to the control input end of the selector; the output end of the selector is connected to the input channel of the clock buffer; the output channel of the clock buffer is connected to the input channel of the clock driving circuit, and the output channel of the clock driving circuit is connected to the switching unit through a connector; the clock driving circuit is in a driving state or a disconnected state under the control of the control unit. In this way, the embodiment of the present application can select a common clock signal or an independent clock signal through the selector, and accurately control the state of the clock driving circuit in combination with the control unit, thereby ensuring the normal operation of the general computing element pool in two different modes.

[0080] It can be seen that the first data input terminal and the second input terminal of the selector serve as two data input terminals of the clock switching unit, and also serve as two input terminals of the first clock switching circuit.

[0081] Reference Figure 9 As shown, in the common clock mode, the control unit of the universal computing resource pool can control the clock driving circuit of the universal computing resource pool to be in a driving state to drive and amplify the common clock signal of the universal computing resource pool. The selector of the universal computing resource pool receives the common clock signal from the CPU and, under the control of the control unit, outputs the common clock signal as the current clock signal of the universal computing resource pool to the clock buffer of the universal computing resource pool. The clock buffer can output the common clock signal to the clock driving circuit. Therefore, referring to Figure 9 As shown, the common clock signal of the general computing resource pool passes through the central processing unit, the selector, and the clock buffer in sequence to reach the clock driving circuit, and is then transmitted to the common clock driving circuit of the switching unit.

[0082] In the independent clock mode, the control unit of the universal computing resource pool can control the common clock driving circuit and the clock driving circuit of the universal computing resource pool to be in the disconnected state. The selector of the universal computing resource pool receives the independent clock signal from the first clock generator of the universal computing resource pool. Under the control of the control unit, the selector of the universal computing resource pool outputs the independent clock signal as the current clock signal of the universal computing resource pool to the clock buffer of the universal computing resource pool. Therefore, referring to Figure 10 As shown, the independent clock signal of the general computing resource pool passes through the first clock generator, the selector, and the clock buffer in sequence.

[0083] In addition, in the common clock mode, the control unit can control the first clock generator to be in an idle state, that is, not working, thereby saving energy. In the independent clock mode, the control unit can control the first clock generator to be in an active state, and further control the first clock generator to be in a spread spectrum state or a non-spread spectrum state.

[0084] In some embodiments, reference Figure 7 As shown, in the second clock switching circuit, a common clock driving circuit is further included before the clock switching unit, for driving the common clock signal before entering the selector. This allows the common clock signal to be driven twice to improve quality and further reduce clock skew when the internal wiring of the switching unit is relatively long and / or the connection line between the general computing resource pool and the switching unit is relatively long.

[0085] Specifically, the BMC monitors the quality of the clock signal output by the clock buffer. When the quality is less than or equal to a preset quality threshold, it controls the common clock driver circuit to be in a driving state; when the quality is greater than or equal to the preset quality threshold, it controls the common clock driver circuit to be in a bridging state. This allows for more accurate control of the clock driver circuit based on actual scenarios, avoiding driving when signal quality is good, thus saving energy.

[0086] In some possible implementations, the common clock driving circuit and the clock driving circuit after the clock buffer are combined to achieve multiplexing of the two clock driving circuits and minimize the size of the second clock switching circuit.

[0087] Figure 11 This is a schematic diagram of the structure of the common clock driving circuit and the clock driving circuit combined in the switching unit provided by the embodiment of the present application. In order to realize the combined setting of the above clock driving circuit and the common clock driving circuit, refer to Figure 11 As shown, in the switching unit, the first input channel of the clock driving circuit is connected to the general computing resource pool, the first output channel of the clock driving circuit is connected to the first data input terminal of the selector, the output terminal of the second clock generator is connected to the second data input terminal of the selector, the output terminal of the control unit is connected to the control input terminal of the selector, and the output terminal of the selector is connected to the input channel DIF_IN_P / N of the clock buffer, which is used to cache the common clock signal output by the general computing resource pool into the clock buffer after the clock driving circuit performs the first drive. For example, the first input channel of the clock driving circuit can be connected to the CDFP connector J24 to connect to the general computing resource pool through the CDFP connector J24.

[0088] The first output channels of the clock buffer, for example, the four first output channels DIF2_P / N to DIF5_P / N, are connected to the second input channels of the clock driver circuit, for outputting the common clock signal after two drives through the second output channels of the clock driver circuit. The second output channels of the clock driver circuit are connected to the accelerated computing resource pool. For example, the four second output channels of the clock driver circuit are connected to the four CDFP connectors J20 to J23, so as to be connected to the accelerated computing resource pool through these four CDFP connectors J20 to J23.

[0089] Under the control of the control unit, the clock drive circuit is in a driving state or a disconnected state. Specifically, in common clock mode, the clock drive circuit is in a driving state to drive the common clock signal twice. In independent clock mode, the clock drive circuit is in a disconnected state and does not transmit the independent clock signal. The independent clock signal is transmitted from the second clock generator via the selector and the clock buffer to the data exchange circuit.

[0090] It can be understood that the first input channel of the above-mentioned second clock switching circuit, for example, the four first input channels DIF0_P / N are connected to the output end of the clock driving circuit of the general computing resource pool to receive a common clock signal from the general computing resource pool; the second output channel of the second clock switching circuit is connected to a data input end of the selector of the accelerated computing resource pool to transmit the common clock signal to the accelerated computing resource pool.

[0091] The embodiment of the present application can realize two drives of a common clock signal through different output channels of the clock driving circuit, thereby realizing the multiplexing of the clock driving circuit, which helps to reduce circuit complexity and circuit size.

[0092] In some embodiments, reference Figure 7 As shown, the second output channel of the clock buffer of the second clock switching circuit, for example, a second output channel DIF0_P / N, is connected to the reference clock input terminal of the data exchange circuit, for example, SYS_REF_CLK_P / N, for outputting the common clock signal after the first drive to the data exchange circuit. In this way, the clock signals can be output to the clock driving circuit and the data exchange circuit respectively through the two different output channels of the clock buffer, facilitating different subsequent processing of the two identical clock signals and preventing mutual interference between the two clock signals.

[0093] Reference Figure 9 As shown, in the common clock mode, the control unit of the switching unit can control the clock driving circuit of the switching unit and the common clock driving circuit to be in the driving state to drive and amplify the common clock signal of the switching unit twice. The common clock driving circuit of the switching unit receives the common clock signal from the clock driving circuit of the general computing resource pool and transmits it to the selector. The selector receives the common clock signal from the common clock driving circuit of the switching unit and, under the control of the control unit, outputs the common clock signal as the current clock signal of the switching unit to the clock buffer of the switching unit. The clock buffer can output the common clock signal to the data switching circuit and the clock driving circuit. Therefore, referring to Figure 9 As shown, the common clock signal of the switching unit successively passes through the common clock driving circuit, the selector, and the clock buffer to reach the data switching circuit. In addition, the common clock signal of the switching unit also passes through the above-mentioned clock buffer to reach the clock driving circuit to be transmitted to the selector of the accelerated computing resource pool.

[0094] In the independent clock mode, the control unit of the switching unit can control the common clock driving circuit and the clock driving circuit of the switching unit to be in the disconnected state. The selector of the switching unit receives the independent clock signal from the second clock generator of the switching unit. Under the control of the control unit, the selector of the switching unit outputs the independent clock signal as the current clock signal of the switching unit to the clock buffer of the switching unit. The clock buffer can output the independent clock signal to the data switching circuit. Therefore, referring to Figure 10 As shown, the independent clock signal of the switching unit successively passes through the second clock generator, the selector, and the clock buffer to reach the data switching circuit.

[0095] In addition, in the common clock mode, the control unit can control the second clock generator to be in an idle state, that is, not working, thereby saving energy. In the independent clock mode, the control unit can control the second clock generator to be in an active state, and further control the second clock generator to be in a spread spectrum state or a non-spread spectrum state.

[0096] In some embodiments, the switching unit includes a management board and a data exchange board, the data exchange board includes a data exchange circuit, a selector, a clock buffer and a clock drive circuit, the management board includes a control unit and a second clock generator, and the data exchange board is provided with a connector interface for inserting a connector. The present application divides the switching unit into blocks to facilitate detection and maintenance of the data exchange board when an abnormality occurs on the core module data exchange board. For multiple data exchange circuits of multiple data exchange boards, in order to use the same second clock generator, the second clock generator needs to be provided on the management board, and each data exchange board is connected to the second clock generator through an MCIO connector to receive an independent clock signal.

[0097] The connector interface is inserted into one end of the connector, and the other end of the connector is inserted into the expansion slot of the general computing resource pool, so that the connection between the general computing resource pool and the switching unit can be realized.

[0098] In one example, the switching unit is equipped with 10 PCIe x16 CDFP interfaces, two of which are used to connect to the general computing resource pool, and the remaining eight CDFP interfaces are used to connect to the accelerated computing resource pool. The switching unit is also equipped with eight x16 PCIe MCIO (Modular Connector Input Output) connectors, which interconnect the eight data exchange circuits via MCIO cables inside the chassis.

[0099] In some embodiments, one or more data exchange boards are stacked, and one or more parallel data exchange circuits are set on each data exchange board. Each data exchange board can be connected to an expansion slot of the general computing resource pool through a connector, so that the number of data exchange circuits that can be connected to the general computing resource pool is M×N, where M is the number of expansion slots of the general computing resource pool and N is the number of data exchange circuits on each data exchange board. For example, when M is 8 and N is 4, the general computing resource pool can be extended to connect up to 32 data exchange circuits. When each data exchange circuit is connected to a GPU, the general computing resource pool can connect to 32 GPUs. In this way, a large number of GPU expansions can be achieved, effectively improving the processing power of the server. In addition, each data exchange board is provided with multiple data exchange circuits, which can improve the stability of the data exchange board and avoid abnormal operation of the data exchange board due to abnormality of one of the data exchange circuits.

[0100] In the embodiment of the present application, each data exchange circuit corresponds to a clock buffer zone, but multiple data exchange circuits on the same data exchange board share a clock driving circuit.

[0101] In some embodiments, the accelerated computing resource pool includes one or more chassis, each chassis including one or more graphics processor boards, each of which includes a graphics processor interface, a third clock generator, a control unit, a selector, a clock buffer, and a clock driver circuit. The graphics processor interface can be connected to a single GPU. Embodiments of the present application enable the accelerated computing resource pool to be configured layer by layer using chassis and graphics processor boards, making it easier to manage and maintain the accelerated computing resource pool.

[0102] In addition to the aforementioned graphics processor board, each chassis may also include: a fan module, an IO (In-Out) board, multiple GPUs, a GPU mounting bracket, an air duct, a graphics processor board, and a PSU (Power Supply Unit). Multiple GPUs and multiple retimer cards can be installed on each graphics processor board, greatly expanding the number of GPUs. This structure maximizes the use of the internal space of the accelerated computing resource pool and allows for the connection of as many GPUs as possible. For example, when the accelerated computing resource pool is equipped with two graphics processor boards, each with six GPUs, the accelerated computing resource pool can accommodate up to 32 GPUs, meeting the requirements of a converged architecture.

[0103] Each of the graphics processor boards is provided with a third clock generator to generate an independent clock signal for each graphics processor.

[0104] Each chassis in the accelerated computing resource pool contains two graphics processor boards (GPUs): a left GPU and a right GPU. Each GPU board is equipped with a third clock generator. Each GPU board uses the CK440 clock generator, which outputs eight independent clock signals, each of which is transmitted to two retimer cards. Each retimer card receives four independent clock signals, and each independent clock signal from each retimer card is converted to two independent clock signals by a 1-to-2 clock buffer. Each independent clock signal from each retimer card is then converted to two independent clock signals, one for each retimer card and one for each GPU. Each chassis has two third clock generators, providing a total of 16 independent clock signals. These signals are output to 16 GPUs via two clock driver circuits. Each of the eight GPUs is connected to the eight output channels of one clock driver circuit via eight expansion slots. Each third clock generator is connected to the CDFP connector via four MUX3 selectors. The CK440 clock signal is selected when using independent clocks, and the signal output from the CDFP connector is selected when using a common clock. After selection, it enters the CLK BUFFER. Each CLK BUFFER provides two clock signal outputs. After the CLK BUFFER output, it enters the clock driver module, connects to 16 PCIe slots, and provides clock signals for 16 GPUs.

[0105] It should be noted that each of the above independent clock signals needs to correspond to a Figure 8 The selectors shown in the figure, the multiple selectors corresponding to the multiple independent clock signals can be regarded as a multiple-input multiple-output selection circuit.

[0106] It is understood that the graphics processors connected to the various graphics processor interfaces on each graphics processor board share a common third clock generator, and the clock buffer has one input channel and one or more output channels. This minimizes the number of clock generators and reduces the circuit complexity of the accelerated computing resource pool, while also ensuring the independence of different graphics processing boards and preventing abnormalities in the entire accelerated computing resource pool caused by clock signal anomalies on both graphics processing boards.

[0107] Reference Figure 7 As shown, in the accelerated computing resource pool, the first data input end of the selector is connected to the switching unit, the output end of the third clock generator is connected to the second data input end of the selector, and the output end of the control unit is connected to the control input end of the selector; the output end of the selector is connected to the input channel of the clock buffer; the output channel of the clock buffer is connected to the input channel of the clock driving circuit, and the output channel of the clock driving circuit is connected to the graphics processor interface through the expansion slot and the connector; the clock driving circuit is in a driving state or a bridging state under the control of the control unit.

[0108] In the common clock mode, the control unit of the accelerated computing resource pool can control the clock driving circuit of the accelerated computing resource pool to be in a driving state to drive and amplify the common clock signal of the accelerated computing resource pool. The selector of the accelerated computing resource pool receives the common clock signal from the clock driving circuit of the switching unit and outputs the common clock signal as the current clock signal of the accelerated computing resource pool to the clock buffer of the accelerated computing resource pool under the control of the control unit. The clock buffer can output the common clock signal to the GPU. Therefore, referring to Figure 9 As shown, the common clock signal of the accelerated computing resource pool passes through the selector, clock buffer, clock driving circuit and graphics processor interface to reach the graphics processor.

[0109] In the independent clock mode, the control unit of the accelerated computing resource pool can control the clock driving circuit of the accelerated computing resource pool to be in a bridge state to transmit an independent clock signal. The selector of the accelerated computing resource pool receives the independent clock signal from the third clock generator of the accelerated computing resource pool and outputs the independent clock signal as the current clock signal of the accelerated computing resource pool to the clock buffer of the accelerated computing resource pool under the control of the control unit. The clock buffer can output the independent clock signal to the GPU. Therefore, referring to Figure 10 As shown, the independent clock signal of the accelerated computing resource pool reaches the graphics processor through the third clock generator, the selector, the clock buffer, the clock driving circuit and the graphics processor interface.

[0110] In addition, in the common clock mode, the control unit can control the third clock generator to be in an idle state, that is, not working, thereby saving energy. In the independent clock mode, the control unit can control the third clock generator to be in an active state, and further control the third clock generator to be in a spread spectrum state or a non-spread spectrum state.

[0111] In summary, refer to Figure 9 As shown, in the common clock mode, the control unit controls the clock drive circuit of the general computing resource pool, the clock drive circuit of the switching unit, the common clock drive circuit of the switching unit, and the clock drive circuit of the accelerated computing resource pool to be in the driving state. At this time, the common clock signal passes through the central processing unit, the selector of the general computing resource pool, the clock buffer of the general computing resource pool, the clock drive circuit of the general computing resource pool, the common clock drive circuit of the switching unit, the selector of the switching unit, the clock buffer of the switching unit, the clock drive circuit of the switching unit, the selector of the accelerated computing resource pool, the clock buffer of the accelerated computing resource pool, the clock drive circuit of the accelerated computing resource pool, and the graphics processor interface of the accelerated computing resource pool, and finally reaches the graphics processor.

[0112] Reference Figure 10 As shown, in the independent clock mode, the control unit controls the clock driving circuit of the general computing resource pool, the clock driving circuit of the switching unit, and the common clock driving circuit of the switching unit to be in the disconnected state, and controls the clock driving circuit of the accelerated computing resource pool to be in the bridged state. At this time, the independent clock signal of the general computing resource pool passes through the first clock generator, the selector of the general computing resource pool, and the clock buffer of the general computing resource pool in sequence. The independent clock signal of the switching unit passes through the second clock generator, the selector of the switching unit, the clock buffer of the switching unit, and the data switching circuit of the switching unit in sequence. The independent clock signal of the accelerated computing resource pool passes through the third clock generator, the selector of the accelerated computing resource pool, the clock buffer of the accelerated computing resource pool, the clock driving circuit of the accelerated computing resource pool, and the graphics processor interface of the accelerated computing resource pool in sequence, and finally reaches the graphics processor.

[0113] In some possible implementations, a clock using circuit is further connected after any clock buffer in the general computing resource pool, the switching unit, and the accelerated computing resource pool, for operating based on a common clock signal or an independent clock signal. For example, in the accelerated computing resource pool, a retimer card may also be connected after the clock buffer to drive the retimer card. The embodiment of the present application can drive any circuit in the general computing resource pool, the switching unit, and the accelerated computing resource pool by a common clock signal or an independent clock signal to ensure the normal operation of the general computing resource pool, the switching unit, and the accelerated computing resource pool.

[0114] It is understood that all connectors in the embodiments of the present application are connectors provided in the retimer, and the connectors are used to recover and retime the input signal. In this way, the signal transmission quality of the connector can be improved as much as possible, which helps to improve the accuracy of the server's data processing.

[0115] Finally, it should be noted that the connection between the general computing resource pool, the switching unit and the accelerated computing resource pool of the present application can be achieved through the above-mentioned connector.

[0116] As can be seen from the above description, the control unit of the present application has multiple control functions, including controlling the operating state of the clock generator and the operating state of the clock drive circuit. Therefore, the control unit can output two control signals, namely a first control signal and a second control signal.

[0117] Figure 12 1 is a schematic diagram of a control unit controlling a clock generator, a clock driving circuit, and a selector provided by an embodiment of the present application. Figure 12 The clock generator includes a first clock generator, a second clock generator and a third clock generator.

[0118] Reference Figure 12 As shown, the first control signal is used to indicate the common clock mode or the independent clock mode and is output to the clock driving circuit, the clock generator, and the selector. The clock driving circuit determines its operating state as a driving state, a bridging state, or a disconnected state based on the common clock mode or the independent clock mode. The clock generator determines whether it is in an operating state or an idle state based on the common clock mode or the independent clock mode. The selector determines whether the common clock signal or the independent clock signal is selected as the output clock signal based on the common clock mode or the independent clock mode.

[0119] Reference Figure 12 As shown, the second control signal is used to indicate spread spectrum or non-spread spectrum and is output to the clock generator. The clock generator determines whether to be in the spread spectrum state or the non-spread spectrum state according to the second control signal.

[0120] The present application also provides a server, characterized in that it includes the aforementioned computer system.

[0121] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0122] The above describes in detail a computer system and server provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, various improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A computer system, characterized in that: include: A general computing resource pool, comprising: a central processing unit, a first clock generator, and a first clock switching circuit, wherein the first clock switching circuit is configured to switch between a common clock signal generated by the central processing unit and an independent clock signal generated by the first clock generator; an exchange unit comprising: a second clock generator, a second clock switching circuit, and a data exchange circuit, wherein the second clock switching circuit is configured to switch the common clock signal and the independent clock signal generated by the second clock generator, and output the switched clock signal to the data exchange circuit; The accelerated computing resource pool includes: a third clock generator, a third clock switching circuit and a graphics processor interface, wherein the third clock switching circuit is used to switch the common clock signal and the independent clock signal generated by the third clock generator, and output the switched clock signal to the graphics processor interface.

2. The system according to claim 1, wherein: Any one of the first clock switching circuit, the second clock switching circuit or the third clock switching circuit includes a clock driving circuit, and the clock driving circuit is used to drive the common clock signal for long-distance transmission.

3. The system according to claim 2, characterized in that The clock switching circuit further includes: a control unit and a clock switching unit, wherein the control unit is connected to the clock switching unit, and the control unit is used to control the clock switching unit to switch between the independent clock signal and the common clock signal.

4. The system according to claim 3, characterized in that The clock switching unit includes a selector and a clock buffer. The selector is connected to the control unit and is used to cache the common clock signal or the independent clock signal in the clock buffer under the control of the control unit.

5. The system according to claim 4, characterized in that The clock driving circuit is connected after the clock buffer zone.

6. The system according to claim 5, characterized in that The control unit is also connected to the clock driving circuit, and is further used to control the working state of the clock driving circuit, where the working state includes: a driving state, a bridging state, and a disconnecting state.

7. The system according to claim 4, wherein: The control unit is further connected to the respective clock generators and is used to control the clock generators to be in an operating state or an idle state, wherein the operating state includes a spread spectrum state and a non-spread spectrum state.

8. The system according to claim 5, wherein: The general computing resource pool includes a main board and an expansion board. The first clock generator, the central processing unit, the control unit, the selector and the clock buffer are set on the main board, and the clock driving circuit and the expansion slot for inserting the connector are set on the expansion board.

9. The system according to claim 8, characterized in that In the general computing resource pool, the output of the central processing unit is connected to the first data input of the selector, the output of the first clock generator is connected to the second data input of the selector, and the output of the control unit is connected to the control input of the selector; The output end of the selector is connected to the input channel of the clock buffer; The output channel of the clock buffer is connected to the input channel of the clock driving circuit, and the output channel of the clock driving circuit is connected to the switching unit through the connector; The clock driving circuit is in a driving state or a disconnected state under the control of the control unit.

10. The system according to claim 5, wherein: In the second clock switching circuit, a common clock driving circuit is further included before the clock switching unit, for driving the common clock signal before entering the selector.

11. The system according to claim 10, wherein: The common clock driving circuit and the clock driving circuit after the clock buffer are combined and arranged.

12. The system according to claim 11, characterized in that In the switching unit, the first input channel of the clock driving circuit is connected to the general computing resource pool, the first output channel of the clock driving circuit is connected to the first data input terminal of the selector, the output terminal of the second clock generator is connected to the second data input terminal of the selector, the output terminal of the control unit is connected to the control input terminal of the selector, and the output terminal of the selector is connected to the input channel of the clock buffer, so as to cache the common clock signal output by the general computing resource pool into the clock buffer after being driven for the first time by the clock driving circuit; The first output channel of the clock buffer is connected to the second input channel of the clock driving circuit, and is used to output the common clock signal after being driven twice through the second output channel of the clock driving circuit, and the second output channel of the clock driving circuit is connected to the accelerated computing resource pool; The clock driving circuit is in a driving state or a disconnected state under the control of the control unit.

13. The system according to claim 12, wherein: The second output channel of the clock buffer is connected to the data exchange circuit, and is used to output the common clock signal after the first driving to the data exchange circuit.

14. The system according to claim 5, wherein: The exchange unit includes a management board and a data exchange board. The data exchange board includes the data exchange circuit, the selector, the clock buffer and the clock drive circuit. The management board includes the control unit and the second clock generator. The data exchange board is provided with a connector interface for inserting a connector.

15. The system according to claim 14, wherein: One or more data exchange boards are stacked, and each data exchange board is provided with one or more data exchange circuits arranged in parallel.

16. The system according to claim 5, wherein: The accelerated computing resource pool includes one or more chassis, each chassis includes one or more graphics processor boards, and each graphics processor board includes the graphics processor interface, the third clock generator, the control unit, the selector, the clock buffer, and the clock driving circuit.

17. The system according to claim 16, wherein: The graphics processors connected to the graphics processor interface on the graphics processor board share one third clock generator, and the clock buffer has one input channel and one or more output channels.

18. The system according to claim 5, wherein: In the accelerated computing resource pool, the first data input terminal of the selector is connected to the switching unit, the output terminal of the third clock generator is connected to the second data input terminal of the selector, and the output terminal of the control unit is connected to the control input terminal of the selector; The output end of the selector is connected to the input channel of the clock buffer; The output channel of the clock buffer is connected to the input channel of the clock driving circuit, and the output channel of the clock driving circuit is connected to the graphics processor interface through an expansion slot and a connector; The clock driving circuit is in a driving state or a bridging state under the control of the control unit.

19. The system according to claim 5, wherein: A clock using circuit is further connected after the clock buffer and is configured to operate based on the common clock signal or the independent clock signal.

20. The system of claim 8, 9, 14 or 18, wherein: The connector is provided in the reset clock and is used to recover and retime the input common clock signal or the input independent clock signal.

21. A server, characterized in that: A system comprising any one of claims 1 to 20.

Images