Intelligent PCIE SSD optimization system based on hardware acceleration

Abstract

The invention relates to the technical field of storage control, in particular to an intelligent PCIE SSD optimization system based on hardware acceleration, which comprises a channel quality monitoring module, an acceleration path identification module, a parameter mapping screening module, a balanced link loading module and a cooperative transmission execution module. According to the invention, by monitoring the signal voltage sampling value and the clock offset value in real time, dynamic evaluation of the quality of the storage channel, optimization of channel performance configuration and accurate judgment of the performance state of the channel are realized, the accuracy and efficiency of data transmission are improved, and through real-time environmental parameter monitoring, the reliability of data transmission is improved. Data paths can be automatically adjusted according to different temperature and voltage conditions, the reliability and adaptability of the system are improved, transmission parameters are automatically recognized and adjusted, the requirement for manual configuration is reduced, meanwhile, the operation delay and error rate are reduced, the overall throughput performance is enhanced, the data access speed is increased, and the system reliability and adaptability are improved. And the stability and the long-term reliability under different operation conditions are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of storage control, and particularly to an intelligent PCIE SSD optimization system based on hardware acceleration. Background Art

[0002] The technical field of storage control mainly involves the organization, management, and access control mechanisms of data within storage devices, specifically covering key technologies such as controller architecture design, interface protocol management, data scheduling strategies, write-erase balancing algorithms, error detection and correction mechanisms, cache management, power consumption control, and data consistency maintenance. In the application of PCIe SSDs, storage control particularly focuses on the queue scheduling of high-concurrency I / O requests, command initiation and completion management, efficient maintenance of the flash block mapping table, and the firmware and hardware cooperation processing mechanism to achieve the storage system performance of low latency, high throughput, and long lifespan.

[0003] Among them, the intelligent PCIe SSD optimization system is a PCIe interface solid-state drive control system based on an intelligent scheduling and resource adaptive management mechanism, used to improve the data access efficiency of SSDs in multi-service and multi-task scenarios. This solution realizes the identification, classification, and scheduling of different types of I / O requests by introducing functional components such as a load balancing scheduler, a dynamic queue allocation module, and an access mode recognizer, and adjusts the data path based on real-time performance metrics to optimize resource utilization, reduce system latency, and improve the overall throughput performance.

[0004] Traditional optimization systems lack the dynamic response ability to real-time environmental changes. The channel quality assessment is based on static preset standards and does not consider real-time physical environmental changes such as temperature fluctuations and voltage instability, resulting in frequent data transmission errors and performance degradation in actual applications. When dealing with high-concurrency I / O requests, traditional systems fail to effectively distinguish and optimize the performance of each channel, leading to uneven resource allocation and affecting the overall data processing efficiency. This fixed processing method is not flexible enough in a changing application environment and cannot fully utilize the potential performance of the hardware, restricting the performance improvement and application scope expansion of the storage system. Summary of the Invention

[0005] The purpose of the present invention is to solve the deficiencies existing in the prior art, and to propose an intelligent PCIE SSD optimization system based on hardware acceleration.

[0006] To achieve the above purpose, the present invention adopts the following technical solution: an intelligent PCIE SSD optimization system based on hardware acceleration, the system includes:

[0007] The channel quality monitoring module obtains the signal voltage sampling values and clock offset values on each Lane of the SSD, and screens based on three determination conditions: the eye diagram opening degree is less than the set graphic threshold, the voltage fluctuation is greater than the set stability threshold, and the clock offset exceeds the set synchronization threshold. Channels that meet the conditions are marked as channels that need to skip levels, and a set of channel identification sets that need to skip levels is generated;

[0008] Based on the set of channel identification sets that need to skip levels, the acceleration path recognition module calculates the deviation score value between the current channel data and the reference value, selects the GEN level with the lowest deviation score value as the recommended channel skip level, summarizes the recommended levels of all Lanes, and generates a channel skip level list;

[0009] The parameter mapping and screening module retrieves the pre-loaded GEN level configuration data in the firmware channel by channel according to the channel skip level list, corresponds to the current temperature and voltage combination, screens the target parameter combination, constructs the mapping relationship between the channel and the parameters according to the Lane number, and generates a Lane balanced loading parameter table;

[0010] Based on the Lane balanced loading parameter table, the balanced link loading module determines whether the identified channel has the balanced preparation state, assembles all channel status information into a link activation preparation record, and generates a link balance start verification list.

[0011] The improvements of the present invention are as follows: the set of channel identification sets that need to skip levels includes channel number identification, channel matching exception label, training stability determination basis, signal fluctuation identification factor, and channel priority processing identification; the channel skip level list specifically refers to the channel rate target level, rate level adaptation identification, level recommendation label, and level selection reason code; the Lane balanced loading parameter table includes balance level index, electrical configuration number, channel parameter call path, channel parameter structure key value, and configuration mapping relationship key group; the link balance start verification list is specifically a clock lock state label, impedance error determination identification, voltage response state field, channel configuration completion mark, and start confirmation label set.

[0012] The improvements of the present invention are as follows: the channel quality monitoring module includes:

[0013] The voltage fluctuation extraction sub-module obtains the signal voltage sampling values and clock offset values on each Lane of the SSD, combines the real-time monitoring data collected by the power supply voltage and temperature sensors, calculates the voltage change amplitude and current fluctuation interval value of each channel under the current operating temperature and voltage, and determines whether the voltage change amplitude is greater than the voltage stability threshold and whether the current fluctuation interval is greater than the current tolerance threshold, obtains the fluctuation offset degree of each channel under the current operating conditions, and generates current-voltage offset information;

[0014] The synchronization offset analysis sub-module, based on the current-voltage offset information, calls the clock phase data and sampling interval time data of each channel under the current power supply state, calculates the clock phase difference and signal synchronization time difference, determines whether the set synchronization threshold is exceeded, extracts the channels that exceed the threshold and marks them as synchronization abnormal channels, and retains the corresponding eye opening degree values of the abnormal channels to generate the synchronization offset amplitude of the abnormal channels;

[0015] The channel screening and determination sub-module, according to the synchronization offset amplitude of the abnormal channels, extracts the recorded eye opening degrees, calculates the change trend value of the opening degree, and determines whether it is less than the graphic stability threshold. At the same time, it combines the current-voltage offset information and offset amplitude value of the channel for combined judgment, and summarizes the channel numbers that meet the three abnormal conditions as the objects to be processed, generating a set of channel identification numbers that need to skip levels.

[0016] The improvement of the present invention is that the acceleration path recognition module includes:

[0017] The record extraction sub-module, based on the set of channel identification numbers that need to skip levels, extracts the last three GEN2, GEN3, GEN4 level training records of each numbered channel in the system, and reads the ambient temperature, voltage stability rate, and training completion duration during the corresponding training from the records to generate a set of channel training gear samples;

[0018] The similarity calculation sub-module, according to the set of channel training gear samples, reads the real-time eye opening degree, voltage change value, and training preparation time of the current channel, and performs normalization processing on each item of data in the same gear in the sample record respectively, using the formula:

[0019]

[0020] Performs operations to obtain the level deviation score value;

[0021] Among them, R c represents the level deviation score value, E m is the current eye opening degree, E r is the reference gear eye value, V m is the current voltage change value, V r is the historical voltage stability rate, T m is the training preparation time, T r is the historical training duration, S r is the reference gear level serial number;

[0022] The level screening sub-module, according to the level deviation score value, determines whether the deviation ratio is lower than the set deviation threshold, extracts the GEN level corresponding to the lowest level deviation score value in each channel score, records it as the channel skip level recommended level, and assembles and summarizes the recommended levels of each channel according to the Lane number, generating a channel skip level list.

[0023] The improvement of the present invention is that the parameter mapping and screening module includes:

[0024] The parameter calling sub-module extracts the GEN level of each channel according to the channel skip level list, retrieves the GEN level configuration data pre-loaded in the firmware channel by channel, extracts the pre-emphasis value, de-emphasis ratio, equalization coefficient group and impedance target value, organizes them into a structured parameter set according to the Lane number, and generates a channel configuration parameter structure group;

[0025] The combination matching sub-module calls the training success parameter data recorded by each channel under the current temperature and voltage combination according to the channel configuration parameter structure group, reads the historical success times, configured temperature values, historical impedance data and eye diagram opening degrees of the known parameter combinations under each channel, compares the current channel eye diagram opening situation, and uses the formula:

[0026]

[0027] Calculate to obtain the matching adaptation value of the channel parameter combination;

[0028] Among them, C z represents the combined historical training success times, E z represents the average value of the eye diagram opening degrees corresponding to the combination in the historical record, ΔT z represents the normalized temperature difference value between the current channel environment temperature and the historical configuration temperature of the corresponding combination, R ez represents the difference ratio between the current channel target impedance and the reference impedance of the corresponding combination, D z represents the total number of failures of the corresponding combination in the historical record, M pz represents the matching adaptation value of the channel parameter combination;

[0029] The mapping generation sub-module selects the parameter combination with the highest adaptation matching value for each channel according to the matching adaptation value of the channel parameter combination, establishes the key-value correspondence between the Lane number and the parameter combination, and constructs an index list in the Lane order to generate the Lane equalization loading parameter table.

[0030] The improvement of the present invention is that the equalization link loading module includes:

[0031] The parameter writing sub-module writes the pre-emphasis value, equalization coefficient group and target impedance value corresponding to each channel into the PHY register area based on the Lane equalization loading parameter table. After completing the configuration of each channel, it records the parameter writing status flag and register response delay information, establishes the mapping pair between the Lane and the parameter response status, and generates the parameter loading and writing delay value;

[0032] The feedback measurement submodule loads the write delay value according to the parameters, reads the current impedance value, voltage adjustment amplitude, and clock phase-locked time of each channel's reverse feedback after configuration, calculates the deviation between the feedback index and the target parameter, compares it with the corresponding error threshold, extracts the channel numbers for which all three errors are less than the threshold, identifies them as meeting the feedback standard, and generates a channel feedback error ratio set;

[0033] The channel confirmation submodule screens the channel numbers with qualified feedback based on the channel feedback error ratio set, extracts the configuration completion status mark, integrates the channel information that meets the balancing conditions into a unified link loading record, establishes a structured activation preparation information set, and generates a link balancing startup verification list.

[0034] The present invention is improved in that the system further comprises:

[0035] The collaborative transmission execution module initiates the training sequence TS1 instruction according to the link equalization startup checklist, issues a jump handshake request for the target GEN level, and compares the number of response channels with the total number of channels after the channel returns the TS2 confirmation response. It calculates the handshake success rate and compares it with the set success rate threshold. If the judgment passes, it instructs the SSD to enter the L0 transmission state and record the channels with successful jumps and the loaded parameter content, generating a jump equalization success mapping record;

[0036] The level-skipping equalization success mapping record includes a channel level-skipping result mapping table, a GEN level handshake success tag, a transmission status record field, a parameter loading history index, and a confirmed completion channel set.

[0037] The present invention is improved in that the collaborative transmission execution module includes:

[0038] The handshake initiation submodule generates a TS1 training request sequence for each channel based on the link equalization startup checklist and the recorded channel configuration status and GEN level configuration items, writes the GEN level target value field and issues a handshake request, records the number of TS2 response sequences and channel number sequence returned by the host, and generates a handshake response channel set;

[0039] The channel confirmation submodule counts the response ratio between the number of channel responses and the total number of transmissions according to the handshake response channel set, and calculates the channel response interval difference value and the number of handshake packet losses using the formula:

[0040]

[0041] Calculate the handshake stability coefficient of the acquisition channel;

[0042] Among them, S x Indicates the handshake stability coefficient of the channel, A x Indicates the proportion of handshake fields in the data segment sent by the channel, Lx Represents the packet loss rate of channel handshake, T x Represents the total duration of channel handshake feedback, B x Represents the number of buffer write bursts at the host receiving end corresponding to the channel, D x Represents the variance value of the handshake delay between channels;

[0043] The mapping generation sub-module excludes the channels with stability coefficients lower than the set response threshold according to the handshake stability coefficients of the channels, aggregates the remaining channels into the channel set that can enter the L0 state, retrieves the GEN level and parameter group number configured for the channels, establishes a triple mapping index table of channel number, skip level, and parameter group, integrates and generates a unified record structure in the channel order, and generates a successful skip-level balance mapping record.

[0044] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0045] In the present invention, by real-time monitoring of the signal voltage sampling value and the clock offset value, the dynamic evaluation of the storage channel quality is realized, the channel performance configuration is optimized, and by comprehensively analyzing the eye opening degree, voltage, and current fluctuations, the performance state of the channel is accurately determined, improving the accuracy and efficiency of data transmission. Through real-time monitoring of environmental parameters, the data path can be automatically adjusted according to different temperature and voltage conditions, improving the reliability and adaptability of the system. By automatically identifying and adjusting transmission parameters, the need for manual configuration is reduced, while the operation delay and error rate are reduced, enhancing the overall throughput performance, improving the data access speed, and ensuring stability and long-term reliability under different operating conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Is the system flow chart of the present invention;

[0047] Figure 2 Is the flow chart of the channel quality monitoring module of the present invention;

[0048] Figure 3 Is the flow chart of the acceleration path identification module of the present invention;

[0049] Figure 4 Is the flow chart of the parameter mapping and screening module of the present invention;

[0050] Figure 5 Is the flow chart of the equalization link loading module of the present invention;

[0051] Figure 6 Is the flow chart of the cooperative transmission execution module of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0052] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0053] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, in the description of the present invention, the meaning of "a plurality of" is two or more unless otherwise specifically defined.

[0054] Please refer to Figure 1 , the present invention provides a technical solution: an intelligent PCIE SSD optimization system based on hardware acceleration, and the system includes:

[0055] The channel quality monitoring module obtains the signal voltage sampling value and clock offset value on each Lane of the SSD, reads the eye diagram opening degree, voltage stability, and current fluctuation range of each channel, and collects the working environment parameters detected by the current power supply voltage and temperature sensor. Integrate the data group according to the Lane number, and screen based on three determination conditions: the eye diagram opening degree is less than the set graphic threshold, the voltage fluctuation is greater than the set stability threshold, and the clock offset exceeds the set synchronization threshold. Mark the channels that meet the conditions as channels to be skipped, and generate a set of channel identification to be skipped;

[0056] Based on the set of channel identification to be skipped, the acceleration path identification module reads the historical records of successfully completing GEN2, GEN3, and GEN4 link establishments in the last three trainings of each marked channel, extracts the eye diagram opening reference value, voltage stability rate, and training time-consuming records under the corresponding temperature range, calculates the deviation score value between the current channel data and the reference value, selects the GEN level with the lowest deviation score value as the recommended skip level for the channel, summarizes the recommended levels of all Lanes, and generates a channel skip level list;

[0057] The parameter mapping and screening module retrieves the GEN level configuration data pre-loaded in the firmware channel by channel according to the channel skip level list, including pre-emphasis value, de-emphasis ratio, equalization coefficient group, and target impedance value, corresponding to the current temperature and voltage combination, screens the target parameter combination, constructs the mapping relationship between the channel and the parameter according to the Lane number, and generates a Lane equalization loading parameter table;

[0058] Based on the Lane equalization loading parameter table, the equalized link loading module writes the selected parameters of each channel into the PHY register area, sets the pre-emphasis, equalization coefficient group and impedance value, reads the configuration and then feeds back the impedance matching error, voltage adjustment amplitude and clock phase-locked time in reverse. If all three feedback values are less than the set error threshold, it indicates that the channel is ready for equalization. It assembles the status information of all channels into a link activation preparation record and generates a link equalization start verification list;

[0059] According to the link equalization start verification list, the cooperative transmission execution module issues a training sequence TS1 instruction, sends a skip-level handshake request for the target GEN level, and compares the number of response channels with the total number of channels after the channel returns a TS2 confirmation response, calculates the handshake success rate and compares it with the set success rate threshold. If the determination is passed, it instructs the SSD to enter the L0 transmission state and records the channels with successful skip-level and the loaded parameter content, generating a skip-level equalization success mapping record;

[0060] The set of channels requiring skip-level identification includes channel number identification, channel matching exception label, training stability determination basis, signal fluctuation identification factor and channel priority processing identification. The channel skip-level grade list specifically refers to the channel rate target level, rate level adaptation identification, grade recommendation label and grade selection reason code. The Lane equalization loading parameter table includes equalization level index, electrical configuration number, channel parameter call path, channel parameter structure key value and configuration mapping relationship key group. The link equalization start verification list is specifically the clock locking state label, impedance error determination identification, voltage response state field, channel configuration completion mark and start confirmation label set. The skip-level equalization success mapping record includes the channel skip-level result mapping table, GEN level handshake success label, transmission state record field, parameter loading history index and confirmed completed channel set.

[0061] Please refer to Figure 2 , the channel quality monitoring module includes:

[0062] The voltage fluctuation extraction sub-module obtains the signal voltage sampling value and clock offset value on each Lane of the SSD, combines the real-time monitoring data collected by the power supply voltage and temperature sensors, calculates the voltage change amplitude and current fluctuation interval value of each channel under the current operating temperature and voltage, and determines whether the voltage change amplitude is greater than the voltage stability threshold and whether the current fluctuation interval is greater than the current tolerance threshold, obtaining the fluctuation offset degree of each channel under the current operating conditions and generating current-voltage offset information;

[0063] To obtain the signal voltage sampling values and current feedback values on all lanes of the SSD, it is necessary to call the voltage signals and current feedback data sampled once every 0.5 microseconds at each front-end sensing sampling point per channel. The time range of the data points is set to 10 microseconds, so a total of 20 groups of sample values are collected per channel and stored in the form of an array. The sample values, such as the voltage sequence, are V s1 ,V s2 ,...,V s20 , and the current sequence is I s1 ,I s2 ,...,I s20 , combined with the current supply voltage (set to 3.3V) and the real-time monitoring value of the temperature sensor (set to 50°C), a basic state of the channel operating environment is constructed. Calculate the voltage change amplitude per channel, that is, ΔV = max(V s1..s20 ) - min(V s1..s20 ). The calculation method of the current fluctuation range value is the same, set as ΔI = max(I s1..s20 ) - min(I s1..s20 ). To determine whether the channel is in an abnormal state of voltage or current fluctuation, it is necessary to set the voltage stability threshold and the current tolerance threshold. The voltage stability threshold is referenced by the recommended working voltage range of the SSD main control chip. The normal working voltage is set to 3.3V ± 4.5%, so the allowable voltage fluctuation range is ±0.1485V, rounded up to 0.15V for easy grading judgment. Therefore, a voltage fluctuation exceeding 0.3V (i.e., ±0.15V bidirectionally) is set as the voltage stability threshold. The current tolerance threshold is referenced by the current dynamic range of the PHY layer register in the signal loading state and is set to a floating range of 0.1A according to the data manual, that is, the threshold is set to 0.1A. If ΔV > 0.3V and ΔI > 0.1A for a certain channel, mark this channel as a fluctuating channel, write its number into the channel evaluation table and further enter the next-level step to determine the synchronization offset state. At this stage, it is necessary to generate the ratio of the voltage change amplitude to the current fluctuation range for subsequent channel behavior structure judgment. The formula is In the example, if ΔV = 0.35V and ΔI = 0.08A, then R vi = 0.35 / 0.08 = 4.375. In this section, to evaluate whether this ratio is abnormal, it is necessary to refer to the general power consumption stability benchmark, and its warning value is 4.0, which is determined based on the impedance voltage response balance point under the simulation board experiment. If the Rvi value exceeds 4.0, it means that the voltage response to the current change is abnormal and should trigger a channel attention mark. This ratio represents the voltage instability performance intensity of the channel under the condition of unit current fluctuation. If it exceeds the preset evaluation benchmark value of 4, it is considered that the fluctuation is serious, and the voltage-current offset ratio is recorded as an effective evaluation value and participates in the subsequent channel identification generation.

[0064] The synchronization offset analysis submodule uses the current and voltage offset information to call the clock phase data and sampling interval time data of each channel under the current power supply state, calculates the clock phase difference and signal synchronization time difference, and determines whether it exceeds the set synchronization threshold. It extracts the channels that exceed the threshold and marks them as synchronization abnormal channels. It also retains the eye opening value corresponding to the abnormal channel and generates the synchronization offset amplitude of the abnormal channel.

[0065] Based on the current-voltage offset ratio, it is necessary to further call the phase-locked signal sampling data fed back by the current clock control register of each channel, and assume that the phase-locked output of each channel is the clock reference pulse interval sequence θ1, θ2, ..., θ 20 The theoretical sampling interval of each channel is 10ns. In the actual environment, there will be perturbations. It is necessary to calculate the phase difference between consecutive sampling points. The phase difference of each channel clock is defined as Δφ=max(θ i -θ i-1 ), taking 10ns as the ideal benchmark, if channel A has θ i-1 =10.1ns,θ i =10.5ns, then Δφ=0.4ns. Here, the synchronization threshold is set according to the stable boundary value of the phase-locked loop output inside the PHY module. If the sampling point in the PLL feedback continuously deviates by more than 0.3ns, it will cause a sampling synchronization fault. Therefore, the synchronization threshold is set to 0.3ns. When Δφ>0.3ns, it is considered to be a phase-locked fluctuation state. At the same time, the eye opening value ε of the channel signal sampling is extracted. If it is a normalized value after modularization, the range is limited to 0.0, 1.0. For example, if the sampling result is ε=0.58 and Δφ>0.3ns, the channel is considered to have synchronization anomalies. The two parameter values of Δφ and ε need to be recorded to form a channel structure evaluation table. The synchronization offset amplitude is defined as S sync =Δφ×(1-ε), substitute the sample value S sync =0.4×(1-0.58)=0.168ns. The synchronization offset assessment reference value is set based on the average minimum fault tolerance of 0.15ns in the phase-locked stability assessment experiment results. When the synchronization offset amplitude exceeds this value, it is considered that the offset fluctuation affects the stable response of the system in the initial stage of training. If it is greater than the set synchronization assessment reference amplitude of 0.15ns, the channel is recorded as an abnormal channel and its number is included in the subsequent graphical trend calculation process.

[0066] The channel screening and judgment submodule extracts the recorded eye opening according to the abnormal channel synchronization offset amplitude, calculates the eye opening change trend value, and determines whether it is less than the graph stability threshold. At the same time, it combines the channel current and voltage offset information with the offset amplitude value to make a combined judgment. The channel numbers that meet all three abnormal conditions are aggregated as the objects to be processed, and a set of channel identifications that need to be skipped is generated;

[0067] According to the synchronous offset amplitude of the abnormal channel, it is necessary to perform timing analysis on the eye opening degree ε sequence recorded by the abnormal channel. Let the continuous 8 - time eye opening degree sampling of each channel be the array ε1, ε2,..., ε8, and the opening degree change trend value is the absolute average value of its first - order difference, defined as If the recorded values of a certain channel are 0.62, 0.59, 0.55, 0.54, 0.52, 0.49, 0.47, 0.45, then T ε =(|0.59 - 0.62|+...+|0.45 - 0.47|) / 7 = 0.0243. The graphic stability threshold in the opening trend judgment is set according to the acceptable range of the channel graphic quality degradation rate in the modulus determination. If it is less than 0.03, it is considered that the trend is declining and tending to converge, and it is vulnerable to non - adjustable factors. The value setting depends on twice the grating calculation accuracy error of ±0.015 under the board - level ADC reflection response as the steady - state limit, that is, 0.03. If this value is less than the graphic stability threshold of 0.03, it is judged that the opening trend converges, indicating that this channel may be subject to the co - existence state of signal interference and hardware jitter in the current environment. Then, combined with the conditions that the voltage - current offset ratio of this channel is 4.375 and the synchronous offset amplitude is 0.168 ns, a joint determination is carried out. The channel marking rule is defined as that when all three evaluation indicators exceed their corresponding thresholds, that is, the voltage - current ratio is greater than 4, the synchronous offset amplitude is greater than 0.15 ns, and the opening trend value is less than 0.03, then this channel is officially marked as a channel to be skipped, and the number is written into the structure control word, and finally a set of channel identifiers to be skipped is generated. This combination rule is used to logically separate the channels under multiple mismatches of physical interference, electrical instability, and protocol synchronization, and provide an effective initial identification set for subsequent path identification.

[0068] Please refer to Figure 3 , the acceleration path recognition module includes:

[0069] The record extraction sub - module, based on the set of channel identifiers to be skipped, extracts the last three GEN2, GEN3, GEN4 - level training records of each numbered channel in the system, and reads the corresponding environmental temperature, voltage stability rate, and training completion duration during the training from the records, and generates a channel training gear sample set;

[0070] Obtain all the channel numbers in the set of channel identifiers to be skipped. Let the channel number set be C1, C2,..., C n, the number is passed into the SSD host training log reading interface to read the training records of the last three times of GEN2, GEN3, and GEN4 levels for each numbered channel. Suppose the three records of channel C_5 are GEN2 - success, GEN3 - failure, and GEN4 - success respectively. Extract the three indicators of temperature, voltage stability rate, and training time consumed carried in the corresponding training process record fields. Set the training temperatures to 45°C, 48°C, and 50°C respectively. The voltage stability rates during the training process are recorded as 98%, 95%, and 96% respectively. The training completion durations are 240 μs, timeout, and 220 μs. For the definition of the voltage stability rate, the normalized result of the average voltage / maximum voltage is adopted. The stability reference value is set to 95%. According to the 3.3V ± 5% fluctuation range defined by JEDEC in the flash memory interface standard, that is, the stable range is from 3.135V to 3.465V. When the fluctuation is greater than ±0.165V, it is regarded as unstable. After normalization, exceeding 0.95 is considered stable. Therefore, a stability rate value greater than 0.95 recorded in the training record indicates that the voltage maintains an excellent state, and a lower value enters the non - ideal state classification. The training completion time directly reads the return value of the channel timer register, and the unit is microseconds. The generated training gear sample set structure is a three - field tuple "temperature, voltage stability rate, time consumed", which is combined into a third - order sample dictionary form after being indexed and mapped by the GEN level. For example: GEN2:{45,0.98,240}, GEN3:{48,0.95,timeout}, GEN4:{50,0.96,220}. Organize the data of each gear into the historical training mapping base of this channel, and finally generate the channel training gear sample set.

[0071] The similarity calculation sub - module reads the real - time eye - opening degree, voltage change value, and training preparation time of the current channel according to the channel training gear sample set, and performs normalization processing on each item of data in the same gear in the sample record respectively. The formula is used:

[0072]

[0073] Calculate to obtain the grade deviation score value;

[0074] Among them, R c represents the grade deviation score value, E m is the current eye - opening degree, E r is the reference gear eye - value, V m is the current voltage change value, V r is the historical voltage stability rate, T m is the training preparation time, T r is the historical training time consumed, S r is the reference gear level serial number;

[0075] According to the channel training gear sample set, read the real-time status indicators of the current channel, including the eye diagram opening degree, voltage change value, and training preparation time. Assume that the eye diagram opening degree read for the current channel C_5 in the current training state is E m = 0.72, the voltage change value is V m = 0.14V, the training preparation time is T m = 180 μs. Extract the reference values corresponding to GEN2 from the training gear sample set generated in the previous step as E r = 0.69, V r = 0.15V, T r = 240 μs. The GEN level serial number is defined as: GEN2 is S r = 2, GEN3 is 3, GEN4 is 4. To perform standardization processing on the above differences, the three participating items are expressed in the form of direct differences or square roots, and then processed with the GEN level serial number plus one as the normalization divisor, and substituted into the original formula:

[0076]

[0077] After substituting the parameters, the calculation process is as follows:

[0078] |E m - E r | = |0.72 - 0.69| = 0.03;

[0079] |V m - V r | = |0.14 - 0.15| = 0.01V;

[0080] |T m - T r | = |180 - 240| = 60, then

[0081] Substitute into the formula to get:

[0082]

[0083] Among them, E m represents the real-time eye diagram opening degree in the current training environment, and the data is collected from the PHY link monitoring module, with the unit of normalized ratio value; E r represents the opening degree value in the GEN2 training history record; V m is the voltage fluctuation amplitude within the current sampling period, and the calculation method is the maximum voltage minus the minimum voltage; V r is the average stable amplitude in the GEN2 historical record, with the unit of volt; T m is the delay counter value from the current configuration to the start of training, with the unit of microsecond; T ris the time taken to complete the previous training task in GEN2 gear; S r is the GEN level serial number. No weight factor is used in this formula. Therefore, the three feature terms have equivalent weights in the scoring value. If a weight control mechanism needs to be added later, a weighting factor can be introduced to the difference term, but the current version maintains the consistency of the comparison benchmark. The deviation threshold is set to 2.8 based on the median extreme difference of the scoring distribution between channels in the empirical training records. That is, if R c <2.8, it is considered a successful matching level. This scoring result represents the comprehensive deviation intensity of the current channel C_5 from the GEN2 training gear in the three dimensions of eye diagram, voltage, and time. The lower the value, the higher the degree of matching with the historical state, and the more suitable it is as a skip-level target. This deviation scoring value will be used to determine the level in the following paragraph.

[0084] The level screening sub-module judges whether the deviation ratio is lower than the set deviation threshold according to the level deviation scoring value, extracts the GEN level corresponding to the lowest level deviation scoring value in each channel's score, records it as the channel skip-level recommended level, and assembles and summarizes the recommended levels of each channel according to the Lane number to generate a channel skip-level list;

[0085] According to the deviation scoring value, it is necessary to screen the minimum value of the scoring results corresponding to all GEN gears of the current channel to select the GEN level with the smallest score as the channel skip-level recommended level. Suppose the scoring results of channel C_5 in the three gears are: the scoring value corresponding to GEN2 is 2.5953 (calculated in the previous paragraph), the GEN3 scoring value is 3.1821, and the GEN4 scoring value is 2.9914. Comparing the three values, the minimum value is 2.5953 corresponding to GEN2. The deviation threshold is set to 2.8, and the setting basis is the upper quartile value of the deviation degree between all channels and their matching gears statistically obtained from a large number of historical scoring data during the actual operation of the SSD device, which represents the maximum error tolerance critical point for accurate matching. This set value allows the training environment to still consider this gear reasonable under certain temperature and voltage differences. Therefore, if the scoring value is less than 2.8, it means that the channel highly coincides with the training characteristics of a certain gear, and it can be directly selected as the skip-level target. When performing the judgment step, the system first sorts the GEN scoring results and compares them with the deviation threshold of 2.8, and only screens the GEN levels less than this threshold. If there are multiple qualified ones, the minimum scoring item is selected. The scoring result of channel C_5 satisfies that GEN2 is the minimum and less than the threshold, so it is recorded as the channel recommended level GEN2, completing the scoring-level mapping action. Finally, traverse all channel numbers, summarize the recommended GEN levels of each channel in sequence according to the Lane number, form an index data structure such as: Lane0:GEN2,Lane1:GEN4,Lane2:GEN3..., and uniformly organize the format for output to generate a channel skip-level list.

[0086] Please refer to Figure 4 , the parameter mapping and filtering module includes:

[0087] The parameter call sub-module extracts the GEN level of each channel according to the channel skip level list, retrieves the GEN level configuration data pre-loaded in the firmware channel by channel, extracts the pre-emphasis value, de-emphasis ratio, equalization coefficient group and impedance target value, and organizes them into a structured parameter set according to the Lane number, generating a channel configuration parameter structure group;

[0088] According to the GEN levels of each channel contained in the channel skip level list, retrieve the configuration templates preset in the firmware channel by channel. Assume that the current processing channel is Lane_3, and its GEN recommended level is GEN3. There are 4 different configuration templates pre-loaded in the GEN3 level configuration index table. The fields recorded in the template are pre-emphasis value Pre, de-emphasis ratio Post, equalization coefficient group EqSet, and impedance target value Zref. The units of Pre and Post are dB, the unit of EqSet is the normalized level value, and the unit of Zref is ohm. The field group read from the current template is: Pre = 6dB, Post = 3dB, EqSet = 0.85, Zref = 50Ω. After associating it with the Lane number, it forms a structured array item. The channel skip level list contains a total of 8 channel numbers, from Lane_0 to Lane_7. The GEN levels cover three gears of GEN2 to GEN4. GEN2 corresponds to 3 preset templates, and GEN4 has 5 preset templates. The different number of templates is determined by the hardware firmware resource limit. After the retrieval is completed, all the configuration groups corresponding to the GEN levels of each channel are associated and sorted according to the channel number. The data structure is designed as a key-value mapping: the key is the Lane number, and the value is the configuration array. Each group of configurations in the array is represented by a field pair, and finally a channel configuration parameter structure group is formed. The data type of all configuration groups is a fixed value plus a range label. For example, the Pre value is limited to 4 - 10dB, the Post value is limited to 2 - 6dB, the EqSet is normalized to the range of 0.5 - 1.0, and the Zref is limited to the interval of 40 - 60Ω. If the read data is not within the interval range, the template is marked as invalid and excluded from the configuration set.

[0089] The combination matching sub-module calls the training success parameter data recorded for each channel under the current temperature and voltage combination according to the channel configuration parameter structure group, reads the historical success times, configured temperature values, historical impedance data and eye diagram opening degrees of the known parameter combinations for each channel, compares the current channel eye diagram opening situation, and uses the formula:

[0090]

[0091] Calculate to obtain the matching adaptation value of the channel parameter combination;

[0092] Among them, C zRepresents the number of successful times in combined historical training, E z Represents the average eye diagram opening degree corresponding to the combination in the historical record, ΔT z Represents the normalized value of the temperature difference between the current channel environment temperature and the historical configuration temperature of the corresponding combination, R ez Represents the difference ratio between the current channel target impedance and the reference impedance of the corresponding combination, D z Represents the total number of failure times that the corresponding combination appears in the historical record, M pz Represents the matching and adaptation value of the channel parameter combination;

[0093] According to the channel configuration parameter structure group, before performing the adaptability scoring on each group of parameter combinations, first collect the operating temperature value of the current channel and the actual sampled eye diagram opening degree. Set the working temperature of the current Lane_3 to 54 °C, the eye diagram opening degree to 0.73, the target impedance to 52 Ω. A total of 3 groups of available templates are found in the GEN3 level configuration, and the corresponding successful times in the historical record are C z = 7, 9, 11 times, and the eye diagram average values E z Are 0.71, 0.69, 0.74 respectively, the historical configuration temperatures are 52 °C, 53 °C, 55 °C, the impedance historical values are 50 Ω, 49 Ω, 53 Ω, and the failure times D z Are 1, 3, 2 times respectively. The absolute value of the difference between the current temperature of 54 °C and the template temperature is |ΔT z |, and it is normalized to [0, 1]. Assume the maximum allowable temperature difference is 10 °C, that is, the normalized temperature difference = actual difference / 10. The impedance difference ratio is calculated as R ez = |Z m -Z r | / Z r , where Z_m is the current channel target impedance of 52 Ω, Z_r is the template impedance. Substituting the data, the three groups of parameters are as follows:

[0094] The first group: C z = 7, E z = 0.71, ΔT z = |54 - 52| / 10 = 0.2, R ez = |52 - 50| / 50 = 0.04, D z = 1;

[0095] The second group: C z = 9, E z = 0.69, ΔT z = 0.1, R ez = 0.06, D z = 3;

[0096] The third group: C z = 11, E z = 0.74, ΔTz = 0.1, R ez = 0.019, D z = 2;

[0097] Substitute into the formula to calculate the matching adaptation value:

[0098]

[0099] The final result shows that among the three groups of templates, the matching adaptation value M of the third group of parameter combinations p3 = 2.634 is the largest. This value represents the optimal fitting degree when the current channel configuration matches the historical data, with small deviation, stable eye diagram performance, controllable impedance deviation, and low failure rate. Therefore, it is selected as the best configuration for this channel.

[0100] Parameter description:

[0101] C z : The number of times the template has been successfully trained in history, indicating the reliability of the template;

[0102] E z : The average eye diagram opening degree recorded during successful training, with a value range of [0.0, 1.0];

[0103] ΔT z : The normalization of the difference between the current temperature and the historical temperature of the template, with a normalization reference set to 10°C;

[0104] R ez : The impedance difference ratio, defined as the absolute difference between the target impedance and the historical impedance divided by the historical impedance;

[0105] D z : The number of times this combination has failed in the past, used as a failure penalty factor;

[0106] M pz : The matching adaptation value of the channel parameter combination, the larger the value, the better the matching.

[0107] The advantage of the formula is that by simultaneously introducing the eye diagram opening performance, environmental differences (temperature difference normalization), impedance differences, and historical success and failure distributions to construct a comprehensive scoring model, the scoring mechanism has anti-interference ability and multi-factor correlation, and through and ΔT z inhibits the linear amplification of extreme deviation terms and improves the stability of the model. [[ID=5⑧]]

[0108] The mapping generation sub-module selects the parameter combination with the highest adaptation matching value for each channel according to the matching adaptation value of the channel parameter combination, establishes the key-value correspondence between the Lane number and the parameter combination, and constructs an index list in Lane order to generate the Lane equalization loading parameter table;

[0109] According to the adaptation values matched for each channel combination, select the group with the highest score among the retrieved templates for each channel. Suppose the three score values of Lane_3 have been obtained, and the maximum value is M p3 = 2.634, then select the third group of configurations as the final configuration item for Lane_3. Here, a key-value relationship needs to be established to map Lane_3 to the configuration number P3 of this group. Perform this operation for other channels in sequence. The Lane numbers are arranged in ascending order starting from 0 and summarized into a structured mapping list, such as:

[0110] Lane0:P2,Lane1:P4,Lane2:P1,Lane3:P3... The record format is written into the controller data exchange block in JSON format to complete the preparation for configuration distribution. Finally, generate a Lane equalization loading parameter table for subsequent PHY register loading operations and status feedback verification. This parameter table is the core data structure in the system configuration closed-loop link and directly determines the execution result of the distributed configuration and the accuracy of the equalization path construction.

[0111] Please refer to Figure 5 , the equalization link loading module includes:

[0112] Based on the Lane equalization loading parameter table, the parameter writing sub-module writes the pre-emphasis value, equalization coefficient group, and target impedance value corresponding to each channel into the PHY register area. After completing the configuration of each channel, record the parameter writing status flag and register response delay information, establish a mapping pair between Lane and the parameter response status, and generate a parameter loading and writing delay value;

[0113] Based on the Lane equalization loading parameter table, the system sequentially calls the corresponding parameter sets for each channel number. Each item contains three control fields: pre-emphasis value, equalization coefficient group, and target impedance value. Suppose the pre-emphasis value to be written for the Lane_2 channel is 2.5 dB, the corresponding coefficient group is 0.9, 1.0, 0.85, and the target impedance value is set to 33 Ω. The system first initializes the PHY register interface status, enables the write permission channel, and writes each parameter to its corresponding register address field by field. For example, the pre-emphasis value is written to address 0xA0, the equalization coefficient group is written to addresses 0xA1 - 0xA3, and the target impedance is written to address 0xA4. After each write is completed, the register control bit is read to determine whether the write is completed, and the built-in timer module is used to record the response time from the issuance of the write instruction to the return of the register ACK signal. If the ACK responses for the three fields written to Lane_2 are 4 μs, 6 μs, and 5 μs respectively, the maximum response value is recorded as the write delay value for this channel, which is 15 μs in total. The write status flag value is a binary flag of "completed" or "failed". The failure flag appears when the register response value is incorrect or the time limit is exceeded. For example, when the response delay value exceeds 20 μs, it is recorded as a failure. In the current example, 15 μs is within the valid range. The mapping is constructed as: Lane_2 → completed, 15 μs. All channel records are summarized to generate the parameter loading write delay value.

[0114] The feedback measurement sub-module calculates the deviation value between the feedback index and the target parameter according to the parameter loading write delay value, reads the current impedance value, voltage adjustment amplitude, and clock phase-locked time that each channel feeds back in reverse after configuration, and compares them with the corresponding error thresholds. The channel numbers with all three errors less than the threshold are extracted and marked as feedback compliant, generating a set of channel feedback error ratios.

[0115] According to the parameter loading write delay value, the system enters the feedback reading stage, sequentially calls the feedback interface for each channel, and reads the three indicators of the current impedance value, voltage adjustment amplitude, and clock phase-locked time for the configured channels. Suppose the data read back after the write to Lane_2 is completed are the current impedance of 35.1 Ω, the voltage adjustment amplitude of 0.12 V, and the phase-locked time of 210 μs. Error calculations are performed with the set target impedance of 33 Ω, the reference voltage adjustment amplitude of 0.1 V, and the target phase-locked time of 200 μs, resulting in an impedance deviation of The voltage adjustment amplitude error is The phase-locked time error is The system setting error thresholds are as follows: the impedance difference threshold is 0.08, the voltage amplitude modulation threshold is 0.25, and the phase-locked time deviation threshold is 0.1. The setting basis is the signal tolerance specification allowed for the SSD link establishment. For example, the impedance deviation recommended by JEDEC does not exceed 10%, and here it is set to 8% for convergence control. The phase-locked time is set to the maximum tolerance deviation of 10% according to the stable phase-locked requirement in the control chip manual, and after normalization, it is 0.1 threshold. The voltage amplitude modulation is set to 0.25 with reference to the sampling average voltage tolerance. After all numerical calculations, none of them exceed their respective thresholds. Therefore, Lane_2 is recorded as a feedback-compliant channel, and its number and the ratio of the three errors are recorded to generate a set of channel feedback error ratios.

[0116] The channel confirmation sub-module filters the channel numbers of the feedback-compliant channels according to the set of channel feedback error ratios, extracts the configuration completion status flag, integrates the channel information that meets the equalization conditions into a unified link loading record, establishes a structured activation preparation information set, and generates a link equalization start verification list.

[0117] According to the set of channel feedback error ratios, the system filters all feedback-compliant channels, checks whether the parameter writing status flag is "completed", and further extracts the PHY controller status fields of these channels. Only the channels with the configuration confirmation flag bit of 1 read can enter the next activation preparation set generation process. Suppose Lane_2 and Lane_3 meet all conditions, and their numbers, the loaded parameter content, the response delay value, and the error value are jointly encapsulated into a structured data structure to form a complete link loading confirmation record. After the system summarizes all channel confirmation records uniformly, it organizes them in the form of a Lane index structure body to generate a link equalization start verification list. This list will be used as the basis for the decision input in the next stage of the TS handshake stage.

[0118] Please refer to Figure 6 , and the cooperative transmission execution module includes:

[0119] Based on the link equalization start verification list, the handshake initiation sub-module generates a TS1 training request sequence for each channel according to the recorded channel configuration status and GEN level configuration item, writes the GEN level target value field and sends a handshake request, records the number of TS2 response sequences returned by the host and the channel number sequence, and generates a set of handshake response channels.

[0120] According to the channel configuration status and GEN level configuration items recorded in the link balance startup check list, the system sequentially retrieves the GEN level fields and loading parameter groups corresponding to each channel, and writes them into the control section of the TS1 training sequence packet. The GEN target level item is directly assigned according to the content of the check list. For example, if the target level of Lane_4 is GEN3, the target level field in its TS1 structure is set to 03h. Subsequently, based on the TS instruction sending mechanism, the system uses the PHY channel broadcast mechanism to send the TS1 frame. Suppose there are 16 Lanes in the channel group, and the system sequentially completes the TS1 writing and sending operations for all Lanes at intervals of 500 ns. After the host receives it, it returns a TS2 response packet. The system calls the built-in TS2 detection mechanism of the controller to record the response frame in the receive buffer. Suppose the response channel number set is Lane0, Lane1, Lane3, Lane4, Lane6, Lane7, Lane9, Lane 12 , Lane 13 , a total of 9 channels, record their numbers and timestamps as receipt logs for subsequent stability judgment operations, and generate a handshake response channel set.

[0121] Based on the handshake response channel set, the channel confirmation sub-module calculates the response ratio between the number of channel responses and the total number of transmissions, and calculates the channel response interval difference value and the number of handshake packet losses. The formula is:

[0122]

[0123] Calculate the handshake stability coefficient of the channel through operation;

[0124] Among them, S x represents the handshake stability coefficient of the channel, A x represents the proportion of the handshake field in the channel data transmission segment, L x represents the channel handshake packet loss rate, T x represents the total handshake feedback duration of the channel, B x represents the buffer write burst count of the corresponding channel at the host receiving end, and D x represents the variance value of the handshake delay between channels;

[0125] Based on the handshake response channel set, it is counted that the number of TS2 response channels is 9, and the response ratio compared with the total number of transmissions of 16 is Calculate the handshake stability coefficient for each channel. Taking Lane_4 as an example, the proportion of its handshake field A x is 0.22, the packet loss rate L x is set to 0.04, the total feedback duration T x is 1.6 ms, the host burst write count B x is 3, and the handshake delay variance D xSubstituting 2.25μs2 into the formula:

[0126]

[0127] Finally:

[0128] S x = 0.0817 + 1.5 = 1.5817;

[0129] The system sets the response threshold to 1.3. Based on the stable delay mean variance determination threshold formed by the channel jitter range within ±3μs in the actual SSD link handshake behavior, and through the setting of the 95% channel stable interval in the historical response record, if the current Lane_4 result is greater than 1.3, it is determined as a stable channel. If a channel has a response coefficient lower than the threshold due to sudden delay or abnormal TS2 response time, it is removed from the candidates. Finally, the channel numbers that meet the stable conditions are selected to form a set for subsequent activation record mapping, and the channel handshake stability coefficient is generated.

[0130] The mapping generation sub-module excludes the channels with a handshake stability coefficient lower than the set response threshold according to the channel, aggregates the remaining channels into a channel set that can enter the L0 state, retrieves the GEN level and parameter group number configured for the channel, establishes a triple mapping index table of channel number, skip level, and parameter group, and integrates and generates a unified record structure in the channel order to generate a successful skip-level balance mapping record;

[0131] According to the set of channel numbers determined to be stable in the channel handshake stability coefficient, if the filtered channel set is Lane0, Lane1, Lane3, Lane4, Lane7, Lane9, the system sequentially calls the GEN skip level and the loaded parameter group number corresponding to each channel in the verification list. Suppose the skip level of Lane_4 is GEN3 and the corresponding parameter group number is P17, then record the triple {Lane_4, GEN3, P17}. After arranging all channel triples in ascending order of Lane number and outputting them as a structured record table, this table serves as a mapping reference for the subsequent data path scheduling and L0 state initialization configuration of the SSD main control program. The record format is Lane x , GEN level, parameter group number, and finally form a complete structure set to generate a successful skip-level balance mapping record.

[0132] The above is only a preferred embodiment of the present invention, and does not limit the present invention in other forms. Any person skilled in the art may use the disclosed technical content to make changes or modifications into equivalent embodiments with equivalent changes and apply them to other fields. However, as long as it does not depart from the technical content of the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. An intelligent PCIE SSD optimization system based on hardware acceleration, characterized in that, The system includes: The channel quality monitoring module acquires the signal voltage sampling values and clock offset values on each Lane of the SSD, screens based on three determination conditions: the eye diagram opening degree is less than the set graphic threshold, the voltage fluctuation is greater than the set stability threshold, and the clock offset exceeds the set synchronization threshold, marks the channels that meet the conditions as channels to be skipped, and generates a set of channel identification for channels to be skipped; The acceleration path identification module calculates the deviation score value between the current channel data and the reference value based on the set of channel identification for channels to be skipped, selects the GEN level with the lowest deviation score value as the recommended skip level for the channel, summarizes the recommended levels of all Lanes, and generates a channel skip level list; The parameter mapping and screening module retrieves the GEN level configuration data pre-loaded in the firmware channel by channel according to the channel skip level list, corresponds to the current temperature and voltage combination, screens the target parameter combination, constructs the mapping relationship between the channel and the parameter according to the Lane number, and generates a Lane balanced loading parameter table; The balanced link loading module determines whether the marked channels have the balanced preparation status based on the Lane balanced loading parameter table, assembles all channel status information into a link activation preparation record, and generates a link balance start verification list.

2. The intelligent PCIE SSD optimization system based on hardware acceleration according to claim 1, wherein The set of channel identification for channels to be skipped includes the channel number identification, the channel matching exception label, the training stability determination basis, the signal fluctuation identification factor, and the channel priority processing identification. The channel skip level list specifically refers to the channel rate target level, the rate level adaptation identification, the level recommendation label, and the level selection reason code. The Lane balanced loading parameter table includes the balance level index, the electrical configuration number, the channel parameter call path, the channel parameter structure key value, and the configuration mapping relationship key group. The link balance start verification list is specifically the clock lock status label, the impedance error determination identification, the voltage response status field, the channel configuration completion mark, and the start confirmation label set.

3. The intelligent PCIE SSD optimization system based on hardware acceleration according to claim 2, wherein, The channel quality monitoring module includes: The voltage fluctuation extraction sub-module acquires the signal voltage sampling values and clock offset values on each Lane of the SSD, combines the real-time monitoring data collected by the power supply voltage and temperature sensors, calculates the voltage change amplitude and current fluctuation interval value of each channel under the current operating temperature and voltage, and determines whether the voltage change amplitude is greater than the voltage stability threshold and whether the current fluctuation interval is greater than the current tolerance threshold, obtains the fluctuation offset degree of each channel under the current operating conditions, and generates the current-voltage offset information; The synchronization offset analysis sub-module, based on the current-voltage offset information, calls the clock phase data and sampling interval time data of each channel under the current power supply state, calculates the clock phase difference and signal synchronization time difference, determines whether it exceeds the set synchronization threshold, extracts the channels that exceed the threshold and marks them as synchronization abnormal channels, and retains the eye diagram opening degree value corresponding to the abnormal channels, and generates the abnormal channel synchronization offset amplitude; The channel screening and determination sub-module extracts the recorded eye diagram opening degree according to the abnormal channel synchronization offset amplitude, calculates the opening degree change trend value, and determines whether it is less than the graphic stability threshold. At the same time, it combines the current-voltage offset information and the offset amplitude value of the channel for combined judgment, and summarizes the channel numbers that meet the three abnormal conditions as the objects to be processed, generating a set of channel identification numbers that need to skip levels.

4. The hardware-acceleration-based intelligent PCIE SSD optimization system according to claim 3, wherein, The acceleration path recognition module includes: The record extraction sub-module extracts the last three GEN2, GEN3, and GEN4 level training records of each numbered channel in the system based on the set of channel identification numbers that need to skip levels, and reads the ambient temperature, voltage stability rate, and training completion duration during the corresponding training from the records, generating a channel training gear sample set; The similarity calculation sub-module reads the real-time eye diagram opening degree, voltage change value, and training preparation time of the current channel according to the channel training gear sample set, and performs normalization processing on each item of data in the same gear in the sample record respectively, using the formula: Calculate to obtain the level deviation score value; Among them, R c represents the level deviation score value, E m is the current eye diagram opening degree, E r is the eye diagram value of the reference gear, V m is the current voltage change value, V r is the historical voltage stability rate, T m is the training preparation time, T r is the historical training time consumption, S r is the reference gear level serial number; The level screening sub-module determines whether the deviation ratio is lower than the set deviation threshold according to the level deviation score value, extracts the GEN level corresponding to the lowest level deviation score value in each channel score, records it as the channel skip-level recommended level, and assembles and summarizes the recommended levels of each channel according to the Lane number, generating a channel skip-level list.

5. The hardware acceleration-based intelligent PCIE SSD optimization system according to claim 4, wherein The parameter mapping and screening module includes: The parameter call sub-module extracts the GEN level of each channel according to the channel skip-level list, retrieves the GEN level configuration data pre-loaded in the firmware channel by channel, extracts the pre-emphasis value, de-emphasis ratio, equalization coefficient group, and impedance target value, and organizes them into a structured parameter set according to the Lane number, generating a channel configuration parameter structure group; The combination matching sub-module calls the training success parameter data recorded by each channel under the current temperature and voltage combination according to the channel configuration parameter structure group, reads the historical success times, configured temperature value, historical impedance data, and eye diagram opening degree of the known parameter combinations under each channel, compares the current channel eye diagram opening situation, and uses the formula: Calculate to obtain the matching and adaptation value of the channel parameter combination; Among them, C z represents the number of successful combined historical trainings, E z represents the average eye diagram opening degree corresponding to the corresponding combination in the historical record, ΔT z represents the normalized temperature difference between the current channel environment temperature and the historical configuration temperature of the corresponding combination, R ez represents the difference ratio between the current channel target impedance and the reference impedance of the corresponding combination, D z represents the total number of failures of the corresponding combination in the historical record, M pz represents the matching adaptation value of the channel parameter combination; The mapping generation sub-module selects the parameter combination with the highest adaptation and matching value for each channel according to the matching and adaptation value of the channel parameter combination, establishes the key-value correspondence between the Lane number and the parameter combination, and constructs an index list in the Lane order, generating a Lane equalization loading parameter table.

6. The hardware-acceleration-based intelligent PCIE SSD optimization system according to claim 5, wherein, The equalization link loading module includes: The parameter writing sub-module writes the corresponding pre-emphasis value, equalization coefficient group, and target impedance value of each channel into the PHY register area based on the Lane equalization loading parameter table. After completing the configuration of each channel, it records the parameter writing status flag and the register response delay information, establishes the mapping pair between the Lane and the parameter response status, and generates the parameter loading and writing delay value; The feedback measurement sub-module loads the write delay value according to the parameter, reads the current impedance value, voltage adjustment amplitude, and clock phase-locked time fed back in reverse for each channel after configuration, calculates the deviation value between the feedback index and the target parameter, compares it with the corresponding error threshold, extracts the channel numbers for which all three errors are less than the threshold and marks them as feedback compliant, and generates a set of channel feedback error ratios. The channel confirmation sub-module filters the channel numbers that are feedback compliant according to the set of channel feedback error ratios, extracts the configuration completion status flag, integrates the channel information that meets the equalization condition into a unified link loading record, establishes a structured activation preparation information set, and generates a link equalization start verification list.

7. The hardware acceleration-based intelligent PCIE SSD optimization system according to claim 6, wherein The system further includes: The cooperative transmission execution module initiates a training sequence TS1 instruction according to the link equalization start verification list, sends a skip-level handshake request of the target GEN level, and compares the number of response channels with the total number of channels after the channel returns a TS2 confirmation response, calculates the handshake success rate and compares it with the set success rate threshold. If the determination passes, it instructs the SSD to enter the L0 transmission state and records the channels with successful skipping and the loaded parameter content, and generates a skip-level equalization success mapping record. The skip-level equalization success mapping record includes a channel skip result mapping table, a GEN level handshake success label, a transmission state record field, a parameter loading history index, and a confirmed completion channel set.

8. The hardware-acceleration-based intelligent PCIE SSD optimization system according to claim 7, wherein The cooperative transmission execution module includes: The handshake initiation sub-module generates a TS1 training request sequence for each channel based on the link equalization start verification list, writes the GEN level target value field and sends a handshake request according to the recorded channel configuration status and GEN level configuration item, records the number of TS2 response sequences returned by the host and the channel number sequence, and generates a handshake response channel set. The channel confirmation sub-module calculates the response ratio between the number of channel responses and the total number of transmissions according to the handshake response channel set, and calculates the channel response interval difference value and the number of handshake packet losses, using the formula: Performs operations to obtain the handshake stability coefficient of the channel. Among them, S x represents the handshake stability coefficient of the channel, A x represents the proportion of the handshake field in the data segment sent by the channel, L x represents the handshake packet loss rate of the channel, T x represents the total duration of the handshake feedback of the channel, B x represents the number of buffer write bursts of the host receiving end corresponding to the channel, D x represents the variance value of the handshake delay between channels; The mapping generation sub-module excludes the channels with a stability coefficient lower than the set response threshold according to the handshake stability coefficient of the channel, aggregates the remaining channels into a set of channels that can enter the L0 state, retrieves the GEN level and parameter group number configured for the channel, establishes a triple mapping index table of channel number, skip level, and parameter group, and integrates and generates a unified record structure in the channel order to generate a skip-level equalization success mapping record.

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