Visual editing method of multivariate reverse Polish expression

Abstract

The invention discloses a visual editing method of a multivariate reverse Polish expression, which relates to the technical field of data coding and comprises the following steps of: S1, setting business variables at least comprising a train control system exclusive logic condition and an interlocking system exclusive Boolean logic condition according to business characteristics of a rail transit signal system; s2, constructing business expressions based on the business variables, wherein the business expressions comprise a mind mapping expression and an interlocking Boolean logic arithmetic expression; s3, respectively converting the mind mapping expression and the interlocking Boolean logic arithmetic expression into corresponding target expressions; s4, performing multi-dimensional verification on the target expression based on an expression verification mechanism, and completing multi-element visual editing of the reverse Polish expression; the reverse Polish expression editing process is simplified, construction of the reverse Polish expression for specific service parameters is achieved, a channel for dynamically selecting the service parameters to modify the reverse Polish expression is provided, the editing efficiency and accuracy are improved, and the diversity and efficiency of the service reverse Polish expression are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data encoding, and specifically to a visual editing method for a multi-element reverse Polish expression. Background Art

[0002] The reverse Polish expression (postfix expression) places the operator after the operand. This expression method has significant advantages for computers, can simplify the calculation logic, improve the operation efficiency, and is a commonly used expression evaluation method in many programming languages and computing systems. However, when the current reverse Polish expression is edited independently by users, its intuitiveness and readability are relatively low, increasing the difficulty of understanding and use. Its fixed variable and operator selection and combination methods are difficult to flexibly and accurately generate expressions for the requirements of expressions with multiple types of variables, multiple operators, and even specific business requirements of users, and its writability is poor; at the same time, due to poor readability, the accuracy verification of the expression is usually the verification of conventional syntax and the number of operators, and the accuracy of checking the logical relevance between variables including operators is lacking, making it difficult to accurately judge the correctness of the expression. Summary of the Invention

[0003] The purpose of the present invention is to address the problems of low efficiency and poor effect in editing business expressions caused by the poor readability and writability of conventional reverse Polish expression editing technologies and the failure to consider business variable requirements; a visual editing method for a multi-element reverse Polish expression is proposed. By setting business variables including exclusive logic conditions of the train control system and exclusive Boolean logic conditions of the interlocking system, a business expression including a mind map expression and an interlocking Boolean logic arithmetic expression is constructed; the mind map expression and the interlocking Boolean logic arithmetic expression are respectively converted into corresponding target expressions and verified, simplifying the editing process of the reverse Polish expression, improving the editing efficiency and accuracy, realizing the construction of a reverse Polish expression for specific business parameters, providing a channel for dynamically selecting business parameters to modify the reverse Polish expression, enhancing the diversity and efficiency of the business reverse Polish expression, and overcoming the problems of poor readability and writability of conventional editing technologies and the failure to consider business variable requirements, resulting in low efficiency and poor effect in editing business expressions.

[0004] To solve the above technical problems, the technical solution adopted by the present invention is: a visual editing method for a multi-element reverse Polish expression, including the following steps: S1. Set business variables including at least exclusive logic conditions of the train control system and exclusive Boolean logic conditions of the interlocking system according to the business characteristics of the rail transit signal system; S2. Construct a business expression based on the business variables, including a mind map expression and an interlocking Boolean logic arithmetic expression; S3. Convert the mind map expression and the interlocking Boolean logic arithmetic expression into corresponding target expressions respectively; S4. Perform multi-dimensional verification on the target expression based on the expression verification mechanism to complete the multi-variable visualization editing of the reverse Polish expression.

[0005] In this solution, business variables of the exclusive business logics of the train control system and the interlocking system are set according to the business characteristics of the rail transit signal system, enabling the expression variables to directly inherit the business logic, accurately reflecting the actual requirements of the rail transit signal system, and helping to improve the pertinence and accuracy of the expressions; by constructing a mind map expression, an intuitive display of the business logic is provided, which helps users quickly understand complex business logics and can quickly check the logic correctness. The interlocking Boolean logic arithmetic expression provides an accurate arithmetic expression for facilitating logical operations and verification; then, the mind map expression and the interlocking Boolean logic arithmetic expression are converted into the target reverse Polish expression, realizing an efficient and readable reverse Polish expression editing method that includes exclusive business parameters, improving the readability and writability of the expressions; through multi-dimensional verification of the target expression, the syntax correctness and logical consistency of the reverse Polish expression are ensured, errors are promptly discovered and corrected, and the accuracy and editing efficiency of the expression are further improved.

[0006] Preferably, the S1 includes: Define business variables according to the business rules and exclusive business parameters of the train control system to obtain the first business variables of the train control system; according to the business logic of the interlocking system, use the relay variables of the electric interlocking as the second business variables of the exclusive business of the interlocking system.

[0007] Preferably, the S2 includes: Determine the first minimum granular variables for establishing the train control reverse Polish expression based on the business characteristic parameters of the rail transit signal system; respond to user requirements and select the first business variables, the first minimum granular variables, and exclusive operators to construct a mind map expression.

[0008] Preferably, the S2 further includes: Determine the second minimum granular variables for establishing the interlocking Boolean logic expression based on the relay variables of the electric interlocking; Edit the interlocking Boolean logic arithmetic expression based on business requirements by selecting the second business variables and the second minimum granular variables.

[0009] Preferably, the S3 includes: Decompose the mind map expression sequentially to obtain the first expression parameters and the first expression operators; Based on the reverse Polish expression rule, sequentially combine the first expression parameters and postpone the first expression operators to obtain the train control reverse Polish expression; Query the first expression parameter and the first expression operator in the system parameter library and the system symbol library respectively; If the query of the first expression parameter is successful and the query of the first expression operator is successful, extract the system parameter number corresponding to the first expression parameter and the system symbol number corresponding to the first expression operator, and fill them in according to the order of the train control reverse Polish expression to obtain the target train control expression.

[0010] Preferably, the S3 further includes: Decompose the interlocking Boolean logic arithmetic expression to obtain a second expression parameter and a second expression operator; Based on the reverse Polish expression rule, sequentially combine the second expression parameters, and postpone the second expression operator to obtain the target interlocking Boolean logic expression.

[0011] Preferably, in the S4, the multi-dimensional verification of the target expression based on the expression verification mechanism includes: Perform a primary verification on the target train control expression or the target interlocking Boolean logic expression according to the syntax verification mechanism, and perform a secondary verification on the target train control expression or the target interlocking Boolean logic expression according to the logic verification mechanism to obtain a standard target train control expression or target interlocking Boolean logic expression.

[0012] Preferably, the performing a primary verification on the target train control expression or the target interlocking Boolean logic expression according to the syntax verification mechanism includes: Perform nested syntax checking on the target train control expression or the target interlocking Boolean logic expression. If the number of expression parameters or expression operators does not match, an error prompt is issued at the abnormal position; Synchronously, perform capacity syntax checking on the target train control expression or the target interlocking Boolean logic expression. When the expression length is greater than or equal to the edge threshold, it is determined that the expression has exceeded the capacity, and the expression is split into several sub-expressions according to the expression splitting principle.

[0013] Preferably, the performing a secondary verification on the target train control expression or the target interlocking Boolean logic expression according to the logic verification mechanism includes: Perform a sufficient and necessary condition check on the sub-expression branches of the target train control expression or the target interlocking Boolean logic expression based on the sufficient and necessary condition mechanism. If the sufficient and necessary conditions of the corresponding service variables are missing in the sub-expression branches, an error is generated in the target expression; Frequency monitor the service variables that are non-necessary and sufficient conditions in the target train control expression or the target interlocking Boolean logic expression based on the conditional self-learning mechanism. If the occurrence frequency of the service variables with the same non-necessary and sufficient condition reaches the threshold, a variable duplication prompt is issued. Judge whether the target train control expression or the target interlocking Boolean logic expression is complete based on the expression integrity mechanism. If the target expression only has inputs but no outputs, the target expression editing fails. Based on the logical dynamic check mechanism, perform integrity check on the service functions corresponding to the service variables that are necessary and sufficient conditions in the target train control expression or the target interlocking Boolean logic expression. If the functional logic corresponding to the service variable complies with the specification, the corresponding service function item is valid.

[0014] Preferably, the method further includes: converting the mind map expression into a circuit expression. The specific steps are as follows: traverse the mind map connectors in the order from right to left of the mind map expression, and sequentially extract the connection objects on the right side of the mind map connectors, including the first expression parameter and the first expression operator. Convert the first expression operator into the corresponding logic circuit symbol, and combine the extracted first expression parameters and the first expression operator as an object set with the logic circuit symbol to generate a basic circuit expression. Until there is no more mind map connector on the right side of the last service variable, use the current service variable as the assignment variable of the circuit expression, represent it with an assignment circuit symbol, and merge it with the basic circuit expression to obtain the target circuit expression, completing the conversion of the mind map expression to the circuit expression.

[0015] Advantages of the present invention: 1. By using the method of editing a mind map, the editing process of the reverse Polish expression can be greatly simplified. Through an intuitive graphical interface and hierarchical structure, users can construct and modify the reverse Polish expression more efficiently, flexibly, and accurately, significantly improving the editing efficiency, flexibility, and accuracy. 2. Convert the expression into a circuit expression to display the target expression in the form of a circuit diagram, which can make the conditions of the reverse Polish expression more intuitive and clear. This way presents complex logical conditions in a graphical manner, helping users better understand the logical relationship and operation order of the reverse Polish expression. 3. Through the grammar and logic multiple verification mechanism, the grammar correctness and logical consistency of the reverse Polish expression can be automatically checked, errors can be detected and corrected in a timely manner, thereby assisting users to design a more accurate and efficient reverse Polish expression, significantly improving the accuracy and efficiency of the target service expression. Description of the Drawings

[0016] Other features, objectives, and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings. The drawings are only for the purpose of showing preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components.

[0017] Figure 1 It is a flowchart of a visualization editing method for a multi-element reverse Polish expression according to an embodiment of the present invention.

[0018] Figure 2 It is a schematic diagram of a mind map expression according to an embodiment of the present invention.

[0019] Figure 3 It is a schematic diagram of an editing process of a target train control expression according to an embodiment of the present invention.

[0020] Figure 4 It is a schematic diagram of an editing process of a target interlocking Boolean logic expression according to an embodiment of the present invention.

[0021] Figure 5 It is a schematic diagram of the decomposed content of a mind map expression according to an embodiment of the present invention.

[0022] Figure 6 It is a schematic diagram of a small set of first-stage circuit expressions according to an embodiment of the present invention.

[0023] Figure 7 It is a schematic diagram of a large set of second-stage circuit expressions according to an embodiment of the present invention.

[0024] Figure 8 It is a schematic diagram of a target circuit expression according to an embodiment of the present invention.

[0025] Figure 9 It is a schematic diagram of a reverse Polish expression operator conversion circuit symbol according to an embodiment of the present invention.

[0026] Figure 10 It is a schematic diagram of an interlocking logic circuit expression according to an embodiment of the present invention.

[0027] Figure 11 It is a schematic diagram of the parsing of an interlocking logic circuit expression symbol according to an embodiment of the present invention. Detailed implementation manners

[0028] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific implementation manners described herein are only the best embodiments of the present invention, which are only used to explain the present invention and do not limit the protection scope of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0029] Embodiment 1: As Figure 1 shown, a visualization editing method for a multi-element reverse Polish expression includes the following steps: S1. Set service variables that at least include exclusive logic conditions of the train control system and exclusive Boolean logic conditions of the interlocking system according to the service characteristics of the rail transit signal system.

[0030] Specifically, S1 includes: Define service variables according to the service rules and exclusive service parameters of the train control system to obtain the first service variable of the train control system; according to the service logic of the interlocking system, use the relay variables of the electric centralized interlocking as the second service variable of the exclusive service of the interlocking system.

[0031] In some embodiments, in the rail transit system, the exclusive services at least include train control parameters and interlocking logic. Regardless of which service, the parameters are freely named and composed in the service system, that is, custom service variables that conform to the service characteristics are defined in the editor. For example, the first service variable defined according to the exclusive logic variable conditions of the train control and the second service variable defined according to the exclusive Boolean logic variable conditions of the interlocking. At the same time, define specific operation logics for performing logical operations on exclusive service parameters. For example, define the train control arithmetic expression: RRM mode conversion condition is satisfied = stopped stably & ATS agrees to enter the RRM mode & in the ZC positioning & having the UTO positive and negative authorization points of ZC; the interlocking Boolean logic arithmetic expression: S0101_LKJEN = S0101_LFSJC * S0101_LFXSJC * SPKS0105_RFJ * S0103_LZJ * ~S0103_YZJ * ~S0103_LKJ * ~S0103_YKJ * QZFST.

[0032] In this embodiment, by presetting the exclusive logic conditions of the train control and the interlocking, the lack of service semantics caused by the use of general variables in the traditional method is avoided, the logical errors caused by variable ambiguity are avoided, the problem of "unbound service semantics and need for secondary mapping" in the conventional method is solved, the expression directly carries the service logic, the cross-domain understanding cost is reduced, the accuracy and pertinence of the expression are improved, the editing errors caused by unclear or incorrect service logic are reduced, and the editing efficiency is improved.

[0033] S2. Construct business expressions based on the business variables, including mind map expressions and interlocking Boolean logic arithmetic expressions.

[0034] Specifically, S2 includes: Determine the first minimum granular variable for establishing the train control reverse Polish expression based on the business characteristic parameters of the rail transit signal system; select the first business variable, the first minimum granular variable, and exclusive operators in response to user requirements to construct a mind map expression.

[0035] Specifically, S2 further includes: Determine the second minimum granular variable for establishing the interlocking Boolean logic expression based on the relay variables of the electric interlocking; Select the second business variable and the second minimum granular variable according to business requirements to edit the interlocking Boolean logic arithmetic expression.

[0036] In some embodiments, business parameters (business variables in this embodiment) are divided into two forms: minimum granular business variables (i.e., the first minimum granular variable and the second minimum granular variable) and combined function business variables. Since the functional business parameters of the expression are superimposed by different minimum granular business parameters, the functional business parameters that cannot be split secondarily are the minimum granular business variables, and the intermediate functional business parameters obtained by superposition are not restricted in the expression.

[0037] In some examples, as Figure 2 shown, the editing steps of the mind map expression include: input business variables in the editor, edit that "General CC Health" consists of "EB Application Normal" and a sub-expression, and the sub-expression is respectively composed of four conditions: "Platform Module Health", "Track Database Available", "CC Board Health", and "Input IO Train Integrity". Then the arithmetic expression of this mind map is: ① General CC Health = (Platform Module Health & Track Database Available & CC Board Health & Input IO Train Integrity) & EB Application Normal; where "Platform Module Health", "Track Database Available", "CC Board Health", "Input IO Train Integrity", and "EB Application Normal" are all minimum granular business parameters, while "General CC Health" is the maximum superimposed combination parameter that needs to be output externally, so as to obtain the mind map expression corresponding to the train control arithmetic expression.

[0038] In some other examples, the definition of the second smallest particle variable uses the 6502 professional relay variable (relay-type centralized electric interlocking variable). According to business requirements, the second smallest particle variable is selected to edit the arithmetic expression of the interlocking Boolean logic. For example, S0102_LXJJ = (S0102_LFKJ + S0102_LXJ * S0102_LXJJ) * ~S0102_LQJ * ~S0102_LXJYR * S0102_LKJEN * (S0102_DDJF + S0102_LXJJ8L * ~S0102_DDJF) + S0102_FTKJ + S0102_LJYJ * ~S0102_LQJ * ~S0102_LXJYR * S0102_LXJJ * LCA + S0102_LXJJ_B * REMO.

[0039] It should be noted that the parameters of the custom expression will not be subjected to syntax checking, but the arithmetic operators should meet the specifications of the arithmetic operators. For example, "*" represents the AND operation of two conditions, "+" represents the OR operation of two conditions, "~" represents the negation of a condition, and "=" represents the assignment of a condition.

[0040] In this embodiment, based on the set first service variable and second service variable, a mind map expression and an interlocking Boolean logic arithmetic expression are constructed, which respectively display the service logic from different perspectives to facilitate user understanding and editing. Among them, the mind map expression provides an intuitive display of the service logic, which helps the editor quickly understand the complex service logic; the interlocking Boolean logic arithmetic expression provides an accurate arithmetic expression, which is convenient for logical operations and verification, solves the problems of reverse Polish syntax being abstract, having poor readability and writability, and realizes the alignment of the service and technology perspectives through the visual intermediate layer.

[0041] S3. Convert the mind map expression and the interlocking Boolean logic arithmetic expression into corresponding target expressions respectively.

[0042] Specifically, S3 includes: Sequentially decompose the mind map expression to obtain the first expression parameters and the first expression operators; Based on the reverse Polish expression rule, sequentially combine the first expression parameters and postpone the first expression operators to obtain the train control reverse Polish expression; Query the first expression parameters and the first expression operators in the system parameter library and the system symbol library respectively; If the query of the first expression parameters is successful and the query of the first expression operators is successful, extract the system parameter numbers corresponding to the first expression parameters and the system symbol numbers corresponding to the first expression operators, and fill them in according to the order of the train control reverse Polish expression to obtain the target train control expression.

[0043] Preferably, step S3 further includes: Decompose the interlock Boolean logic arithmetic expression to obtain second expression parameters and second expression operators; Based on the reverse Polish expression rule, sequentially combine the second expression parameters, and postpone the second expression operators to obtain a target interlock Boolean logic expression.

[0044] In some embodiments, as Figure 3 shown, in steps Y12 and Y13, decompose the symbols defined in the system, do not decompose the equal sign or parentheses in the general expression, and decompose the parameters and symbols in the expression to obtain: "General CC health", "Platform module health", "&", "Track database available", "&", "CC board health", "&", "Input IO train integrity", "&", "EB application normal". The combination obtained in this way still cannot meet the requirements of the reverse Polish expression, and it needs to be transformed by postponing the operation symbols to obtain the train control reverse Polish expression: "General CC health", "Platform module health", "Track database available", "CC board health", "Input IO train integrity", "EB application normal", "&", "&", "&", "&".

[0045] Further, in step Y14, bring the first expression parameters and the first expression operators obtained by decomposition into the system parameter library and the system symbols for searching respectively. Among them, since the service variables are further divided into the smallest granular variables and the combined function service variables, and since there are many types of each variable, in order to improve the search efficiency, underline the combined function service variables for distinction, so that they can be searched in different categories respectively. If not found, go back to Y11 for re - editing. If found, it means that the syntax check is passed and enter step Y15.

[0046] Further, in step Y15, record the parameter numbers found to obtain "1584", "68", "76", "87", "135", "54", "1", "1", "1", "1". Here, the numbering rule is that the combined function service parameters are based on a four - digit number starting from 1000, the smallest granular service parameters are numbered with two - to - three - digit numbers between 10 and 999, and the symbols take values between 1 and 9. This numbering method can better distinguish the meanings of services.

[0047] It should be noted that the parameter numbers are preset in non - custom expressions because syntax verification is required, that is, it is necessary to check whether there are corresponding numbers for the compiled expressions. For custom parameters, no numbering is required, and the filling is to match the expression parameter names (service variables in this embodiment) with the preset numbers.

[0048] In some other embodiments, as Figure 4 shown, in steps Y22 and Y23, the interlocking Boolean logic arithmetic expression is decomposed, the second expression parameters obtained by the decomposition are arranged and combined in sequence, and the second expression operators obtained by the decomposition are combined in sequence and placed after the combination of the second expression parameters to form a reverse Polish expression, thereby obtaining the target interlocking Boolean logic expression. In step Y24, the second expression parameters and the second expression operators are respectively queried with the expression parameters and expression symbols in the system, and the system numbers queried are matched with the expression parameter names (i.e., the second service variables) to complete the editing of the target interlocking Boolean logic expression.

[0049] In this embodiment, the reverse Polish expression has the advantage of being able to clearly define the operation order without parentheses. The mind map expression and the interlocking Boolean logic arithmetic expression are respectively converted into corresponding target expressions, namely the target train control reverse Polish expression and the interlocking Boolean logic reverse Polish expression, expressing the complex service logic in a simple and clear manner, reducing the editing difficulty, and significantly improving the readability and writability of the expression.

[0050] S4. Perform multi-dimensional verification on the target expression based on an expression verification mechanism to complete the multi-element visual editing of the reverse Polish expression.

[0051] Specifically, in S4, the performing multi-dimensional verification on the target expression based on an expression verification mechanism includes: Performing a first verification on the target train control expression or the target interlocking Boolean logic expression according to a syntax verification mechanism, and performing a second verification on the target train control expression or the target interlocking Boolean logic expression according to a logic verification mechanism to obtain a standard target train control expression or a target interlocking Boolean logic expression.

[0052] Specifically, the performing a first verification on the target train control expression or the target interlocking Boolean logic expression according to a syntax verification mechanism includes: Performing nested syntax checking on the target train control expression or the target interlocking Boolean logic expression. If the number of expression parameters or expression operators does not match, an error prompt is issued at the abnormal position; Synchronously, performing capacity syntax checking on the target train control expression or the target interlocking Boolean logic expression. When the expression length is greater than or equal to the marginal threshold, it is determined that the expression has exceeded the capacity, and the expression is split into several sub-expressions according to the expression splitting principle.

[0053] In some embodiments, a recursive edge value definition is added to the editor. When the business parameter or operator of an expression is greater than the threshold value preset for the edge value, it is determined that the capacity is exceeded, which avoids the user writing a large number of conditions in one expression, causing pressure on subsequent expression calculations. When the business parameter or operator of an expression is greater than the threshold value preset for the edge value, it is determined that the capacity is exceeded. At this time, the editor will suggest that the user decompose the long expression into multiple sub-expressions and then tell the user in the way prompted by the editor. For example: S14_LXJJ8L = S14_LKJ * S14_LFSJC * (28 - 30DG_DGJ1T * 27DG_DGJ1T * 16DG_DGJ1T * 10DG_DGJ1T * 6 - 9DG_DGJ1T * 3 - 4DG_DGJ1T * 12 - 13DG_DGJ1T * 30_FBJ * 28_DBJ * 27_DBJ * 16_DBJ * 15_DBJ * 10_FBJ * 9_DBJ * 8_DBJ * 6_DBJ * 7_DBJ * 3_DBJ * 2_DBJ * 4_DBJ * 5_DBJ * ~S14_DKJ * ~X54_LKJ * ~X54_YKJ * ~X54_DKJ * X54_LZJ * ~X54_DZJ + 28 - 30DG_DGJ1T * 27DG_DGJ1T * 16DG_DGJ1T * 15DG_DGJ1T * 14DG_DGJ1T * 7 - 8DG_DGJ1T * 6 - 9DG_DGJ1T * 3 - 4DG_DGJ1T * 30_FBJ * 28_DBJ * 27_DBJ * 16_FBJ * 15_FBJ * 14_DBJ * 7_FBJ * 6_FBJ * 8_DBJ * 9_DBJ * 3_DBJ * 2_DBJ * 4_DBJ * 5_DBJ * ~S14_DKJ * ~X54_LKJ * ~X54_YKJ * ~X54_DKJ * X54_LZJ * ~X54_DZJ + 28 - 30DG_DGJ1T * 27DG_DGJ1T * 16DG_DGJ1T * 15DG_DGJ1T * 14DG_DGJ1T * 7 - 8DG_DGJ1T * 30_FBJ * 28_DBJ * 27_DBJ * 16_FBJ * 15_FBJ * 14_DBJ * 7_DBJ * 6_DBJ * 8_DBJ * 9_DBJ * ~S14_DKJ * ~X55_LKJ * ~X55_YKJ * ~X55_DKJ*X55_LZJ*~X55_DZJ; When the expression does not meet the edge threshold, the editor will automatically decompose it: S14_LXJJ8L = S14_LKJ*S14_LFSJC*(A + B + C); A = 28 - 30DG_DGJ1T*27DG_DGJ1T*16DG_DGJ1T*10DG_DGJ1T*6 - 9DG_DGJ1T*3 - 4DG_DGJ1T*12 - 13DG_DGJ1T*30_FBJ*28_DBJ*27_DBJ*16_DBJ*15_DBJ*10_FBJ*9_DBJ*8_DBJ*6_DBJ*7_DBJ*3_DBJ*2_DBJ*4_DBJ*5_DBJ*~S14_DKJ*~X54_LKJ*~X54_YKJ*~X54_DKJ*X54_LZJ*~X54_DZJ; B = 28 - 30DG_DGJ1T*27DG_DGJ1T*16DG_DGJ1T*15DG_DGJ1T*14DG_DGJ1T*7 - 8DG_DGJ1T*6 - 9DG_DGJ1T*3 - 4DG_DGJ1T*30_FBJ*28_DBJ*27_DBJ*16_FBJ*15_FBJ*14_DBJ*7_FBJ*6_FBJ*8_DBJ*9_DBJ*3_DBJ*2_DBJ*4_DBJ*5_DBJ*~S14_DKJ*~X54_LKJ*~X54_YKJ*~X54_DKJ*X54_LZJ*~X54_DZJ; C = 28 - 30DG_DGJ1T*27DG_DGJ1T*16DG_DGJ1T*15DG_DGJ1T*14DG_DGJ1T*7 - 8DG_DGJ1T*30_FBJ*28_DBJ*27_DBJ*16_FBJ*15_FBJ*14_DBJ*7_DBJ*6_DBJ*8_DBJ*9_DBJ*~S14_DKJ*~X55_LKJ*~X55_YKJ*~X55_DKJ*X55_LZJ*~X55_DZJ.

[0054] Furthermore, the expression splitting principle includes at least: ① When the types of operation symbols in a long expression are too many, split the sub - expressions with different symbols for operation; ② When the long expression forms too many branches, split the sub - expressions of the long branches; ③ When the elements of the long expression are too many, split the sub - expressions proportionally; It should be noted that in the splitting principle, whether it is the number of symbol types, the number of branches, or the number of elements, they can all be flexibly defined according to actual business requirements. In principle, any expression is an assignment operation, so any assignment operation that does not meet the general equation is considered a syntax error.

[0055] Furthermore, the edge threshold can be flexibly set according to requirements. The setting principle is determined by the maximum capacity that the corresponding software can handle. For example, the maximum capacity of the interlocking software to process an expression is 10 branches, and each branch has no more than 10 parameters. When the software determines that the current expression has more than 10 branches or any one branch exceeds 10 parameters, it is considered to exceed the threshold.

[0056] In this embodiment, syntax verification is used to ensure the syntax correctness of the expression. When the number of expression parameters or operators does not match, an error prompt can be immediately issued at the abnormal position, which helps to quickly locate and correct errors, improving the accuracy and reliability of the expression. Capacity check is used to ensure that the expression will not exceed the processing capacity or storage limit of the system due to excessive length. When the expression length is greater than or equal to the edge threshold, it can be determined that the expression exceeds the capacity, and it is split into several sub-expressions according to the expression splitting principle to reduce the processing difficulty and storage pressure of the system, while improving the readability and maintainability of the expression, and avoiding problems such as system performance degradation or crashes caused by overly long expressions.

[0057] Specifically, the secondary verification of the target train control expression or the target interlocking Boolean logic expression according to the logic verification mechanism includes: Based on the sufficient and necessary condition mechanism, perform a sufficient and necessary condition check on the sub-expression branches of the target train control expression or the target interlocking Boolean logic expression. If the sufficient and necessary conditions of the corresponding business variables are missing in the sub-expression branches, an error is generated for the target expression; Based on the condition self-learning mechanism, monitor the frequency of business variables that are not sufficient and necessary conditions in the target train control expression or the target interlocking Boolean logic expression. If the frequency of the same business variable that is not a sufficient and necessary condition reaches the threshold, a variable duplication prompt is issued; Based on the expression integrity mechanism, determine whether the target train control expression or the target interlocking Boolean logic expression is complete. If the target expression has only inputs and no outputs, the target expression editing fails; Based on the logic dynamic check mechanism, perform an integrity check on the business functions corresponding to the business variables that are sufficient and necessary conditions in the target train control expression or the target interlocking Boolean logic expression. If the functional logic corresponding to the business variable complies with the specification, the corresponding business function item is valid.

[0058] In some embodiments, the necessary and sufficient condition definition mechanism splits an expression into multiple branches for inspection. Some commonly used branches are pre-defined with conditions in the system, that is, some service parameters of certain branches are used as forced binding parameters, serving as the necessary and sufficient conditions for this branch. Users can add other conditions to this branch, but cannot reduce the necessary and sufficient conditions. When the complete expression is formed, the system will check the necessary and sufficient conditions of these branches. If they do not meet the requirements, an error will be directly generated.

[0059] Furthermore, the condition self-learning mechanism is mainly aimed at the fact that the system may not consider the pre-defined necessary and sufficient conditions perfectly. As the expression evolves and upgrades, there will be an increase in the necessary and sufficient comparisons. Then, by adding the condition self-learning mechanism, when a certain branch is recorded, if a service parameter that is not a necessary and sufficient condition is recorded multiple times, then when the designer edits the same expression or sub-expression, the system will automatically provide the newly added service parameters that were previously recorded, and will also give a prompt message when the expression editing is completed.

[0060] Furthermore, the expression integrity mechanism is based on the various attributes existing in the expression, such as the input expression, output expression, and intermediate expressions. For the realization of a certain function, there will always be an input expression and an output expression. By combining multiple intermediate defined expressions, such as input expression ① S0101_LJQ = S0101.S0103_JQ + S0101.S0103_JQ2, intermediate defined expressions ②, ③ S0101_LJ_VO = S0101_LDR*(~S0101_DDJ + S0101_DDJ*STA_QZDDJ)*(SRA + SYSADELAY + S0101_LDRBT*~SRA*SYSBDELAY*VIGX*~VCB_OUTD); the input expression is the route request, the output expression is the signal opening, and the intermediate expressions are some inspection conditions for the route opening. The system will perform integrity checks on each input and output. If an expression has only an input but no output, it is considered that the expression does not form a complete logical expression. Conversely, if there is only an output but no input, it is also considered that the expression structure is incomplete and the determination fails; the intermediate defined expressions are optional. In this embodiment, the service variables of the intermediate expressions are not subject to parameter verification.

[0061] Furthermore, the logical dynamic inspection mechanism combines with the expression integrity mechanism for verification. The service parameters are classified according to functions, and the integrity of each service function is checked separately in the form of function items. Among them, only the necessary and sufficient conditions pre-defined by the system are checked here. If the function item cannot run through the logic, it is considered that the function item fails. If it can run through, it is considered that the function item is valid.

[0062] In this embodiment, the accuracy and integrity of the target expression are ensured through the necessary and sufficient condition definition mechanism. When constructing the expression, there is no need to manually check all conditions, reducing the error rate. When the intermediate expression changes, only the predefined necessary and sufficient conditions need to be updated, and they can be automatically applied to all relevant expressions; through the condition self-learning mechanism, new business parameters are automatically learned and recorded, and the system can gradually improve the predefined necessary and sufficient conditions, improving the accuracy and efficiency of logical checks, and further enhancing the flexibility and adaptability of the editor; through the expression integrity mechanism, each target expression can be correctly executed, avoiding system crashes or anomalies caused by incomplete logic; through the logical dynamic check mechanism combined with input and output checks, the integrity of the business function is verified to ensure that the business functions corresponding to business variables are all complete and the business logics between business variables match, ensuring the accuracy and reliability of the expression calculation result.

[0063] Specifically, the method further includes: converting the mind map expression into a circuit expression, and the specific steps are as follows: traversing the mind map connectors in the order from right to left of the mind map expression, and sequentially extracting the connection objects on the right side of the mind map connectors, including the first expression parameter and the first expression operator; Converting the first expression operator into a corresponding logic circuit symbol, and generating a basic circuit expression by combining all the extracted first expression parameters and the first expression operator as an object set with the logic circuit symbol; Until there is no more mind map connector on the right side of the last business variable, taking the current business variable as the assignment variable of the circuit expression, representing it with an assignment circuit symbol, and merging it with the basic circuit expression to obtain the target circuit expression, completing the conversion of the mind map expression to the circuit expression.

[0064] As an alternative implementation Figure 5As shown, first extract the parameters, operators, and connectors of the expressions in the mind map. Since the minimum particles of parameters, operation symbols, and connection symbols are defined in the system in advance, the system can directly divide them into parameter classes according to the internal definitions: "General CC Health", "EB Application Normal", "Platform Module Health", "Track Database Available", "CC Board Health", "Input IO Train Integrity"; operation symbol classes: "&", "&", "&", "|"; connection symbol classes: "Expression"1, "Expression"2. The order of forming the circuit expression is in the order from right to left according to the mind map. Find the first connection symbol, which is ["Expression"2: "Platform Module Health" "&" "Track Database Available" "&" "CC Board Health" "&" "Input IO Train Integrity"], and then define all the connection objects on the right side of this connection symbol as a small set to form a small set of the first-stage circuit expression, as shown in Figure 6 shown; Then find the second connection symbol, which is ["Expression"1: "Expression"2 "|" "EB Application Normal"], and then define all the connection objects on the right side of this connection symbol as a large set to form a large set of the second-stage circuit expression, as shown in Figure 7 shown; Stop when there is no longer a link symbol on the left side of the last business parameter. Then consider this business parameter as the assignment variable of this circuit expression and represent it with an assignment circuit symbol, finally forming the circuit expression, as shown in Figure 8 shown.

[0065] As another alternative implementation, converting the reverse Polish expression into a circuit expression includes the steps: first extract the parameters, operators, and connectors of the expressions in the mind map, obtaining: "General CC Health", "Platform Module Health", "Track Database Available", "CC Board Health", "Input IO Train Integrity", "&", "&", "&", "EB Application Normal", "|". First, determine that the right side of the expression equation is "General CC Health" underlined + business parameter, indicating that this is a composite parameter. Then, determine the connection shape of the circuit expression according to the operation symbols, that is, 3 "&" and 1 "|". According to the arrangement rule of the reverse Polish expression, the parameters are in front and the operation symbols are behind. Thus, it can be determined that the five parameters have a relationship of four in series and one in parallel to form the basic circuit diagram, as shown in Figure 9 shown; Arrange the reverse Polish expression in sequence from 1 to 10, search from left to right. The number 1 is the parameter that meets the requirements and is directly placed on the right side of the circuit expression. Then, look down to find that the connection operator is number 6, and then find out how many consecutive connection operators are numbers 6 - 8 (the connection operators must be consecutive during the search process). Since the number of connection operators = the number of parameter symbols - 1, and the business parameter symbols are numbers 2 - 5, the equation 3 = 4 - 1 holds. Thus, the syntax correctness of the logical expression can be verified; and fill the four "AND" parameters numbered 2 - 5 into the series circuit. According to this logic, number 10 is the "OR" operation, and fill number 9 into the parallel circuit. Finally, the business variable equation can be obtained, as shown in Table 1, Table 1 Business Variable Equation Finally, establish the target circuit expression according to the business variable inequality, as Figure 8 shown.

[0066] Furthermore, to verify whether the conversion of the reverse Polish expression to the circuit expression is correct, it can be verified by reverse parsing the circuit expression into the reverse Polish expression. The steps are as follows: A1. As Figure 10 shown, use the matrix method for circuit expression graphic recognition; divide the entire matrix principle into 9 vertical regions numbered 1 - 8 and 5 horizontal regions numbered one to four, and then divide each region horizontally into two parts by a dotted line to form 2 regions. Region 1 is the business parameter parsing region, and region 2 is the parameter node parsing region. Cut Figure 7 through the matrix grid, which is divided into 90 regions in total. Here, these 90 regions are defined as pixel grids. Then, by analyzing the content of the pixel grids, the corresponding business parameters and circuit expression symbols are obtained. The parsing method is to mark the black dot 1 in the first column and the first row in the figure, that is, a large pixel grid is formed at the upper left corner of the black dot 1. Then, mark the red dot 1 in the first column and the first row in the figure, that is, a small pixel grid is formed at the upper left corner of the red dot. The large pixel grid parses a complete business parameter, including two small pixel grid parts: the parameter name and the circuit expression symbol; A2. As Figure 11 shown, after extracting all the circuit expression symbols, analyze the connection operators; among them, when the circuit expression symbol is a normally open node, it is a normal operation, and when the circuit expression symbol is a normally closed node, it is a negation operation. When two circuit expression symbols are serially connected, it is an "AND operation", and when two are parallel connected, it is an "OR operation"; A3. For all the connection points in Figure 11 , press The serial numbers are numbered according to the principle from left to right and from top to bottom. The initial node ① is the search origin, and the search order is consistent with the numbering rule order. The connection point numbers of the service parameters are used for parameter extraction, and the connection point numbers are extracted after the operator conversion. Then, ③ and ⑤ are converted into S0102_LFKJ, ⑨ is converted into +, ⑤ and ⑩ are converted into *, where the connection points of non-circuit expression symbols are denoted as +; ⑩, is converted into ~S0102_LQJ, ② and ⑨ form a rectangular frame and are parsed as (), ④ and ⑥ are converted into S0102_LXJ, ⑥ and ⑦ are converted into *, ⑦ and ⑧ are converted into S0102_LXJJ. Thus, the reverse Polish expression corresponding to the circuit expression can be obtained: (S0102_LFKJ + S0102_LXJ * S0102_LXJJ) * ~S0102_LQJ.

[0067] In this embodiment, reverse parsing the mind map and the original expression from the formed circuit expression can improve the design efficiency, and through the reverse derivation mechanism, comparing with the original expression can ensure the correctness of the tool generation.

[0068] The above specific implementation manners are the preferred implementation manners of the present invention, and do not limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to this specific implementation manner. All equivalent changes made according to the shape, structure, and method of the present invention are within the protection scope of the present invention.

Claims

1. A visual editing method for a multi-element reverse Polish expression, characterized in that: It includes the following steps: S1. Set service variables including at least the exclusive logical conditions of the train control system and the exclusive Boolean logical conditions of the interlocking system according to the service characteristics of the rail transit signal system; S2. Construct service expressions based on the service variables, including mind map expressions and interlocking Boolean logical arithmetic expressions; S3. Convert the mind map expressions and the interlocking Boolean logical arithmetic expressions into corresponding target expressions respectively; S4. Perform multi-dimensional verification on the target expressions based on the expression verification mechanism to complete the multi-variable visualization editing of the reverse Polish expressions.

2. The visual editing method for the multi-element reverse Polish expression according to claim 1, characterized in that: The S1 includes: defining service variables according to the service rules and exclusive service parameters of the train control system to obtain the first service variables of the train control system; According to the service logic of the interlocking system, use the relay variables of the electric interlocking as the second service variables of the exclusive service of the interlocking system.

3. The visual editing method for the multiple reverse Polish expressions according to claim 2, characterized in that: The S2 includes: determining the first minimum granular variables for establishing the train control reverse Polish expression based on the service characteristic parameters of the rail transit signal system; Responding to the user's requirements, select the first service variables, the first minimum granular variables and the exclusive operators to construct mind map expressions.

4. The visual editing method of the multi-element reverse Polish expression according to claim 2, characterized in that: The S2 further includes: Determine the second minimum granular variables for establishing the interlocking Boolean logical expression based on the relay variables of the electric interlocking; Edit the interlocking Boolean logical arithmetic expression by selecting the second service variables and the second minimum granular variables based on the service requirements.

5. The visual editing method for the multi-element reverse Polish expression according to claim 1, characterized in that: The S3 includes: sequentially decompose the mind map expression to obtain the first expression parameters and the first expression operators; Based on the reverse Polish expression rule, sequentially combine the first expression parameters and postpone the first expression operators to obtain the train control reverse Polish expression; Query the first expression parameters and the first expression operators in the system parameter library and the system symbol library respectively; If the query of the first expression parameters is successful and the query of the first expression operators is successful, extract the system parameter numbers corresponding to the first expression parameters and the system symbol numbers corresponding to the first expression operators, and fill them in according to the order of the train control reverse Polish expression to obtain the target train control expression.

6. The visual editing method of the multi-element reverse Polish expression according to claim 1, wherein: The S3 further includes: Decompose the interlocking Boolean logical arithmetic expression to obtain the second expression parameters and the second expression operators; Based on the reverse Polish expression rule, sequentially combine the second expression parameters and postpone the second expression operators to obtain the target interlocking Boolean logical expression.

7. The visual editing method for the multi-element reverse Polish expression according to claim 5 or 6, characterized in that: In the S4, the multi-dimensional verification of the target expression based on the expression verification mechanism includes: Perform a primary verification on the target train control expression or the target interlocking Boolean logical expression according to the syntax verification mechanism, and perform a secondary verification on the target train control expression or the target interlocking Boolean logical expression according to the logic verification mechanism to obtain a standard target train control expression or a target interlocking Boolean logical expression.

8. The visual editing method of the multi-element reverse Polish expression according to claim 7, characterized in that: The primary verification of the target train control expression or the target interlocking Boolean logical expression according to the syntax verification mechanism includes: Perform nested syntax checking on the target train control expression or the target interlocking Boolean logic expression. If the number of expression parameters or expression operators does not match, an error prompt is issued at the abnormal position. Synchronously, perform capacity syntax checking on the target train control expression or the target interlocking Boolean logic expression. When the expression length is greater than or equal to the edge threshold, the expression is determined to have exceeded the capacity, and the expression is split into several sub-expressions according to the expression splitting principle.

9. The visual editing method of the multivariate reverse Polish expression according to claim 7, characterized in that: The secondary verification of the target train control expression or the target interlocking Boolean logic expression according to the logic verification mechanism includes: Perform sufficient and necessary condition checking on the sub-expression branches of the target train control expression or the target interlocking Boolean logic expression based on the sufficient and necessary condition mechanism. If the sufficient and necessary conditions of the corresponding service variables are missing in the sub-expression branches, an error occurs in the target expression. Perform frequency monitoring on the service variables that are not sufficient and necessary conditions in the target train control expression or the target interlocking Boolean logic expression based on the condition self-learning mechanism. If the occurrence frequency of the service variables with the same non-sufficient and necessary condition reaches the threshold, a variable duplication prompt is issued. Judge whether the target train control expression or the target interlocking Boolean logic expression is complete based on the expression integrity mechanism. If the target expression has only inputs but no outputs, the target expression editing fails. Perform integrity checking on the service functions corresponding to the service variables that are sufficient and necessary conditions in the target train control expression or the target interlocking Boolean logic expression based on the logic dynamic checking mechanism. If the functional logic corresponding to the service variable conforms to the specification, the corresponding service function item is valid.

10. The visual editing method of the multi-element reverse Polish expression according to claim 5, characterized in that: The method further includes: converting the mind map expression into a circuit expression, and the specific steps are as follows: Traverse the mind map connectors of the mind map expression in the order from right to left, and sequentially extract the connection objects on the right side of the mind map connectors, including the first expression parameters and the first expression operators. Convert the first expression operator into the corresponding logic circuit symbol, and combine the extracted all the first expression parameters and the first expression operators as an object set with the logic circuit symbol to generate a basic circuit expression. Until there is no more mind map connector on the right side of the last service variable, use the current service variable as the assignment variable of the circuit expression, represent it with the assignment circuit symbol, and merge it with the basic circuit expression to obtain the target circuit expression, completing the conversion of the mind map expression to the circuit expression.

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