Multi-level page table traversal acceleration method, system, equipment and medium

Abstract

The invention provides a multi-level page table traversal acceleration method, system and device and a medium, and belongs to the technical field of computers. The method comprises the following steps: inputting a virtual address into a path predictor and a dynamic weight hierarchical cache, and collecting an instruction access proportion, a TLB hit rate and a pre-fetching success rate in real time; performing hash calculation according to a preset bit of the virtual address through a path predictor, and querying a historical record table to obtain a prediction path and a confidence level so as to determine a query range; when the cache is hit, scores of hit entries are calculated, priority ranking and elimination decision making of the cache entries are carried out, and meanwhile, the cache entries are managed by adopting a hybrid replacement algorithm; under a preset condition, starting a prefetch operation through an adaptive prefetch engine, calculating and dynamically expanding a prefetch step length, and preventing memory bandwidth contention through two-stage monitoring; when the instruction access proportion, the TLB hit rate and the prefetching success rate meet conditions, an instruction priority mode is activated, and scores of hit entries are updated by adjusting related calculation parameters.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and more specifically relates to a method, system, device and medium for accelerating multi-level page table traversal. Background Art

[0002] In modern processor architectures, the multi-level page table mechanism is the core technology for implementing the translation from virtual addresses to physical addresses. With the improvement of processor performance and the expansion of memory space, the efficiency of page table traversal directly affects the overall system performance. However, the traditional multi-level page table traversal scheme has the following significant technical drawbacks: First, the low cache efficiency problem restricts the address translation performance. Existing TLBs (Translation Lookaside Buffers) generally adopt a fixed replacement strategy (such as the LRU algorithm), without considering the actual benefit differences of page table entries at different levels. For example, in a four-level page table structure, a hit in the L3-level page table entry can directly skip the queries at the L2 and L1 levels, and its actual benefit is 3 times that of an L1-level hit; but the traditional LRU algorithm only uses the access time as the replacement basis and cannot quantify the benefit differences at different levels, resulting in high-value page table entries being frequently evicted. This "lack of awareness of hierarchical benefits" makes it difficult for the TLB hit rate to break through the bottleneck, especially in deep page table scenarios where the performance loss is significant.

[0003] Second, the locality failure of the prefetch mechanism leads to a sharp drop in cross-level access efficiency. Due to the tree-like nature of the page table structure, the page table entries corresponding to consecutive virtual addresses are sparsely distributed in physical memory, rather than linearly continuously stored. Existing linear prefetch mechanisms (such as fixed-step prefetch) cannot adapt to the branch characteristics of the tree structure during cross-level access, resulting in a prefetch hit rate drop of more than 40%. For example, when the page table traversal path jumps from the PUD (second-level page table) to the PTE (fourth-level page table), the prefetched page table entries are misaligned with the actual access path, causing waste of memory bandwidth and additional latency.

[0004] Furthermore, the resource competition between instruction pages and data pages forms a vicious cycle of performance degradation. When instruction page table entries and data page table entries share the STLB (Secondary TLB), frequent instruction accesses will continuously occupy the cache space of data page table entries. The traditional scheme lacks differentiated management of page types, resulting in frequent invalidation of data page table entries, and thus triggering a recheck of the page table during data access; and the absence of data page table entries further exacerbates the TLB conflict, forming a vicious cycle of "cache competition - increased invalidation". Especially in instruction-intensive workloads, this problem will cause the data access latency to increase by more than 30%.

[0005] The essence of the above problem lies in that the existing page table traversal scheme optimizes the cache management, prefetching strategy, page type control and other links separately, lacking a cross-level collaborative management mechanism. Each module operates independently and cannot perform dynamic linkage based on the page table level characteristics, access patterns and resource states, resulting in limited system-level performance optimization. Summary of the Invention

[0006] In view of the above problems, the purpose of the present invention is to provide a multi-level page table traversal acceleration method, system, device and medium, which realizes page table traversal acceleration, cache hit rate improvement and memory bandwidth optimization through path prediction, dynamic cache grading, adaptive prefetching and instruction priority parameter adjustment.

[0007] To achieve the above object, the present invention is realized through the following technical solutions: In a first aspect, an embodiment of the present application provides a multi-level page table traversal acceleration method, including: Input the virtual address into a path predictor and a dynamic weight hierarchical cache respectively, and collect the instruction access ratio, TLB hit rate and prefetch success rate in real time; The path predictor performs hash calculation according to the preset bits of the virtual address, queries the historical record table to obtain the predicted path and confidence level; the dynamic weight hierarchical cache determines the query range according to the confidence level; When the cache hits, calculate the score of the hit entry using the comprehensive scoring formula, perform priority sorting and elimination decision of the cache entry based on the score, and manage the cache entry using a hybrid replacement algorithm at the same time; When the preset trigger condition is met, start the prefetch operation through the adaptive prefetch engine, calculate using Q4.12 fixed-point numbers and dynamically expand the prefetch step size, and prevent memory bandwidth contention through two-level monitoring at the same time; When the instruction access ratio, TLB hit rate and prefetch success rate meet the preset conditions, activate the instruction priority mode, and update the score of the hit entry by adjusting the relevant parameters of the comprehensive scoring formula.

[0008] In an alternative embodiment, the step of inputting the virtual address into a path predictor and a dynamic weight hierarchical cache respectively, and collecting the instruction access ratio, TLB hit rate and prefetch success rate in real time includes: Input the virtual address VA[47:0] into a path predictor and a dynamic weight hierarchical cache respectively; Detect the instruction access ratio in real time using a 32-bit sliding window counter. When the CPU executes an instruction, the counter value counter is incremented by 1; when the CPU accesses data, the counter value counter is decremented by 1. Calculate the instruction access ratio InstrRatio in real time through the formula InstrRatio=(counter+32768) / 65536.0; Calculate the TLB hit rate by reading the number of TLB hits and misses recorded in the hardware performance counter; Read the number of prefetch hits and misses recorded in the hardware performance counter and calculate the prefetch success rate; Broadcast the collected instruction access ratio, TLB hit rate, and prefetch success rate through the 32-bit status bus every cycle; in the 32-bit status bus, bit segment [7:0] represents the operation mode encoding, bit segment [15:8] represents the instruction ratio, bit segment [23:16] represents the prefetch success rate, and bit segment [31:24] represents the TLB hit rate.

[0009] In an optional embodiment, the path predictor performs a hash calculation based on the preset bits of the virtual address, queries the history record table to obtain the predicted path and the confidence level; the dynamic weight hierarchical cache determines the query range according to the confidence level, including: The path predictor performs a hash calculation based on the virtual address VA[47:39], queries the history record table to obtain the predicted path and the path prediction confidence Z; Determine the confidence level according to the path prediction confidence Z; when Z≥6, it is a high confidence level; when 5<Z<6, it is a medium confidence level; when Z≤5, it is a low confidence level Determine the page table level to be queried according to the confidence level; the page table adopts a four-level page table of PGD, PUD, PMD, and PTE; When the confidence level is a high confidence level, only query the range of prediction level ±1; when the confidence level is a low confidence level, perform a full-level parallel query.

[0010] In an optional embodiment, when the cache hits, use the comprehensive scoring formula to calculate the score of the hit entry, perform priority sorting and replacement decision of the cache entry based on the score, and at the same time manage the cache entry using a hybrid replacement algorithm, including: When the cache hits, the score Score of the hit entry is calculated using the comprehensive scoring formula Score = α • LevelWeight + β• TypeBoost -γ • Δt; where α is the scaling factor of the path prediction confidence, LevelWeight is the weight of the page table level where the cache entry is located, β is the type gain coefficient of the instruction access ratio, TypeBoost is the type gain of the cache entry, γ is the time decay factor related to the prefetch hit rate, and Δt is the access time interval of the cache entry; if the cache entry is in the PGD layer, LevelWeight = 4; if the cache entry is in the PUD layer, LevelWeight = 3; if the cache entry is in the PMD layer, LevelWeight = 2; if the cache entry is in the PTE layer, LevelWeight = 1; Based on the score Score of the hit entry, determine the cache priority of the entry and perform caching; When the number of idle entries in the current cache is greater than or equal to 10% of the total number of entries, classify the cache entries into four hierarchical categories: PGD, PUD, PMD, and PTE, and randomly select 2 candidate entries from each category to classify the cache entries into four hierarchical categories: PGD, PUD, PMD, and PTE, and randomly select 2 candidate entries from each category for replacement; When the number of idle entries in the current cache is less than 10% of the total number of entries, eliminate the entries with Score < 2; For the entries that are continuously hit 3 times, lock them in the cache for 200 cycles.

[0011] In an alternative embodiment, when the preset trigger condition is met, start the prefetch operation through the adaptive prefetch engine, calculate using Q4.12 fixed-point numbers and dynamically expand the prefetch stride, and at the same time prevent memory bandwidth contention through two-level monitoring, including: If the entries at the current PTE level are loaded, the remaining space in the dynamic cache is greater than 20% of the total cache space, and Z ≥ 5, start the prefetch operation through the adaptive prefetch engine; Update the stride value every 100 cycles. The initial stride is ±2 pages, and the updated stride value stride is calculated using the stride calculation formula based on the real-time entry hit rate for dynamic expansion of the stride; Sample the miss rate Q of the L1D-Cache every 50 cycles. When Q > 15% accumulatively for 3 times, turn off the prefetch operation for 200 cycles.

[0012] In an alternative embodiment, the stride calculation formula is:

[0013] Where, It is the entry hit rate.

[0014] In an optional embodiment, when the instruction access ratio, TLB hit rate, and prefetch success rate meet preset conditions, the instruction priority mode is activated, and by adjusting the relevant parameters of the comprehensive scoring formula, the score of the hit entry is updated, including: Real-time detection of the instruction access ratio InstrRatio; When it is detected that InstrRatio > 60%, the TLB hit rate is less than 85%, and the prefetch success rate is greater than 40%, the instruction priority mode is activated, TypeBoost is increased to 1.2 times the current value, the β value is forced to be 0.1, and the score Score of the entry is updated. Real-time dynamically adjust the value of the type gain coefficient β of the instruction access ratio according to the formula β = max(0, min(0.5, 0.2 + 0.5•(InstrRatio - 0.6))), and update the score Score of the entry.

[0015] In a second aspect, an embodiment of the present application further provides a multi-level page table traversal acceleration system, including: An address input and status monitoring module, configured to input a virtual address to a path predictor and a dynamic weight hierarchical cache respectively, and collect the instruction access ratio, TLB hit rate, and prefetch success rate in real time; A path prediction and query planning module, configured to perform hash calculation on the preset bits of the virtual address through the path predictor, query the historical record table to obtain the predicted path and confidence level; determine the query range according to the confidence level through the dynamic weight hierarchical cache; Weight evaluation and cache management, configured to calculate the score of the hit entry using the comprehensive scoring formula when the cache is hit, perform priority sorting and eviction decision on the cache entries based on the score, and manage the cache entries using a hybrid replacement algorithm at the same time; A prefetch strategy adjustment module, configured to start a prefetch operation through an adaptive prefetch engine when a preset trigger condition is met, calculate using Q4.12 fixed-point numbers and dynamically expand the prefetch step size, and prevent memory bandwidth contention through two-level monitoring at the same time; A mode switching and parameter adjustment module, configured to activate the instruction priority mode when the instruction access ratio, TLB hit rate, and prefetch success rate meet preset conditions, and update the score of the hit entry by adjusting the relevant parameters of the comprehensive scoring formula.

[0016] In a third aspect, an embodiment of the present application further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, it implements the steps of the multi-level page table traversal acceleration method described in any one of the above.

[0017] In a fourth aspect, an embodiment of the present application further provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the multi-level page table traversal acceleration method described in any one of the above are implemented.

[0018] As can be seen from the above technical solutions, the present invention has the following advantages: In the multi-level page table traversal acceleration method provided by the present application, through the collaborative work of the path predictor and the dynamic weight hierarchical cache, combined with dynamic indicators such as the instruction access ratio, TLB hit rate, and prefetch success rate collected in real time, efficient optimization of page table traversal is achieved. The path predictor predicts the path based on the virtual address bit hash calculation and queries by confidence level grading. When the confidence level is high, the query range is reduced to reduce the time consumption, and when the confidence level is low, the full-level parallel query ensures accuracy; the dynamic weight hierarchical cache uses a comprehensive scoring formula (fusing hierarchical weight, type gain, and time decay) and a hybrid replacement algorithm to preferentially retain high-level page tables and frequently accessed entries, improving the cache utilization rate. The adaptive prefetch engine starts prefetching based on the PTE loading status, remaining cache space, and prediction confidence level, dynamically adjusts the step size using Q4.12 fixed-point numbers to match the hit rate, and prevents memory bandwidth contention by monitoring the L1D-Cache miss rate, improving the prefetch efficiency. When the instruction access ratio is high and the TLB hit rate is low, the instruction priority mode is activated, the scoring parameters are adjusted to increase the priority of the page table entries related to the instruction, and the instruction access latency is reduced. The overall solution effectively improves the TLB hit rate, reduces the page table traversal latency, optimizes the memory bandwidth allocation, and significantly improves the system performance in instruction-intensive scenarios.

[0019] The present application performs a hash calculation on the virtual address through the path predictor to achieve accurate prediction of the access path, and dynamically adjusts the query range according to the confidence level. When the confidence level is high, it focuses on the range of ±1 of the predicted level, and when the confidence level is low, it performs a full-level parallel query, greatly reducing the invalid traversal and improving the query efficiency.

[0020] The present application realizes intelligent sorting and elimination of cache entries based on the comprehensive scoring formula. Combining multi-dimensional factors such as page table level weight, instruction access ratio, and time decay, it preferentially retains high-value entries, improves the cache hit rate, and reduces the memory access latency.

[0021] The present application dynamically triggers prefetching through the prefetch engine according to the PTE loading status, cache space, and prediction confidence level, uses the Q4.12 fixed-point number algorithm to dynamically expand the prefetch step size, and intelligently adjusts the prefetch switch by monitoring the L1D-Cache miss rate, avoiding memory bandwidth contention while improving the prefetch hit rate.

[0022] This application activates the instruction priority mode by real-time monitoring of the instruction access ratio, TLB hit rate, and prefetch success rate. By increasing the TypeBoost value of instruction-related entries and adjusting the β parameter, it ensures the priority caching of page table entries for critical instructions, significantly reducing the instruction execution latency and improving CPU utilization.

[0023] This application realizes cycle-level broadcasting of performance metrics through a 32-bit status bus, combines hardware performance counters to collect key data such as TLB hits and prefetch success rates in real time, forms a deep collaboration between software algorithms and hardware architectures, fully utilizes the efficiency of hardware resources, and achieves system-level performance optimization. Brief Description of the Drawings

[0024] To more clearly illustrate the technical solutions of the present invention, the drawings required for description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 It is a schematic flowchart of the multi-level page table traversal acceleration method provided by this application.

[0026] Figure 2 It is a schematic flowchart of another multi-level page table traversal acceleration method provided by this application.

[0027] Figure 3 It is a schematic flowchart of the multi-level path prediction generation method provided by this application.

[0028] Figure 4 It is a schematic flowchart of the dynamic weight hierarchical cache management method provided by this application.

[0029] Figure 5 It is a schematic flowchart of the cross-level adaptive prefetch control method provided by this application.

[0030] Figure 6 It is a schematic flowchart of the system status monitoring and mode switching method provided by this application.

[0031] Figure 7 It is a schematic structural diagram of the multi-level page table traversal acceleration system provided by this application.

[0032] Figure 8 It is a schematic structural diagram of the electronic device provided by this application. Detailed Embodiments

[0033] In the following detailed description of the specific steps of the multi-level page table traversal acceleration method, various embodiments of the present disclosure will be more comprehensively described. The present disclosure can have various embodiments, and adjustments and changes can be made therein. However, it should be understood that there is no intention to limit the various embodiments of the present disclosure to the specific embodiments disclosed herein, but the present disclosure should be understood to cover all adjustments, equivalents, and / or alternative solutions that fall within the spirit and scope of the various embodiments of the present disclosure.

[0034] Hereinafter, the term "comprising" or "may comprise" that can be used in various embodiments of the present disclosure indicates the presence of the disclosed function, operation, or element, and does not limit the addition of one or more functions, operations, or elements. In addition, as used in various embodiments of the present disclosure, the terms "comprising", "having", and their cognates are only intended to indicate a specific feature, number, step, operation, element, component, or combination of the foregoing items, and should not be construed as first excluding the existence of one or more other features, numbers, steps, operations, elements, components, or the combination of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components, or the combination of the foregoing items.

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0036] Please refer to Figure 1 Shown is a method flowchart of a multi-level page table traversal acceleration method in a specific embodiment. The method includes: S1: Input the virtual address into the path predictor and the dynamic weight hierarchical cache respectively, and collect the instruction access ratio, TLB hit rate, and prefetch success rate in real time.

[0037] In the specific implementation manner, first input the virtual address VA[47:0] into the path predictor and the dynamic weight hierarchical cache respectively.

[0038] At the same time, use a 32-bit sliding window counter to detect the instruction access ratio in real time. When the CPU executes an instruction, the counter value counter is incremented by 1; when the CPU accesses data, the counter value counter is decremented by 1. The instruction access ratio InstrRatio is calculated in real time through the formula InstrRatio = (counter + 32768) / 65536.0 to achieve accurate monitoring of the instruction and data access ratios.

[0039] Calculate the TLB hit rate by reading the number of TLB hits and misses recorded in the hardware performance counter. Read the number of prefetch hits and misses recorded in the hardware performance counter, and calculate the prefetch success rate. Broadcast the collected instruction access ratio, TLB hit rate, and prefetch success rate through a 32-bit status bus every cycle; the status bus broadcasts every cycle through a 32-bit status bus, where [7:0] represents the operation mode encoding, [15:8] represents the instruction ratio, [23:16] represents the prefetch success rate, and [31:24] represents the TLB hit rate, so as to realize the sharing of status information and collaborative work among modules.

[0040] S2: Through the path predictor, perform a hash calculation based on the preset bits of the virtual address, query the historical record table to obtain the predicted path and confidence level; determine the query range according to the confidence level through the dynamic weight hierarchical cache.

[0041] In the specific implementation, first, perform a hash calculation by the path predictor based on the virtual address VA[47:39], query the historical record table to obtain the predicted path and the path prediction confidence Z. For example, the path predictor uses a 4-way set-associative structure historical record table, and updates the confidence value of the corresponding path after each page table traversal, adding 3 when hitting and subtracting 5 when missing, performs a CRC8 hash calculation on VA[47:39] to obtain the index, and outputs the confidence level.

[0042] Then, determine the confidence level according to the path prediction confidence Z; when Z≥6, it is a high confidence level; when 5<Z<6, it is a medium confidence level; when Z≤5, it is a low confidence level. Determine the page table level to be queried according to the confidence level; the page table adopts a four-level page table of PGD, PUD, PMD, and PTE, that is, a four-level page table (PGD→PUD→PMD→PTE) using the x86 architecture.

[0043] When the confidence level is high, only query the range of the predicted level ±1; when the confidence level is low, perform a full-level parallel query.

[0044] S3: When the cache hits, calculate the score of the hit entry using the comprehensive scoring formula, perform priority sorting and eviction decision on the cache entries based on the score, and at the same time use a hybrid replacement algorithm to manage the cache entries.

[0045] In the specific implementation, when the cache is hit, the score Score of the hit entry is calculated using the comprehensive scoring formula Score = α • LevelWeight + β • TypeBoost - γ • Δt; where α is the scaling factor of the path prediction confidence, LevelWeight is the weight of the page table level where the cache entry is located, β is the type gain coefficient of the instruction access ratio, TypeBoost is the type gain of the cache entry, γ is the time decay factor related to the prefetch hit rate, and Δt is the access time interval of the cache entry; if the cache entry is in the PGD layer, LevelWeight = 4; if the cache entry is in the PUD layer, LevelWeight = 3; if the cache entry is in the PMD layer, LevelWeight = 2; if the cache entry is in the PTE layer, LevelWeight = 1.

[0046] It should be noted that the initial hierarchical weight of the dynamic weight hierarchical cache can be flexibly configured according to the actual page table level and application scenario. At the same time, in the cumulative mode of actual benefit calculation, the weight accumulation rules for each level apply to page table systems with different hierarchical structures.

[0047] From this, it can be seen that the dynamic weight hierarchical cache adopts a multi-dimensional scoring model, including three dimensions: hierarchical weight, type gain, and time decay. The initial hierarchical weights are set as L4 = 4, L3 = 3, L2 = 2, L1 = 1. The actual benefit calculation adopts the cumulative mode. For example, when L3 is hit, the total weight = L3 + L2 + L1 = 6; the type gain is through the type gain coefficient β of the instruction access ratio, and the time decay uses a 48-bit high-precision timer to calculate the access time interval Δt of the cache entry; in the comprehensive scoring formula, α is dynamically scaled by the path prediction confidence, β is calculated by the monitoring module in real time for the instruction ratio, and γ changes dynamically with the prefetch hit rate.

[0048] After the calculation is completed, according to the score Score of the hit entry, determine the cache priority of the entry and perform caching; When the number of idle entries in the current cache is greater than or equal to 10% of the total number of entries, classify the cache entries into four hierarchical categories: PGD, PUD, PMD, and PTE. Randomly select 2 candidate entries from each category to classify the cache entries into four hierarchical categories: PGD, PUD, PMD, and PTE. Randomly select 2 candidate entries from each category for replacement; When the number of idle entries in the current cache is less than 10% of the total number of entries, eliminate the entries with Score < 2; For the entries that are continuously hit 3 times, lock them in the cache for 200 cycles.

[0049] S4: When the preset trigger condition is met, start the prefetch operation through the adaptive prefetch engine, perform calculations using Q4.12 fixed-point numbers and dynamically expand the prefetch step size, and at the same time prevent memory bandwidth contention through two-level monitoring.

[0050] In the specific implementation manner, the preset trigger condition is that the entry loading of the current PTE level is completed, the remaining space in the dynamic cache is greater than 20% of the total cache space, and Z≥5. If this condition is met, start the prefetch operation through the adaptive prefetch engine.

[0051] After starting, update the step size value every 100 cycles. The initial step size is ±2 pages. Calculate and update the step size value stride according to the step size calculation formula using the real-time entry hit rate to perform dynamic expansion of the step size; at the same time, sample the miss rate Q of the L1D-Cache every 50 cycles. When Q>15% accumulates 3 times, turn off the prefetch operation for 200 cycles.

[0052] It should be specifically noted that the step size calculation formula in the dynamic step size adjustment can be adaptively adjusted according to different hardware architectures and performance requirements, but it is necessary to determine the dynamic expansion method of the step size based on the logarithmic analysis of the recent hit rate to ensure the effectiveness and adaptability of the prefetch operation.

[0053] S5: When the instruction access ratio, TLB hit rate, and prefetch success rate meet the preset conditions, activate the instruction priority mode, and update the scores of the hit entries by adjusting the relevant parameters of the comprehensive scoring formula.

[0054] In the specific implementation manner, detect the instruction access ratio InstrRatio in real time; When it is detected that InstrRatio>60%, the TLB hit rate is less than 85%, and the prefetch success rate is greater than 40%, activate the instruction priority mode, increase TypeBoost to 1.2 times the current value, force the β value to be set to 0.1, and update the score Score of the entry; at the same time, dynamically adjust the value of the type gain coefficient β of the instruction access ratio according to the formula β = max(0, min(0.5, 0.2 + 0.5•(InstrRatio - 0.6))) in real time, and update the score Score of the entry.

[0055] In this embodiment, the virtual address is hashed by the path predictor and the access path is predicted in combination with the historical record. The dynamic weight hierarchical cache adjusts the query range according to the confidence level. The comprehensive scoring formula integrates the hierarchical weight, instruction type gain, and time decay factors to optimize the cache priority. The adaptive prefetch engine uses the Q4.12 fixed-point number algorithm to dynamically expand the prefetch step size and monitors the cache miss rate. The instruction priority mode adjusts the scoring parameters according to the real-time performance metrics, achieving a significant optimization of the page table traversal latency reduction, TLB hit rate improvement, memory bandwidth efficient utilization, and system performance in instruction-intensive scenarios.

[0056] Further, as a refinement and extension of the specific implementation manner of the above embodiment, in order to fully illustrate the specific implementation process in this embodiment, another method for accelerating multi-level page table traversal is provided. Taking the four-level page table (PGD → PUD → PMD → PTE) of the x86 architecture as an example, this method is also applicable to page table systems with other hierarchical structures.

[0057] As Figure 2 shown, this method works collaboratively according to the following steps: Address input stage: The virtual address VA[47:0] is input to the path predictor and the dynamic weight hierarchical cache simultaneously. The monitoring module collects the instruction / data access ratio in real time.

[0058] Parallel prediction stage: The path predictor queries the historical record table according to the VA[47:39] hash value, and outputs the predicted path (such as direct access from PUD to PTE) and the confidence level (high / medium / low three levels). The dynamic weight hierarchical cache selects the query range according to the confidence level: for high confidence level (≥6), only query the range of prediction level ±1 (such as query PUD + PMD when predicting PUD); for low confidence level (≤5), perform parallel query of all levels.

[0059] Weight calculation stage: When the cache hits, the scoring module calculates the Score value of the hit entry according to the formula: Score = α • LevelWeight + β• TypeBoost -γ • Δt where, LevelWeight adopts the preset value of the register (extended to PGD = 4, PUD = 3, PMD = 2, PTE = 1 in the four-level page table scenario) Prefetch adjustment stage: The prefetch engine operates dynamically according to the following conditions: Trigger condition: PTE loading is completed, and the remaining cache space > 20%, and the prediction confidence level ≥ 5; Step size calculation: (Implemented using Q4.12 fixed-point number).

[0060] Conflict monitoring stage: When the L1D-Cache miss rate is > 15% for three consecutive times, the prefetch function is turned off for 200 cycles.

[0061] In an embodiment of the present invention, based on step S2, a possible embodiment will be given below to non-restrictively elaborate on its specific implementation.

[0062] Reference Figure 3 As shown, this embodiment discloses a multi-level path prediction generation method, including: historical table update and prediction generation.

[0063] The historical table update adopts a 4-way set-associative structure. After each page table traversal, the confidence value of the corresponding path is updated. When there is a hit, it is incremented by 3, and when there is a miss, it is decremented by 5. Each item stores the following content: struct { uint8_t va_tag[5]; / / Hash value of VA[47:43] uint16_t path_bits; / / Bitmap of successful paths (bit0: PGD, bit1: PUD,...) uint8_t confidence; / / Confidence counter (0 - 15) } For prediction generation, a CRC8 hash calculation is performed on VA[47:39] to obtain an index, and the confidence level is output. The relevant commands are as follows: if(confidence >= 12) return HIGH; else if(confidence >= 6) return MEDIUM; else return LOW; In an embodiment of the present invention, based on step S3, a possible embodiment will be given below to non-restrictively elaborate on its specific implementation.

[0064] Reference Figure 4 As shown, this embodiment discloses a dynamic weight hierarchical cache management method, including: entry replacement decision, high-frequency protection mechanism, and instruction priority mode.

[0065] Entry replacement decision: When the number of free entries ≥ 10%, they are bucketed by level (four buckets: PGD / PUD / PMD / PTE), and 2 candidate entries are randomly sampled from each bucket; when the number of free entries < 10%: Activate the Score threshold filter, and preferentially eliminate entries with Score < 2.0.

[0066] High-frequency protection mechanism: For entries that are continuously hit 3 times, set 200 cycle lock marks (lock_bit = 1), and during the locking period, the Score value is weighted by 1.5.

[0067] Instruction priority mode: When the monitoring module detects that InstrRatio > 60%, the TypeBoost coefficient of the instruction page is increased to 1.2 times, and the β value of the data page is forced to be set to 0.1.

[0068] In one embodiment of the present invention, based on step S4, the following will give a possible embodiment to non-restrictively elaborate on its specific implementation.

[0069] Reference Figure 5 As shown, this embodiment discloses a cross-level adaptive prefetch control method, including dynamic step size adjustment and conflict detection.

[0070] Dynamic step size adjustment updates the step size value every 100 cycles, and the hardware implementation uses a shifter to calculate 2 n . The specific commands are as follows: always_comb begin hit_log = (hit_rate>0)? $clog2(hit_rate*100) : 0; stride = 1<<(hit_log[3:0]&4'b0011); / / Limit the maximum step size to 8 end Conflict detection includes short-term detection and long-term regulation. Short-term detection means sampling the Miss event counter of the L1D-Cache every 50 cycles, and long-term regulation means that after 3 consecutive high misses, the prefetch engine is switched to the low-power mode (only maintaining ±1 page prefetch).

[0071] In one embodiment of the present invention, based on step S5, the following will give a possible embodiment to non-restrictively elaborate on its specific implementation.

[0072] Reference Figure 6 As shown, this embodiment discloses a system state monitoring and mode switching method, including instruction ratio detection, mode switching decision-making, and status bus transmission.

[0073] Instruction ratio detection uses a 32-bit sliding window counter: +1 for each instruction access, -1 for each data access. InstrRatio = (counter + 32768) / 65536.0 is calculated in real time.

[0074] The mode switching decision activates the instruction priority mode when multiple conditions are met simultaneously: InstrRatio > 60%, TLB hit rate < 85%, prefetch success rate > 40%.

[0075] Status bus transmission is broadcast via a 32-bit status bus per cycle, where [7:0] represents the running mode encoding, [15:8] represents the instruction ratio, [23:16] represents the prefetch success rate, and [31:24] represents the TLB hit rate.

[0076] As Figure 7 shown, the following is an embodiment of the multi-level page table traversal acceleration system provided by the present disclosure. This system belongs to the same inventive concept as the multi-level page table traversal acceleration methods of the above embodiments. For the details not described in detail in the embodiment of the multi-level page table traversal acceleration system, reference can be made to the embodiments of the above multi-level page table traversal acceleration methods.

[0077] A multi-level page table traversal acceleration system includes: An address input and status monitoring module for inputting virtual addresses to a path predictor and a dynamic weight hierarchical cache respectively, and collecting the instruction access ratio, TLB hit rate, and prefetch success rate in real time; A path prediction and query planning module for performing hash calculation according to the preset bits of the virtual address through the path predictor, querying the historical record table to obtain the predicted path and confidence level; determining the query range according to the confidence level through the dynamic weight hierarchical cache; Weight evaluation and cache management for calculating the score of the hit entry using a comprehensive scoring formula when the cache hits, performing priority sorting and eviction decision of the cache entries based on the score, and managing the cache entries using a hybrid replacement algorithm at the same time; A prefetch strategy adjustment module for starting a prefetch operation through an adaptive prefetch engine when a preset trigger condition is met, calculating using Q4.12 fixed-point numbers and dynamically expanding the prefetch step size, and preventing memory bandwidth contention through two-level monitoring at the same time; A mode switching and parameter adjustment module for activating the instruction priority mode when the instruction access ratio, TLB hit rate, and prefetch success rate meet the preset conditions, and updating the score of the hit entry by adjusting the relevant parameters of the comprehensive scoring formula.

[0078] The multi-level page table traversal acceleration system provided in this embodiment calculates the hash value of the preset bits of the virtual address through a path predictor and combines the historical records to predict the access path. It determines the query range according to the confidence level by using a dynamic weight hierarchical cache, and optimizes the cache entry priority by fusing the page table level weight, instruction type gain and time decay factor with a comprehensive scoring formula. It cooperates with an adaptive prefetching engine to dynamically expand the prefetch step size using Q4.12 fixed-point numbers and prevent memory bandwidth contention by monitoring the cache miss rate. In addition, it activates the priority mode in an instruction-intensive scenario to adjust the scoring parameters, achieving a significant reduction in page table traversal latency, an improvement in TLB and cache hit rates, an efficient allocation of memory bandwidth, and an optimization of the overall system performance.

[0079] Figure 8 Schematic diagram of the hardware structure of an electronic device for implementing each embodiment of the present invention.

[0080] The multi-level page table traversal acceleration method provided in the embodiments of this application can be applied to electronic devices. Those skilled in the art can understand that the structure of the electronic device involved in the embodiments of the present invention does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements. In the embodiments of the present invention, the electronic device includes, but is not limited to, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of this application described herein and / or claimed.

[0081] The electronic device may include a processor, an external memory interface, an internal memory, a universal serial bus (USB) interface, a charging management module, a power management module, a battery, a wireless communication module, an audio module, a speaker, a microphone, a sensor module, a key, a camera, a display screen, and a SIM card interface, etc.

[0082] The processor may include one or more processing units. For example, the processor may include a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors.

[0083] Among them, the processor may be the nerve center and command center of the electronic device. The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of fetching and executing instructions.

[0084] A memory may also be provided in the processor for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store the instructions or data that the processor has just used or recycled. If the processor needs to use the instruction or data again, it can directly call it from this memory. This avoids repeated accesses, reduces the waiting time of the processor, and thus improves the system efficiency.

[0085] The external memory interface can be used to connect an external memory card, such as a MicroSD card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor through the external memory interface to achieve the data storage function. For example, files such as music and videos are saved in the external memory card.

[0086] The internal memory can be used to store computer-executable program code, and the computer-executable program code includes instructions. The processor executes various functional applications and data processing of the electronic device by running the instructions stored in the internal memory. The internal memory may include a program storage area and a data storage area. The internal memory may include a high-speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0087] The wireless communication function of the electronic device can be implemented through an antenna, a wireless communication module, a modem processor, a baseband processor, etc.

[0088] The wireless communication module can provide solutions for wireless communications applied to electronic devices, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite systems (GNSS), frequency modulation (FM), near field communication (NFC), infrared technology (IR), etc.

[0089] The electronic device can implement audio functions through an audio module, speakers, receivers, microphones, headphone jacks, application processors, etc.

[0090] The electronic device can implement a shooting function through an ISP, a camera, a video codec, a GPU, a display screen, and an application processor, etc.

[0091] The electronic device can implement a display function through a GPU, a display screen, and an application processor, etc.

[0092] The GPU is a microprocessor for image processing, connecting the display screen and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor may include one or more GPUs, which execute program instructions to generate or change display information.

[0093] The display screen is used to display images, videos, etc. The display screen includes a display panel.

[0094] The above electronic device realizes the multi-level page table traversal acceleration method of this application. The virtual address is hashed by the path predictor and combined with historical records to predict the path. The dynamic weight hierarchical cache adjusts the query range according to the confidence level. The comprehensive scoring formula fuses the hierarchical weight, instruction type gain, and time decay to optimize the cache priority. The adaptive prefetch engine uses the Q4.12 fixed-point number algorithm to dynamically expand the prefetch step size and monitors the cache miss rate. And the instruction priority mode adjusts the scoring parameters according to real-time metrics, achieving the beneficial effects of reducing page table traversal latency, improving TLB hit rate, optimizing memory bandwidth utilization, and enhancing performance in instruction-intensive scenarios.

[0095] In the storage medium provided by this application, there is a program product capable of implementing the multi-level page table traversal acceleration method.

[0096] The multi-level page table traversal acceleration method includes: Input the virtual address into the path predictor and the dynamic weight hierarchical cache respectively, and collect the instruction access ratio, TLB hit rate, and prefetch success rate in real time; The path predictor performs hash calculation based on the preset bits of the virtual address, queries the historical record table to obtain the predicted path and confidence level; the dynamic weight hierarchical cache determines the query range according to the confidence level; When the cache hits, calculate the score of the hit entry using the comprehensive scoring formula, perform priority sorting and eviction decision of the cache entries based on the score, and manage the cache entries using a hybrid replacement algorithm at the same time; When the preset trigger condition is met, start the prefetch operation through the adaptive prefetch engine, calculate using Q4.12 fixed-point numbers and dynamically expand the prefetch step size, and prevent memory bandwidth contention through two-level monitoring at the same time; When the instruction access ratio, TLB hit rate, and prefetch success rate meet the preset conditions, activate the instruction priority mode, and update the score of the hit entry by adjusting the relevant parameters of the comprehensive scoring formula. In some possible implementation manners, the multi-level page table traversal acceleration method of the present disclosure may be implemented in the form of a program product, which includes program code. When the program product runs on a terminal device, the program code is used to cause the terminal device to execute the steps according to various exemplary embodiments of the present disclosure described in the "Exemplary Method" section of this specification.

[0097] The storage medium of the present disclosure may adopt any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0098] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for accelerating multi-level page table traversal, characterized in that including: Input the virtual address into the path predictor and the dynamic weight hierarchical cache respectively, and collect the instruction access ratio, TLB hit rate, and prefetch success rate in real time; The path predictor performs a hash calculation based on the preset bits of the virtual address, and queries the historical record table to obtain the predicted path and confidence level; the dynamic weight hierarchical cache determines the query range according to the confidence level; When the cache hits, calculate the score of the hit entry using the comprehensive scoring formula, perform priority sorting and eviction decision of the cache entry based on the score, and at the same time manage the cache entry using the hybrid replacement algorithm; When the preset trigger condition is met, start the prefetch operation through the adaptive prefetch engine, calculate using Q4.12 fixed-point numbers and dynamically expand the prefetch step size, and at the same time prevent memory bandwidth contention through two-level monitoring; When the instruction access ratio, TLB hit rate, and prefetch success rate meet the preset conditions, activate the instruction priority mode, and update the score of the hit entry by adjusting the relevant parameters of the comprehensive scoring formula.

2. The multi-level page table traversal acceleration method according to claim 1, wherein The step of inputting the virtual address into the path predictor and the dynamic weight hierarchical cache respectively, and collecting the instruction access ratio, TLB hit rate, and prefetch success rate in real time includes: Input the virtual address VA[47:0] into the path predictor and the dynamic weight hierarchical cache respectively; Use a 32-bit sliding window counter to detect the instruction access ratio in real time. When the CPU executes an instruction, the counter value counter is incremented by 1; when the CPU accesses data, the counter value counter is decremented by 1. Calculate the instruction access ratio InstrRatio in real time through the formula InstrRatio=(counter+32768) / 65536.0; Calculate the TLB hit rate by reading the number of TLB hits and misses recorded in the hardware performance counter; Read the number of prefetch hits and misses recorded in the hardware performance counter, and calculate the prefetch success rate; Broadcast the collected instruction access ratio, TLB hit rate, and prefetch success rate through the 32-bit status bus every cycle; in the 32-bit status bus, bit segment [7:0] represents the operation mode encoding, bit segment [15:8] represents the instruction ratio, bit segment [23:16] represents the prefetch success rate, and bit segment [31:24] represents the TLB hit rate.

3. The multi-level page table traversal acceleration method according to claim 2, wherein The step of the path predictor performing a hash calculation based on the preset bits of the virtual address, querying the historical record table to obtain the predicted path and confidence level; and the dynamic weight hierarchical cache determining the query range according to the confidence level includes: The path predictor performs a hash calculation based on the virtual address VA[47:39], and queries the historical record table to obtain the predicted path and the path prediction confidence Z; Determine the confidence level according to the path prediction confidence Z; when Z≥6, it is a high confidence level; when 5<Z<6, it is a medium confidence level; when Z≤5, it is a low confidence level Determine the page table level to be queried according to the confidence level; the page table adopts a four-level page table of PGD, PUD, PMD, and PTE; When the confidence level is high, only query the range of ±1 levels of the prediction hierarchy; when the confidence level is low, perform a full-hierarchy parallel query.

4. The multi-level page table traversal acceleration method according to claim 3, wherein When the cache is hit, use the comprehensive scoring formula to calculate the score of the hit entry, perform priority sorting and eviction decision of the cache entry based on the score, and at the same time use a hybrid replacement algorithm to manage the cache entry, including: When the cache is hit, use the comprehensive scoring formula Score = α • LevelWeight + β• TypeBoost -γ •Δt to calculate the score Score of the hit entry; where α is the scaling factor of the path prediction confidence, LevelWeight is the weight of the page table level where the cache entry is located, β is the type gain coefficient of the instruction access ratio, TypeBoost is the type gain of the cache entry, γ is the time decay factor related to the prefetch hit rate, and Δt is the access time interval of the cache entry; if the cache entry is in the PGD layer, LevelWeight = 4; if the cache entry is in the PUD layer, LevelWeight = 3; if the cache entry is in the PMD layer, LevelWeight = 2; if the cache entry is in the PTE layer, LevelWeight = 1; Determine the cache priority of the entry according to the score Score of the hit entry and perform caching; When the number of free entries in the current cache is greater than or equal to 10% of the total number of entries, classify the cache entries into four level categories of PGD, PUD, PMD, and PTE, and randomly select 2 candidate entries for each category to classify the cache entries into four level categories of PGD, PUD, PMD, and PTE, and randomly select 2 candidate entries for each category for replacement; When the number of free entries in the current cache is less than 10% of the total number of entries, evict the entries with Score < 2; For the entries that are continuously hit 3 times, lock them in the cache for 200 cycles.

5. The multi-level page table traversal acceleration method according to claim 4, wherein When the preset trigger condition is met, start the prefetch operation through the adaptive prefetch engine, calculate using Q4.12 fixed-point numbers and dynamically expand the prefetch step size, and at the same time prevent memory bandwidth contention through two-level monitoring, including: If the entry in the current PTE level is loaded, the remaining space in the dynamic cache is greater than 20% of the total cache space, and Z≥5, start the prefetch operation through the adaptive prefetch engine; Update the step size value every 100 cycles, the initial step size is ±2 pages, and calculate and update the step size value stride using the step size calculation formula according to the real-time entry hit rate to perform dynamic expansion of the step size; Sample the miss rate Q of the L1D-Cache every 50 cycles, and when Q>15% accumulatively for 3 times, turn off the prefetch operation for 200 cycles.

6. The multi-level page table traversal acceleration method according to claim 5, wherein The step size calculation formula is: Among them, is the entry hit rate.

7. The multi-level page table traversal acceleration method according to claim 6, characterized in that When the instruction access ratio, TLB hit rate, and prefetch success rate meet the preset conditions, activate the instruction priority mode, and update the score of the hit entry by adjusting the relevant parameters of the comprehensive scoring formula, including: Real-time detect the instruction access ratio InstrRatio; When InstrRatio > 60%, TLB hit rate < 85%, and prefetch success rate > 40% are detected, the instruction priority mode is activated, TypeBoost is increased to 1.2 times the current value, the β value is forced to be set to 0.1, and the score of the entry is updated. Dynamically adjust the value of the type gain coefficient β of the instruction access ratio in real time according to the formula β = max(0, min(0.5, 0.2 + 0.5•(InstrRatio - 0.6))), and update the score of the entry.

8. A multi-level page table traversal acceleration system, characterized in that The system adopts the multi-level page table traversal acceleration method described in any one of claims 1 to 7. The system includes: An address input and status monitoring module, configured to input the virtual address into the path predictor and the dynamic weight hierarchical cache respectively, and collect the instruction access ratio, TLB hit rate, and prefetch success rate in real time. A path prediction and query planning module, configured to perform hash calculation according to the preset bits of the virtual address through the path predictor, query the historical record table to obtain the predicted path and confidence level; determine the query range according to the confidence level through the dynamic weight hierarchical cache. Weight evaluation and cache management, configured to calculate the score of the hit entry using the comprehensive scoring formula when the cache is hit, perform priority sorting and eviction decision of the cache entries based on the score, and manage the cache entries using the hybrid replacement algorithm at the same time. A prefetch strategy adjustment module, configured to start the prefetch operation through the adaptive prefetch engine when the preset trigger condition is met, calculate using Q4.12 fixed-point numbers and dynamically expand the prefetch step size, and prevent memory bandwidth contention through two-level monitoring at the same time. A mode switching and parameter adjustment module, configured to activate the instruction priority mode when the instruction access ratio, TLB hit rate, and prefetch success rate meet the preset conditions, and update the score of the hit entry by adjusting the relevant parameters of the comprehensive scoring formula.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the multi-level page table traversal acceleration method described in any one of claims 1 to 7.

10. A storage medium, on which a computer program is stored, characterized in that, When the computer program is executed by the processor, it implements the steps of the multi-level page table traversal acceleration method described in any one of claims 1 to 7.

Images