BFM random response method, electronic device and storage medium

Abstract

The present invention relates to the field of chip design, and in particular to a BFM random response method, electronic device, and storage medium. The method configures a fast response time period and a fast response probability for each bus function model, and calculates the response probability of the current bus function model in each fast response time period; the steps of each bus function model performing a random response according to the response probability include: generating a random number, sequentially comparing the random number with each response probability, and when the random number is less than or equal to the jth response probability, the current bus function model responds in the jth fast response time period; and calculating the RT by the random number. i The random response probability within different multiples of time periods is used to achieve the goal of balancing simulation speed and real scenarios.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and in particular to a BFM random response method, electronic equipment and storage medium. Background Art

[0002] The RTL (Register Transfer Level) interface is responsible for reading and writing data. In digital verification (DV), a bus functional model (BFM) is configured to respond to these read and write requests. For example, when an RTL interface reads data, the BFM must return the data to the interface. Each interface must have a corresponding BFM to respond. The BFM response time during simulation is not the same as the actual full-chip response time. For example, during simulation, the BFM returns data to the RTL interface after 5-10 clock cycles; in a real-world scenario, it may take 5,000 or even 10,000 clock cycles to return the data to the corresponding interface. IP verification differs from the real-world chip due to the high traffic volume. For example, a real-world chip might continuously send 1,000 to 10,000 data records to verify correct interface behavior. However, if each data record requires 5,000 or even 10,000 clock cycles to respond, simulation time becomes very long, significantly reducing simulation efficiency and posing a significant challenge to chip verification.

[0003] For example, during simulation, data is returned in 10 clock cycles; in real-world scenarios, data is returned in 1000 clock cycles. In this case, the simulation fails to accurately simulate the real-world scenario. If the current design can only respond correctly within 100 clock cycles, it will fail to respond correctly beyond 100 clock cycles. Since the simulation has not verified the real-world response time of 1000 clock cycles, it may fail to respond correctly in the real world, ultimately leading to erroneous results.

[0004] Therefore, there is an urgent need for a return method that can take into account both simulation speed and real-world scenarios. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention adopts a technical solution: a BFM random response method, which includes the following steps:

[0006] S100, obtaining N interfaces INTER in the chip to be tested and the bus function model BFM of each interface in the verification system, where INTER={inter1,inter2,…,inter i ,…,inter N},interi For the i-th interface inter i , the value range of i is 1 to N; BFM={BFM1,BFM2,…,BFM i ,…,BFM N}, BFM i For inter i Bus Functional Model BFM i .

[0007] S200, configuring a fast response time period and a fast response probability for each bus function model, where BFM i Configure the rapid response time range (RT). i and the probability of rapid response a i .

[0008] S300, according to the fast response time period and the fast response probability, obtain the response probability of each bus function model in each fast response time period; wherein, BFM i In K RT i The response probability within is P i ={P i1 ,P i2 ,…,P ij ,…,P iK}, P ij For BFM i At the jth RT i The response probability within, j ranges from 1 to K; where P ij Satisfied: P ij = (1-a i ) j-1 ×a i .

[0009] S400, each bus function model performs a random response according to the response probability, wherein BFM i Each random response step includes:

[0010] S410, generate BFM i The random number r i , r i The value range is 0 to 1.

[0011] S420, compare the r i With P i Each response probability in, when the r i Less than or equal to the P ij When BFM i At the jth RT i Respond within.

[0012] In addition, the present invention also provides a non-transitory computer-readable storage medium, which stores at least one instruction or at least one program, and the at least one instruction or at least one program is loaded and executed by a processor to implement the above method.

[0013] In addition, the present invention also provides an electronic device including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0014] The present invention has at least the following beneficial effects:

[0015] The present invention provides a BFM random response method, electronic device and storage medium, which configures a fast response time period and a fast response probability for each bus function model, and calculates the response probability of the current bus function model in each fast response time period; generates a random number, compares the random number with the response probability of the current bus function model in each fast response time period, and then determines the fast response time period of the random response; calculates RT by random number i The random response probability within different multiples of time periods is used to achieve the goal of balancing simulation speed and real scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A flow chart of a BFM random response method provided by an embodiment of the present invention;

[0018] Figure 2 BFM provided by the embodiment of the present invention i Flowchart of the random response steps for each time. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0021] See also Figure 1 , which shows a BFM random response method, the method comprising the following steps:

[0022] S100, obtaining N interfaces INTER in the chip to be tested and the bus function model BFM of each interface in the verification system, where INTER={inter1,inter2,…,inter i ,…,inter N},inter i For the i-th interface inter i , the value range of i is 1 to N; BFM={BFM1,BFM2,…,BFM i ,…,BFM N}, BFM i For inter i Bus Functional Model BFM i .

[0023] The Bus Functional Model (BFM) primarily defines how data is transmitted and interacted between system components via the bus. It describes how signals and messages are exchanged between modules under different conditions to achieve specific functionality. During verification, the BFM abstracts bus interconnections and provides a high-level interface for implementing a testbench that stimulates RTL modules.

[0024] As an example, inter i Used to achieve direct data transfer between the hard disk and system memory. BFM i Used to simulate inter i Various functions during the data transfer process, such as the initiation of DMA requests, the timing of data transfer, and the response after the transfer is completed.

[0025] S200, configuring a fast response time period and a fast response probability for each bus function model, where BFM i Configure the rapid response time range (RT). i and the probability of rapid response a i .

[0026] The fast response time period is the time period in which the bus function model is expected to respond quickly. This time period is a length of time, not a specific time point range. i is [t0 i ,t1 i As an example, RT i The value is [100,200], and the time unit is milliseconds.

[0027] Among them, t0i The value of t1 is the shortest time to complete an event, which is a fixed lower limit determined based on the basic characteristics of the event itself. i It is determined based on the simulation time of each bus function model; when each bus function model is executed in a single test case, its simulation time has a preset upper limit value. i Dynamic adjustment is performed within the limits of the preset upper limit. That is, t1 i The value is greater than t0 i and must be less than or equal to the upper limit of the simulation time.

[0028] The quick response probability is the possibility of responding within the current quick response time period.

[0029] In order to accurately and reasonably configure the fast response time period and fast response probability for each bus functional model, it is necessary to comprehensively consider two key factors: the protocol characteristics of the interface itself and the workload.

[0030] In one embodiment, according to i The protocol being followed determines the event type generated. The fast response probability is determined based on the priority of the event types for different interfaces, providing a stable and reliable foundation for subsequent simulation processes. The event type priority refers to the event type of each interface. Different interfaces correspond to different event types. When configuring the fast response probability, the priority of the event type is determined accordingly. The fast response probability of interfaces with higher-priority event types is set higher, while the fast response probability of interfaces with lower-priority event types is set lower. It should be noted that when it comes to interfaces with a specific protocol bus, the interface strictly performs all operations according to the corresponding protocol. This means that the events generated during operation are completely defined by the protocol, and therefore the event types are fixed. For example, the SPI (Serial Peripheral Interface) protocol bus interface has major operational event types including master-initiated clock signal generation, slave select signal switching, and data transmission and reception. These event types are specified by the SPI protocol, and any interface based on the SPI protocol adheres to this standard.

[0031] In one embodiment, inter i Load size and RT i The size of the load is negatively correlated. The greater the load, the i The smaller the value of ; the smaller the load, the RT i The larger the value of i The load is determined by the product of events and the number of entries.

[0032] S300, according to the fast response time period and the fast response probability, obtain the response probability of each bus function model in each fast response time period; wherein, BFM i In K RT i The response probability within is P i ={P i1 ,P i2 ,…,P ij ,…,P iK}, P ij For BFM i At the jth RT i The response probability within, j ranges from 1 to K; where P ij Satisfied: P ij = (1-a i ) j-1 ×a i .

[0033] In one embodiment, S300 further includes providing a BFM i Initialize a counter, the value of the counter j is the jth RT currently being calculated i The response probability P ij ; After calculating P ij After that, the counter value is updated to j+1, and the response probability is calculated again according to S300 until j=K. After calculating P iK Stop when K×RT i BFM in the simulation process i The maximum response time can be used to configure the value of K based on experience. It should be noted that when the interface functionality is simple, since system behavior is relatively easy to predict and simulate, and there is no need to simulate an excessively long response time, K can be set to a smaller value. However, when the interface may have various complex interactions and delays, K can be set to a larger value to more fully simulate the longer response times that may occur in real-world scenarios.

[0034] It should be noted that each bus function model corresponds to a counter.

[0035] In one embodiment, S310 further includes a counter management step:

[0036] S311 , define a data container having a size equal to the number N of bus function models, for storing the counter.

[0037] In one embodiment, the data container is an array or a hash table (such as a Python dictionary). If a hash table is used, its key is the index of the BFM, and its value is initialized to 1. Other types of data containers also fall within the scope of protection of the present invention.

[0038] S312, initialize the value corresponding to each element in the data container to 1, indicating that from the first RT i Start calculating.

[0039] S313, calculate each BFM at different RT i When the response probability is within , the value of the corresponding counter is obtained from the data container.

[0040] S314: After calculating the response probability, increase the value of the corresponding counter in the data container by 1.

[0041] S315: After each update, check whether the value of the counter reaches K. If so, stop calculating the response probability of the BFM.

[0042] The management steps S311-S315 can reduce the complexity of resource management, simplify the code structure, and improve the readability and maintainability of the code.

[0043] S400: Each bus function model performs a random response according to the response probability.

[0044] Among them, see Figure 2 , BFM i Each random response step includes:

[0045] S410, generate BFM i The random number r i , r i The value range is 0 to 1.

[0046] In one embodiment, the random number in S410 is generated by a random number generator each time the response time is simulated, and is uniformly distributed in the range of 0 to 1. The uniform distribution of random numbers can ensure the accuracy of probability calculation.

[0047] In one embodiment, the random number generation algorithm is a lagged Fibonacci generator, a pseudo-random number generation algorithm based on Mersenne prime numbers, or a Xorshift algorithm. Other algorithms for generating random numbers also fall within the scope of protection of the present invention.

[0048] S420, compare the r i With P i Each response probability in, when the r i Less than or equal to the P ij When BFM i At the jth RT i Respond within.

[0049] In one embodiment, the comparison step includes: starting from j=1, comparing ri With P ij If the size between i Greater than the P ij , then BFM i No response, update j to j+1, and continue to compare r i With P ij The size between; if r i Less than or equal to the P ij , then BFM i At the jth RT i Respond within 1 second and stop comparing.

[0050] When the value of j is determined, the response time is the jth RT i As an example, when j=3, RT i The value is [100, 200], measured in milliseconds. This means the response time is randomly selected between the third millisecond interval [100, 200], or between 300 and 400 milliseconds. Once the response time is determined, the bus function model performs the corresponding operation at that response time. For example, the bus function model processes the received data at the determined response time and sends it back to the requester.

[0051] Due to a i It is usually configured as a larger probability value, so in most cases the bus functional model will be in the first RT i This can speed up the overall simulation speed and meet the requirements of debugging simulation time. i The random response probability within different multiples of the time period can simulate the long response time of a full chip with a low probability, making the simulation closer to the real scene without excessively affecting the simulation speed; achieving the goal of taking into account both simulation speed and real scene. In addition, the method provided by the present invention can also be adjusted by adjusting RT i The length and a i The size of the time weight can be flexibly adjusted to accommodate different verification requirements.

[0052] In summary, the present invention provides a BFM random response method, which configures a fast response time period and a fast response probability for each bus function model, and calculates the response probability of the current bus function model in each fast response time period; generates a random number, compares the random number with the response probability of the current bus function model in each fast response time period, and then determines the fast response time period of the random response; calculates RT by random number i The random response probability within different multiples of time periods is used to achieve the goal of balancing simulation speed and real scenarios.

[0053] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0054] An embodiment of the present invention further provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0055] An embodiment of the present invention further provides a computer program product comprising program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0056] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0057] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A BFM random response method, characterized in that: The method comprises the following steps: S100, obtaining N interfaces INTER in the chip to be tested and the bus function model BFM of each interface in the verification system, where INTER={inter1,inter2,…,inter i ,…,inter N },inter i For the i-th interface inter i , the value range of i is 1 to N; BFM={BFM1,BFM2,…,BFM i ,…,BFM N }, BFM i For inter i Bus Functional Model BFM i ; S200, configure K fast response time periods and fast response probabilities for each bus function model, where i Configure the rapid response time range (RT). i and the probability of rapid response a i ; wherein the fast response time period is the time period in which the bus function model is expected to respond quickly; wherein, RT i is [t0 i ,t1 i ], t0 i The shortest time to complete an event, t1 i is greater than t0 i And it is less than or equal to the upper limit of the simulation time of the bus function model; S300, according to the fast response time period and the fast response probability, obtain the response probability of each bus function model in each fast response time period; wherein, BFM i In K RT i The response probability within is P i ={P i1 ,P i2 ,…,P ij ,…,P iK }, P ij For BFM i At the jth RT i The response probability within, j ranges from 1 to K; where P ij Satisfied: P ij = (1-a i ) j-1 ×a i ; S400, each bus function model performs a random response according to the response probability, wherein BFM i Each random response step includes: S410, generate BFM i The random number r i , r i The value range is 0 to 1; S420, compare the r i With P i Each response probability in, when the r i Less than or equal to the P ij When BFM i At the jth RT i Respond within.

2. The method according to claim 1, characterized in that S300 also includes BFM i Initialize a counter, the value of the counter j is the jth RT currently being calculated i The response probability P ij ; After calculating P ij After that, the counter value is updated to j+1, and the response probability is calculated again according to S300 until j=K. After calculating P iK Stop when 3. The method according to claim 2, characterized in that S310 also includes the counter management step: S311, defining a data container having a size equal to the number N of bus function models for storing a counter; S312, initialize the value corresponding to each element in the data container to 1, indicating that from the first RT i Start calculation; S313, calculate each BFM at different RT i When the response probability is within , the value of the corresponding counter is obtained from the data container; S314, after calculating the response probability, increase the value of the corresponding counter in the data container by 1; S315: After each update, check whether the value of the counter reaches K. If so, stop calculating the response probability of the BFM.

4. The method according to claim 3, characterized in that The data container is an array or a hash table.

5. The method according to claim 1, wherein The random number generation algorithm is a lagged Fibonacci generator, a pseudo-random number generation algorithm based on Mersenne primes, or a Xorshift algorithm.

6. The method according to claim 1, characterized in that In S400, the comparison step includes: starting from j=1, comparing r i With P ij If the size between i Greater than the P ij , then BFM i No response, update j to j+1, and continue to compare r i With P ij The size between; if r i Less than or equal to the P ij , then BFM i At the jth RT i Respond within 1 second and stop comparing.

7. The method according to claim 1, characterized in that According to inter i The protocol followed determines the type of event generated; the probability of a quick response is determined based on the priority of the event type of different interfaces.

8. The method according to claim 1, characterized in that inter i Load size and RT i The size is negatively correlated.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by a processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The device comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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