Digital circuit optimization method and system based on logic clustering

Abstract

The invention discloses a digital circuit optimization method and system based on logic clustering. The method comprises the following steps: S1, counting fan-out information of all registers in a circuit netlist; s2, according to the fan-out information of the registers, screening out the registers of which the fan-out quantity is greater than a first preset threshold value and the logic series is greater than a second preset threshold value and which are located on the critical path, and generating a candidate register list; s3, obtaining register fan-out first-level combinatorial logic information; s4, performing clustering operation on the logic units based on the first-level combinational logic information, and dividing physically adjacent logic units into the same cluster according to the physical position relationship of the logic units; s5, associating the clustered logic units together and adjusting the connection relation of the logic units; s6, carrying out equivalence check; and S7, rearranging and wiring the circuit according to the modified netlist. The physical distance of a time sequence path can be effectively reduced, the time sequence performance of the circuit is optimized, and the method is suitable for large-scale integrated circuit design.

Description

Technical Field

[0001] The present invention mainly relates to the field of integrated circuit design, and particularly relates to a digital circuit optimization method and system based on logic clustering. Background Art

[0002] In CMOS digital circuit design, registers are key components of timing paths, and timing optimization is one of the key steps to ensure circuit performance. With the continuous expansion of the scale of integrated circuits, the scale of timing paths grows exponentially, and the influence of exponentially growing physical rules on timing convergence becomes increasingly significant. Especially when dealing with large fan-out registers (i.e., one register drives hundreds or thousands of subsequent logic units), the timing optimization of these paths becomes extremely challenging. Currently, commercial electronic design automation (EDA) tools usually adopt the method of inserting inverters or buffer trees to optimize such timing paths when dealing with large fan-out registers. However, the current methods have the following deficiencies: 1. The insertion positions of inverters / buffers are unreasonable; commercial EDA tools usually insert inverters or buffers based on global optimization algorithms, but these algorithms often cannot fully consider the characteristics of local timing paths. For example, in some cases, inverters or buffers are inserted into non-critical paths, resulting in waste of resources; while on critical paths, the number of inserted inverters or buffers is insufficient to effectively reduce signal transmission delay.

[0003] 2. Lack of sufficient consideration for physical layout; when commercial EDA tools insert inverters or buffers, they often easily ignore the influence of physical layout. For example, the insertion of inverters or buffers does not drive relevant logic units together nearby, but is intertwined with each other, resulting in an increase in the length of signal lines, thereby introducing additional delay and power consumption. In addition, this unreasonable physical layout may also lead to routing congestion, further weakening the performance of circuit implementation.

[0004] In summary, when current commercial EDA tools deal with large fan-out registers, there are problems such as unreasonable insertion positions of inverters / buffers and lack of sufficient consideration for physical layout, which are difficult to meet the requirements of high-performance design of microprocessors. Therefore, there is an urgent need for a timing optimization method that can efficiently handle large fan-out registers to overcome the deficiencies of the prior art and improve the performance and reliability of circuit design. Summary of the Invention

[0005] In view of the technical problems existing in the prior art, the present invention provides a digital circuit optimization method and system based on logic clustering for realizing efficient optimization of timing paths.

[0006] To solve the above technical problems, the technical solution proposed by the present invention is: A digital circuit optimization method based on logic clustering, comprising the steps: S1. Statistically register fan-out information: Statistically the fan-out information of all registers in the circuit netlist, that is, the number of all subsequent logic units directly driven by the register output signal or indirectly driven across inverters and buffers, and generate a fan-out information table; S2. Generate a candidate register list: According to the fan-out information of all registers, filter out the registers with a fan-out number greater than the first preset threshold, a logic level greater than the second preset threshold and located on the critical path, and generate a candidate register list final_reg_list; S3. Obtain the primary combinational logic information of register fan-out: For each register in the candidate register list final_reg_list, obtain its primary combinational logic information; the primary combinational logic refers to the combinational logic units directly driven by the register output signal and indirectly driven across inverters / buffers; S4. Primary combinational logic clustering: Based on the primary combinational logic information obtained in S3, perform a clustering operation on the logic units, and divide the physically adjacent logic units into the same clustering cluster according to the physical position relationship of the logic units; S5. Modify the netlist after clustering: After completing the logic clustering, modify the netlist of the circuit, that is, associate the clustered logic units together and adjust their connection relationships; S6. Equivalence check: After the netlist modification is completed, perform an equivalence check to ensure that the function of the modified circuit is the same as that of the original circuit; if the equivalence check passes, proceed to the next step, otherwise return to step S5 to correct the connection relationship; S7. Re-layout and routing: Re-layout and route the circuit according to the modified netlist.

[0007] Preferably, the specific steps of S1 include: S101. Traverse all registers in the circuit netlist and record the output signals of each register; S102. Analyze the logic units driven by each output signal, including combinational logic units, inverter units and buffer units, add the combinational logic units to the combinational list com_list, and add the inverter units and buffer units to the inverter and buffer unit list inv_buf_list; S103. Find other combinational logic units driven by the inverter units and buffer units. For each inverter unit and buffer unit in the inv_buf_list, sequentially search for all combinational logic units directly driven by its output signal and all combinational logic units driven across inverters or buffers, and add these combinational logic units to the combinational list com_list; S104. Count the number of combinational logic units fanned out by each register in the combination list com_list in step S103, and generate a fan-out information table.

[0008] Preferably, the specific steps of S2 include: S201. Set a threshold for the fan-out quantity, filter out the registers with a fan-out quantity greater than this threshold to form an initial candidate register list init0_reg_list; S202. Filter out the registers on the long path with a logic level exceeding the preset threshold from the candidate register list init0_reg_list to form a new candidate register list init1_reg_list; S203. Analyze the timing information of each register in the new candidate register list init1_reg_list, judge whether each register in init1_reg_list is on the critical path, and select the registers on the critical path to determine the final candidate register list final_reg_list.

[0009] Preferably, the candidate register list final_reg_list includes one or more elements such as the register name, the register fan-out quantity, the timing path length, and whether it is on the critical path.

[0010] Preferably, the specific steps of S3 include: S301. Traverse the candidate register list final_reg_list, obtain the output signal of each register, analyze the logic units driven by each output signal, including combinational logic units, inverter units, and buffer units, add the combinational logic units to the combination list com_list, and add the inverter units and buffer units to the inv_buf_list; S302. Find other combinational logic units driven by the inverter units and buffer units. For each inverter unit and buffer unit in the inv_buf_list, sequentially search for all the combinational logic units directly driven by its output signal and all the combinational logic units driven across inverters or buffers, and add these combinational logic units to the combination list com_list; S303. Count the number of combinational logic units fanned out by each register in the combination list com_list in step S302, and generate a fan-out information table.

[0011] Preferably, the specific steps of S4 include: S401. Specify the size of the clustering cluster according to the logic characteristics and fan-out constraints, denoted as Num; S402. Calculate the number of initial clustering clusters: For each register in the candidate register list final_reg_list, calculate the multiple relationship between the number of elements Num_ele in the corresponding combination list com_list and the clustering cluster size Num, and use the rounded-down value rounddown(Num_ele / Num) as the number of initial clustering clusters init_cl_num; where rounddown represents rounding down. S403. Initialize the central coordinates of each clustering cluster: Randomly select Num + 1 units from the combination list com_list, calculate the mean of their physical positions, and use it as the initial value of the central coordinates of the current clustering cluster; repeat this process init_cl_num times to obtain the initial values of the central coordinates of all clustering clusters. S404. Initialize the clustering clusters: Traverse each logical unit in the combination list com_list, calculate the distance between its physical position and the initial values of the central coordinates of each clustering cluster in turn, and classify this logical unit into the clustering cluster with the closest distance. S405. Optimize the clustering clusters: Recalculate the mean of the physical positions of the logical units in each clustering cluster, and use this mean to update the central coordinates of the clustering cluster; repeat this process several times until the benefit brought by the update is lower than a certain set threshold, and then stop the loop. S406. Record the clustering cluster information: Record the final number of clustering clusters f_cl_num corresponding to each register, and the list of elements in each clustering.

[0012] Preferably, the specific steps of S5 include: S501. For each register in the candidate register list final_reg_list and its corresponding clustering cluster, first disconnect the original connections of the input pins pin of the units within the clustering cluster. S502. For each clustering cluster, judge its phase relationship with the phase of the register output: If the clustering cluster is in phase with the register output, insert a buffer between the register output and the clustering cluster, and connect the output of the buffer to the input pins pin of the units within the clustering cluster; if the clustering cluster is out of phase with the register output, insert an inverter, and connect the output of the inverter to the input pins pin of the units within the clustering cluster. S503. Connect the input of the inserted buffer or inverter to the register output, and delete other inverter or buffer loads on the register output. S504. Save the modified netlist.

[0013] The present invention also discloses a digital circuit optimization system based on logic clustering, including a memory and a processor connected to each other. A computer program is stored on the memory, and when the computer program is run by the processor, it executes the steps of the method described above.

[0014] Compared with the prior art, the advantages of the present invention are as follows: The logic clustering-based digital circuit optimization method of the present invention realizes the efficient optimization of timing paths through steps such as statistical register fan-out information, clustering combinational logic, modifying the netlist, equivalence checking, and re-layout and routing. Specifically, the present invention first comprehensively statistics the register fan-out information in the circuit netlist, accurately identifies the number of logic units driven by each register and their distribution; based on these data, a candidate register list is further generated to screen out those registers that have a greater impact on the timing path. This process can not only accurately locate the critical timing paths but also provide clear targets for subsequent optimization operations.

[0015] During the optimization process, the present invention avoids the common resource waste and signal delay problems in traditional methods by reasonably arranging the insertion positions of inverters or buffers. For example, in some traditional optimization methods, the insertion of buffers or inverters is often lack of pertinence, which may lead to unnecessary resource occupation or introduce additional delays. However, the present invention can accurately insert inverters or buffers according to the actual needs by analyzing the register fan-out information and the timing path length, so as to effectively improve the driving ability and transmission quality of the signal without increasing additional delays, and significantly improve the timing optimization effect.

[0016] In summary, the logic clustering-based digital circuit optimization method of the present invention can accurately identify critical timing paths by statistical register fan-out information and generating a candidate register list, and reasonably arrange the insertion positions of inverters or buffers to avoid resource waste and signal delay problems, thereby improving the timing optimization effect. The present invention can reasonably cluster relevant logic units through logic clustering, netlist modification, and re-layout and routing, and drive them nearby in the physical layout, which can effectively reduce the length of the timing path and optimize the timing performance of the circuit. Compared with traditional timing optimization methods, the present invention has higher efficiency and better optimization effect, and is especially suitable for large-scale integrated circuit design.

[0017] The present invention optimizes the two major defects of existing commercial EDA tools in processing large fan-out registers, namely, the unreasonable insertion position of inverters / buffers and the neglect of physical layout. The present invention can accurately locate the optimization target. By performing fan-out statistics and critical path screening, it preferentially optimizes large fan-out registers (final_reg_list) that have a significant impact on timing, avoiding resource waste. This method combines physical layout and logical clustering, clusters based on the physical positions of logic units, shortens the interconnect distance, reduces signal propagation delay and the risk of routing congestion; at the same time, when inserting buffers / inverters, redundant loads are deleted, the driving capabilities are balanced, and signal integrity is improved.

[0018] The present invention ensures the consistency of the optimized circuit function through equivalence checking, avoids introducing logic errors, and has high reliability. The digital circuit optimization method and system based on logical clustering support integration with mainstream EDA tools and are applicable to large-scale circuit design. Under a certain sub-20-nanometer process, when this method is implemented on a certain core module, the maximum setup timing violation is reduced by 11 ps, and the number of timing violations is reduced by 11.1%, greatly improving the design performance. The advantage of this method also lies in its scalability to other optimization scenarios. Description of the Drawings

[0019] Figure 1 It is a flowchart of the digital circuit optimization method based on logical clustering provided by an embodiment of the present invention.

[0020] Figure 2 It is a flowchart of obtaining the first-level combinational logic information of the register fan-out provided by an embodiment of the present invention.

[0021] Figure 3 It is a flowchart of the first-level combinational logic clustering provided by an embodiment of the present invention.

[0022] Figure 4 It is a flowchart of modifying the netlist after clustering provided by an embodiment of the present invention. Detailed Embodiments

[0023] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0024] As Figure 1 shown, the digital circuit optimization method based on logical clustering provided by an embodiment of the present invention includes the steps: S1. Statistically analyze the fan-out information of registers: Statistically analyze the fan-out information of all registers in the circuit netlist, that is, the number of all subsequent logic units directly driven by the register output signal or indirectly driven across inverters and buffers, and generate a fan-out information table; S2. Generate a candidate register list: Based on the fan - out information of all registers counted in S1, filter out the registers that have a greater impact on the timing path (registers with a fan - out quantity greater than the first preset threshold, a logic level greater than the second preset threshold, and located on the critical path), and generate a candidate register list final_reg_list. The candidate register list final_reg_list includes elements such as register name, register fan - out quantity, timing path length, and whether it is on the critical path. S3. Obtain the primary combinational logic information of register fan - out: For each register in the candidate register list final_reg_list, obtain its primary combinational logic information. The primary combinational logic refers to the combinational logic units directly driven by the register output signal and indirectly driven across inverters / buffers. S4. Clustering of primary combinational logic: Based on the primary combinational logic information obtained in S3, perform a clustering operation on the logic units. The clustering algorithm divides the physically adjacent logic units into the same clustering cluster according to the physical location relationship of the logic units. The clustered logic units can be regarded as a whole, which is convenient for subsequent optimization operations. S5. Modify the netlist after clustering: After completing the logic clustering, modify the netlist of the circuit. Associate the clustered logic units together and adjust their connection relationships. By modifying the netlist, the physical distance of the timing path can be reduced, thereby optimizing the timing performance of the circuit. S6. Equivalence check: After the netlist modification is completed, perform an equivalence check to ensure that the function of the modified circuit is the same as that of the original circuit. The equivalence check is implemented through formal verification or simulation tools to ensure that the optimization operation does not introduce functional errors. If inconsistencies are found, return to step S5 to correct the connection relationships. S7. Re - layout and routing: Finally, according to the modified netlist, perform re - layout and routing of the circuit. Re - layout and routing include steps such as layout, clock tree synthesis, global routing, and detailed routing. During the layout process, it is necessary to ensure that the buffers / inverters inserted in step S5 are not optimized, and the other processes are the same as before.

[0025] In this embodiment, the specific steps of step S1 include: S101. Traverse all registers in the circuit and record the output signals of each register. S102. Analyze the logic units driven by each output signal, including combinational logic units, inverter units, and buffer units. Add the combinational logic units to the combinational list com_list, and add the inverter units and buffer units to the inverter and buffer unit list inv_buf_list. S103. Find other combinational logic units driven by the inverter units and buffer units. For each inverter unit and buffer unit in the inv_buf_list, sequentially search for all the combinational logic units directly driven by its output signal and all the combinational logic units driven across inverter units or buffer units, and add these combinational logic units to the combination list com_list; S104. Count the number of combinational logic units fanned out by each register in the combination list com_list, and generate a fan-out information table.

[0026] In this embodiment, the specific steps of step S2 include: S201. Set a threshold for the fan-out number, and filter out the registers with a fan-out number greater than this threshold to form an initial candidate register list init0_reg_list; S202. Analyze the timing path length, and filter out the registers on the long path with a logic level exceeding the preset threshold from the candidate register list init0_reg_list to form a new candidate register list init1_reg_list; S203. Analyze the timing information of each register in the new candidate register list init1_reg_list, and determine whether each register in the init1_reg_list is in the critical path (if the slack value of the timing path is negative, it is determined that the register is in the critical path), and select the registers on the critical path to determine the final candidate register list final_reg_list.

[0027] As Figure 2 shown, the specific steps of step S3 include: S301. Traverse the candidate register list final_reg_list, obtain the output signal of each register, analyze the logic units driven by each output signal, including combinational logic units, inverter units, and buffer units, add the combinational logic units to the combination list com_list, and add the inverter units and buffer units to the inv_buf_list; S302. Find other combinational logic units driven by the inverter units and buffer units. For each inverter unit and buffer unit in the inv_buf_list, sequentially search for all the combinational logic units directly driven by its output signal and all the combinational logic units driven across inverters or buffers, and add these combinational logic units to the combination list com_list; S303. Count the number of combinational logic units fanned out by each register in the combined list com_list of step S302, and generate a fan-out information table. For the combined list com_list corresponding to each register, record the type of each primary combinational logic unit, the connected pin, and the physical location information loc.

[0028] As Figure 3 shown, the specific steps of step S4 are as follows: S401. According to the logic characteristics and fan-out constraints, specify the size of the clustering cluster, denoted as Num. In this embodiment, to comprehensively consider constraints such as timing and electromigration, the clustering cluster size is set to 24.

[0029] S402. Calculate the number of initial clustering clusters: For each register in the candidate register list final_reg_list, calculate the multiple relationship between the number of elements Num_ele in the corresponding com_list and the clustering cluster size Num, and use the rounded-down value rounddown(Num_ele / Num) as the initial number of clustering clusters init_cl_num, where rounddown means rounding down; S403. Initialize the center coordinates of each clustering cluster: Randomly select Num + 1 units from com_list, calculate the mean of their physical positions, and use it as the initial value of the center coordinates of the current clustering cluster; Repeat the above process init_cl_num times to obtain the initial values of all clustering cluster center coordinates; S404. Initialize the clustering clusters: Traverse each unit in com_list, calculate the distance between its physical position and the initial values of the center coordinates of each clustering cluster in turn, and classify the unit into the clustering cluster with the closest distance; S405. Optimize the clustering clusters: Recalculate the mean of the physical positions of the logic units in each clustering cluster, and use this mean to update the center coordinates of the clustering cluster; Repeat this process several times until the benefit brought by the update is lower than a certain set threshold and stop the loop; S406. Record the clustering cluster information: Record the final number of clustering clusters f_cl_num corresponding to each register, and the list of elements in each clustering.

[0030] As Figure 4 shown, the specific steps of step S5 are as follows: S501. For each register in the candidate register list final_reg_list and its corresponding clustering cluster, first disconnect the original connections of the input pins pin of the units within the clustering cluster; S502. For each clustering cluster, determine the phase relationship between its phase and the phase of the register output: If the clustering cluster is in phase with the register output, insert a buffer between the register output and the clustering cluster, and connect the output of the buffer to the input pins pin of each unit within the clustering cluster; if the clustering cluster is out of phase with the register output, insert an inverter and connect the output of the inverter to the input pins pin of each unit within the clustering cluster. S503. Connect the input of the inserted buffer or inverter to the register output, and remove other inverter or buffer loads on the register output. S504. Save the modified netlist.

[0031] The digital circuit optimization method based on logic clustering of the present invention realizes the efficient optimization of the timing path through steps such as statistically analyzing the register fan-out information, clustering combinational logic, modifying the netlist, equivalence checking, and re-layout and routing. Specifically, the present invention first comprehensively statistically analyzes the register fan-out information in the circuit netlist to accurately identify the number of logic units driven by each register and their distribution; based on this data, a candidate register list is further generated to screen out those registers that have a greater impact on the timing path. This process can not only accurately locate the critical timing path but also provide a clear target for subsequent optimization operations.

[0032] During the optimization process, the present invention avoids the common problems of resource waste and signal delay in traditional methods by reasonably arranging the insertion positions of inverters or buffers. For example, in some traditional optimization methods, the insertion of buffers or inverters often lacks pertinence, which may lead to unnecessary resource occupation or introduce additional delays. However, the present invention can accurately insert inverters or buffers according to actual needs by analyzing the register fan-out information and the timing path length, thereby effectively improving the signal driving ability and transmission quality without increasing additional delays and significantly improving the timing optimization effect.

[0033] In summary, the digital circuit optimization method based on logic clustering of the present invention can accurately identify the critical timing path by statistically analyzing the register fan-out information and generating a candidate register list, and reasonably arrange the insertion positions of inverters or buffers to avoid resource waste and signal delay problems, thereby improving the timing optimization effect. Through logic clustering, netlist modification, and re-layout and routing, the present invention reasonably clusters related logic units and drives them nearby in the physical layout, which can effectively reduce the length of the timing path and optimize the timing performance of the circuit. Compared with traditional timing optimization methods, the present invention has higher efficiency and better optimization effect, and is particularly suitable for large-scale integrated circuit design.

[0034] The present invention optimizes the two major defects of existing commercial EDA tools in processing large fan-out registers, namely, the unreasonable insertion position of inverters / buffers and the neglect of physical layout. The present invention can accurately locate the optimization target. Through fan-out statistics and critical path screening, it preferentially optimizes large fan-out registers (final_reg_list) that have a significant impact on timing, avoiding resource waste. This method combines physical layout and logical clustering, clusters based on the physical positions of logic units, shortens the interconnection distance, reduces the signal propagation delay and the risk of routing congestion; at the same time, when inserting buffers / inverters, redundant loads are deleted, the driving capabilities are balanced, and the signal integrity is improved.

[0035] The present invention ensures that the optimized circuit has the same function through equivalence checking, avoids introducing logic errors, and has high reliability. The digital circuit optimization method and system based on logical clustering support integration with mainstream EDA tools and are applicable to large-scale circuit design. Under a certain sub-20-nanometer process, when this method is implemented on a certain core module, the maximum setup timing violation is reduced by 11 ps, and the number of timing violations is reduced by 11.1%, greatly improving the design performance. The advantage of this method also lies in its scalability to other optimization scenarios.

[0036] An embodiment of the present invention further provides a digital circuit optimization system based on logical clustering, which includes a memory and a processor connected to each other. A computer program is stored on the memory, and when the computer program is run by the processor, it executes the steps of the method described above. The optimization system of the present invention corresponds to the above optimization method and has the same advantages as those of the above optimization method. Implementing all or part of the processes in the above embodiment method of the present invention can also be completed by hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above method embodiment can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable storage medium includes: any entity or device capable of carrying computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium, etc. The memory is used to store computer programs and / or modules. The processor realizes various functions by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory. The memory may include high-speed random access memory and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one magnetic disk storage device, flash device, or other volatile solid-state storage devices, etc.

[0037] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art of this technology, several improvements and refinements made without departing from the principle of the present invention should be regarded as within the protection scope of the present invention.

Claims

1. A digital circuit optimization method based on logical clustering, characterized in that, Including the steps: S1. Stat register fan-out information: Stat the fan-out information of all registers in the circuit netlist, that is, the number of all subsequent logic units directly driven by the register output signal or indirectly driven across inverters and buffers, and generate a fan-out information table; S2. Generate a candidate register list: According to the fan-out information of all registers, filter out the registers with a fan-out number greater than the first preset threshold, a logic level greater than the second preset threshold and located on the critical path, and generate a candidate register list final_reg_list; S3. Obtain the primary combinational logic information of register fan-out: For each register in the candidate register list final_reg_list, obtain its primary combinational logic information; The primary combinational logic refers to the combinational logic units directly driven by the register output signal and indirectly driven across inverters / buffers; S4. Primary combinational logic clustering: Based on the primary combinational logic information obtained in S3, perform a clustering operation on the logic units. According to the physical position relationship of the logic units, divide the physically adjacent logic units into the same clustering cluster; S5. Modify the netlist after clustering: After completing the logic clustering, modify the netlist of the circuit, that is, associate the clustered logic units together and adjust their connection relationships; S6. Equivalence check: After the netlist modification is completed, perform an equivalence check to ensure that the function of the modified circuit is the same as that of the original circuit; If the equivalence check passes, proceed to the next step, otherwise return to step S5 to correct the connection relationship; S7. Re-layout and routing: Re-layout and route the circuit according to the modified netlist.

2. The digital circuit optimization method based on logical clustering according to claim 1, wherein The specific steps of S1 include: S101. Traverse all registers in the circuit netlist and record the output signals of each register; S102. Analyze the logic units driven by each output signal, including combinational logic units, inverter units and buffer units, add the combinational logic units to the combinational list com_list, and add the inverter units and buffer units to the inverter and buffer unit list inv_buf_list; S103. Find other combinational logic units driven by the inverter units and buffer units. For each inverter unit and buffer unit in the inv_buf_list, sequentially search for all combinational logic units directly driven by its output signal and all combinational logic units driven across inverters or buffers, and add these combinational logic units to the combinational list com_list; S104. Stat the number of combinational logic units fanned out by each register in the combinational list com_list in step S103 and generate a fan-out information table.

3. The digital circuit optimization method based on logical clustering according to claim 1, wherein The specific steps of S2 include: S201. Set the threshold of the fan-out number, filter out the registers with a fan-out number greater than this threshold, and form an initial candidate register list init0_reg_list; S202. Screen out the registers on the long path with the logic level exceeding the preset threshold from the candidate register list init0_reg_list to form a new candidate register list init1_reg_list; S203. Analyze the timing information of each register in the new candidate register list init1_reg_list, determine whether each register in init1_reg_list is in the critical path, and select the registers on the critical path to determine the final candidate register list final_reg_list.

4. The digital circuit optimization method based on logical clustering according to claim 3, wherein The candidate register list final_reg_list includes one or more elements such as the register name, the number of register fan-outs, the timing path length, and whether it is in the critical path.

5. The digital circuit optimization method based on logical clustering according to any one of claims 1-4, characterized in that The specific steps of S3 include: S301. Traverse the candidate register list final_reg_list, obtain the output signal of each register, analyze the logic units driven by each output signal, including combinational logic units, inverter units, and buffer units, add the combinational logic units to the combinational list com_list, and add the inverter units and buffer units to the inv_buf_list; S302. Find other combinational logic units driven by the inverter units and buffer units. For each inverter unit and buffer unit in the inv_buf_list, sequentially search for all combinational logic units directly driven by its output signal and all combinational logic units driven across inverters or buffers, and add these combinational logic units to the combinational list com_list; S303. Count the number of combinational logic units fanned out by each register in the combinational list com_list in step S302 and generate a fan-out information table.

6. The digital circuit optimization method based on logical clustering according to claim 5, wherein The specific steps of S4 include: S401. Specify the size of the clustering cluster according to the logic characteristics and fan-out constraints, denoted as Num; S402. Calculate the number of initial clustering clusters: For each register in the candidate register list final_reg_list, calculate the multiple relationship between the number of elements Num_ele in the corresponding combinational list com_list and the clustering cluster size Num, and use the rounded-down value rounddown(Num_ele / Num) as the number of initial clustering clusters init_cl_num; where rounddown represents rounding down; S403. Initialize the center coordinates of each clustering cluster: Randomly select Num + 1 units from the combinational list com_list, calculate the mean of their physical positions as the initial value of the center coordinates of the current clustering cluster; repeat this process init_cl_num times to obtain the initial values of the center coordinates of all clustering clusters; S404. Initialize the clustering clusters: Traverse each logic unit in the combinational list com_list, sequentially calculate the distance between its physical position and the initial values of the center coordinates of each clustering cluster, and classify the logic unit into the clustering cluster with the closest distance; S405. Optimize the clustering clusters: Recalculate the mean of the physical positions of the logical units in each clustering cluster, and use this mean to update the center coordinates of the clustering cluster; repeat this process several times until the benefit brought by the update is lower than a set threshold, and then stop the loop. S406. Record the clustering cluster information: Record the final clustering number f_cl_num corresponding to each register, and the list of elements in each clustering.

7. The digital circuit optimization method based on logical clustering according to any one of claims 1-4, characterized in that The specific steps of S5 include: S501. For each register and its corresponding clustering cluster in the candidate register list final_reg_list, first disconnect the original connections of the input pins pin of the units within the clustering cluster. S502. For each clustering cluster, judge the phase relationship between its phase and the phase of the register output: If the clustering cluster is in phase with the register output, insert a buffer between the register output and the clustering cluster, and connect the output of the buffer to the input pins pin of the units within the clustering cluster; if the clustering cluster is out of phase with the register output, insert an inverter, and connect the output of the inverter to the input pins pin of the units within the clustering cluster. S503. Connect the input of the inserted buffer or inverter to the register output, and delete other inverter or buffer loads on the register output. S504. Save the modified netlist.

8. A digital circuit optimization system based on logical clustering, comprising a memory and a processor connected to each other, wherein a computer program is stored on the memory, characterized in that, The computer program, when run by a processor, executes the steps of the method according to any one of claims 1-7.

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