Semiconductor design method and device

Abstract

The invention provides a semiconductor design method and device. The semiconductor design method comprises the following steps: inputting design data of a first type into a first neural network model; inputting the second type of design data into a second neural network model of a different type from the first neural network model; generating a fused feature by fusing a calculation result of the second neural network model with a feature generated by calculation up to the first layer of the first neural network model and obtained from the first layer of the first neural network model; inputting the fusion feature into a second layer of the first neural network after the first layer of the first neural network model; and after the calculation of the first neural network model based on the fused features is completed, executing tasks related to the wiring ability of the circuit.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2024-0015240, filed with the Korean Intellectual Property Office on January 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor design method and apparatus. Background Art

[0003] Semiconductor design mainly includes logic design and physical design. In the logic design process, specifications including the functions and performance of a semiconductor chip can be defined, the functions of the chip can be implemented using logic gates and circuits, and simulations can be performed to check the operations. In the logic design process, register transfer level (RTL) code can be generated as a result, and the result can be written in a hardware description language (such as Verilog or VHSIC Hardware Description Language (VHDL)).

[0004] In the physical design process, the physical form of the chip to be actually manufactured can be designed based on the logic design. In the physical design process, in order to generate the geometry of the chip and generate design data that can be used in the actual manufacturing process, detailed processes (such as floorplanning (or pre-layout), power planning, placement, routing, and verification) can be performed. Floorplanning can plan the overall layout of the chip, determine the positions of functional blocks, and optimize the connections between the blocks. Power planning can establish a plan for supplying and distributing power to the chip and can design the power grid. Regarding placement, a process of placing circuit components (such as unit components on a netlist, cells, etc.) defined in the logic design into physical positions can be performed, and in the routing process, circuit paths connecting the placed circuit components can be generated. These detailed processes can be carefully performed to meet the design rules or performance goals regarding the manufacturing settings of the chip. Summary of the Invention

[0005] This summary of the invention introduces a selection of concepts in a simplified form, which will be further described in the detailed description below. This summary of the invention does not necessarily identify the key features or essential features of the claimed subject matter; the following claims set forth the scope of the claimed subject matter.

[0006] In one general aspect, a semiconductor design method is executed by one or more processors and the method includes: inputting a first type of design data into a first neural network model; inputting a second type of design data into a second neural network model, wherein the first neural network has an architecture configured for the first type of design data and the second neural network has an architecture configured for the second type of design data; generating a fused feature by fusing the calculation result of the second neural network model with the feature generated by the calculation up to the first layer of the first neural network, the feature being obtained from the first layer of the first neural network; inputting the fused feature into the second layer of the first neural network model, wherein the second layer of the first neural network is after the first layer in the first neural network model; and performing a task related to the routability of a circuit based on the output inferred by the first neural network model from the fused feature.

[0007] The first neural network model may include a graph-based neural network model, the first type of design data may include graph-based circuit design data, the second neural network model may include an image-based neural network model, and the second type of design data may include image-based circuit design data.

[0008] The method may further include converting an image-based feature generated by the calculation up to the third layer of the second neural network model and obtained from the third layer of the second neural network model into a graph-based feature, wherein the generation of the fused feature is completed by fusing the converted graph-based feature with the feature obtained from the first layer of the first neural network model.

[0009] The step of converting into a graph-based feature may include: obtaining grid cell information corresponding to the image-based feature; and combining the grid cell information and the image-based feature.

[0010] The step of converting into a graph-based feature may include: performing upsampling on the image-based feature; and converting the upsampled image-based feature into a graph-based feature.

[0011] The first neural network model may include an image-based neural network model, the first type of design data may include image-based circuit design data, the second neural network model may include a graph-based neural network model, and the second type of design data may include graph-based circuit design data.

[0012] The method may further include converting the graph-based feature for which the calculation up to the third layer of the second neural network model is completed into an image-based feature, and the fused feature may be generated by fusing the converted image-based feature with the feature obtained from the first layer of the first neural network.

[0013] The steps of converting to image-based features may include: arranging the graph-based features in the form of an image; and combining the arranged image and the features obtained from the first layer of the first neural network.

[0014] The steps of converting to image-based features may further include: performing downsampling on the arranged image in consideration of the resolution of the features obtained from the first layer of the first neural network.

[0015] Tasks related to the routability of a circuit may include a congestion prediction task or a design rule violation prediction task.

[0016] In another overall aspect, a semiconductor design method may include: obtaining a first graph-based feature generated by computations up to the first layer of a graph neural network (GNN), the first feature being obtained from the first layer of the GNN; obtaining a second image-based feature generated by computations up to the second layer of a convolutional neural network (CNN), the second image-based feature being obtained from the second layer of the CNN; generating a third feature by fusing the first feature and the second feature; inputting the third feature into a layer of the GNN after the first layer of the GNN in a first operation mode to perform a prediction related to the routability of a circuit; and inputting the third feature into a layer of the CNN after the second layer of the CNN in a second operation mode to perform a prediction related to the routability of a circuit.

[0017] The step of generating the third feature may include: performing upsampling on the second feature; obtaining grid cell information corresponding to the upsampled second feature; and combining the grid cell information and the upsampled second feature to generate the third feature.

[0018] Generating the third feature may include: arranging the first feature in the form of an image; performing downsampling on the arranged image; and combining the downsampled arranged image and the second feature to generate the third feature.

[0019] In yet another general aspect, a semiconductor design device includes: one or more processors; and one or more memory devices storing instructions configured to cause the one or more processors to perform processing, the processing including: inputting a first type of design data into a first neural network model, inputting a second type of design data into a second neural network model having an architecture different from that of the first neural network model, generating a fused feature by fusing the calculation result of the second neural network model with the features generated by computations up to the first layer of the first neural network, the features being obtained from the first layer of the first neural network, inputting the fused feature into the second layer of the first neural network after the first layer of the first neural network model, and after completing the calculation of the first neural network model based on the fused feature, performing a task related to the routability of a circuit.

[0020] The processing may further include: converting the image-based features generated through the calculations up to the third layer of the second neural network model into graph-based features, the image-based features being obtained from the third layer, and generating the fused features by fusing the converted graph-based features with the features obtained from the first layer of the first neural network.

[0021] The step of converting into graph-based features may include: obtaining grid cell information corresponding to the image-based features, and combining the grid cell information and the image-based features.

[0022] The step of converting into graph-based features may include: performing upsampling on the image-based features; and converting the upsampled image-based features into graph-based features.

[0023] The processing may further include: converting the graph-based features generated through the calculations up to the third layer of the second neural network model into image-based features, the graph-based features being obtained from the third layer, and generating the fused features by fusing the converted image-based features with the features obtained from the first layer of the first neural network.

[0024] The step of converting into image-based features may include: arranging the graph-based features in the form of an image; and combining the arranged image and the features obtained from the first layer of the first neural network model.

[0025] The step of converting into image-based features may further include: performing downsampling on the arranged image in consideration of the resolution of the features obtained from the first layer of the first neural network.

[0026] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Illustrates a semiconductor design device according to one or more embodiments.

[0028] Figures 2 to 5 Illustrates the operation of a semiconductor design device according to one or more embodiments.

[0029] Figure 6 Illustrates a semiconductor design method according to one or more embodiments.

[0030] Figure 7 Illustrates a semiconductor design method according to one or more embodiments.

[0031] Figure 8 Illustrates a computing device according to one or more embodiments.

[0032] Throughout the drawings and the detailed description, unless otherwise described or provided, the same or similar reference numerals will be understood to represent the same or similar elements, features, and structures. The drawings may not be to scale, and for clarity, illustration, and convenience, the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated. Detailed Description

[0033] The following detailed description is provided to assist the reader in obtaining a thorough understanding of the methods, apparatuses, and / or systems described herein. However, after understanding the disclosure of this application, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will be apparent. For example, except for operations that must occur in a specific order, the order of the operations described herein is merely exemplary and is not limited to the order of the operations set forth herein, but may be changed as will be apparent after understanding the disclosure of this application. Additionally, descriptions of features known after understanding the disclosure of this application may be omitted for greater clarity and conciseness.

[0034] The features described herein may be embodied in different forms and should not be construed as limited to the examples described herein. Instead, only the examples described herein are provided to illustrate some of the many possible ways of implementing the methods, apparatuses, and / or systems described herein that will be apparent after understanding the disclosure of this application.

[0035] The terms used herein are for describing various examples only and will not be used to limit the disclosure. Unless the context clearly indicates otherwise, the articles "a" and "the" are intended to include the plural forms as well. As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more of them. As a non-limiting example, the terms "comprises," "comprising," and "having" specify the presence of the stated features, numbers, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0036] Throughout the specification, when a component or element is described as "connected to," "coupled to," or "joined to" another component or element, it may be directly "connected to," "coupled to," or "joined to" the other component or element, or one or more other components or elements may reasonably be interposed therebetween. When a component or element is described as "directly connected to," "directly coupled to," or "directly joined to" another component or element, no other elements may be interposed therebetween. Similarly, expressions such as "between" and "immediately between" and "adjacent to" and "immediately adjacent to" may also be interpreted as described above.

[0037] Although terms such as "first", "second", and "third" or A, B, (a), (b), etc. may be used herein to describe various components, elements, regions, layers, or parts, these components, elements, regions, layers, or parts should not be limited by these terms. Each of these terms is not used to define, for example, the nature, order, or sequence of the corresponding component, element, region, layer, or part, but is only used to distinguish the corresponding component, element, region, layer, or part from other components, elements, regions, layers, or parts. Thus, without departing from the teachings of the examples, the first component, first element, first region, first layer, or first part mentioned in the examples described herein may also be referred to as the second component, second element, second region, second layer, or second part.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and based on the understanding of the disclosure of this application. Unless explicitly defined as such herein, terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the disclosure of this application, and should not be interpreted in an idealized or overly formal sense. The use of the term "may" herein with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such a feature, while not all examples are so limited.

[0039] Figure 1 A semiconductor design device according to one or more embodiments is shown. As described later, the semiconductor design device may be implemented as one or more processors or computers.

[0040] Referring Figure 1 , the semiconductor design device may execute a program (in the form of instructions) loaded in one or more memory devices and executed by one or more processors. For example, the semiconductor design device may be implemented as the computing device 50 described Figure 8 . In this case, one or more processors may correspond to the processor 510 of the computing device 50, and one or more memory devices may correspond to the memory 520 of the computing device 50. The program may be executed by one or more processors to perform a function for predicting routability based on a deep learning model. In this specification, these functions executed by the program are represented by the term "…… part" to distinguish them logically.

[0041] The semiconductor design device according to an embodiment may include a fusion feature generation part 10, a graph-based deep learning model 22, and an image-based deep learning model 32.

[0042] The physical design process of a semiconductor chip typically includes detailed processes such as floorplanning, power planning, placement, routing, and verification. In the case of placement and routing, more detailed steps for refinement can be performed. For example, after performing floorplanning, detailed steps of global placement, detailed placement, trial routing, global routing, and detailed routing verification can be performed ( "routing" and "wiring" can be used interchangeably). In the global placement step, the overall layout of the chip can be planned, and the approximate positions of functional blocks and standard cells can be determined. In the detailed placement step, circuit elements can be placed in their correct (final) positions on the chip, and such correct / final positions are determined based on their approximate positions initially determined in the global placement. In summary, global placement determines the rough positions, and detailed placement determines the exact / final positions. After completing the placement of components, initial / trial routing is attempted. Initial / trial routing can involve test routing that is performed to verify the effectiveness of the placement and the effectiveness of the routing strategy, and when potential problem areas are identified before actual routing, the routing strategy can be adjusted based on the test routing. Subsequently, in the non-trial global routing / wiring step, the electrical connection paths between the various constituent elements of the chip are determined based essentially on, for example, the connection information in the netlist. In the detailed routing verification step, after completing the detailed routing, it can be verified whether the design rules are followed and the performance goals are achieved.

[0043] It is important to note that in the detailed routing verification step, when a design rule is violated or a performance goal is not met, the design process can return to a previous stage and optimization can be repeatedly performed, or, when the design process instead returns to a previous step and the level to be addressed is exceeded, the process can return to the floorplanning step and the overall layout of the chip may need to be changed. In such cases, significant delays and overheads can occur in semiconductor design. To minimize the delays and overheads, a semiconductor design apparatus according to an embodiment can predict routability (whether a final routing that meets the goals / rules can be derived) based on a deep learning model. The prediction of routability can not only (i) optimize the use of the limited space on the chip and provide a layout and routing that complies with the design rules, but also (ii) analyze routing congestion in the early design steps to identify and adjust areas that may be problematic in later steps of the design process (before performing the later steps). In summary, a deep learning model can be of the type of neural network that extracts high-level features from input data through multiple processing layers and performs tasks such as classification, recognition, and prediction based on the high-level features. The details of the model are as follows.

[0044] Refer to Figure 1, the graph-based deep learning model 22 may have a dedicated neural network structure for processing chip design information (e.g., circuit information) encoded as graph data. The graph data or just the graph can be nodes and edges connecting the nodes. Each node may have various adjacent nodes, so the graph data typically may have an unstructured form. The graph-based deep learning model 22 may (i) learn new features of a node by aggregating the features of the node and the information of its adjacent nodes based on the graph data in which the chip design information is encoded (i.e., graph-based design data 20), and may also (ii) select adjacent nodes that are highly important in this process or apply weights to the connections of the node. In some embodiments, the graph-based deep learning model 22 may be implemented by various neural networks having a GNN architecture, such as graph neural network (GNN), graph convolutional network (GCN), graph attention network (GAT), and graph sampling and aggregation (GraphSAGE), etc. Specifically, in some embodiments, the graph-based deep learning model 22 may be implemented by a heterogeneous graph neural network (hetero GNN). Here, the hetero GNN may be a form of GNN specifically designed to process heterogeneous graphs including different types of nodes and edges. In other words, the hetero GNN may model the complex relationships between different types of nodes and edges.

[0045] The image-based deep learning model 32 may have a dedicated neural network structure (architecture) for processing chip design information (e.g., circuit information) encoded as image data. Here, "image" represents a grid of pixels, where each pixel has fixed adjacent pixels; image data typically may have a standardized form. The image-based deep learning model 32 may be specifically configured to learn a spatial hierarchy and identify and analyze visual patterns based on the image data in which the chip design information is encoded (i.e., image-based design data 30). In some embodiments, the image-based deep learning model 32 may be implemented by a convolutional neural network (CNN) or various neural networks having a CNN architecture.

[0046] If only the graph-based model is used for design, the inductive bias of spatially related data is not reflected in the neural network structure, which may lead to unnecessary wiring overload. On the other hand, when only the image-based model is used for design, the relationships between spatially separated but topologically connected pixels or the information between cells and nets may not be used for learning, and when semiconductor chips have various sizes, the chip design information must be encoded into an image of a specific size, so one pixel may correspond to (represent) multiple cells, resulting in information loss.

[0047] To solve this problem, a semiconductor design device according to an embodiment described herein can encode chip design information into both graph data and image data, and the graph data and the image data can be used to generate graph-based design data 20 and image-based design data 30; routability can be predicted using both a graph-based deep learning model 22 and an image-based deep learning model 32. A fusion feature generation part 10 can operate between the graph-based deep learning model 22 and the image-based deep learning model 32 to generate a fusion feature by fusing the feature calculated from the graph-based deep learning model 22 and the feature calculated from the image-based deep learning model 32, and provide the fused / fusion feature to the graph-based deep learning model 22 or the image-based deep learning model 32.

[0048] More specifically, the graph-based deep learning model 22 can (i) receive the graph-based design data 20 as an input and receive the fusion feature (from the fusion feature generation part 10) to (ii) output an output graph 24. The output graph 24 can be appropriately processed, transformed, and used according to an embodiment or the purpose of analysis (e.g., as a routing congestion prediction graph 26 for centrally analyzing routing congestion among the routabilities of a circuit). In this case, the fusion feature generation part 10 can (i) generate a fusion feature by fusing the image-based calculation result of the image-based deep learning model 32 and the feature generated (and obtained from an intermediate layer) by the calculation through an intermediate layer among the layers up to the graph-based deep learning model 22, and (ii) provide the fusion feature to the graph-based deep learning model 22.

[0049] In addition, the image-based deep learning model 32 can receive the image-based design data 30 and receive the fusion feature from the fusion feature generation part 10 to output an output image 34. The output image 34 can be appropriately processed, transformed, and used according to an embodiment or the purpose of analysis (e.g., as a routing congestion prediction image 36 for centrally analyzing routing congestion among the routabilities of a circuit). In this case, the fusion feature generation part 10 can (i) generate a fusion feature by fusing the graph-based calculation result of the graph-based deep learning model 22 and the feature generated (and obtained from an intermediate layer) by the calculation through an intermediate layer among the layers up to the image-based deep learning model 32 (and obtained from the intermediate layer), and (ii) provide the fusion feature to the image-based deep learning model 32.

[0050] In this way, by converting graph-based features into image-based features and fusing them or converting image-based features into graph-based features and using the fused features as features, the problems that may occur when only using the graph-based or image-based models described above can be solved.

[0051] Next, refer to Figures 2 to 5 the operation of a semiconductor design device according to one or more embodiments.

[0052] Figures 2 to 5 Illustrate the operation of a semiconductor design device according to one or more embodiments.

[0053] Refer to Figure 2 , the first graph-based deep learning model 221 and the second graph-based deep learning model 222 may correspond to Figure 1 the graph-based deep learning model 22 in Figure 1 . The first image-based deep learning model 321 and the second image-based deep learning model 322 may correspond to

[0054] the image-based deep learning model 32 in

[0055] . As described above, the deep learning model 221 and the deep learning model 222, and the deep learning model 321 and the deep learning model 322 may have different types / architectures. That is, the deep learning model 221 and the deep learning model 222 may be included in (or be) the graph-based deep learning model, and the deep learning model 321 and the deep learning model 322 may be included in (or be) the image-based deep learning model.

[0056] Semiconductor circuit design data can be represented as, for example, cells, nets, pins, etc. A cell is a unit representing the basic functions of a circuit, and can be, for example, a single constituent element (such as a logic gate (AND, OR, NOT, etc.), a flip-flop or a latch), or a collection of more complex functions configured by a combination of these constituent elements. A net defines the path of a signal within a circuit and can indicate an electrical connection between two or more cells. A pin, which is an interface of a cell, corresponds to a point for receiving a signal from outside the cell or for outputting a signal from the cell; each cell can have one or more input pins and one or more output pins. This topological information can be encoded in a graphical form. The first type of design data can correspond to the graphical form of the data. In addition, the deep learning model 221 can use the graph constructed using the topological information as an input.

[0057] In addition, after the layout step of the design process, the position information where the cells are laid out can be processed in the form of an image. For example, one pixel can be represented as a grid cell (or G-cell), and a collection of grid cells included in a net can be represented as a grid net (or G-net). Based on this geometric grid cell information, the occupancy or density (e.g., the number of components) represented by each cell can be encoded in the form of an image. The second type of design data can correspond to this image. In addition, the deep learning model 321 can use the image of geometric features as an input.

[0058] Specifically, the deep learning model 221 and the deep learning model 222 can be implemented as heterogeneous GNNs, so they can be capable of processing graphs configured with different types of nodes and edges (such as cells, nets, pins, and grid cells). In this case, attributes (such as cell location, node name (instance name / identifier), standard cell and IP (intellectual property identifier) name, cell size, and the number of connected nets (degree)) can be used as graph features regarding cells; attributes (such as net name and the number of connected cells) can be used as graph features regarding nets; and attributes (such as pin name and the indices of connected cells and nets) can be used as graph features regarding pins.

[0059] The deep learning model 321 and the deep learning model 322 can be implemented as CNNs, and an image representing the position of a macro as 0 and 1 as an image feature related to the macro is used as an input to the model, or an image representing the distribution information of nets as an image feature related to rectangular uniform line density (RUDY) can be used as an input to the model.

[0060] The semiconductor design device can generate a fused feature by fusing the image-based calculation result of the deep learning model 321 with the graph-based feature generated (and obtained from the first layer) through the calculation up to the first layer of the deep learning model 221. Subsequently, the semiconductor design device can input the fused feature into the second layer of the deep learning model 222, where the second layer comes after the first layer of the deep learning model 221. After completing the calculations of the deep learning model 221 and the deep learning model 222, the semiconductor design device can perform tasks related to the routability of the circuit by using the output graph 24. In addition, the semiconductor design device can input the second type of design data 30 into the deep learning model 321 and the deep learning model 322. Here, the second type of design data may include image-based circuit design data. In addition, the semiconductor design device can input the first type of design data 20 into the deep learning model 221 and the deep learning model 222. Here, the first type of design data may include graph-based circuit design data.

[0061] The semiconductor design device can generate a fused feature by fusing the calculation result of the deep learning model 221 with the feature generated (and obtained from the first layer) through the calculation up to the first layer of the deep learning model 321, and can perform this operation through the fused feature generation part 10. Subsequently, the semiconductor design device can input the fused feature into the second layer of the deep learning model 322. After completing the calculations of the deep learning model 321 and the deep learning model 322, the semiconductor design device can perform tasks related to the routability of the circuit by using the output image 34.

[0062] That is, whether for learning / training or for inference, the fused feature generation part 10 can convert the image-based feature into a graph form or convert the graph-based feature into an image form so that information can be exchanged between the deep learning model 221 and the deep learning model 222 and the deep learning model 321 and the deep learning model 322. Therefore, the performance of the model can be improved by preferably encoding the information of the semiconductor circuit in various forms without loss.

[0063] Refer to Figure 3, the first type of design data (e.g., graph-based circuit design data 20) and the second type of design data (e.g., image-based circuit design data 30) can be processed by sharing image-based features and grid cell features corresponding to graph-based features via "the first and second layers of deep learning models 221 and 222" and via "the first and second layers of deep learning models 321 and 322". Since the pixel information of the image is encoded into the GNN in the form of grid cells, the image-to-graph conversion module 110 can upsample the image to match the original image size, combine the upsampled image with the grid cell features, and then send the combined image to the next layer (e.g., the second layer of the second deep learning model 222). The graph-to-image conversion module 120 can convert the graph into an image form, downsample the converted graph to match the size of the image-based features, combine the downsampled graph with the existing image-based features, and then send the combined graph to the next image layer (e.g., the second layer of the second deep learning model 322).

[0064] That is, the fusion feature generation part 10 can convert the image-based feature 421 generated (and obtained from the third layer of the deep learning model 321) through the calculation up to the third layer of the deep learning model 321 into a graph-based feature by the image-to-graph conversion module 110. In addition, the fusion feature generation part 10 can generate the fusion feature 41 by fusing the converted graph-based feature with the feature obtained from the first layer of the deep learning model 221. In some embodiments, if necessary, the fusion feature generation part 10 can perform upsampling on the image-based feature 421 by the upsampling module 112. In this case, the image-to-graph conversion module 110 can convert the upsampled image-based feature into a graph-based feature.

[0065] In addition, the fusion feature generation part 110 can convert the graph-based feature 41 generated (and obtained from the third layer of the deep learning model 221) through the calculation up to the third layer of the deep learning model 221 into an image-based feature 422 by the graph-to-image conversion module 120. In addition, the fusion feature generation part 10 can generate the fusion feature 42 by fusing the converted image-based feature 422 with the feature 421 obtained from the first layer of the deep learning model 321. In some embodiments, if necessary, the fusion feature generation part 10 can perform downsampling on the result of the graph-to-image conversion module 120 based on the resolution of the feature 421 obtained from the first layer of the deep learning model 321 by the downsampling module 122.

[0066] In the case of wire congestion prediction, when the result of wire congestion prediction is to be obtained in the form of an image (an image that can indicate where wire congestion may occur), learning can be performed by applying the mean squared error (MSE) loss function to the output image 34. When the result of wire congestion prediction is to be obtained in the form of a graph (a graph indicating wire congestion), the MSE loss function can be applied to the predicted values of the grid cell nodes shown in the output graph 24 (for example, the predicted value of grid cell G0 is 0.19, the predicted value of grid cell G1 is 0.01, and the predicted value of grid cell G8 is 0.78) to perform learning. For wire congestion prediction, when only using GNN, when only using CNN, and when mixing and using GNN and CNN according to the embodiment, as shown in Table 1 below, the RMSE (root MSE) is obtained.

[0067] Table 1

[0068] As confirmed by empirical experiments, when GNN and CNN are mixed and used, the performance is excellent. Tasks related to determining the routability of a circuit that can be performed using a semiconductor design device may include a congestion prediction task or a design rule violation prediction task. By changing (through inter-model exchange) the input and output features, it may be feasible to perform several types of routing-related tasks. For example, when the congestion value (which is the target of the input data used in the congestion prediction task) is used as the input value and the learning target is predicted as a design rule violation (represented as an image), the same model structure can be used to perform the design rule violation prediction task. Table 2 shows examples of tasks related to the routability of a circuit that can be performed using a semiconductor design device according to the embodiment.

[0069] Table 2

[0070] Refer to Figure 4, the image-to-graph conversion module 110 can obtain grid cell information from the feature map FM1 corresponding to the image-based features, in order to convert the image-based features (features 421 obtained from the first layer of the deep learning model 321) into graph-based features. Here, the feature map FM1 can be the features 421 generated (and obtained from the first layer of the deep learning model 321) through the calculations up to the first layer of the deep learning model 321, or can be the features for which upsampling has been performed by the upsampling module 112. The image-to-graph conversion module 110 can convert the image-based features into graph-based features by combining the grid cell information and the image-based features, and thus the fused feature 41 can be generated. Here, the combination of the grid cell information and the image-based features can be achieved by at least one of a concatenation operation, a summation operation, and an attention operation for the grid cell information and the image-based features. The image-to-graph conversion module 110 can send the generated fused feature 41 to the deep learning model 222. That is, the graph-based features H1 and graph-based features H2 corresponding to the grid cell G5 and the grid cell G8 are respectively combined with the image-based features F1 and image-based features F2, and thus, the image-based features F1 and image-based features F2 can finally be generated as the graph-based fused feature 41. For the grid cell G5 and the grid cell G8, the corresponding positions on the image can be known using the grid cell index (e.g., node identifier), and thus it can be specified from the attributes of the grid cell G5 and the grid cell G8 that the image-based features corresponding to the grid cell G5 and the grid cell G8 are the features F1 and the features F2.

[0071] Referring to Figure 5 , as described in more detail below, the graph-to-image conversion module 120 can generate the feature map FM2 by arranging the graph-based features in the form of an image, in order to convert the graph-based features (features 41 obtained from the first layer of the deep learning model 221) into image-based features 422. Thereafter, the arranged features 422 after downsampling by the downsampling module 122 and the features 421 (obtained from the first layer of the deep learning model 321) can be combined to generate the fused feature 42. Here, the combination of the arranged features 422 after downsampling and the features 421 can be achieved by at least one of a concatenation operation, a summation operation, and an attention operation for the arranged features 422 after downsampling and the features 421. The fused feature generation part 10 can send the generated fused feature 42 to the deep learning model 322, and the deep learning model 322 can perform inference based on the fused feature 42 to generate an output from the output layer of the deep learning model 322.

[0072] That is to say, the graph-based features H1 and H2 corresponding to the grid cell G5 and the grid cell G8, respectively, can be rearranged in image form and reshaped into tensors, and downsampling (e.g., max pooling) can be applied to match the resolution of the CNN layer 322. In this way, the feature 422 generated by stacking the graph-based features at the corresponding positions on the image can be combined with the image-based feature 421 to finally generate the image-based fused feature 42.

[0073] Figure 6 Illustrates a semiconductor design method according to one or more embodiments.

[0074] Referring to Figure 6 , the semiconductor design method may include: inputting first-type design data into a first deep learning model (S601), inputting second-type design data into a second deep learning model of a different type from the first deep learning model (S602), generating a fused feature by fusing the calculation result of the second deep learning model with the feature obtained from the first layer of the first deep learning model (S603), inputting the fused feature into a second layer in a later stage of the first layer of the first deep learning model (S604), and performing a task related to the routability of the circuit after completing the calculation of the first deep learning model (S605).

[0075] Figure 7 Illustrates a semiconductor design method according to one or more embodiments.

[0076] Referring to Figure 7 , the semiconductor design method according to an embodiment may include: obtaining a graph-based first feature generated (and obtained from the first layer of the GNN) through the calculation up to the first layer of the GNN (S701), obtaining an image-based second feature generated (and obtained from the second layer of the CNN) through the calculation up to the second layer of the CNN (S702), generating a third feature by fusing the first feature and the second feature (S703), inputting the third feature into a layer of the GNN after the first layer of the GNN in a first operation mode to perform a prediction of "indicating the routability of the circuit" (S704), and inputting the third feature into a layer of the CNN after the second layer of the CNN in a second operation mode to perform a prediction related to the routability of the circuit (S705).

[0077] Here, the first operation mode may be an operation mode in which graph data can be finally obtained in a routable manner, and the second operation mode may be an operation mode in which image data can be finally obtained in a routable manner. For example, when it is desired to obtain a prediction result for routing congestion in the form of a graph, the semiconductor design device can be operated in the first operation mode, and when it is desired to obtain a prediction result for routing congestion in the form of an image, the semiconductor design device can be operated in the second operation mode.

[0078] In the first operation mode, step S703 may include: performing upsampling on the second feature to obtain grid cell information corresponding to the upsampled second feature, and generating a third feature by combining the grid cell information with the upsampled second feature. In addition, in the second operation mode, step S703 may include: arranging the first feature in the form of an image, performing downsampling on the arranged image, and generating a third feature by combining the downsampled arranged image and the second feature.

[0079] In either case, since graph-based features are converted to and fused with image-based features, or image-based features are converted to and fused with graph-based features, it is feasible to minimize the latency and overhead in the design and improve the performance of routability prediction while avoiding the problems that may occur when only using a graph-based model or only using an image-based model as described above.

[0080] Figure 8 A block diagram of a computing device according to one or more embodiments is shown.

[0081] Referring to Figure 8 , the computing device 50 can be used to implement the semiconductor design method and device according to the embodiment. With the above description, those skilled in the art can easily form source code (e.g., similar to the above description), and the source code can be compiled, interpreted, etc. into executable instructions. When executed by the computing device 50, the executable instructions will cause the computing device 50 to perform operations consistent with the operations described above. In addition, although the application to circuit design is described as an example application, it will be understood that the computing device 50 configured as described above will make the computing device 50 itself more efficient when performing various applications and functions.

[0082] The computing device 50 may include at least one of a processor 510 (in fact, one or more processors of any kind), a memory 530, a user interface input device 540, a user interface output device 550, and a storage device 560 that communicate via a bus 520. The computing device 50 may also include a network interface 570 electrically or wirelessly connected to the network 40. The network interface 570 can send or receive signals to and from other entities via the network 40.

[0083] The processor 510 can be implemented in various types, such as a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a natural processing unit (NPU), a microcontroller (MCU), etc., and can be any semiconductor device that executes instructions stored in the memory 530 or the storage device 560. The processor 510 can be configured to implement the functions and methods described above with respect to the embodiments.

[0084] The memory 530 and the storage device 560 can include various types of volatile or non-volatile storage media. For example, the memory can include a read-only memory (ROM) 531 and a random access memory (RAM) 532. In this embodiment, the memory 530 can be disposed inside or outside the processor 510, and the memory 530 can be connected to the processor 510 through various known components.

[0085] In some embodiments, at least part of the components or functions of the semiconductor design method and apparatus according to the embodiments can be implemented as a program or software (in the form of instructions) executed on the computing device 50, and the program or software can be stored in a computer-readable medium. Specifically, the computer-readable medium according to the embodiments can be a computer-readable medium of a computer that writes a program for executing the steps included in the semiconductor design method according to the embodiments to the processor 510 that executes the program or instructions stored in the memory 530 or the storage device 560.

[0086] In some embodiments, at least part of the components or functions of the semiconductor design method and apparatus according to the embodiments can be implemented using the hardware or circuits of the computing device 50 or can be implemented using separate hardware or circuits that can be electrically connected to the computing device 50.

[0087] According to the embodiments described so far, it is possible to minimize the delay and overhead caused by the iterative optimization method in the conventional semiconductor design by predicting routability based on a deep learning model. In addition, it is feasible to improve the performance in routability prediction by encoding the design data of the semiconductor chip into various types to train the deep learning model.

[0088] Herein, with respect to Figures 1 to 8The described computing devices, electronic devices, processors, memories, displays, information output systems and hardware, storage devices, and other devices, apparatuses, units, modules, and components are implemented by or represent hardware components. Examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer can be implemented by one or more processing elements (such as, logic gate arrays, controllers, and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond and execute instructions in a defined manner to achieve a desired result). In one example, a processor or computer includes or is connected to one or more memories that store instructions or software executed by the processor or computer. The hardware components implemented by the processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) to perform the operations described in this application. The hardware components can also access, manipulate, process, create, and store data in response to the execution of the instructions or software. For simplicity, the singular terms "processor" or "computer" may be used in the description of the examples described in this application, but in other examples, multiple processors or computers may be used or a processor or computer may include multiple processing elements or multiple types of processing elements or both. For example, a single hardware component or two or more hardware components can be implemented by a single processor or two or more processors or a processor and a controller. One or more hardware components can be implemented by one or more processors or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors or additional processors and additional controllers. One or more processors or a processor and a controller can implement a single hardware component or two or more hardware components. The hardware components can have any one or more of different processing configurations. Examples of hardware components include single processors, independent processors, parallel processors, single instruction single data (SISD) multiprocessors, single instruction multiple data (SIMD) multiprocessors, multiple instruction single data (MISD) multiprocessors, and multiple instruction multiple data (MIMD) multiprocessors.

[0089] Figures 1 to 8The method of performing the operations described in this application, as illustrated, is performed by computing hardware (e.g., by one or more processors or computers), which is implemented as described above to implement instructions or software for performing the operations performed by the method described in this application. For example, a single operation or two or more operations may be performed by a single processor or two or more processors or a processor and a controller. One or more operations may be performed by one or more processors or a processor and a controller, and one or more other operations may be performed by one or more other processors or additional processors and additional controllers. One or more processors or a processor and a controller may perform a single operation or two or more operations.

[0090] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods as described above may be written as a computer program, code segment, instruction, or any combination thereof to individually or jointly direct or configure one or more processors or computers to operate as a machine or special-purpose computer to perform the operations performed by the hardware components and methods as described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) that is directly executed by one or more processors or computers. In another example, the instructions or software include higher-level code that is executed by one or more processors or computers using an interpreter. The instructions or software may be written in any programming language based on the block diagrams and flowcharts shown in the figures and the corresponding descriptions herein, which disclose algorithms for performing the operations performed by the hardware components and methods as described above.

[0091] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and execute the methods described above, as well as any associated data, data files, and data structures, can be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random-access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage, hard disk drive (HDD), solid state drive (SSD), card-type memory (such as, multimedia card or micro card (e.g., Secure Digital (SD) or Extreme Digital (XD))), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk), and any other device that is configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers such that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed across a networked computer system such that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed by one or more processors or computers in a distributed manner.

[0092] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of this application that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of each feature or aspect in an example is to be considered applicable to similar features or aspects in other examples. Appropriate results can be achieved if the described techniques are performed in a different order and / or if the components in the described system, architecture, device, or circuit are combined in a different manner and / or replaced or supplemented by other components or their equivalents.

[0093] Accordingly, in addition to the above disclosure, the scope of the disclosure can also be defined by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.

Claims

1. A semiconductor design method executed by one or more processors, the semiconductor design method comprising: Inputting design data of a first type into a first neural network model; Inputting design data of a second type into a second neural network model, wherein the first neural network model has an architecture configured for the design data of the first type and the second neural network model has an architecture configured for the design data of the second type; Generating a fused feature by fusing the calculation result of the second neural network model with the features generated by the calculation up to the first layer of the first neural network model, the features being obtained from the first layer of the first neural network model; Inputting the fused feature into the second layer of the first neural network model, wherein the second layer of the first neural network model is after the first layer of the first neural network model; and Performing a task related to the routability of a circuit based on the output inferred by the first neural network model from the fused feature.

2. The semiconductor design method according to claim 1, wherein the first neural network model includes a graph-based neural network model, the design data of the first type includes graph-based circuit design data, the second neural network model includes an image-based neural network model, and the design data of the second type includes image-based circuit design data.

3. The semiconductor design method according to claim 2, further comprising: Converting the image-based features generated by the calculation up to the third layer of the second neural network model and obtained from the third layer of the second neural network model into graph-based features, and wherein the fused feature is generated by fusing the converted graph-based features with the features obtained from the first layer of the first neural network model.

4. The semiconductor design method according to claim 3, wherein, The step of converting the image-based features into graph-based features includes: Obtaining grid cell information corresponding to the image-based features; and Combining the grid cell information and the image-based features to convert the image-based features into graph-based features.

5. The semiconductor design method according to claim 3, wherein, The step of converting the image-based features into graph-based features includes: Performing upsampling on the image-based features; and Converting the upsampled image-based features into graph-based features.

6. The semiconductor design method according to claim 1, wherein the first neural network model includes an image-based neural network model, the design data of the first type includes image-based circuit design data, the second neural network model includes a graph-based neural network model, and the design data of the second type includes graph-based circuit design data.

7. The semiconductor design method according to claim 6, further comprising: Converting the graph-based features generated by the calculation up to the third layer of the second neural network model into image-based features, and wherein the fused feature is generated by fusing the converted image-based features with the features obtained from the first layer of the first neural network model.

8. The semiconductor design method according to claim 7, wherein, The step of converting the graph-based features into image-based features includes: Arranging the graph-based features in the form of an image; and wherein the step of generating the fused feature includes: Generate a fused feature based on the arranged graph-based feature and the feature obtained from the first layer of the first neural network model.

9. The semiconductor design method according to claim 8, wherein, The step of converting the graph-based feature into an image-based feature further includes: performing downsampling on the arranged graph-based feature based on the resolution of the feature obtained from the first layer of the first neural network model.

10. The semiconductor design method according to claim 1, wherein, Tasks related to the routability of the circuit include a congestion prediction task or a design rule violation prediction task.

11. A semiconductor design method, executed by one or more processors and including: Obtain a first graph-based feature generated by computations up to the first layer of a graph neural network, the first feature being obtained from the first layer of the graph neural network; Obtain a second image-based feature generated by computations up to the second layer of a convolutional neural network, the image-based second feature being obtained from the second layer of the convolutional neural network; Generate a third feature by fusing the first feature and the second feature; Input the third feature into a layer of the graph neural network after the first layer of the graph neural network in a first operation mode to perform a prediction related to the routability of the circuit; And Input the third feature into a layer of the convolutional neural network after the second layer of the convolutional neural network in a second operation mode to perform a prediction related to the routability of the circuit.

12. The semiconductor design method according to claim 11, wherein, The step of generating the third feature includes: Performing upsampling on the second feature; Obtaining grid cell information corresponding to the upsampled second feature; and Combining the grid cell information and the upsampled second feature to generate the third feature.

13. The semiconductor design method according to claim 11, wherein, The step of generating the third feature includes: Arranging the first feature in image form; Performing downsampling on the arranged first feature; and Combining the downsampled arranged first feature and the second feature to generate the third feature.

14. A semiconductor design apparatus, including: One or more processors; And One or more memory devices storing instructions configured to cause the one or more processors to perform processing, the processing including: Inputting a first type of design data into a first neural network model and inputting a second type of design data into a second neural network model having an architecture different from that of the first neural network model, Generating a fused feature by fusing the calculation result of the second neural network model with the feature generated by computations up to the first layer of the first neural network, the feature being obtained from the first layer of the first neural network model, Inputting the fused feature into the second layer of the first neural network model after the first layer of the first neural network model, and After completing the calculation of the first neural network model based on the fused feature, performing a task related to the routability of the circuit.

15. The semiconductor design device according to claim 14, wherein, The processing further includes: Converting an image-based feature generated by computations up to the third layer of the second neural network model into a graph-based feature, the image-based feature being obtained from the third layer, and The fused feature is generated by fusing the converted graph-based feature with the feature obtained from the first layer of the first neural network model.

16. The semiconductor design device according to claim 15, wherein, The step of converting the image-based feature into a graph-based feature includes: Obtain grid cell information corresponding to image-based features, and Combine the grid cell information and the image-based features to convert the image-based features into graph-based features.

17. The semiconductor design device as claimed in claim 15, wherein, The step of converting the image-based features into graph-based features includes: Performing upsampling on the image-based features; and Converting the upsampled image-based features into graph-based features.

18. The semiconductor design device according to claim 14, wherein The processing further includes: Converting the graph-based features generated by the calculation up to the third layer of the second neural network model into image-based features, the graph-based features being obtained from the third layer, and Generating a fused feature by fusing the converted image-based features with the features obtained from the first layer of the first neural network model.

19. The semiconductor design device according to claim 18, wherein, The step of converting the graph-based features into image-based features includes: Arranging the graph-based features in the form of an image; and Wherein, the step of generating the fused feature includes: Generating a fused feature based on the arranged graph-based features and the features obtained from the first layer of the first neural network model.

20. The semiconductor design device as described in claim 19, wherein, Converting the graph-based features into image-based features further includes: performing downsampling on the arranged graph-based features based on the resolution of the features obtained from the first layer of the first neural network model.

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